Semiconductor device

Abstract

To provide a semiconductor device capable of improving the slew rate of output voltage.SOLUTION: A semiconductor device comprises: a low-side driver M0 whose gate-to-source withstand voltage is lower than the externally input power supply voltage VDD; a power supply circuit 11 that outputs a first voltage V1 lower than the power supply voltage VDD; a first circuit that drives the gate of the low-side driver M0 using the first voltage V1 as a power supply; and a second circuit that supplies current Ia to the gate of the low-side driver M0 from the power supply voltage node to which the power supply voltage VDD is supplied.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Gate drivers are known that drive the gates of voltage-controlled transistors, such as MOS field-effect transistors or insulated gate bipolar transistors.

[0003] For example, an output element with a gate withstand voltage lower than the power supply voltage (e.g., 15 to 40 V) requires a low-voltage (e.g., 5 V or 3 V) internal power supply circuit (LDO: Low drop out). Because the power supply voltage cannot be applied directly to the gate of the output element, a drive current must generally be applied to the gate of the output element via an internal power supply circuit that is lower than the gate withstand voltage, and the drive current applied to the gate depends on the capacity of the internal power supply circuit.

[0004] On the other hand, in inexpensive, single-function, high-speed gate driver devices (output elements) for driving external elements, the output terminals often consist of a power supply terminal, a ground terminal, and a drive output terminal, making it impossible to add external capacitance.

[0005] In this case, to ensure the instantaneous drive current of the pre-stage transistor (pre-driver) required to drive the output element at high speed, it is necessary to increase the capacitance installed at the output of the internal power supply circuit that serves as the power source for the pre-driver (adding internal capacitance).As a result, there is a trade-off between increasing the area of ​​the internal power supply circuit and high-speed drive, which can be said to be a factor in increasing the chip area.

[0006] Output elements with low gate breakdown voltages have high current drive capability and are suited to large current on and off operations. However, it is necessary to apply drive current to the gate of the output element via an internal power supply circuit with a voltage lower than the gate breakdown voltage. If the capacity of the internal power supply circuit is reduced in order to keep the chip size below the required size, the current drive capability of the output element cannot be fully utilized, and the slew rate cannot be shortened, i.e., it cannot be improved. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 5794195 specification Summary of the Invention [Problem to be solved by the invention]

[0008] A semiconductor device capable of improving the slew rate of an output voltage is provided. [Means for solving the problem]

[0009] The semiconductor device of the embodiment includes a first transistor having a gate-source breakdown voltage lower than an externally input power supply voltage, a first power supply circuit that outputs a first voltage lower than the power supply voltage, a first circuit that drives the gate of the first transistor using the first voltage as a power supply, and a second circuit that supplies a first current to the gate of the first transistor from a power supply voltage node to which the power supply voltage is supplied. [Brief explanation of the drawings]

[0010] For drawings [Figure 1] 1 is a circuit diagram showing an outline of the configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the details of the configuration of the semiconductor device according to the first embodiment. [Figure 3] 4 is a timing chart showing the operation of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing a configuration of a first modified example of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a configuration of a second modified example of the semiconductor device according to the first embodiment. [Figure 6] FIG. 10 is a circuit diagram showing a configuration of a third modified example of the semiconductor device according to the first embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a configuration of a fourth modified example of the semiconductor device according to the first embodiment. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of a fifth modified example of the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a circuit diagram showing a configuration of a sixth modified example of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram showing details of the configuration of a semiconductor device according to a second embodiment. [Figure 11] 10 is a timing chart showing the operation of the semiconductor device according to the second embodiment. [Figure 12] FIG. 10 is a circuit diagram showing a configuration of a first modified example of the semiconductor device according to the second embodiment. [Figure 13] FIG. 10 is a circuit diagram showing a configuration of a second modified example of the semiconductor device according to the second embodiment. [Figure 14] FIG. 10 is a circuit diagram showing details of the configuration of a semiconductor device according to a third embodiment. [Figure 15] 10 is a timing chart showing the operation of the semiconductor device according to the third embodiment. [Figure 16] FIG. 10 is a circuit diagram showing a configuration of a first modified example of the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0012] The functional blocks in the embodiments can be realized as either hardware or computer software, or a combination of both. It is not essential that the functional blocks be distinguished as in the following example. For example, some functions may be performed by functional blocks other than the illustrated functional blocks. Furthermore, the illustrated functional blocks may be further divided into smaller functional sub-blocks.

[0013] The semiconductor device of the embodiment includes a gate driver (or gate drive circuit) that drives the gate of a voltage-controlled transistor, for example, a MOS field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT). The gate driver is a circuit that controls the gate voltage (i.e., gate-source voltage) of the transistor to be driven and switches the transistor between an on state and an off state. The following explanation focuses on the output circuit section of the gate driver, which is a feature of the present invention. Therefore, the input circuit section, isolation circuit section, output control section, and protection circuit section will not be explained, but it is assumed that these are included. In addition, the drawings show the technically distinctive parts.

[0014] 1. First embodiment A semiconductor device according to a first embodiment will be described. The first embodiment shows an example in which paths are provided for flowing current from a node supplied with a power supply voltage VDD to the gate of a transistor constituting a driver, and from the gate of the transistor constituting the driver to a node supplied with a ground voltage GND. The power supply voltage VDD is a power supply voltage input to the semiconductor device from the outside. The ground voltage GND is a reference voltage input to the semiconductor device from the outside.

[0015] 1.1 Configuration of semiconductor device First, an outline of the configuration of the semiconductor device of the first embodiment will be described below. Fig. 1 is a circuit diagram showing an outline of the configuration of the semiconductor device of the first embodiment.

[0016] The semiconductor device 1 of the first embodiment includes, as a minimum configuration, a low-side driver M0, a high-side driver M1, a low-side pre-driver 10, and a high-side pre-driver 20, and is configured with at least three terminals: a power supply terminal, a ground terminal, and an output terminal. A power supply voltage VDD is supplied to the power supply terminal from an external source. A ground voltage GND is supplied to the ground terminal from an external source. The output terminal is a terminal for driving an external transistor.

[0017] The low-side pre-driver 10 drives the gate of the low-side driver M0. That is, the low-side pre-driver 10 controls the gate-source voltage of the low-side driver M0. The high-side pre-driver 20 drives the gate of the high-side driver M1. That is, the high-side pre-driver 20 controls the source-gate voltage of the high-side driver M1. The low-side driver M0 and the high-side driver M1 drive the gate of the transistor MX to be driven. That is, the low-side driver M0 and the high-side driver M1 control the gate-source voltage of the transistor MX to be driven.

[0018] Although not shown, the semiconductor device 1 may have a protection function such as DESAT, an active Miller clamp, a detection function for heat generation, and terminals associated with the function. The same applies to the other embodiments below.

[0019] The low-side driver M0 includes, for example, a MOS field-effect transistor. More specifically, the low-side driver M0 is an n-channel DMOS (Double-diffused Metal Oxide Semiconductor) field-effect transistor. The high-side driver M1 includes, for example, a MOS field-effect transistor. More specifically, the high-side driver M1 is a p-channel DMOS (Double-diffused Metal Oxide Semiconductor) field-effect transistor. The low-side driver M0 and the high-side driver M1 used here are, for example, transistors with a source-drain breakdown voltage higher than the power supply voltage VDD and a source-gate breakdown voltage lower than the power supply voltage VDD. The source-gate breakdown voltage of each of the low-side driver M0 and the high-side driver M1 is lower than the source-drain breakdown voltage. The low-side pre-driver 10 and the high-side pre-driver 20 will be described in detail later.

[0020] A control signal SA1 is input to the input terminal of the low-side pre-driver 10. An output terminal of the low-side pre-driver 10 is connected to the gate of the low-side driver M0. A control signal SB1 is input to the input terminal of the high-side pre-driver 20. An output terminal of the high-side pre-driver 20 is connected to the gate of the high-side driver M1.

[0021] The source of the low-side driver M0 is connected to a node to which a ground voltage GND is supplied (hereinafter referred to as a ground voltage GND node). The ground voltage GND is, for example, 0 V. The source of the high-side driver M1 is connected to a node to which a power supply voltage VDD is supplied (hereinafter referred to as a power supply voltage VDD node). The power supply voltage is, for example, 20 V. The drains of the low-side driver M0 and the high-side driver M1 are connected to an output terminal TO.

[0022] An output voltage VOX output from an output terminal TO is output to the gate of an external transistor MX. The transistor MX includes, for example, a MOS field-effect transistor or an IGBT. For example, a load LO is connected to one end of the transistor MX. A power supply voltage VDDX, which is a voltage different from the power supply voltage VDD, is supplied to the load LO. The transistor MX is switched on or off depending on the output voltage VOX. This controls the supply of the power supply voltage VDDX to the load LO.

[0023] Next, a detailed configuration of the semiconductor device 1 of the first embodiment will be described. Fig. 2 is a circuit diagram showing the detailed configuration of the semiconductor device of the first embodiment. Fig. 2 mainly shows the low-side pre-driver 10 and the high-side pre-driver 20 in detail.

[0024] The low-side pre-driver 10 includes transistors M11, M12, M13, and M14, a power supply circuit 11, a gate voltage protection circuit 12, and a gate boost circuit 13.

[0025] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage within the semiconductor device 1. The voltage V1 is, for example, 5 V, primarily drives the low-side driver M0, and is often equal to or less than half the power supply voltage VDD.

[0026] The gate withstand voltage protection circuit 12 limits the gate voltage so that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage, thereby protecting the low-side driver M0. Here, it is assumed that the gate-source withstand voltage of the low-side driver M0 is 7V, for example. In this case, a margin is provided for the gate-source withstand voltage of 7V, and the gate-source voltage is limited so that it does not exceed 5V. When the gate voltage exceeds 5V, the gate withstand voltage protection circuit 12 flows a current from the gate of the low-side driver M0 to the ground voltage GND node, thereby lowering the gate voltage, so that the gate-source voltage of the low-side driver M0 does not exceed 5V.

[0027] The gate boost circuit 13 supplies current from the power supply voltage VDD node to the gate of the low-side driver M0, and boosts the voltage of the gate of the low-side driver M0. The gate boost circuit 13 includes transistors M15, M16, and M17, a resistor R1, and a gate control circuit G1.

[0028] The transistor M15 includes, for example, an n-channel MOS field effect transistor. The transistors M16 and M17 each include, for example, a p-channel MOS field effect transistor. More specifically, the transistors M16 and M17 each are p-channel DMOS field effect transistors. The transistors M16 and M17 form a current mirror circuit. Therefore, the current Ia flowing through the transistor M17 is approximately the same as the current Ic flowing through the transistor M16. The resistor R1 limits the current Ic flowing through the transistors M15 and M16.

[0029] The gate control circuit G1 receives the control signal SA1 and outputs a pulse based on the control signal SA1 or a rectangular signal shorter than the control signal SA1 to the gate of the transistor M15.

[0030] Each of the transistors M11 and M13 includes, for example, a p-channel MOS field effect transistor, and each of the transistors M12 and M14 includes, for example, an n-channel MOS field effect transistor.

[0031] The high-side pre-driver 20 includes transistors M21 and M22, a power supply circuit 21, a gate voltage protection circuit 22, a level shifter 23, and a gate voltage reduction circuit 24.

[0032] The power supply circuit 21 supplies a voltage V2 as an internal power supply voltage within the semiconductor device 1. The voltage V2 is, for example, 15 V, and is a driving voltage obtained by subtracting the source-gate voltage of the high-side driver M1 to be controlled from the power supply voltage VDD.

[0033] The gate withstand voltage protection circuit 22 protects the high-side driver M1 by limiting the gate voltage so that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage. Here, it is assumed that the source-gate withstand voltage of the high-side driver M1 is, for example, 7V. In this case, a margin is provided for the source-gate withstand voltage of 7V, and the source-gate voltage is limited to not exceed 5V. To prevent the gate voltage of the high-side driver M1 from falling below 15V, the gate withstand voltage protection circuit 22 passes current from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1 when the gate voltage drops below 15V.

[0034] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20 V when the control signal SB1 is 5 V, and outputs 15 V when the control signal SB1 is 0 V.

[0035] The gate voltage step-down circuit 24 flows a current from the gate of the high-side driver M1 to the ground voltage GND node, thereby stepping down the voltage of the gate of the high-side driver M1. The gate voltage step-down circuit 24 includes a transistor M23, a resistor R2, and a gate control circuit G2.

[0036] The transistor M23 includes, for example, an n-channel MOS field-effect transistor. More specifically, the transistor M23 is an n-channel DMOS field-effect transistor. The resistor R2 limits the current Ib flowing through the transistor M23.

[0037] The gate control circuit G2 receives the control signal SB1 and outputs a pulse based on the control signal SB1 or a rectangular signal shorter than the control signal SB1 to the gate of the transistor M23.

[0038] The transistor M21 includes, for example, a p-channel MOS field effect transistor, and the transistor M22 includes, for example, an n-channel MOS field effect transistor.

[0039] The circuit connections of the semiconductor device 1 shown in FIG. 2 will be described below.

[0040] The control signal SA1 is input to a node A1, which is connected to the gate of a transistor M13 and the gate of a transistor M14.

[0041] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The output terminal of power supply circuit 11 is connected to the source of transistor M13 and the source of transistor M11.

[0042] The drain of the transistor M11 is connected to the drain of the transistor M12. The drains of the transistors M11 and M12 are connected to the gate of the low-side driver M0. The sources of the transistor M14, the transistor M12, and the low-side driver M0 are connected to the ground voltage GND node.

[0043] A gate breakdown voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0044] The node A1 is also connected to the input terminal of the gate control circuit G1. The output terminal of the gate control circuit G1 is connected to the gate of the transistor M15. The drain of the transistor M15 is connected to the gate and drain of the transistor M16 and the gate of the transistor M17. The source of the transistor M15 is connected to the ground voltage GND node via the resistor R1.

[0045] The drain of the transistor M17 is connected to the gate of the low-side driver M0. The sources of the transistors M16 and M17 are connected to the power supply voltage VDD node.

[0046] The control signal SB1 is input to a node B1. The node B1 is connected to an input terminal of a level shifter 23. The output terminal of the level shifter 23 is connected to a node B2. The node B2 is connected to the gate of a transistor M21 and the gate of a transistor M22.

[0047] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The output terminal of the power supply circuit 21 is connected to the source of the transistor M22.

[0048] The source of the transistor M21 and the source of the high-side driver M1 are connected to the power supply voltage VDD node.

[0049] A gate breakdown voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0050] The node B1 is also connected to the input terminal of the gate control circuit G2. The output terminal of the gate control circuit G2 is connected to the gate of the transistor M23. The drain of the transistor M23 is connected to the gate of the high-side driver M1. The source of the transistor M23 is connected to the ground voltage GND node via the resistor R2.

[0051] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0052] 1.2 Operation of semiconductor devices Next, a description will be given of the operation of the semiconductor device 1 of the first embodiment. Fig. 3 is a timing chart showing the operation of the semiconductor device 1 of the first embodiment, and shows the voltages and currents of the various parts within the semiconductor device 1.

[0053] The operation will be described below when the output voltage VOX output from the output terminal TO of the semiconductor device 1 transitions (1) from 20 V to 0 V, and (2) from 0 V to 20 V. A ground voltage GND (e.g., 0 V) ​​is supplied to the low-side driver M0, and a power supply voltage VDD (e.g., 20 V) is supplied to the high-side driver M1. A control signal SA1 is input to the node A1, and a control signal SB1 is input to the node B1.

[0054] (1) When the output voltage VOX transitions from 20V to 0V First, at time t0, 20V is output as the output voltage VOX from the output terminal TO. At this time, the control signal SA1 input to the node A1 is set to an "L" level (hereinafter referred to as "L"), for example, 0V, and the output voltage from the gate control circuit G1 is set to 0V. Also, the control signal SB1 input to the node B1 is set to an "H" level (hereinafter referred to as "H"), for example, 5V, and the output voltage from the gate control circuit G2 is set to 0V.

[0055] Next, at time t1, the control signal SB1 is set to "L." Then, the output voltage from the level shifter 23 drops from 20V to 15V, and the voltage at node B2 is set to 15V. As a result, 15V is supplied to the gate of transistor M21. 20V is supplied to the source of transistor M21 from the power supply voltage VDD node. This causes transistor M21 to transition from the off state to the on state.

[0056] Meanwhile, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the on state to the off state.

[0057] When transistor M21 is set to the ON state and transistor M22 is set to the OFF state, 20 V is supplied to the gate of high-side driver M1. 20 V is supplied to the source of high-side driver M1. This causes high-side driver M1 to transition from the ON state to the OFF state. This causes high-side driver M1 to stop supplying 20 V to output terminal TO.

[0058] Next, at time t2, the control signal SA1 is set to "H." Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. This causes the transistor M13 to transition from the ON state to the OFF state.

[0059] Meanwhile, 5 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the off state to the on state, thereby setting the voltage at the node A2 to 0 V.

[0060] When node A2 is set to 0 V, 0 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the off state to the on state.

[0061] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the on state to the off state.

[0062] When transistor M11 is set to the ON state and transistor M12 is set to the OFF state, the power supply circuit 11 begins supplying 5V to the gate of the low-side driver M0. As a result, the voltage at the gate of the low-side driver M0 begins to transition from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, when the voltage at the gate of the low-side driver M0 transitions to 5V, the low-side driver M0 transitions from the OFF state to the ON state. As a result, the low-side driver M0 begins supplying 0V to the output terminal TO.

[0063] Also, at time t2, the control signal SA1 is set to "H." Then, 5V is output from the gate control circuit G1 to the gate of transistor M15 for a time shorter than the "H" period of the control signal SA1. When 5V is supplied to the gate of transistor M15, transistor M15 transitions from the OFF state to the ON state. This causes a current Ic to flow through the current path of transistor M15. The current Ic is, for example, 10 mA.

[0064] Here, transistors M16 and M17 form a current mirror circuit. Therefore, the current Ia flowing through the current path of transistor M17 has the same current value as current Ic. This current Ia flows from the power supply voltage VDD node through transistor M17 to the gate of the low-side driver M0, charging the gate of the low-side driver M0. Current Ia acts as a boost current to increase the voltage at the gate of the low-side driver M0 from 0V to 5V. As a result, the voltage at the gate of the low-side driver M0 rises rapidly from 0V to 5V.

[0065] As a result of the above operation, at time t3, 0V is output as the output voltage VOX from the output terminal TO. As described above, the current Ia flowing from the power supply voltage VDD node to the gate of the low-side driver M0 rapidly increases the voltage at the gate of the low-side driver M0 from 0V to 5V. This causes the low-side driver M0 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR1 in FIG. 3, the output voltage VOX output from the output terminal TO rapidly drops from 20V to 0V. In other words, the slew rate of the output voltage VOX can be improved.

[0066] As a result, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V from time t3 to t4.

[0067] A gate voltage protection circuit 12 is provided between the gate of the low-side driver M0 and the ground voltage GND node. The gate voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from exceeding the gate-source breakdown voltage due to the inflow of current Ia. For example, the gate voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from exceeding 5V.

[0068] When current Ia flows from the power supply voltage VDD node to the gate of the low-side driver M0, the voltage at the gate of the low-side driver M0 rises. Then, when the voltage at the gate of the low-side driver M0 reaches 5V, the gate voltage protection circuit 12 begins operating. As a result, current Iaa flows from the gate of the low-side driver M0 to the ground voltage GND node via the gate voltage protection circuit 12, causing the voltage at the gate of the low-side driver M0 to drop. This limits the gate-source voltage of the low-side driver M0 to 5V or less. More specifically, at time t2, current Ia begins to flow from the power supply voltage VDD node to the gate of the low-side driver M0. At time t2a, before time t3, when the gate-source voltage of the low-side driver M0 reaches 5V, the gate voltage protection circuit 12 begins operating, causing current Iaa to begin flowing from the gate of the low-side driver M0 to the ground voltage GND node. Then, at time t3, the flow of currents Ia and Iaa is stopped. This prevents the low-side driver M0 from being destroyed when a voltage higher than the gate-source breakdown voltage is applied between the gate and source. It is desirable to set time t3 so that the time during which current Iaa flows is as short as possible.

[0069] In addition, a resistor R1 is connected between the source of the transistor M15 and the ground voltage GND node. The resistor R1 adjusts the current Ic that flows through the current path of the transistor M15 when the transistor M15 is set to the on state. By adjusting the value of the current Ic using the resistor R1, the value of the current Ia serving as the boost current can be adjusted. This makes it possible to adjust the rate at which the gate-source voltage of the low-side driver M0 rises from 0V to 5V.

[0070] (2) When the output voltage VOX transitions from 0V to 20V At time t3, 0 V is output from output terminal TO as output voltage VOX. At this time, control signal SA1 input to node A1 is set to "H", for example, 5 V, and the output voltage from gate control circuit G1 is set to 0 V. Also, control signal SB1 input to node B1 is set to "L", for example, 0 V, and the output voltage from gate control circuit G2 is set to 0 V.

[0071] Next, at time t4, the control signal SA1 is set to "L." This sets the voltage at node A1 to 0 V. As a result, 0 V is supplied to the gate of transistor M13. 5 V is supplied to the source of transistor M13 from the power supply circuit 11. This causes transistor M13 to transition from the off state to the on state.

[0072] Meanwhile, 0 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the ON state to the OFF state, thereby setting the voltage at the node A2 to 5 V.

[0073] When node A2 is set to 5 V, 5 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the on state to the off state.

[0074] Meanwhile, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the off state to the on state.

[0075] When transistor M11 is set to the off state and transistor M12 is set to the on state, 0V begins to be supplied to the gate of low-side driver M0. As a result, the voltage at the gate of low-side driver M0 begins to transition from 5V to 0V. 0V is supplied to the source of low-side driver M0. Therefore, when the voltage at the gate of low-side driver M0 transitions to 0V, low-side driver M0 transitions from the on state to the off state. As a result, low-side driver M0 stops supplying 0V to output terminal TO.

[0076] Next, at time t5, the control signal SB1 is set to "H." Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage at node B2 is set to 20V. Therefore, 20V is supplied to the gate of transistor M21. 20V is also supplied to the source of transistor M21. This causes transistor M21 to transition from the ON state to the OFF state.

[0077] Meanwhile, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the off state to the on state.

[0078] When transistor M21 is set to the OFF state and transistor M22 is set to the ON state, the power supply circuit 21 begins supplying 15 V to the gate of high-side driver M1. As a result, the gate voltage of high-side driver M1 begins to transition from 20 V to 15 V. 20 V is supplied to the source of high-side driver M1. Therefore, when the gate voltage of high-side driver M1 transitions to 15 V, high-side driver M1 transitions from the OFF state to the ON state. As a result, high-side driver M1 begins supplying 20 V to output terminal TO.

[0079] Also, at time t5, the control signal SB1 is set to "H." Then, 5V is output from the gate control circuit G2 to the gate of transistor M23 for a time shorter than the period during which the control signal SB1 is "H." When 5V is supplied to the gate of transistor M23, transistor M23 transitions from the OFF state to the ON state. This causes a current Ib to flow through the current path of transistor M23. The current Ib is, for example, 10 mA.

[0080] This current Ib is drawn from the gate of the high-side driver M1 through the transistor M23 to the ground voltage GND node, lowering the gate voltage of the high-side driver M1, causing the gate voltage of the high-side driver M1 to rapidly drop from 20 V to 15 V.

[0081] As a result of the above operation, at time t6, 20V is output as the output voltage VOX from the output terminal TO. As described above, the current Ib flowing from the gate of the high-side driver M1 to the ground voltage GND node rapidly reduces the voltage at the gate of the high-side driver M1 from 20V to 15V. This causes the high-side driver M1 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR2 in FIG. 3, the output voltage VOX output from the output terminal TO rapidly rises from 0V to 20V. In other words, the slew rate of the output voltage VOX can be improved.

[0082] As a result, the supply of 0V from the low-side driver M0 to the output terminal TO is cut off, and 20V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20V from time t6 to t7.

[0083] A gate voltage protection circuit 22 is provided between the power supply voltage VDD node and the gate of the high-side driver M1. The gate voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from dropping due to the flow of current Ib, causing the source-gate voltage to exceed the source-gate breakdown voltage. For example, the gate voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from dropping below 15 V.

[0084] When current Ib is drawn from the gate of the high-side driver M1 to the ground voltage GND node, the gate voltage of the high-side driver M1 drops. When the gate voltage of the high-side driver M1 reaches 15V, the gate voltage protection circuit 22 begins operating. As a result, current Ibb flows from the power supply voltage VDD node to the gate of the high-side driver M1 via the gate voltage protection circuit 22, raising the gate voltage of the high-side driver M1. This limits the gate voltage of the high-side driver M1 to 15V or higher. More specifically, at time t5, current Ib begins to flow from the gate of the high-side driver M1 to the ground voltage GND node. At time t5a, before time t6, when the gate voltage of the high-side driver M1 drops to 15V, the gate voltage protection circuit 22 begins operating, causing current Ibb to begin flowing from the power supply voltage VDD node to the gate of the high-side driver M1. Then, at time t6, the flow of currents Ib and Ibb stops. This prevents the high-side driver M1 from being destroyed when the gate voltage drops and the source-gate voltage exceeds the source-gate breakdown voltage. It is desirable to set the time during which the current Ibb flows as short as possible.

[0085] Furthermore, a resistor R2 is connected between the source of transistor M23 and the ground voltage GND node. When transistor M23 is set to the on state, resistor R2 adjusts the current Ib that flows through the current path of transistor M23. By adjusting the value of current Ib using resistor R2, the rate at which the voltage at the gate of high-side driver M1 decreases from 20 V to 15 V can be adjusted.

[0086] In the operation of the first embodiment, a dead time is provided between when the high-side driver M1 is set to the off state and when the low-side driver M0 starts to transition from the off state to the on state. For example, at time t1, the gate voltage of the high-side driver M1 is set to 20 V, setting the high-side driver M1 to the off state. Then, at time t2, the gate voltage of the low-side driver M0 starts to transition from 0 V to 5 V, starting the transition of the low-side driver M0 from the off state to the on state.

[0087] Similarly, after the low-side driver M0 is set to the OFF state, a dead time is provided before the high-side driver M1 starts to transition from the OFF state to the ON state. For example, at time t4, the gate voltage of the low-side driver M0 is set to 0 V, setting the low-side driver M0 to the OFF state. Then, at time t5, the gate voltage of the high-side driver M1 starts to transition from 20 V to 15 V, starting the transition of the high-side driver M1 from the OFF state to the ON state.

[0088] In this way, when the on state of the high-side driver M1 and the low-side driver M0 is switched, a period is provided during which both the high-side driver M1 and the low-side driver M0 are in the off state, thereby preventing problems such as a short circuit between the power supply voltage VDD and the ground voltage GND.

[0089] 1.3 Modifications of semiconductor devices Next, a modification of the semiconductor device of the first embodiment will be described.

[0090] 1, the control signals SA1 and SB1 are directly input as electrical signals to the low-side pre-driver 10 and the high-side pre-driver 20, respectively, but an electrically isolated transmitter circuit and receiver circuit may be provided at the input stages of the low-side pre-driver 10 and the high-side pre-driver 20, and the signal may be transmitted from the transmitter circuit to the receiver circuit. Below, a first modification in which the semiconductor device is provided with a transmitter circuit and a receiver circuit is shown.

[0091] 4 is a circuit diagram showing the configuration of Modification 1 of the first embodiment. The semiconductor device 1A includes a control circuit 30, a transmission circuit 31, a reception circuit 32, and a control circuit 33, which are provided at the input stages of the low-side pre-driver 10 and the high-side pre-driver 20. Between the transmission circuit 31 and the reception circuit 32, for example, an insulating unit 34 is provided.

[0092] The power supplies for operating the control circuits 30 and 33, the transmission circuit 31 and the reception circuit 32, and the terminals and connections related thereto are omitted. The same applies to the following modifications 2 to 4.

[0093] The control circuit 30 receives an input signal VIN from the outside. The control circuit 30 generates a drive signal for driving the transmission circuit 31 based on the received input signal VIN and outputs the drive signal to the transmission circuit 31. The transmission circuit 31 generates a signal based on the drive signal supplied from the control circuit 30 and transmits the generated signal to the reception circuit 32 via the insulating unit 34. The reception circuit 32 generates a signal based on the signal transmitted from the transmission circuit 31 and outputs the generated signal to the control circuit 33.

[0094] The control circuit 33 generates control signals SA1 and SB1 based on the signal supplied from the receiving circuit 32. The control circuit 33 outputs the generated control signals SA1 and SB1 to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0095] The transmitting circuit 31 and the receiving circuit 32 are electrically insulated by, for example, an insulating section 34. Signals are transmitted from the transmitting circuit 31 to the receiving circuit 32 using, for example, optical signals, magnetic signals, or electric field signals.

[0096] Below, modifications 2 to 4 will be described, in which optical signals, magnetic signals, or electric field signals are used to transmit signals from the transmitting circuit 31 to the receiving circuit 32.

[0097] 5 is a circuit diagram showing the configuration of Modification 2 of Embodiment 1. The semiconductor device 1B is an example in which an optical signal is used to transmit a signal from a transmitting circuit 31 to a receiving circuit 32.

[0098] The transmitting circuit 31 includes a light emitting element, for example, a light emitting diode Da. The receiving circuit 32 includes a light receiving element, for example, a photodiode Db.

[0099] The control circuit 30 generates a drive signal for driving the light-emitting diode Da in the transmission circuit 31 based on the input signal VIN and outputs the drive signal to the transmission circuit 31. The transmission circuit 31 causes the light-emitting diode Da to emit light using the drive signal generated by the control circuit 30. Light emitted from the light-emitting diode Da in the transmission circuit 31 is received by a photodiode Db in the reception circuit 32 via an insulating unit 34. The photodiode Db converts the received light into an electrical signal. The reception circuit 32 outputs the electrical signal converted by the photodiode Db to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electrical signal supplied from the reception circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0100] Other configurations and operations of the semiconductor device 1B are similar to those of the first embodiment shown in FIGS.

[0101] 6 is a circuit diagram showing the configuration of Modification 3 of Embodiment 1. The semiconductor device 1C is an example in which a magnetic signal is used to transmit a signal from a transmitting circuit 31 to a receiving circuit 32.

[0102] The transmission circuit 31 includes, for example, an inductor La. The reception circuit 32 includes, for example, an inductor Lb.

[0103] The control circuit 30 generates a drive signal for driving the inductor La in the transmission circuit 31 based on the input signal VIN and outputs the drive signal to the transmission circuit 31. The transmission circuit 31 uses the drive signal generated by the control circuit 30 to cause a current to flow through the inductor La. When a current flows through the inductor La in the transmission circuit 31, a magnetic field is generated near the inductor La. The magnetic field generated by the inductor La also changes the magnetic field near the inductor Lb in the reception circuit 32 via the insulating part 34. The inductor Lb generates a current due to an electromotive force corresponding to the magnetic field generated by the inductor La. The reception circuit 32 outputs an electrical signal corresponding to the current generated in the inductor Lb to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electrical signal supplied from the reception circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0104] Although not shown, in order to improve noise (EMS (Electromagnetic susceptibility) and EMI (Electromagnetic interference)) resistance and CMTI (Common mode transient immunity) characteristics, the transmitting circuit 31 and the receiving circuit 32 may transmit differential signals, in which case signal transmission is carried out by two inductor coil pairs.

[0105] 7 is a circuit diagram showing the configuration of Modification 4 of Embodiment 1. The semiconductor device 1D is an example in which an electric field signal is used to transmit a signal from a transmitting circuit 31 to a receiving circuit 32.

[0106] The transmitting circuit 31 includes, for example, a first electrode Ea. The receiving circuit 32 includes, for example, a second electrode Eb. The first electrode Ea and the second electrode Eb form a capacitive element (that is, a capacitor) Ca.

[0107] The control circuit 30 generates a signal for applying a voltage to the first electrode Ea in the transmission circuit 31 based on the input signal VIN and outputs the signal to the transmission circuit 31. The transmission circuit 31 applies a voltage to the first electrode Ea using the signal generated by the control circuit 30. When a voltage is applied to the first electrode Ea in the transmission circuit 31, an electric charge is stored in the first electrode Ea. Then, in accordance with the electric charge stored in the first electrode Ea, an electric charge is stored in the second electrode Eb in the reception circuit 32 via the insulating unit 34. The reception circuit 32 outputs an electric signal generated by the electric charge stored in the second electrode Eb to the control circuit 33. The control circuit 33 generates control signals SA1 and SB1 based on the electric signal supplied from the reception circuit 32. The control signals SA1 and SB1 generated by the control circuit 33 are input to the low-side pre-driver 10 and the high-side pre-driver 20, respectively.

[0108] Although not shown, in order to improve noise (EMS and EMI) resistance and CMTI characteristics, the transmitting circuit 31 and the receiving circuit 32 may transmit differential signals, in which case the signals are transmitted by two pairs of capacitance elements.

[0109] In the above-mentioned variants 1 to 4, a control circuit 30 is provided and the input signal VIN is input to the transmission circuit 31 via the control circuit 30, but there are also cases where the control circuit 30 is not provided and the input signal VIN is input directly to the transmission circuit 31.

[0110] 2 uses resistor elements R1 and R2 with fixed resistance values, but variable resistor elements with temperature dependency may be used instead of resistor elements R1 and R2. By replacing resistor elements R1 and R2 with variable resistor elements, it is possible to prevent the on-resistance of low-side driver M0 and high-side driver M1 from increasing and the current driving capability from decreasing when the temperature of semiconductor device 1E rises. Below, a fifth variation is shown in which variable resistor elements are used instead of resistor elements R1 and R2.

[0111] 8 is a circuit diagram showing the configuration of Modification 5 of Embodiment 1. A semiconductor device 1E includes variable resistance elements VR1 and VR2 having temperature dependency in place of the resistance elements R1 and R2, respectively.

[0112] For example, when the temperature of the semiconductor device 1E rises, the on-resistance of the low-side driver M0 increases, and the current driving capability decreases. Therefore, the current Ia is increased to rapidly change the voltage at the gate of the low-side driver M0 from 0V to 5V. This compensates for the decrease in the current driving capability of the low-side driver M0. Similarly, the current Ib is increased to rapidly change the voltage at the gate of the high-side driver M1 from 20V to 15V. This compensates for the decrease in the current driving capability of the high-side driver M1.

[0113] Specifically, the variable resistance elements VR1 and VR2 have temperature characteristics in which their resistance values ​​decrease as the temperature increases. When the temperature of the semiconductor device 1E increases, the resistance value of the variable resistance element VR1 decreases as the temperature of the semiconductor device 1E increases. When the resistance value of the variable resistance element VR1 decreases, the current value of the current Ic increases, and the current value of the current Ia also increases. This allows the gate voltage of the low-side driver M0 to rapidly increase from 0V to 5V, thereby accelerating the operation of the low-side driver M0 to supply 0V.

[0114] Similarly, when the temperature of the semiconductor device 1E increases, the resistance value of the variable resistance element VR2 decreases as the temperature of the semiconductor device 1E increases. As the resistance value of the variable resistance element VR2 decreases, the current value of the current Ib increases. This allows the gate voltage of the high-side driver M1 to rapidly decrease from 20 V to 15 V, thereby speeding up the operation of the high-side driver M1 to supply 20 V.

[0115] Although variable resistance elements VR1 and VR2 having a temperature characteristic in which the resistance value decreases as the temperature increases are used here, elements or circuits other than resistance elements may be used as long as they have a temperature characteristic in which the resistance value decreases as the temperature increases.Furthermore, a circuit that increases the current value of the current Ic as the temperature increases may also be used.

[0116] Alternatively, a diode may be provided between the transistor M11, which supplies the voltage V1, and the gate of the transistor M12 and the low-side driver M0. Furthermore, a diode may be provided between the transistor M22, which supplies the voltage V2, and the gate of the transistor M21 and the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. Variation 6, in which a diode is provided, is shown below.

[0117] 9 is a circuit diagram showing the configuration of Modification 6 of the first embodiment. The semiconductor device 1F includes a transistor M11 that supplies a voltage V1 from a power supply circuit 11, and a diode D1 connected between the transistor M12 and the gate of the low-side driver M0. The semiconductor device 1F further includes a transistor M22 that supplies a voltage V2 from a power supply circuit 21, and a diode D2 connected between the transistor M21 and the gate of the high-side driver M1.

[0118] The anode of diode D1 is connected to the drain of transistor M11, the cathode of diode D1 is connected to the drain of transistor M12 and the gate of low-side driver M0, the anode of diode D2 is connected to the drain of transistor M21 and the gate of high-side driver M1, and the cathode of diode D2 is connected to the drain of transistor M22.

[0119] The provision of diode D1 prevents current Ia from the transistor M17 from flowing back through transistor M11 to the power supply circuit 11. Furthermore, the provision of diode D2 prevents current from being drawn from the power supply circuit 21 via transistor M22 due to a voltage drop at the gate of transistor M1 caused by the current drawn by transistor M23. Although not shown, the diode D1 (or D2) may be replaced with a resistor, or a resistor may be inserted in series with the diode D1 (or D2) to limit the current drawn from the power supply circuit 11 (or power supply circuit 21), thereby reducing the impact on the power supply circuit 11 (or power supply circuit 21).

[0120] Although not shown, a resistor may be placed in parallel with the diode D1 (or D2) so that the forward voltage VF of the diode D1 (or D2) can be cancelled after a certain period of time.

[0121] 1.4 Effects of the First Embodiment According to the semiconductor device including the gate driver of the first embodiment, the slew rate of the output voltage can be improved.

[0122] Generally, for example, the power supply voltage used in a gate driver on a semiconductor device is 4V to 50V, and in most cases, it is 15V to 50V. However, the gate-source voltage of the MOS field-effect transistor, which is the output element of the gate driver, may only have a withstand voltage lower than the power supply voltage (e.g., 5V). In such cases, a power supply circuit is provided inside the semiconductor device to drive the gate of the output element. In such cases, a gate driver with a limited number of terminals connectable to the outside cannot provide the output of the internal power supply circuit as a terminal, and therefore cannot attach an external bypass capacitor to the output of the internal power supply circuit. In such cases, it is necessary to drive the output element at high speed using the internal power supply circuit. For this reason, it is necessary to increase the current driving capacity of the internal power supply circuit, which may increase the chip area, i.e., the area of ​​the semiconductor device.

[0123] In contrast, the configuration of the first embodiment includes a gate boost circuit 13 that supplies current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from that of the power supply circuit 11 provided within the semiconductor device as an internal power supply circuit. This rapidly boosts the voltage at the gate of the low-side driver M0 from 0V to 5V. This allows the low-side driver M0 to transition rapidly from an OFF state to an ON state without increasing the current drive capability of the power supply circuit 11, i.e., without increasing the chip area (the area of ​​the semiconductor device), thereby increasing the slew rate of the output voltage output from the low-side driver M0. Furthermore, a gate step-down circuit 24 that flows current Ib from the gate of the high-side driver M1 to the ground voltage GND node rapidly reduces the voltage at the gate of the high-side driver M1 from 20V to 15V. This allows the high-side driver M1 to transition rapidly from an OFF state to an ON state without increasing the current drive capability of the power supply circuit 21 provided within the semiconductor device as an internal power supply circuit, i.e., without increasing the chip area. This rapidly boosts the slew rate of the output voltage output from the high-side driver M1.

[0124] Furthermore, in the configuration of the first embodiment, by providing a gate withstand voltage protection circuit 12 between the gate of the low-side driver M0 and the ground voltage GND node, it is possible to limit the gate voltage so that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage. This makes it possible to prevent breakdown of the low-side driver M0, which would occur if the gate voltage increases and the gate-source voltage becomes higher than the gate-source withstand voltage. Furthermore, by providing a gate withstand voltage protection circuit 22 between the power supply voltage VDD node and the gate of the high-side driver M1, it is possible to limit the gate voltage so that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage. This makes it possible to prevent breakdown of the high-side driver M1, which would occur if the gate voltage decreases and the source-gate voltage becomes higher than the source-gate withstand voltage.

[0125] Furthermore, in the configuration of the first embodiment, by providing elements or circuits that increase the currents Ia and Ib as the temperature of the semiconductor device rises, the slew rate of the output voltages output from the low-side driver M0 and the high-side driver M1 can be increased even when the temperature rises.

[0126] The problems and advantages of this embodiment will be described in detail below.

[0127] The circuit on the semiconductor device includes a low-side driver M0 with a gate breakdown voltage lower than the power supply voltage VDD supplied to the power supply terminal, and a power supply circuit 11 that uses the power supply voltage VDD as its power source and outputs a voltage V1 that is lower than the gate breakdown voltage of the low-side driver M0. However, the output of voltage V1 is not connected to a terminal that can be connected to an external device, so an external coupling capacitor cannot be provided. To increase the slew rate of the output voltage VOX output from the output terminal TO, the gate capacitance of the low-side driver M0 needs to be charged quickly. However, providing a coupling capacitor within the circuit to prevent a drop in voltage V1 when transistor M11 is turned on would increase the chip area of ​​the semiconductor chip.

[0128] Therefore, when the low-side driver M0 is set to the ON state, the transistor M11, which is powered by the voltage V1, is turned ON, and at the same time, a boost current is passed to the gate of the low-side driver M0 while the transistor M17 is ON, using a path that passes current directly from the power supply voltage VDD to the gate of the low-side driver M0 via the transistor M17. This speeds up the charging of the gate capacitance of the low-side driver M0, regardless of the current capacity of the power supply circuit 11 that supplies the voltage V1. As a result, in this embodiment, the slew rate when the output voltage VOX switches from "H" (20 V) to "L" (0 V) is increased (for example, from 20 ns to 12 ns).

[0129] 2. Second embodiment A semiconductor device according to a second embodiment will be described. The second embodiment shows an example in which the gate voltages of the transistors constituting the low-side driver M0 and the high-side driver M1 are monitored and the currents Ia and Ib are adjusted, respectively, so that the gate-source voltage does not exceed the gate-source breakdown voltage. In the second embodiment, differences from the first embodiment will be mainly described.

[0130] 2.1 Configuration of semiconductor device The outline of the configuration of the semiconductor device of the second embodiment is similar to that of the first embodiment shown in Fig. 1. Here, the explanation of the outline of the configuration of the semiconductor device will be omitted, and the details of the configuration will be explained first.

[0131] FIG. 10 is a circuit diagram showing the details of the configuration of the semiconductor device of the second embodiment.

[0132] The semiconductor device 2 of the second embodiment includes a low-side driver M0, a high-side driver M1, a low-side pre-driver 10, and a high-side pre-driver 20.

[0133] The low-side pre-driver 10 includes transistors M11, M12, M13, and M14, a power supply circuit 11, a gate withstand voltage protection circuit 12, and a gate boost circuit 14.

[0134] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage within the semiconductor device 2. The voltage V1 is, for example, 5V.

[0135] The gate withstand voltage protection circuit 12 limits the gate voltage to protect the low-side driver M0 so that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage. When the gate voltage exceeds 5 V, the gate withstand voltage protection circuit 12 flows a current from the gate of the low-side driver M0 to the ground voltage GND node, thereby lowering the gate voltage so that the gate voltage of the low-side driver M0 does not exceed 5 V.

[0136] The gate boost circuit 14 supplies a current Ia from the power supply voltage VDD node to the gate of the low-side driver M0 based on the control signal SA1 and the voltage at the gate of the low-side driver M0, thereby boosting the voltage at the gate of the low-side driver M0. The gate boost circuit 14 includes transistors M15, M16, and M17, a resistor R1, and a gate control circuit G3.

[0137] The gate control circuit G3 monitors the voltage at the gate of the low-side driver M0, and when the gate-source voltage exceeds a set threshold voltage, outputs a voltage to the gate of the transistor M15 to turn the transistor M15 off. For example, based on the voltage at the gate of the low-side driver M0 and the control signal SA1, the gate control circuit G3 outputs a signal (e.g., 5V) to turn the transistor M15 on when the gate-source voltage of the low-side driver M0 is lower than a set threshold voltage (e.g., 5V). On the other hand, when the gate-source voltage of the low-side driver M0 is equal to or higher than the set threshold voltage (e.g., 5V), the gate control circuit G3 outputs a signal (e.g., 0V) to turn the transistor M15 off.

[0138] The transistors M16 and M17 form a current mirror circuit, so that the current Ia flowing through the transistor M17 is approximately the same as the current Ic flowing through the transistor M16. The resistor R1 limits the current Ic flowing through the transistors M15 and M16.

[0139] The high-side pre-driver 20 includes transistors M21 and M22, a power supply circuit 21, a gate voltage protection circuit 22, a level shifter 23, and a gate voltage reduction circuit 25.

[0140] The power supply circuit 21 supplies a voltage V2 as an internal power supply voltage within the semiconductor device 2. The voltage V2 is, for example, 15V.

[0141] The gate withstand voltage protection circuit 22 limits the gate voltage so that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage, thereby protecting the high-side driver M1. When the gate voltage drops below 15 V, the gate withstand voltage protection circuit 22 passes a current from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1.

[0142] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20 V when the control signal SB1 is 5 V, and outputs 15 V when the control signal SB1 is 0 V.

[0143] The gate voltage step-down circuit 25 flows a current Ib from the gate of the high-side driver M1 to the ground voltage GND node based on the control signal SB1 and the voltage at the gate of the high-side driver M1, thereby stepping down the voltage at the gate of the high-side driver M1. The gate voltage step-down circuit 25 includes a transistor M23, a resistor R2, and a gate control circuit G4.

[0144] The gate control circuit G4 monitors the voltage at the gate of the high-side driver M1, and when the source-gate voltage exceeds a set threshold, outputs a voltage to the gate of the transistor M23 to turn the transistor M23 off. For example, based on the voltage at the gate of the high-side driver M1 and a control signal SB1 (the voltage at node B1), the gate control circuit G4 outputs a signal (e.g., 5 V) to turn the transistor M23 on when the source-gate voltage of the high-side driver M1 is lower than a set threshold voltage (e.g., 5 V). On the other hand, when the source-gate voltage of the high-side driver M1 is equal to or higher than the set threshold voltage (e.g., 5 V), the gate control circuit G4 outputs a signal (e.g., 0 V) ​​to turn the transistor M23 off. The resistor element R2 limits the current Ib flowing through the transistor M23.

[0145] The circuit connections of the semiconductor device 2 shown in FIG. 10 will be described below.

[0146] The control signal SA1 is input to a node A1, which is connected to the gate of a transistor M13 and the gate of a transistor M14.

[0147] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The output terminal of power supply circuit 11 is connected to the source of transistor M13 and the source of transistor M11.

[0148] The drain of the transistor M11 is connected to the drain of the transistor M12. The drains of the transistors M11 and M12 are connected to the gate of the low-side driver M0. The sources of the transistor M14, the transistor M12, and the low-side driver M0 are connected to the ground voltage GND node.

[0149] A gate breakdown voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0150] The node A1 is connected to a first input terminal of a gate control circuit G3. The gate of the low-side driver M0 is connected to a second input terminal of the gate control circuit G3. The output terminal of the gate control circuit G3 is connected to the gate of the transistor M15.

[0151] The drain of the transistor M15 is connected to the gate and drain of the transistor M16 and the gate of the transistor M17. The source of the transistor M15 is connected to the ground voltage GND node via the resistor R1.

[0152] The drain of the transistor M17 is connected to the gate of the low-side driver M0. The sources of the transistors M16 and M17 are connected to the power supply voltage VDD node.

[0153] The control signal SB1 is input to a node B1. The node B1 is connected to an input terminal of a level shifter 23. The output terminal of the level shifter 23 is connected to a node B2. The node B2 is connected to the gate of a transistor M21 and the gate of a transistor M22.

[0154] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The output terminal of the power supply circuit 21 is connected to the source of the transistor M22.

[0155] The source of the transistor M21 and the source of the high-side driver M1 are connected to the power supply voltage VDD node.

[0156] A gate breakdown voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0157] The node B1 is connected to a first input terminal of a gate control circuit G4. The gate of the high-side driver M1 is connected to a second input terminal of the gate control circuit G4. The output terminal of the gate control circuit G4 is connected to the gate of the transistor M23.

[0158] The drain of the transistor M23 is connected to the gate of the high-side driver M1, and the source of the transistor M23 is connected to the ground voltage GND node via a resistor R2.

[0159] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0160] Although an example is shown here in which the gate voltage protection circuits 12 and 22 are provided, it is also possible to omit the gate voltage protection circuits 12 and 22. By omitting them, the power consumption of the circuit can be reduced, the circuit area can be reduced, and a lower cost design can be achieved.

[0161] 2.2 Operation of the Second Embodiment 11 is a timing chart showing the operation of the semiconductor device 2 according to the second embodiment, illustrating the voltages and currents at various points within the semiconductor device 2. As shown in FIG.

[0162] The operation will be described below when the output voltage VOX output from the output terminal TO of the semiconductor device 2 (1) transitions from 20 V to 0 V, and (2) transitions from 0 V to 20 V. A ground voltage (e.g., 0 V) ​​is supplied to the low-side driver M0, and a power supply voltage (e.g., 20 V) is supplied to the high-side driver M1. A control signal SA1 is input to the node A1, and a control signal SB1 is input to the node B1.

[0163] (1) When the output voltage VOX transitions from 20V to 0V First, at time t0, 20V is output from output terminal TO as output voltage VOX. At this time, control signal SA1 input to node A1 is set to "L", for example, 0V, and the output voltage from gate control circuit G3 is set to 0V. Also, control signal SB1 input to node B1 is set to "H", for example, 5V, and the output voltage from gate control circuit G4 is set to 0V.

[0164] Next, at time t1, the control signal SB1 is set to "L." Then, the output voltage from the level shifter 23 drops from 20V to 15V, and the voltage at node B2 is set to 15V. As a result, 15V is supplied to the gate of transistor M21. 20V is supplied to the source of transistor M21 from the power supply voltage VDD node. This causes transistor M21 to transition from the off state to the on state.

[0165] Meanwhile, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the on state to the off state.

[0166] When transistor M21 is set to the ON state and transistor M22 is set to the OFF state, 20 V is supplied to the gate of high-side driver M1. 20 V is supplied to the source of high-side driver M1. This causes high-side driver M1 to transition from the ON state to the OFF state. This causes high-side driver M1 to stop supplying 20 V to output terminal TO.

[0167] Next, at time t2, the control signal SA1 is set to "H." Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. This causes the transistor M13 to transition from the ON state to the OFF state.

[0168] Meanwhile, 5 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the off state to the on state, thereby setting the voltage at the node A2 to 0 V.

[0169] When node A2 is set to 0 V, 0 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the off state to the on state.

[0170] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the on state to the off state.

[0171] When transistor M11 is set to the ON state and transistor M12 is set to the OFF state, the power supply circuit 11 begins supplying 5V to the gate of the low-side driver M0. As a result, the voltage at the gate of the low-side driver M0 begins to transition from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, when the voltage at the gate of the low-side driver M0 transitions to 5V, the low-side driver M0 transitions from the OFF state to the ON state. As a result, the low-side driver M0 begins supplying 0V to the output terminal TO.

[0172] Also, at time t2, when the control signal SA1 is set to "H," 5V is input to the first input terminal of the gate control circuit G3. The gate voltage of the low-side driver M0 is input to the second input terminal of the gate control circuit G3. Here, when the gate-source voltage of the low-side driver M0 is lower than a set threshold voltage (e.g., 5V) and the control signal SA1 is "H," the gate control circuit G3 outputs 5V from the output terminal of the gate control circuit G3. On the other hand, when the gate-source voltage of the low-side driver M0 is equal to or higher than the set threshold voltage, the gate control circuit G3 outputs 0V. Here, because the gate-source voltage of the low-side driver M0 is lower than the set threshold voltage, 5V is supplied from the output terminal of the gate control circuit G3 to the gate of the transistor M15. As a result, the transistor M15 transitions from the OFF state to the ON state. As a result, a current Ic flows through the current path of the transistor M15. The current Ic is, for example, 10 mA.

[0173] Here, transistors M16 and M17 form a current mirror circuit. Therefore, the current Ia flowing through the current path of transistor M17 has the same current value as current Ic. This current Ia flows from the power supply voltage VDD node via transistor M17 to the gate of the low-side driver M0, charging the gate of the low-side driver M0. Current Ia acts as a boost current to increase the gate voltage of the low-side driver M0 from 0V to 5V. As a result, the gate voltage of the low-side driver M0 rises rapidly from 0V to 5V.

[0174] The gate control circuit G3 supplies 5 V to the gate of the transistor M15 until the voltage at the gate of the low-side driver M0 rises to 5 V. Then, when the voltage at the gate of the low-side driver M0 reaches 5 V, the gate control circuit G3 stops supplying 5 V.

[0175] As a result of the above operation, at time t3, 0V is output as the output voltage VOX from the output terminal TO. As described above, the current Ia flowing from the power supply voltage VDD node to the gate of the low-side driver M0 rapidly increases the voltage at the gate of the low-side driver M0 from 0V to 5V. This causes the low-side driver M0 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR3 in FIG. 11, the output voltage VOX output from the output terminal TO rapidly drops from 20V to 0V. In other words, the slew rate of the output voltage VOX can be improved.

[0176] As a result, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V from time t3 to t4.

[0177] In this embodiment, a gate withstand voltage protection circuit 12 is provided in case the gate control circuit G3 cannot limit the gate voltage of the low-side driver M0. The gate withstand voltage protection circuit 12 operates when the gate control circuit G3 cannot limit the gate-source voltage of the low-side driver M0 to or below the gate-source withstand voltage. The gate withstand voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from exceeding the gate-source withstand voltage due to the inflow of current Ia.

[0178] The gate control circuit G3 receives the gate voltage of the low-side driver M0 and a control signal SA1. When the gate-source voltage of the low-side driver M0 is lower than a set threshold voltage (e.g., 5V) and the control signal SA1 is "H," the gate control circuit G3 outputs a signal (e.g., 5V) to set the transistor M15 to an ON state. When the gate voltage of the low-side driver M0 reaches 5V, the gate control circuit G3 outputs a signal (e.g., 0V) to set the transistor M15 to an OFF state. Therefore, a current Ia flows from the power supply voltage VDD node to the gate of the low-side driver M0 until the gate voltage of the low-side driver M0 reaches 5V. When the gate voltage of the low-side driver M0 reaches 5V, the current Ia stops flowing from the power supply voltage VDD node to the gate of the low-side driver M0. Therefore, the gate-source voltage of the low-side driver M0 is limited to 5V or less. This prevents the low-side driver M0 from being destroyed by a voltage higher than its gate-source breakdown voltage being applied between the gate and source.

[0179] A resistor R1 is connected between the source of the transistor M15 and the ground voltage GND node. The resistor R1 adjusts the current Ic that flows through the current path of the transistor M15 when the transistor M15 is turned on. By adjusting the value of the current Ic using the resistor R1, the value of the current Ia that serves as the boost current can be adjusted. This allows the rate at which the voltage at the gate of the low-side driver M0 rises from 0V to 5V to be adjusted.

[0180] (2) When the output voltage VOX transitions from 0V to 20V At time t3, 0 V is output from output terminal TO as output voltage VOX. At this time, control signal SA1 input to node A1 is set to "H", for example, 5 V, and the output voltage from gate control circuit G3 is set to 0 V. Control signal SB1 input to node B1 is set to "L", for example, 0 V, and the output voltage from gate control circuit G4 is set to 0 V.

[0181] Next, at time t4, the control signal SA1 is set to "L." This sets the voltage at node A1 to 0 V. As a result, 0 V is supplied to the gate of transistor M13. 5 V is supplied to the source of transistor M13 from the power supply circuit 11. This causes transistor M13 to transition from the off state to the on state.

[0182] Meanwhile, 0 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the ON state to the OFF state, thereby setting the voltage at the node A2 to 5 V.

[0183] When node A2 is set to 5 V, 5 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the on state to the off state.

[0184] Meanwhile, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the off state to the on state.

[0185] When transistor M11 is set to the off state and transistor M12 is set to the on state, 0V begins to be supplied to the gate of low-side driver M0. As a result, the voltage at the gate of low-side driver M0 begins to transition from 5V to 0V. 0V is supplied to the source of low-side driver M0. Therefore, when the voltage at the gate of low-side driver M0 transitions to 0V, low-side driver M0 transitions from the on state to the off state. As a result, low-side driver M0 stops supplying 0V to output terminal TO.

[0186] Next, at time t5, the control signal SB1 is set to "H." Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage at node B2 is set to 20V. Therefore, 20V is supplied to the gate of transistor M21. 20V is also supplied to the source of transistor M21. This causes transistor M21 to transition from the ON state to the OFF state.

[0187] Meanwhile, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the off state to the on state.

[0188] When transistor M21 is set to the OFF state and transistor M22 is set to the ON state, the power supply circuit 21 begins supplying 15 V to the gate of high-side driver M1. As a result, the gate voltage of high-side driver M1 begins to transition from 20 V to 15 V. 20 V is supplied to the source of high-side driver M1. Therefore, when the gate voltage of high-side driver M1 transitions to 15 V, high-side driver M1 transitions from the OFF state to the ON state. As a result, high-side driver M1 begins supplying 20 V to output terminal TO.

[0189] Furthermore, when the control signal SB1 is set to "H" at time t5, 5V is input to the first input terminal of the gate control circuit G4. The gate voltage of the high-side driver M1 is input to the second input terminal of the gate control circuit G4. Here, when the source-gate voltage of the high-side driver M1 is lower than a set threshold voltage (e.g., 5V) and the control signal SB1 is "H," the gate control circuit G4 outputs 5V from the output terminal of the gate control circuit G4. On the other hand, when the source-gate voltage of the high-side driver M1 is equal to or higher than the set threshold voltage, the gate control circuit G4 outputs 0V. In this case, because the source-gate voltage of the high-side driver M1 is lower than the set threshold voltage, 5V is supplied from the output terminal of the gate control circuit G4 to the gate of the transistor M23. This causes the transistor M23 to transition from an OFF state to an ON state. As a result, a current Ib flows through the current path of the transistor M23. The current Ib is, for example, 10 mA.

[0190] This current Ib flows from the gate of the high-side driver M1 through the transistor M23 to the ground voltage GND node, lowering the gate voltage of the high-side driver M1, causing the gate voltage of the high-side driver M1 to rapidly drop from 20 V to 15 V.

[0191] Gate control circuit G4 supplies 5 V to the gate of transistor M23 until the voltage at the gate of high-side driver M1 drops to 15 V. Then, when the voltage at the gate of high-side driver M1 drops to 15 V, gate control circuit G4 stops supplying 5 V.

[0192] As a result of the above operation, at time t6, 20V is output as the output voltage VOX from the output terminal TO. As described above, the current Ib flowing from the gate of the high-side driver M1 to the ground voltage GND node rapidly reduces the voltage at the gate of the high-side driver M1 from 20V to 15V. This causes the high-side driver M1 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR4 in FIG. 11, the output voltage VOX output from the output terminal TO rapidly rises from 0V to 20V. In other words, the slew rate of the output voltage VOX can be improved.

[0193] As a result, the supply of 0V from the low-side driver M0 to the output terminal TO is cut off, and 20V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20V from time t6 to t7.

[0194] In this embodiment, a gate withstand voltage protection circuit 22 is provided in case the gate control circuit G4 cannot limit the gate voltage of the high-side driver M1. The gate withstand voltage protection circuit 22 operates when the gate control circuit G4 cannot limit the source-gate voltage of the high-side driver M1 to or below the source-gate withstand voltage. The gate withstand voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from decreasing due to the flow of current Ib, causing the source-gate voltage to exceed the source-gate withstand voltage.

[0195] The gate control circuit G4 receives the gate voltage of the high-side driver M1 and a control signal SB1 (the voltage at node B1). When the gate voltage of the high-side driver M1 is higher than 15V, it outputs a signal (e.g., 5V) to turn on the transistor M23. When the gate voltage of the high-side driver M1 drops below 15V, it outputs a signal (e.g., 0V) to turn off the transistor M23. Therefore, a current Ib flows from the gate of the high-side driver M1 to the ground voltage GND node until the gate voltage of the high-side driver M1 drops to 15V. When the gate voltage of the high-side driver M1 drops to 15V, the current Ib stops flowing from the gate of the high-side driver M1 to the ground voltage GND node. Therefore, the gate voltage of the high-side driver M1 is limited to 15V or higher. This prevents the high-side driver M1 from being destroyed when the gate voltage drops and the source-gate voltage exceeds the source-gate breakdown voltage.

[0196] Furthermore, a resistor R2 is connected between the source of transistor M23 and the ground voltage GND node. When transistor M23 is set to the on state, resistor R2 adjusts the current Ib that flows through the current path of transistor M23. By adjusting the value of current Ib using resistor R2, the rate at which the voltage at the gate of high-side driver M1 decreases from 20 V to 15 V can be adjusted.

[0197] In the operation of the second embodiment, a dead time is provided between when the high-side driver M1 is set to the off state and when the low-side driver M0 starts to transition from the off state to the on state. For example, at time t1, the gate voltage of the high-side driver M1 is set to 20 V, setting the high-side driver M1 to the off state. Then, at time t2, the gate voltage of the low-side driver M0 starts to transition from 0 V to 5 V, starting the transition of the low-side driver M0 from the off state to the on state.

[0198] Similarly, after the low-side driver M0 is set to the OFF state, a dead time is provided before the high-side driver M1 starts to transition from the OFF state to the ON state. For example, at time t4, the gate voltage of the low-side driver M0 is set to 0 V, setting the low-side driver M0 to the OFF state. Then, at time t5, the gate voltage of the high-side driver M1 starts to transition from 20 V to 15 V, starting the transition of the high-side driver M1 from the OFF state to the ON state.

[0199] In this way, when the on state of the high-side driver M1 and the low-side driver M0 is switched, a period is provided during which both the high-side driver M1 and the low-side driver M0 are in the off state, thereby preventing problems such as a short circuit between the power supply voltage VDD and the ground voltage GND.

[0200] 2.3 Semiconductor Device Modifications Next, a modification of the semiconductor device of the second embodiment will be described.

[0201] In the semiconductor device 2 shown in FIG. 10, similarly to the first embodiment, the control signals SA1 and SB1 are directly input as electrical signals to the low-side pre-driver 10 and the high-side pre-driver 20, respectively. However, as shown in FIG. 4, an electrically isolated transmitting circuit 31 and receiving circuit 32 may be provided at the input stages of the low-side pre-driver 10 and the high-side pre-driver 20, and a signal may be transmitted from the transmitting circuit 31 to the receiving circuit 32.

[0202] For transmitting signals from the transmitting circuit 31 to the receiving circuit 32, optical signals, magnetic signals, and electric field signals are used, as shown in FIGS. 5, 6, and 7, respectively.

[0203] Furthermore, variable resistance elements having temperature dependency may be used instead of the resistance elements R1 and R2. By replacing the resistance elements R1 and R2 with variable resistance elements, it is possible to prevent the on-resistance of the low-side driver M0 and the high-side driver M1 from increasing and the current driving capability from decreasing when the temperature of the semiconductor device 1E rises. Below, a first modification in which variable resistance elements are provided instead of the resistance elements R1 and R2 is shown.

[0204] 12 is a circuit diagram showing the configuration of Modification 1 of the second embodiment. A semiconductor device 2A includes temperature-dependent variable resistance elements VR1 and VR2 instead of resistance elements R1 and R2. The operation and effects of Modification 1 are similar to those of Modification 5 of the first embodiment shown in FIG. 8, and therefore detailed description thereof will be omitted.

[0205] As described above, for example, when the temperature of the semiconductor device 2A rises, the on-resistance of the low-side driver M0 increases, and the current driving capability decreases. Therefore, the current Ia is increased to rapidly change the voltage at the gate of the low-side driver M0 from 0V to 5V. This compensates for the decrease in the current driving capability of the low-side driver M0. Similarly, the current Ib is increased to rapidly change the voltage at the gate of the high-side driver M1 from 20V to 15V. This compensates for the decrease in the current driving capability of the high-side driver M1.

[0206] Alternatively, a diode may be provided between the transistor M11, which supplies the voltage V1, and the gate of the transistor M12 and the low-side driver M0. Furthermore, a diode may be provided between the transistor M22, which supplies the voltage V2, and the gate of the transistor M21 and the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. A second modification in which a diode is provided is shown below.

[0207] 13 is a circuit diagram showing the configuration of Modification 2 of the second embodiment. The semiconductor device 2B includes a transistor M11 that supplies a voltage V1 from the power supply circuit 11, and a diode D1 connected between the transistor M12 and the gate of the low-side driver M0. Furthermore, the semiconductor device 2B includes a transistor M22 that supplies a voltage V2 from the power supply circuit 21, and a diode D2 connected between the transistor M21 and the gate of the high-side driver M1. The operation and effects of Modification 2 are similar to those of Modification 6 of the first embodiment shown in FIG. 9, and therefore detailed description thereof will be omitted.

[0208] 2.3 Effects of the second embodiment According to the semiconductor device including the gate driver of the second embodiment, the slew rate of the output voltage can be improved.

[0209] The configuration of the second embodiment includes a gate boost circuit 14 that supplies current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from the power supply circuit 11 provided within the semiconductor device as an internal power supply circuit. This rapidly increases the voltage at the gate of the low-side driver M0 from 0V to 5V. This allows the low-side driver M0 to transition quickly from an OFF state to an ON state, thereby increasing the slew rate of the output voltage output from the low-side driver M0. Furthermore, a gate step-down circuit 25 that flows current Ib from the gate of the high-side driver M1 to the ground voltage GND node rapidly decreases the voltage at the gate of the high-side driver M1 from 20V to 15V. This allows the high-side driver M1 to transition quickly from an OFF state to an ON state, thereby increasing the slew rate of the output voltage output from the high-side driver M1.

[0210] The configuration of the second embodiment also includes a gate control circuit G3 that monitors the gate voltage of the low-side driver M0 and outputs a voltage that sets transistor M15 to the off state when the gate-source voltage exceeds a set threshold voltage. The gate control circuit G3 outputs a signal that sets transistor M15 to the on state until the gate-source voltage of the low-side driver M0 reaches a voltage (5 V) that transitions the low-side driver M0 to the on state. Then, when the gate voltage of the low-side driver M0 reaches the voltage that transitions the low-side driver M0 to the on state, it outputs a signal that sets transistor M15 to the off state. This prevents the gate voltage from rising and the gate-source voltage from exceeding the gate-source breakdown voltage, which could otherwise occur in the low-side driver M0.

[0211] The device also includes a gate control circuit G4 that monitors the gate voltage of the high-side driver M1 and outputs a voltage to set transistor M23 to an OFF state when the source-gate voltage exceeds a set threshold voltage. The gate control circuit G4 outputs a signal to set transistor M23 to an ON state until the gate voltage of high-side driver M1 reaches a voltage (15 V) that transitions high-side driver M1 to an ON state. When the gate voltage of high-side driver M1 reaches the voltage that transitions high-side driver M1 to an ON state, the gate control circuit G4 outputs a signal to set transistor M23 to an OFF state. This prevents breakdown of high-side driver M1 that occurs when the gate voltage drops and the source-gate voltage exceeds the source-gate breakdown voltage.

[0212] Furthermore, in the configuration of the second embodiment, by providing elements or circuits that increase the currents Ia and Ib as the temperature of the semiconductor device rises, the slew rate of the output voltages output from the low-side driver M0 and the high-side driver M1 can be increased even when the temperature rises.

[0213] 3. Third embodiment A semiconductor device according to a third embodiment will now be described. The third embodiment illustrates an example in which a capacitive element is provided in a path through which a current Ia flows from a power supply voltage VDD node to the gate of a transistor constituting a low-side driver M0, thereby shortening the time it takes for the gate-source voltage of the low-side driver M0 to reach a threshold voltage. Similarly, a capacitive element is provided in a path through which a current Ib flows from the gate of a transistor constituting a high-side driver M1 to a ground voltage GND node, thereby shortening the time it takes for the source-gate voltage of the high-side driver M1 to reach a threshold voltage. The third embodiment will mainly focus on the differences from the first embodiment.

[0214] 3.1 Configuration of semiconductor device The outline of the configuration of the semiconductor device of the third embodiment is similar to that of the first embodiment shown in Fig. 1. Here, the explanation of the outline of the configuration of the semiconductor device will be omitted, and the details of the configuration will be explained first.

[0215] FIG. 14 is a circuit diagram showing the details of the configuration of the semiconductor device of the third embodiment.

[0216] The semiconductor device 3 of the third embodiment includes a low-side driver M0, a high-side driver M1, a low-side pre-driver 10, and a high-side pre-driver 20.

[0217] The low-side pre-driver 10 includes transistors M11, M12, M13, and M14, a power supply circuit 11, a gate voltage protection circuit 12, and a gate boost circuit 15.

[0218] The power supply circuit 11 supplies a voltage V1 as an internal power supply voltage within the semiconductor device 3. The voltage V1 is, for example, 5V.

[0219] The gate withstand voltage protection circuit 12 limits the gate voltage so that the gate-source voltage of the low-side driver M0 does not exceed the gate-source withstand voltage, thereby protecting the low-side driver M0. When the gate voltage exceeds 5 V, the gate withstand voltage protection circuit 12 flows a current from the gate of the low-side driver M0 to the ground voltage GND node, thereby lowering the gate voltage so that the gate voltage of the low-side driver M0 does not exceed 5 V.

[0220] The gate boost circuit 15 supplies a current Ia from the power supply voltage VDD node and a capacitive element (i.e., a capacitor) C1 to the gate of the low-side driver M0, thereby boosting the voltage of the gate of the low-side driver M0. The gate boost circuit 15 includes transistors M15 and M18, a resistive element R3, a capacitive element C1, a level shifter 16, and a gate control circuit G5.

[0221] The level shifter 16 converts the voltage level of the signal supplied to the node A2 and outputs the converted signal. For example, the level shifter 16 outputs 20V when the signal supplied to the node A2 is 5V, and outputs 15V when the signal supplied to the node A2 is 0V.

[0222] The gate control circuit G5 receives the output signal from the level shifter 16 and outputs a signal based on the output signal to the gate of the transistor M15.

[0223] The high-side pre-driver 20 includes transistors M21 and M22, a power supply circuit 21, a gate voltage protection circuit 22, a level shifter 23, and a gate step-down circuit .

[0224] The power supply circuit 21 supplies a voltage V2 as an internal power supply voltage within the semiconductor device 3. The voltage V2 is, for example, 15V.

[0225] The gate withstand voltage protection circuit 22 limits the gate voltage so that the source-gate voltage of the high-side driver M1 does not exceed the source-gate withstand voltage, thereby protecting the high-side driver M1. When the gate voltage drops below 15 V, the gate withstand voltage protection circuit 22 passes a current from the power supply voltage VDD node to the gate of the high-side driver M1, thereby increasing the gate voltage of the high-side driver M1.

[0226] The level shifter 23 converts the voltage level of the input control signal SB1 and outputs the converted voltage level. For example, the level shifter 23 outputs 20 V when the control signal SB1 is 5 V, and outputs 15 V when the control signal SB1 is 0 V.

[0227] The gate voltage step-down circuit 26 flows a current Ib from the gate of the high-side driver M1 to the ground voltage GND node, thereby stepping down the voltage of the gate of the high-side driver M1. The gate voltage step-down circuit 26 includes transistors M23 and M24, a resistive element R4, a capacitive element (i.e., a capacitor) C2, and a gate control circuit G6.

[0228] The gate control circuit G6 receives the control signal SB1 and outputs a signal based on the control signal SB1 to the gate of the transistor M23.

[0229] The circuit connections of the semiconductor device 3 shown in FIG. 14 will be described below.

[0230] The control signal SA1 is input to a node A1, which is connected to the gate of a transistor M13 and the gate of a transistor M14.

[0231] The drain of transistor M13 is connected to the drain of transistor M14. The drains of transistors M13 and M14 are connected to node A2. Node A2 is connected to the gate of transistor M11 and the gate of transistor M12. The output terminal of power supply circuit 11 is connected to the source of transistor M13 and the source of transistor M11.

[0232] The drain of the transistor M11 is connected to the drain of the transistor M12. The drains of the transistors M11 and M12 are connected to the gate of the low-side driver M0. The sources of the transistor M14, the transistor M12, and the low-side driver M0 are connected to the ground voltage GND node.

[0233] A gate breakdown voltage protection circuit 12 is connected between the gate of the low-side driver M0 and the ground voltage GND node.

[0234] The node A2 is also connected to the input terminal of the level shifter 16. The output terminal of the level shifter 16 is connected to a node A3, which is connected to the input terminal of the gate control circuit G5. The output terminal of the gate control circuit G5 is connected to the gate of the transistor M15.

[0235] The source of the transistor M15 is connected to one end of the resistor R3, one end of the capacitor C1, and the drain of the transistor M18. The other end of the resistor R3, the other end of the capacitor C1, and the source of the transistor M18 are connected to the power supply voltage VDD node. That is, the current paths of the resistor R3, the capacitor C1, and the transistor M18 are connected in parallel between the power supply voltage VDD node and the source of the transistor M15. The gate of the transistor M18 is connected to the output end of the power supply circuit 21. Furthermore, the drain of the transistor M15 is connected to the gate of the low-side driver M0.

[0236] The control signal SB1 is input to a node B1. The node B1 is connected to an input terminal of a level shifter 23. The output terminal of the level shifter 23 is connected to a node B2. The node B2 is connected to the gate of a transistor M21 and the gate of a transistor M22.

[0237] The drain of the transistor M21 is connected to the drain of the transistor M22. The drains of the transistors M21 and M22 are connected to the gate of the high-side driver M1. The output terminal of the power supply circuit 21 is connected to the source of the transistor M22.

[0238] The source of the transistor M21 and the source of the high-side driver M1 are connected to the power supply voltage VDD node.

[0239] A gate breakdown voltage protection circuit 22 is connected between the gate of the high-side driver M1 and the power supply voltage VDD node.

[0240] The node B1 is also connected to the input terminal of the gate control circuit G6. The output terminal of the gate control circuit G6 is connected to the gate of the transistor M23. The drain of the transistor M23 is connected to the gate of the high-side driver M1. The source of the transistor M23 is connected to one end of the resistor R4, one end of the capacitor C2, and the drain of the transistor M24. The other end of the resistor R4, the other end of the capacitor C2, and the source of the transistor M24 are connected to the ground voltage GND node. That is, the current paths of the resistor R4, the capacitor C2, and the transistor M24 are connected in parallel between the source of the transistor M23 and the ground voltage GND node. The gate of the transistor M24 is connected to the output terminal of the power supply circuit 11.

[0241] The drain of the low-side driver M0 and the drain of the high-side driver M1 are connected to the output terminal TO.

[0242] 3.2 Operation of the third embodiment 15 is a timing chart showing the operation of the semiconductor device 3 of the third embodiment, and shows the voltages and currents at various points within the semiconductor device 3. As shown in FIG.

[0243] The operation will be described below when the output voltage VOX output from the output terminal TO of the semiconductor device 3 (1) transitions from 20 V to 0 V, and (2) transitions from 0 V to 20 V. A ground voltage (e.g., 0 V) ​​is supplied to the low-side driver M0, and a power supply voltage (e.g., 20 V) is supplied to the high-side driver M1. A control signal SA1 is input to the node A1, and a control signal SB1 is input to the node B1.

[0244] (1) When the output voltage VOX transitions from 20V to 0V First, at time t10, 20 V is output as the output voltage VOX from the output terminal TO. At this time, the control signal SA1 input to the node A1 is set to "L", for example, 0 V, and the output voltage from the gate control circuit G5 is set to 20 V. Also, the control signal SB1 input to the node B1 is set to "H", for example, 5 V, and the output voltage from the gate control circuit G6 is set to 0 V.

[0245] Next, at time t11, the control signal SB1 is set to "L." Then, the output voltage from the level shifter 23 drops from 20V to 15V, and the voltage at node B2 is set to 15V. As a result, 15V is supplied to the gate of transistor M21. 20V is supplied to the source of transistor M21 from the power supply voltage VDD node. This causes transistor M21 to transition from the off state to the on state.

[0246] Meanwhile, 15 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the on state to the off state.

[0247] When transistor M21 is set to the ON state and transistor M22 is set to the OFF state, 20 V is supplied to the gate of high-side driver M1. 20 V is supplied to the source of high-side driver M1. This causes high-side driver M1 to transition from the ON state to the OFF state. This causes high-side driver M1 to stop supplying 20 V to output terminal TO.

[0248] Next, at time t12, the control signal SA1 is set to "H." Then, the voltage of the node A1 is set to 5V. Therefore, 5V is supplied to the gate of the transistor M13. 5V is supplied to the source of the transistor M13 from the power supply circuit 11. This causes the transistor M13 to transition from the ON state to the OFF state.

[0249] Meanwhile, 5 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the off state to the on state, thereby setting the voltage at the node A2 to 0 V.

[0250] When node A2 is set to 0 V, 0 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the off state to the on state.

[0251] On the other hand, 0 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the on state to the off state.

[0252] When transistor M11 is set to the ON state and transistor M12 is set to the OFF state, the power supply circuit 11 begins supplying 5V to the gate of the low-side driver M0. As a result, the voltage at the gate of the low-side driver M0 begins to transition from 0V to 5V. 0V is supplied to the source of the low-side driver M0. Therefore, when the voltage at the gate of the low-side driver M0 transitions to 5V, the low-side driver M0 transitions from the OFF state to the ON state. As a result, the low-side driver M0 begins supplying 0V to the output terminal TO.

[0253] Furthermore, at time t12, when the control signal SA1 is set to "H" and the voltage at node A2 is set to 0V, the output voltage from the level shifter 16 drops from 20V to 15V, and the voltage at node A3 is set to 15V. Then, 15V is output from the gate control circuit G5 to the gate of transistor M15. Furthermore, 15V is supplied from the power supply circuit 21 to the gate of transistor M18, and 20V is supplied to the source of transistor M18. Therefore, transistor M18 is set to the ON state. When transistor M18 is set to the ON state, 20V is supplied to the source of transistor M15. Therefore, transistor M15 transitions from the OFF state to the ON state. As a result, a current Ia flows through the current path of transistor M15. The current Ia is, for example, 10 mA.

[0254] Here, a capacitive element C1 is provided between the power supply voltage VDD node and the source of transistor M15. As a result, current Ia rapidly flows from capacitive element C1 through transistor M15 into the gate of low-side driver M0, rapidly charging the gate of low-side driver M0 and raising the gate voltage of low-side driver M0 above its threshold voltage. Current Ia acts as a boost current to raise the gate voltage of low-side driver M0 from 0V to 5V. As a result, the gate voltage of low-side driver M0 rapidly rises from 0V to 5V.

[0255] As a result of the above operation, at time t13, 0V is output as the output voltage VOX from the output terminal TO. As described above, the current Ia flowing from the power supply voltage VDD to the gate of the low-side driver M0 rapidly increases the gate voltage of the low-side driver M0 from 0V to 5V. This causes the low-side driver M0 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR5 in FIG. 15, the output voltage VOX output from the output terminal TO rapidly drops from 20V to 0V. In other words, the time it takes for the gate-source voltage of the low-side driver M0 to reach the threshold voltage can be shortened, and the time from when the control signal SA1 is set to "H" until the output voltage VOX starts to change can be shortened. Furthermore, the slew rate of the output voltage VOX can be improved.

[0256] As a result, the supply of 20V from the high-side driver M1 to the output terminal TO is cut off and 0V is supplied from the low-side driver M0 to the output terminal TO, so that the output voltage VOX is set to 0V from time t13 to t14.

[0257] A gate voltage protection circuit 12 is provided between the gate of the low-side driver M0 and the ground voltage GND node. The gate voltage protection circuit 12 prevents the gate-source voltage of the low-side driver M0 from exceeding the gate-source breakdown voltage due to the inflow of the current Ia.

[0258] When current Ia flows into the gate of the low-side driver M0 from the power supply voltage VDD node and the capacitance element C1, the voltage at the gate of the low-side driver M0 rises. Then, when the voltage at the gate of the low-side driver M0 reaches 5V, the gate voltage protection circuit 12 begins operating. Therefore, current Iaa flows from the gate of the low-side driver M0 to the ground voltage GND node via the gate voltage protection circuit 12, causing the gate voltage of the low-side driver M0 to drop. This limits the gate-source voltage of the low-side driver M0 to 5V or less. More specifically, at time t12, current Ia begins to flow from the power supply voltage VDD node to the gate of the low-side driver M0. At time t12a, before time t13, when the voltage at the gate of the low-side driver M0 reaches 5V, the gate voltage protection circuit 12 begins operating, causing current Iaa to begin flowing from the gate of the low-side driver M0 to the ground voltage GND node. Then, at time t13, the flow of currents Ia and Iaa is stopped. This makes it possible to prevent the low-side driver M0 from being destroyed when a voltage higher than the gate-source breakdown voltage is applied to the gate.

[0259] (2) When the output voltage VOX transitions from 0V to 20V At time t13, 0 V is output from output terminal TO as output voltage VOX. At this time, control signal SA1 input to node A1 is set to "H", for example, 5 V, and the output voltage from gate control circuit G5 is set to 15 V. Also, control signal SB1 input to node B1 is set to "L", for example, 0 V, and the output voltage from gate control circuit G6 is set to 0 V.

[0260] Next, at time t14, the control signal SA1 is set to "L." This sets the voltage at node A1 to 0 V. As a result, 0 V is supplied to the gate of transistor M13. 5 V is supplied to the source of transistor M13 from the power supply circuit 11. This causes transistor M13 to transition from the off state to the on state.

[0261] Meanwhile, 0 V is supplied to the gate of the transistor M14, and 0 V is supplied to the source of the transistor M14, causing the transistor M14 to transition from the ON state to the OFF state, thereby setting the voltage at the node A2 to 5 V.

[0262] When node A2 is set to 5 V, 5 V is supplied to the gate of transistor M11. 5 V is supplied to the source of transistor M11 from power supply circuit 11. This causes transistor M11 to transition from the on state to the off state.

[0263] Meanwhile, 5 V is supplied to the gate of the transistor M12, and 0 V is supplied to the source of the transistor M12, causing the transistor M12 to transition from the off state to the on state.

[0264] When transistor M11 is set to the off state and transistor M12 is set to the on state, 0V begins to be supplied to the gate of low-side driver M0. As a result, the voltage at the gate of low-side driver M0 begins to transition from 5V to 0V. 0V is supplied to the source of low-side driver M0. Therefore, when the voltage at the gate of low-side driver M0 transitions to 0V, low-side driver M0 transitions from the on state to the off state. As a result, low-side driver M0 stops supplying 0V to output terminal TO.

[0265] Next, at time t15, the control signal SB1 is set to "H." Then, the output voltage from the level shifter 23 rises from 15V to 20V, and the voltage at node B2 is set to 20V. Therefore, 20V is supplied to the gate of transistor M21. 20V is also supplied to the source of transistor M21. This causes transistor M21 to transition from the ON state to the OFF state.

[0266] Meanwhile, 20 V is supplied to the gate of the transistor M22, and 15 V is supplied to the source of the transistor M22 from the power supply circuit 21. As a result, the transistor M22 transitions from the off state to the on state.

[0267] When transistor M21 is set to the OFF state and transistor M22 is set to the ON state, the power supply circuit 21 begins supplying 15 V to the gate of high-side driver M1. As a result, the gate voltage of high-side driver M1 begins to transition from 20 V to 15 V. 20 V is supplied to the source of high-side driver M1. Therefore, when the gate voltage of high-side driver M1 transitions to 15 V, high-side driver M1 transitions from the OFF state to the ON state. As a result, high-side driver M1 begins supplying 20 V to output terminal TO.

[0268] Also, at time t15, the control signal SB1 is set to "H." Then, 5V is output from the gate control circuit G6 to the gate of the transistor M23. When 5V is supplied to the gate of the transistor M23, the transistor M23 transitions from the OFF state to the ON state. As a result, a current Ib flows through the current path of the transistor M23. The current Ib is, for example, 10 mA.

[0269] Here, a capacitance element C2 is provided between the source of transistor M23 and the ground voltage GND node. As a result, current Ib from the gate of high-side driver M1 is rapidly drawn into capacitance element C2 via transistor M23, causing the gate voltage of high-side driver M1 to drop. As a result, the gate voltage of high-side driver M1 drops rapidly from 20 V to 15 V.

[0270] As a result of the above operation, at time t16, 20V is output as the output voltage VOX from the output terminal TO. As described above, the current Ib flowing from the gate of the high-side driver M1 to the capacitive element C2 rapidly reduces the voltage at the gate of the high-side driver M1 from 20V to 15V. This causes the high-side driver M1 to rapidly transition from the OFF state to the ON state. As a result, as shown by SR6 in FIG. 15, the output voltage VOX output from the output terminal TO rapidly rises from 0V to 20V. In other words, the slew rate of the output voltage VOX can be improved.

[0271] As a result, the supply of 0V from the low-side driver M0 to the output terminal TO is cut off, and 20V is supplied from the high-side driver M1 to the output terminal TO, so that the output voltage VOX is set to 20V from time t16 to t17.

[0272] A gate voltage protection circuit 22 is provided between the power supply voltage VDD node and the gate of the high-side driver M1. The gate voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from dropping due to a current Ib flowing from the gate of the high-side driver M1, causing the gate-source voltage to exceed the gate-source breakdown voltage. For example, the gate voltage protection circuit 22 prevents the gate voltage of the high-side driver M1 from dropping below 15 V.

[0273] When current Ib flows from the gate of the high-side driver M1 to the capacitance element C2, the gate voltage of the high-side driver M1 drops. When the gate voltage of the high-side driver M1 drops to 15V, the gate voltage protection circuit 22 starts operating. Therefore, current Ibb flows from the power supply voltage VDD node to the gate of the high-side driver M1 via the gate voltage protection circuit 22, raising the gate voltage of the high-side driver M1. This limits the gate voltage of the high-side driver M1 to 15V or higher. More specifically, at time t15, current Ib starts flowing from the gate of the high-side driver M1 to the ground voltage GND node. At time t15a, before time t16, when the gate voltage of the high-side driver M1 drops to 15V, the gate voltage protection circuit 22 starts operating, and current Ibb starts flowing from the power supply voltage VDD node to the gate of the high-side driver M1. Then, at time t16, the flow of currents Ib and Ibb stops. This prevents the high-side driver M1 from being destroyed when the gate voltage drops and the source-gate voltage becomes higher than the source-gate breakdown voltage.

[0274] In the operation of the third embodiment, a dead time is provided between when the high-side driver M1 is set to the off state and when the low-side driver M0 starts to transition from the off state to the on state. For example, at time t11, the gate voltage of the high-side driver M1 is set to 20 V, setting the high-side driver M1 to the off state. Then, at time t12, the gate voltage of the low-side driver M0 starts to transition from 0 V to 5 V, starting the transition of the low-side driver M0 from the off state to the on state.

[0275] Similarly, after the low-side driver M0 is set to the OFF state, a dead time is provided before the high-side driver M1 starts to transition from the OFF state to the ON state. For example, at time t14, the gate voltage of the low-side driver M0 is set to 0 V, setting the low-side driver M0 to the OFF state. Then, at time t15, the gate voltage of the high-side driver M1 starts to transition from 20 V to 15 V, starting the transition of the high-side driver M1 from the OFF state to the ON state.

[0276] In this way, when the on state of the high-side driver M1 and the low-side driver M0 is switched, a period is provided during which both the high-side driver M1 and the low-side driver M0 are in the off state, thereby preventing problems such as a short circuit between the power supply voltage VDD and the ground voltage GND.

[0277] 3.3 Semiconductor Device Modifications Next, a modification of the semiconductor device of the third embodiment will be described.

[0278] In the semiconductor device 3 shown in FIG. 14, similarly to the first embodiment, the control signals SA1 and SB1 are directly input as electrical signals to the low-side pre-driver 10 and the high-side pre-driver 20, respectively. However, as shown in FIG. 4, an electrically isolated transmitting circuit 31 and receiving circuit 32 may be provided at the input stages of the low-side pre-driver 10 and the high-side pre-driver 20, and a signal may be transmitted from the transmitting circuit 31 to the receiving circuit 32.

[0279] For transmitting signals from the transmitting circuit 31 to the receiving circuit 32, optical signals, magnetic signals, and electric field signals are used, as shown in FIGS. 5, 6, and 7, respectively.

[0280] Alternatively, a diode may be provided between the transistor M11, which supplies the voltage V1, and the gate of the transistor M12 and the low-side driver M0. Furthermore, a diode may be provided between the transistor M22, which supplies the voltage V2, and the gate of the transistor M21 and the high-side driver M1. By providing these diodes, current is prevented from flowing from the gate of the low-side driver M0 to the power supply circuit 11. Alternatively, current is prevented from flowing from the power supply circuit 21 to the gate of the high-side driver M1. Variation 1, in which a diode is provided, is shown below.

[0281] 16 is a circuit diagram showing the configuration of Modification 1 of the third embodiment. The semiconductor device 3A includes a transistor M11 that supplies a voltage V1 from a power supply circuit 11, and a diode D1 connected between the transistor M12 and the gate of the low-side driver M0. The semiconductor device 3A further includes a transistor M22 that supplies a voltage V2 from a power supply circuit 21, and a diode D2 connected between the transistor M21 and the gate of the high-side driver M1. The operation and effects of Modification 1 are similar to those of Modification 6 of the first embodiment shown in FIG. 9, so detailed description thereof will be omitted.

[0282] 3.3 Effects of the third embodiment According to the semiconductor device including the gate driver of the third embodiment, the slew rate of the output voltage can be improved.

[0283] The configuration of the third embodiment includes a gate boost circuit 15 that supplies current Ia to the gate of the low-side driver M0 from a power supply voltage VDD node different from the power supply circuit 11 provided within the semiconductor device as an internal power supply circuit and from a capacitive element C1, thereby rapidly raising the voltage at the gate of the low-side driver M0 from 0 V to 5 V. This allows the low-side driver M0 to transition quickly from an OFF state to an ON state, thereby increasing the slew rate of the output voltage output from the low-side driver M0. Furthermore, a gate step-down circuit 26 that flows current Ib from the gate of the high-side driver M1 to the ground voltage GND node and capacitive element C2 rapidly lowers the voltage at the gate of the high-side driver M1 from 20 V to 15 V. This allows the high-side driver M1 to transition quickly from an OFF state to an ON state, thereby increasing the slew rate of the output voltage output from the high-side driver M1.

[0284] Furthermore, in the configuration of the third embodiment, by providing a gate withstand voltage protection circuit 12 between the gate of the low-side driver M0 and the ground voltage GND node, it is possible to limit the gate-source voltage of the low-side driver M0 so that it does not exceed the gate-source withstand voltage. This makes it possible to prevent breakdown of the low-side driver M0, which would occur if the gate voltage increases and the gate-source voltage becomes higher than the gate-source withstand voltage. Furthermore, by providing a gate withstand voltage protection circuit 22 between the power supply voltage VDD node and the gate of the high-side driver M1, it is possible to limit the source-gate voltage of the high-side driver M1 so that it does not exceed the source-gate withstand voltage. This makes it possible to prevent breakdown of the high-side driver M1, which would occur if the gate voltage decreases and the source-gate voltage becomes higher than the source-gate withstand voltage.

[0285] 4.Other The semiconductor device of the above-described embodiment can be implemented as follows.

[0286] 1. A first transistor (M0) whose gate-source breakdown voltage is lower than the externally input power supply voltage (VDD), a first power supply circuit (11) that outputs a first voltage (V1) that is lower than the power supply voltage; a first circuit (M11, M12) that drives the gate of the first transistor (M0) using the first voltage (V1) as a power supply; a second circuit (13 (14, 15)) that supplies a first current (Ia) to the gate of the first transistor (M0) from a power supply voltage node to which the power supply voltage is supplied; A semiconductor device comprising:

[0287] 2. The semiconductor device described in 1 above, wherein the supply of the first current (Ia) by the second circuit is carried out for a first period in parallel with the supply of the first voltage to the gate of the first transistor (M0) by the first circuit (M11, M12).

[0288] 3. The second circuit (13) is supplying the first current (Ia) from the power supply voltage node to the gate of the first transistor (M0) until the voltage of the gate of the first transistor (M0) reaches the first voltage (V1); The semiconductor device according to claim 1 or 2, wherein when the voltage of the gate of the first transistor (M0) reaches the first voltage (V1), the supply of the first current from the power supply voltage node to the gate of the first transistor (M0) is stopped.

[0289] 4. The second circuit (13) a current mirror circuit including a second transistor (M17) connected between the power supply voltage node and a gate of the first transistor (M0), and a third transistor (M16) connected between the power supply voltage node and a ground voltage node to which a ground voltage (GND) is supplied; a fourth transistor (M15) connected between the third transistor (M16) and the ground voltage node; 4. The semiconductor device according to any one of 1 to 3 above, comprising:

[0290] 5. The semiconductor device according to claim 4, wherein the second circuit (13) includes a resistive element (R1) connected between the fourth transistor (M15) and the ground voltage node.

[0291] 6. The semiconductor device according to claim 4, wherein the second circuit (13) is connected between the fourth transistor (M15) and the ground voltage node and includes a resistor element (VR1) whose resistance value changes in response to changes in temperature.

[0292] 7. The semiconductor device according to any one of 4 to 6 above, wherein the second circuit (14) comprises a third circuit (G3) having an input terminal connected to the gate of the first transistor (M0), an output terminal connected to the gate of the fourth transistor (M15), and supplying a first signal to the gate of the fourth transistor (M15) depending on the voltage of the gate of the first transistor (M0).

[0293] 8. The third circuit (G3) providing the first signal that sets the fourth transistor (M15) to an on state when the voltage of the gate of the first transistor (M0) is lower than the first voltage; 8. The semiconductor device according to claim 7, wherein the first signal is supplied to set the fourth transistor (M15) to an off state when the voltage of the gate of the first transistor (M0) is equal to or higher than the first voltage.

[0294] 9. The semiconductor device according to claim 1, wherein the second circuit (15) comprises a transistor (M18), a resistive element (R3), and a capacitive element (C1) connected in parallel to each other between the power supply voltage node and the gate of the first transistor (M0).

[0295] 10. The semiconductor device described in any one of 1 to 9 above, further comprising a protection circuit (12) connected between the gate of the first transistor (M0) and a ground voltage node to which a ground voltage (GND) is supplied, and limiting the voltage of the gate of the first transistor (M0) to the voltage level of the first voltage.

[0296] 11. A transmitting circuit (31) that receives the second signal and transmits a third signal in response to the second signal; a receiving circuit (32) electrically insulated from the transmitting circuit, receiving the third signal, and generating a fourth signal in response to the third signal; Further comprising: 11. The semiconductor device according to any one of 1 to 10, wherein the first circuit and the second circuit receive the fourth signal and operate based on the fourth signal.

[0297] 12. The semiconductor device according to claim 11, wherein the third signal transmitted from the transmitting circuit to the receiving circuit is any one of an optical signal, a magnetic signal, and an electric field signal.

[0298] 13. The first circuit comprises: a fifth transistor (M11) and a sixth transistor (M12) connected between an output terminal of the first power supply circuit (11) and a ground voltage node to which a ground voltage is supplied; a diode (D1) connected between the fifth transistor (M11) and the sixth transistor (M12); The first voltage (V1) is supplied to a first terminal of the fifth transistor (M11), The second terminal of the fifth transistor (M11) is connected to the anode of the diode (D1), and the cathode of the diode (D1) is connected to the gate of the first transistor (M0) and the first terminal of the sixth transistor (M12), 13. The semiconductor device according to any one of 1 to 12, wherein the ground voltage is supplied to a second terminal of the sixth transistor (M12).

[0299] 14. The semiconductor device according to any one of 1 to 13 above, wherein the breakdown voltage between the gate and source of the first transistor (M0) is lower than the breakdown voltage between the drain and source of the first transistor (M0).

[0300] 15. The semiconductor device according to any one of the above 1 to 14, wherein the first transistor (M0) is a gate driver that drives the gate of the transistor (MX).

[0301] 16. A seventh transistor (M1) having a breakdown voltage between its source and gate lower than the power supply voltage (VDD); a second power supply circuit (21) that outputs a second voltage (V2) that is lower than the power supply voltage; a fourth circuit (M21, M22) that uses the power supply voltage (VDD) and the second voltage (V2) output from the second power supply circuit (21) as power supplies to drive the gate of the seventh transistor (M1); a fifth circuit (24 (25, 26)) that supplies a second current (Ib) to a ground voltage node to which a ground voltage is supplied from the gate of the seventh transistor (M1); 16. The semiconductor device according to any one of 1 to 15 above, further comprising:

[0302] 17. The fifth circuit (24) is supplying the second current (Ib) from the gate of the seventh transistor (M1) to the ground voltage node until the voltage of the gate of the seventh transistor (M1) reaches the second voltage (V2); 17. The semiconductor device according to claim 16, wherein when the voltage of the gate of the seventh transistor (M1) reaches the second voltage (V2), the supply of the second current from the gate of the seventh transistor (M1) to the ground voltage node is stopped.

[0303] 18. The fifth circuit (24) is an eighth transistor (M23) connected between the gate of the seventh transistor (M1) and the ground voltage node; a resistive element (R2) connected between the eighth transistor (M23) and the ground voltage node; 18. The semiconductor device according to claim 16 or 17, comprising:

[0304] 19. The semiconductor device according to claim 18, wherein the fifth circuit (25) includes a sixth circuit (G4) having an input terminal connected to the gate of the seventh transistor (M1), an output terminal connected to the gate of the eighth transistor (M23), and supplying a second signal to the gate of the eighth transistor (M23) depending on the voltage of the gate of the seventh transistor (M1).

[0305] 20. The fifth circuit (26) is an eighth transistor (M23) connected between the gate of the seventh transistor (M1) and the ground voltage node; a transistor (M24), a resistive element (R4), and a capacitive element (C2) connected in parallel with each other between the source of the eighth transistor (M23) and the ground voltage node; 17. The semiconductor device according to claim 16, comprising:

[0306] In addition, for example, a photocoupler or a digital isolator is used in the semiconductor device including the gate driver of this embodiment.

[0307] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0308] 1...semiconductor device, 1A...semiconductor device, 1B...semiconductor device, 1C...semiconductor device, 1D...semiconductor device, 1E...semiconductor device, 1F...semiconductor device, 2...semiconductor device, 2A...semiconductor device, 2B...semiconductor device, 3...semiconductor device, 3A...semiconductor device, 10...low-side pre-driver, 11...power supply circuit, 12...gate breakdown voltage protection circuit, 13...gate boost circuit, 14...gate boost circuit, 15...gate boost circuit, 16...level shifter, 20...high-side pre-driver, 21...power supply circuit, 22...gate breakdown voltage protection circuit, 23...level shifter, 24...gate step-down circuit, 25...gate step-down circuit, 26...gate step-down circuit, 30...control circuit, 31...transmitting circuit, 32...receiving circuit, 33...control circuit, 34...insulating section, A1...node, A2...node, A3...node, B1...node, B2...node, C1...capacitor, C2...capacitor, Ca ...capacitive element, D1...diode, Da...light-emitting diode, Db...photodiode, Ea...electrode, Eb...electrode, G1...gate control circuit, G2...gate control circuit, G3...gate control circuit, G4...gate control circuit, La...inductor, Lb...inductor, M0...low-side driver, M1...high-side driver, M11...transistor, M12...transistor, M13...transistor, M14...transistor, M15...transistor, M16...transistor, M17...transistor, M18...transistor, M21...transistor, M22...transistor, M23...transistor, M24...transistor, R1...resistive element, R2...resistive element, R3...resistive element, R4...resistive element, SA1...control signal, SB1...control signal, VR1...variable resistive element having temperature characteristics, VR2...variable resistive element having temperature characteristics.

Claims

1. a first transistor having a gate-source breakdown voltage lower than a power supply voltage input from an external source; a first power supply circuit that outputs a first voltage that is lower than the power supply voltage; a first circuit that drives a gate of the first transistor using the first voltage as a power supply; a second circuit that supplies a first current to a gate of the first transistor from a power supply voltage node to which the power supply voltage is supplied; A semiconductor device comprising:

2. 2 . The semiconductor device according to claim 1 , wherein the supply of the first current by the second circuit is executed for a first period in parallel with the supply of the first voltage to the gate of the first transistor by the first circuit.

3. The second circuit is providing the first current from the power supply voltage node to the gate of the first transistor until the voltage of the gate of the first transistor reaches the first voltage; 2 . The semiconductor device according to claim 1 , wherein when the voltage of the gate of the first transistor reaches the first voltage, the supply of the first current from the power supply voltage node to the gate of the first transistor is stopped.

4. The second circuit is a current mirror circuit including a second transistor connected between the power supply voltage node and a gate of the first transistor, and a third transistor connected between the power supply voltage node and a ground voltage node to which a ground voltage is supplied; a fourth transistor connected between the third transistor and the ground voltage node; The semiconductor device according to claim 1 .

5. 5. The semiconductor device according to claim 4, wherein the second circuit comprises a third circuit having an input terminal connected to the gate of the first transistor and an output terminal connected to the gate of the fourth transistor, the third circuit supplying a first signal to the gate of the fourth transistor in response to a voltage of the gate of the first transistor.

6. The third circuit is providing the first signal to set the fourth transistor to an on state when the voltage of the gate of the first transistor is lower than the first voltage; 6. The semiconductor device according to claim 5, wherein the first signal is supplied to set the fourth transistor in an off state when the voltage of the gate of the first transistor is equal to or higher than the first voltage.

7. 2 . The semiconductor device according to claim 1 , wherein the second circuit comprises a transistor, a resistive element, and a capacitive element connected in parallel with each other between the power supply voltage node and the gate of the first transistor.

8. 2. The semiconductor device according to claim 1, further comprising a protection circuit connected between the gate of the first transistor and a ground voltage node to which a ground voltage is supplied, the protection circuit limiting the voltage of the gate of the first transistor to a voltage level of the first voltage.

9. a transmission circuit that receives the second signal and transmits a third signal in response to the second signal; a receiving circuit electrically isolated from the transmitting circuit, receiving the third signal, and generating a fourth signal in response to the third signal; Further comprising: The semiconductor device according to claim 1 , wherein the first circuit and the second circuit receive the fourth signal and operate based on the fourth signal.

10. a fifth transistor having a source-gate breakdown voltage lower than the power supply voltage; a second power supply circuit that outputs a second voltage lower than the power supply voltage; a fourth circuit that drives a gate of the fifth transistor using the power supply voltage and the second voltage output from the second power supply circuit as power supplies; a fifth circuit that supplies a second current to a ground voltage node to which a ground voltage is supplied from a gate of the fifth transistor; The semiconductor device according to claim 1 , further comprising:

11. The fifth circuit is supplying the second current from the gate of the fifth transistor to the ground voltage node until a voltage of the gate of the fifth transistor reaches the second voltage; 11. The semiconductor device according to claim 10, wherein when the voltage of the gate of the fifth transistor reaches the second voltage, the supply of the second current from the gate of the fifth transistor to the ground voltage node is stopped.

12. The fifth circuit is a sixth transistor connected between the gate of the fifth transistor and the ground voltage node; a resistive element connected between the sixth transistor and the ground voltage node; The semiconductor device according to claim 10 .

13. 13. The semiconductor device according to claim 12, wherein the fifth circuit comprises a sixth circuit having an input terminal connected to the gate of the fifth transistor and an output terminal connected to the gate of the sixth transistor, the sixth circuit supplying a second signal to the gate of the sixth transistor in response to a voltage of the gate of the fifth transistor.

Images