Method of manufacturing semiconductor device and semiconductor device

Abstract

To suppress leakage current at an exposed surface of a semiconductor device.SOLUTION: A method of manufacturing a semiconductor device includes: preparing a laminate that includes a semiconductor laminate including an n-side group III nitride semiconductor layer, a p-side group III nitride semiconductor layer, and an undoped group III nitride semiconductor layer arranged between the n-side group III nitride semiconductor layer and the p-side group III nitride semiconductor layer, and an electrode layer arranged on the p-side group III nitride semiconductor layer; dry etching from the surface of the electrode layer to at least the middle of the undoped group III nitride semiconductor layer; cleaning, by wet treatment, an exposed surface of the laminate exposed by the dry etching; and oxidizing a surface subjected to the wet treatment.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, and a semiconductor device. [Background technology]

[0002] Compound semiconductors, which exhibit semiconductor properties through a combination of two or more elements, have a high degree of freedom in designing band gaps, mobility, etc., and are widely used in optical devices, switching devices, power devices, etc. Compound semiconductors are processed into various shapes depending on the application. For microfabrication with small line widths, anisotropic etching using dry processes such as reactive ion etching (RIE) is generally used.

[0003] A method has been proposed for exposing a less damaged c-plane by wet etching the inner surface of a groove formed by dry etching in a semiconductor substrate made of a group III nitride semiconductor (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-188165 A Summary of the Invention [Problem to be solved by the invention]

[0005] When processing a semiconductor material into a desired shape, a stacked body including different types of semiconductor layers may be dry-etched in succession. When a semiconductor layer is dry-etched, leakage current increases at the etched and exposed sidewall, and the voltage rise in the voltage-current characteristic becomes slow. In one aspect of the disclosure, leakage current at the exposed surface of a semiconductor element is reduced. [Means for solving the problem]

[0006] In one embodiment, a method for manufacturing a semiconductor device includes: preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the undoped III-nitride semiconductor layer from a surface of the electrode layer to at least a portion of the undoped III-nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; This includes:

[0007] In another embodiment, a method for manufacturing a semiconductor device includes: preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the n-side Group III nitride semiconductor layer from a surface of the electrode layer to at least a portion of the n-side Group III nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; This includes:

[0008] In one embodiment, the semiconductor device comprises: a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the undoped Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region of the semiconductor laminate located inside the surface region.

[0009] In another embodiment, the semiconductor device comprises: a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the n-side Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region of the semiconductor laminate located inside the surface region. Effect of the Invention

[0010] Leakage current at the exposed surface of the semiconductor element is reduced. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram of a semiconductor element according to a first embodiment. [Figure 2A] 2 is a manufacturing process diagram of the semiconductor element of FIG. 1. [Figure 2B] 2 is a manufacturing process diagram of the semiconductor element of FIG. 1. [Figure 2C] 2 is a manufacturing process diagram of the semiconductor element of FIG. 1. [Figure 2D] 2 is a manufacturing process diagram of the semiconductor element of FIG. 1. [Diagram 3] FIG. 1 is a schematic diagram of a distributed feedback (DFB) laser as an application example of a semiconductor element. [Figure 4A]FIG. 13 is a diagram showing etching depth. [Figure 4B] FIG. 13 is a diagram showing etching depth. [Figure 4C] FIG. 13 is a diagram showing etching depth. [Figure 4D] FIG. 4B is a diagram showing the IV characteristics in FIG. 4A. [Figure 4E] FIG. 4C is a diagram showing the IV characteristics in FIG. 4B. [Figure 4F] FIG. 4D is a diagram showing the IV characteristics in FIG. 4C. [Diagram 5] 1A to 1C are diagrams illustrating the effects of the method and configuration of an embodiment. [Figure 6] FIG. 4 is a schematic diagram of a semiconductor element according to a second embodiment. [Figure 7] 13A to 13C are diagrams illustrating a modified example of the semiconductor element according to the second embodiment. [Figure 8A] 11A to 11C are manufacturing process diagrams of a semiconductor device according to a third embodiment. [Figure 8B] 11A to 11C are manufacturing process diagrams of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment for carrying out the present disclosure will be described with reference to the drawings. The following description is for the purpose of embodying the technical idea of ​​the present disclosure, and unless otherwise specified, the present disclosure is not limited to the following description. In each drawing, the same reference numerals may be attached to components having the same functions. In consideration of the explanation or ease of understanding of the main points, the embodiments may be shown separately for convenience, but partial replacement or combination of the configurations shown in different embodiments or examples is possible. In the embodiments shown later, differences from the embodiments shown earlier will be mainly explained, and overlapping explanations of matters common to the embodiments shown earlier may be omitted. The size and positional relationship of the components shown in each drawing may be exaggerated to clarify the explanation.

[0013] First Embodiment FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 according to a first embodiment. When the semiconductor device 10 is an optical semiconductor device such as a semiconductor laser device, the cross section in FIG. 1 is taken along an XY plane perpendicular to the Z axis, which is the optical axis direction. The semiconductor device 10 has a semiconductor stack 14 including an n-side group III nitride semiconductor layer 11, a p-side group III nitride semiconductor layer 13, and an undoped group III nitride semiconductor layer 12 disposed between the n-side group III nitride semiconductor layer 11 and the p-side group III nitride semiconductor layer 13, and an electrode 15 disposed on the p-side group III nitride semiconductor layer 13. The semiconductor stack 14 has a side surface 17 that extends from the surface of the p-side group III nitride semiconductor layer 13 to at least halfway through the undoped group III nitride semiconductor layer 12, and the side surface 17 and the surface region 19 have a higher oxygen content than an internal region of the semiconductor stack 14 located inside the surface region 19. The surface region 19 may be a region extending from the side surface 17 to, for example, 10 nm.

[0014] A group III nitride semiconductor is a compound of one or more group III elements selected from boron (B), aluminum (Al), gallium (Ga), and indium (In) and nitrogen (N). x Ga 1-x N(0≦x≦1), In y Ga 1-y N (0≦y≦1), AlInGaN, etc. The n-side III-nitride semiconductor layer 11 includes a donor impurity doped in a III-nitride semiconductor at a predetermined concentration. The donor impurity is, for example, Si or Ge at a concentration of 1.0×10 17 cm -3 Above 5.0×10 19 cm -3 The n-side group III nitride semiconductor layer 11 may include one or more layers containing donor impurities at different concentrations, and may include a contact layer, a cladding layer, an optical guiding layer, etc., as described later.

[0015] The undoped Group III nitride semiconductor layer 12 is a layer that is not intentionally doped with impurities. The undoped Group III nitride semiconductor layer 12 has slight conductivity and can operate as an n-type Group III nitride semiconductor. The undoped Group III nitride semiconductor layer 12 has a donor impurity concentration of 1.0×10 17 cm -3 and the concentration of acceptor impurities is less than 1×10 17 cm -3 The impurity concentration may be equal to or less than the detection sensitivity of SIMS. The impurity concentration can be analyzed by, for example, secondary ion mass spectrometry (SIMS). The impurity concentration may be equal to or less than the detection sensitivity of SIMS. The undoped III-nitride semiconductor layer 12 may include an active layer having a quantum well. The active layer may be disposed between the undoped III-nitride semiconductor layer 12 and the n-side III-nitride semiconductor layer 11.

[0016] The p-side III-nitride semiconductor layer 13 is a layer containing a predetermined concentration of acceptor impurities in a III-nitride semiconductor. The acceptor impurities are, for example, Be, Mg, etc., at a concentration of 1.0×10 17 cm -3 Above 1.0×10 21 cm -3 The n-side III nitride semiconductor layer 11 is doped with an acceptor impurity at the concentration below. The p-side III nitride semiconductor layer 13 in contact with the undoped III nitride semiconductor layer 12 has an acceptor impurity and is at least a p-type III nitride semiconductor layer. Depending on the state of voltage application to the electrode 15, free electrons move from the n-side III nitride semiconductor layer 11 to the undoped III nitride semiconductor layer 12, and the interface between the undoped III nitride semiconductor layer 12 and the p-side III nitride semiconductor layer 13 becomes a pn junction surface.

[0017] Surface leakage current may occur on the side of the semiconductor layer exposed by dry etching. In particular, surface leakage current may be a problem on the side wall that is dry etched through the pn junction of the compound semiconductor. Even if the side wall is covered with a protective film, it may be difficult to sufficiently suppress such surface leakage current. In the embodiment, the oxygen content of the exposed side surface 17 and the surface region 19 of the semiconductor laminate 14 is made higher than that of the internal region, thereby reducing the leakage current. The surface region 19 is, for example, a region extending from the side surface 17 to 10 nm inward of the semiconductor laminate 14, preferably a region extending to 5 nm or less. When compared with the same semiconductor layer, the oxygen content of the surface region 19 is higher than that of a region extending more than a dozen nanometers inward from the side surface 17. The oxygen in the surface region 19 may terminate, for example, dangling bonds on the side surface of the semiconductor laminate 14. It is believed that this reduces the leakage current on the side surface of the semiconductor laminate 14. The fact that the surface region 19 contains a lot of oxygen can be confirmed, for example, by a combination of cross-sectional transmission electron microscope (TEM) observation and energy dispersive X-ray spectroscopy (EDX method). For example, the layer containing a lot of oxygen may be formed to a thickness of about several atomic layers from the surface. The layer containing a lot of oxygen may be flat, and may reflect the flatness of the crystal plane. The crystal structure of the surface region 19 may be substantially the same as the crystal structure of the semiconductor laminate 14. This can be inferred by comparing the fast Fourier transform patterns of TEM images in a region 10 nm or less, preferably 5 nm or less, away from the surface and a region 20 nm or more, preferably 25 nm or more, away from the surface. For example, similar fast Fourier transform patterns are obtained.

[0018] The side surface 17 of the semiconductor laminate 14 is located inside the outer periphery of the electrode 15 in a top view. This is a minute step that occurs when the side surface 17 exposed by dry etching of the semiconductor laminate 14 is cleaned by wet processing, and is due to the selectivity of the wet processing solution for the material of the electrode 15 and the Group III nitride semiconductor. After cleaning the side surface 17 of the semiconductor laminate 14 of miscellaneous crystals and damage by wet processing, the semiconductor laminate 14 is placed in an oxygen atmosphere, whereby a surface region 19 having a higher oxygen content than the inner region is obtained.

[0019] <Semiconductor device manufacturing process> 2A to 2D are diagrams showing the manufacturing process of the semiconductor device 10. The semiconductor device can be manufactured, for example, by the following method. As shown in Fig. 2A, a stacked body 200 is prepared on a substrate 101, the stacked body 200 including a semiconductor stacked body 140 having, in this order, an n-side Group III nitride semiconductor layer 110, an undoped Group III nitride semiconductor layer 120, and a p-side Group III nitride semiconductor layer 130, and an electrode layer 150 on the p-side Group III nitride semiconductor layer 130.

[0020] The substrate 101 may be a GaN substrate or a sapphire substrate. The semiconductor laminate 140 is fabricated by a metal organic chemical vapor deposition (MOCVD) method or a physical vapor deposition (PVD) method. As the PVD method, for example, a sputtering method or a molecular beam epitaxy (MBE) method is used. The n-side group III nitride semiconductor layer 110, the undoped group III nitride semiconductor layer 120, and the p-side group III nitride semiconductor layer 130 may be a binary system, a ternary system, or a quaternary system. When the n-side group III nitride semiconductor layer 110 is formed, for example, Si is introduced as an impurity, and when the p-side group III nitride semiconductor layer 130 is formed, Mg is introduced as an impurity. Note that when the undoped group III nitride semiconductor layer 120 is formed, no intentional doping of impurities is performed.

[0021] The electrode layer 150 is formed of, for example, a metal or a light-transmitting metal oxide. The electrode layer 150 is preferably formed of a light-transmitting metal oxide. This allows the Group III nitride semiconductor layer to be selectively wet-treated in a wet process described later, rather than a metal oxide. Examples of light-transmitting metal oxides include ITO (In2O3-SnO2), IZO (In-Zn-O), GZO (Ga-Zn-O), and other metal oxides to which dopants are added, such as Al-doped ZnO. The electrode layer 150 is formed, for example, by a sputtering method using a target having a desired composition ratio. A resist mask 26 is disposed at a predetermined position on the surface of the electrode layer 150. The resist mask 26 is formed into a desired shape by applying a photoresist and then exposing and developing it by a photolithography method. The resist mask 26 may be patterned by an electron beam lithography method.

[0022] In FIG. 2B, the electrode layer 150 and a part of the semiconductor laminate 140 are etched away by anisotropic dry etching such as RIE or ion beam etching using the resist mask 26. In this example, dry etching is performed from the surface of the electrode layer 150 to at least the middle of the undoped group III nitride semiconductor layer 120. In dry etching, etching may be performed continuously from the surface of the electrode layer 150 to the middle of the undoped group III nitride semiconductor layer 120 using a common resist mask 26. For example, the electrode layer 150 made of a transparent metal oxide is plasma etched with a halogen-based gas to which an inert gas has been added, or an organic gas to which H2 or HCl has been added. Then, the p-side group III nitride semiconductor layer 130 and the undoped group III nitride semiconductor layer 120 are etched with plasma containing a chlorine-based gas. This results in a structure including a semiconductor stack 14 with a ridge structure having, in this order, an n-side Group III nitride semiconductor layer 11, an undoped Group III nitride semiconductor layer 12, and a p-side Group III nitride semiconductor layer 13, and an electrode 15 on the p-side Group III nitride semiconductor layer 13.

[0023] The n-side III nitride semiconductor layer 11 may include one or more n-side semiconductor layers in at least one of the layers such as the n-side contact layer, the n-side cladding layer, and the n-side optical guide layer. The p-side III nitride semiconductor layer 13 may include one or more p-type semiconductor layers in at least one of the layers such as the p-side optical guide layer, the p-side cladding layer, and the p-side contact layer. In the semiconductor laminate 14, an active layer or a light absorption layer may be disposed between the n-side III nitride semiconductor layer 11 and the undoped III nitride semiconductor layer 12. In this case, the dry etching step of FIG. 2B may form a ridge structure of a laser resonator, a periodic recess such as a diffraction grating, or a pixel separation groove of a light receiving element. This makes it possible to obtain a laser resonator, a diffraction grating, or a light receiving element with reduced leakage current.

[0024] In FIG. 2C, the exposed surface of the semiconductor laminate 14 exposed by dry etching is cleaned by wet processing. This wet processing is surface cleaning using an alkaline etchant. This allows the exposed surface of the semiconductor laminate 14 to be efficiently processed. Examples of alkaline etchants include tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), and sodium hydroxide (NaOH). When using a TMAH aqueous solution, the TMAH concentration is 2% or more and 5% or less. The temperature of the etchant is 50° C. or more and less than 100° C., preferably 50° C. or more and 80° C. or less, and it is desirable to clean the surface at a relatively low temperature and at a slow etching rate. As an example, the structure obtained in FIG. 2B is immersed in a 2.38% TMAH aqueous solution heated to 60° C. for 60 minutes. This wet processing removes miscellaneous crystals and damaged layers on the dry-etched surface, and the m-plane of the group III nitride semiconductor is exposed on the side surface 17. The m-plane is a plane parallel to the c-axis of the crystal of the III-nitride semiconductor, that is, a plane perpendicular to the c-plane. In the wet process, the side surface 17, which extends from the surface of the p-side III-nitride semiconductor layer 13 to the middle of the undoped III-nitride semiconductor layer 12, recedes inward from the outer periphery 151 of the electrode 15, and a slight step 153 is generated between the lower end of the electrode 15 and the side surface 17. This results in a clean surface. The m-plane obtained by this wet process is a surface exposed by removing miscellaneous crystals and damaged layers from the dry-etched surface, and is not a surface that has been intentionally etched. After the wet process is completed, a wet etching process may be further added to obtain a semiconductor laminate 14 of a desired thickness.

[0025] In FIG. 2D, the wet-processed surface is oxidized. This process can reduce leakage current at the exposed surface that penetrates the pn junction of the semiconductor element. This oxidation process includes leaving the wet-processed structure of FIG. 2C in an oxygen-containing atmosphere for a predetermined time. Oxidation forms the side surface 17 and surface region 19 of the semiconductor stack 14 that have a higher oxygen content than the internal region of the semiconductor stack 14. The formation of the side surface 17 and surface region 19 with a higher oxygen content reduces leakage current at the etched surface that penetrates the pn junction (i.e., the interface between the p-side III nitride semiconductor layer 13 and the undoped III nitride semiconductor layer 12). The oxygen-containing atmosphere means an atmosphere with an oxygen content of 10% or more and 99% or less, preferably 20% or more and 99% or less, by volume. The oxygen-containing atmosphere may be air. Finally, an n-side electrode that is electrically connected to the n-side III nitride semiconductor layer 11 is provided at an appropriate location to obtain a semiconductor element.

[0026] <Application to semiconductor laser element> FIG. 3 is a schematic diagram of a semiconductor element 10A applied to a semiconductor laser element. FIG. 3 is a cross section of the semiconductor element 10A in a YZ plane parallel to the optical axis of the semiconductor element 10A. The semiconductor element 10A is, for example, a distributed feedback (DFB) laser, and has periodic recesses 171 provided in the resonance direction (Z direction). The inner wall of the periodic recesses 171 becomes the side surface 17 penetrating the pn junction. The recesses 171 penetrate the interface between the p-side group III nitride semiconductor layer 13 and the undoped group III nitride semiconductor layer 12 from the surface of the electrode 15 to reach the middle of the undoped group III nitride semiconductor layer 12. The periodic recesses 171 can increase the reflectance at a predetermined wavelength. The interval between the periodic recesses 171 is about the length of the wavelength at which the semiconductor laser element oscillates, for example, the length of the wavelength in vacuum / (2×effective refractive index). The interval between the periodic recesses 171 may be, for example, 400 nm or less, 300 nm or less, 200 nm or less, or 100 nm or less. In one cross section of FIG. 3, the exposed first side surface and the exposed second side surface face each other, and the distance between the first side surface and the second side surface is shorter than the interval between the periodic recesses 171, and may be, for example, 10 nm to 350 nm, 10 nm to 250 nm, 10 nm to 150 nm, or 10 nm to 70 nm. When the interval between the periodic recesses 171 is as short as the length of the oscillation wavelength and the interval between the two opposing side surfaces is even shorter, there is a possibility that the insulating film cannot be sufficiently filled into the recesses 171. However, in the method according to the embodiment, the exposed side surface 17 is oxidized, so that the leakage current can be efficiently reduced. In a top view (XZ plane), the side surface 17 of the recess 171 is slightly recessed inward from the outer periphery of the electrode 15. The side surface 17 exposed in each recess 171 has a surface region 19 that has a higher oxygen content than the inside of the semiconductor laminate 14. In Fig. 3, a part of the surface region 19 is omitted from illustration in order to make the drawing easier to see.

[0027] 3, each side surface 17 of the periodic recess 171 is oxidized after a damaged layer containing miscellaneous crystals is removed by wet processing, thereby reducing leakage current, thereby enabling the light extraction efficiency or wall plug efficiency (WPE) of the semiconductor element 10A to be maintained high.

[0028] FIG. 4A shows a schematic diagram of a state where RIE is not performed. FIG. 4B shows a schematic diagram of a state where RIE is performed from the electrode 15 to the p-side group III nitride semiconductor layer 13. FIG. 4C shows a schematic diagram of a state where RIE is further performed from FIG. 4B to the undoped group III nitride semiconductor layer 12. FIG. 4D shows the current-voltage (I-V) characteristics of the state shown in FIG. 4A. FIG. 4E shows the I-V characteristics of the state shown in FIG. 4B. FIG. 4F shows the I-V characteristics of the state shown in FIG. 4C. FIG. 5 shows the effect of the method and configuration of the embodiment. In FIG. 4A to FIG. C, a sample having the same layer structure as FIG. 3 is fabricated. GaN is used as the group III compound semiconductor, and Si is added as a donor impurity and Mg is added as an acceptor impurity. As shown in FIG. 4A, the electrode 15 is formed of ITO, and a metal electrode electrically connected to the n-GaN is provided to measure the I-V characteristics. As shown in FIG. 4D, when the applied voltage was gradually increased in a state without RIE, that is, in a state where an ITO layer was formed on a semiconductor laminate 200 (see FIG. 2A), a current began to flow at 2.7V.

[0029] As shown in Figure 4B, a shallow recess was formed by RIE in the stack including the ITO layer, reaching from the ITO surface to halfway through the p-GaN. In this state, the interface between the p-GaN and the undoped i-GaN was not exposed. The current-voltage characteristics were measured without any wet treatment after RIE. As shown in Figure 4E, when the applied voltage was gradually increased, current began to flow at 2.7 V, the same as without RIE.

[0030] As shown in Figure 4C, a groove was formed by RIE in a laminate including an ITO layer, reaching from the ITO surface to halfway through the i-GaN, and the current-voltage characteristics were measured without wet processing. In this state, the interface between p-GaN and undoped i-GaN is exposed on the side formed by RIE. As shown in Figure 4F, when the applied voltage was gradually increased, leakage current began to flow at 1.7 V, but no light emission was observed up to 2.7 V. The flow of current that does not contribute to light emission in this way reduces the WPE. Furthermore, the non-uniform flow of current causes uneven light emission and damage to the element.

[0031] In Figure 5, using the same layer structure as Figure 3, a groove was formed by RIE from the surface of the ITO layer to halfway through the i-GaN, and the side exposed by RIE was subjected to wet treatment. After that, it was left in an air atmosphere at room temperature for 13 hours. Two samples were used, and the current-voltage characteristics were measured for each sample before the wet treatment (labeled "Before WE" in the figure), immediately after the wet treatment (labeled "Immediately after WE" in the figure), and after being left in an air atmosphere for 13 hours (labeled "WE+13h left in the figure" in the figure).

[0032] In the sample before the wet processing, leakage current flows at a voltage of 1.7 V, as shown by the dotted line. This is the same as the current-voltage characteristics in Figure 4C when RIE is performed up to i-GaN and no wet processing is performed (see Figure 4F). In the sample after the wet processing, as shown by the dashed-dotted line, the current rise voltage is slightly higher than in the sample before the wet processing, but leakage current begins to flow at a voltage of 2 V or less.

[0033] In contrast, the current rise voltage of the sample left in the air after the wet treatment is improved to 2.7V. This is the same as the current-voltage characteristics (see FIGS. 4D and 4E) of the sample not subjected to RIE in FIG. 4A, or the sample only subjected to shallow RIE that does not penetrate the pn junction in FIG. 4B. It is considered that by removing miscellaneous crystals and damaged layers by the wet treatment to expose the crystal face (m-face) of GaN, and then placing it in an oxygen-containing atmosphere, the oxygen content increases near the exposed face, and the flow of carriers along the exposed face is reduced. The time of placing in the oxygen atmosphere is not limited to 13 hours, and may be any time that allows the side face (m-face) after the wet treatment to be naturally oxidized. The temperature of the oxygen-containing atmosphere may be controlled to be higher than room temperature. For example, the sample is left for a predetermined time at a temperature of room temperature or higher and lower than 475°C, preferably room temperature or higher and lower than 450°C, more preferably room temperature or higher and lower than 300°C, and even more preferably room temperature or higher and lower than 100°C. Since the degree of progress of natural oxidation varies depending on the temperature, the time of placing in the oxygen-containing atmosphere may be determined according to the set temperature. This can suppress leakage current in a semiconductor element including fine recesses and improve WPE. In particular, when the semiconductor element is a semiconductor laser element, it is preferable to set the temperature of the oxygen-containing atmosphere to be room temperature or higher and 100°C or lower, preferably room temperature or higher and 50°C or lower. This can reduce the possibility of the electrode 15 deteriorating and the possibility of affecting the characteristics of the semiconductor laser element. In addition, even if the temperature change from room temperature is small and the difference in linear expansion coefficient between the electrode 15 and the p-side Group III nitride semiconductor layer 13 is large, it can reduce the possibility of the electrode 15 peeling off.

[0034] <Second embodiment> 6 is a schematic diagram of a semiconductor device 10B of the second embodiment. The semiconductor device 10B has a semiconductor stack 14B including an n-side Group III nitride semiconductor layer 11B, a p-side Group III nitride semiconductor layer 13, and an active layer 22 disposed between the n-side Group III nitride semiconductor layer 11B and the p-side Group III nitride semiconductor layer 13, and an electrode 15 disposed on the p-side Group III nitride semiconductor layer 13. The semiconductor stack 14B has a side surface 17B that extends from the surface of the p-side Group III nitride semiconductor layer 13 to at least halfway through the n-side Group III nitride semiconductor layer 11B. The side surface 17B and the surface region 19 have a higher oxygen content than the inner region. This results in a semiconductor device with reduced leakage current from the side surface.

[0035] The materials, compositions, etc. of the p-side III-nitride semiconductor layer 13 and the n-side III-nitride semiconductor layer 11B are the same as those of the first embodiment. The active layer 22 has a quantum well structure having one or more well layers and multiple barrier layers formed of III-nitride semiconductors, for example. The quantum well may be a single quantum well or multiple quantum wells. The materials, compositions, film thicknesses, number of repetitions, etc. of the well layers and barrier layers of the active layer 22 are designed so that the active layer 22 emits light having a peak in a predetermined wavelength band, for example, in the range of 200 nm to 1600 nm. The active layer 22 may be designed to have a peak in a predetermined wavelength band, in the range of 360 nm to 700 nm, using AlGaN, GaN, InGaN, etc.

[0036] As in the first embodiment, the n-side III-nitride semiconductor layer 11B may include one or more layers including a contact layer, a cladding layer, an optical guide layer, etc. The p-side III-nitride semiconductor layer 13 may include one or more layers including a contact layer, a cladding layer, an optical guide layer, etc. The electrode 15 is preferably made of a light-transmitting metal oxide. This can reduce unnecessary light absorption by the electrode 15 and increase the light emission efficiency. In addition, by controlling the refractive index of the electrode 15, the design of the optical waveguide can be made easier.

[0037] In the semiconductor device 10B, the side surface 17B of the semiconductor laminate 14B reaches halfway through the n-side III nitride semiconductor layer 11B and penetrates the interface between the active layer 22 and the n-side III nitride semiconductor layer 11B. Generally, leakage current at the side surface 17B penetrating the pn junction is a problem, but the oxygen content of the side surface 17B and the surface region 19 is made higher than that of the inside of the semiconductor laminate 14B to suppress the leakage current at the side surface 17B. The side surface 17B of the semiconductor laminate 14B is located inside the outer periphery 151 of the electrode 15. This is due to the wet treatment performed after the semiconductor laminate 14B is processed by dry etching, and a slight step 153 is generated at the lower end of the electrode 15. The wet treatment removes the damaged layer on the exposed surface exposed by dry etching, and the m-plane of the III nitride semiconductor crystal is exposed on the side surface 17B. The structure after the wet processing is placed in an oxygen-containing atmosphere for a predetermined time, whereby side surfaces 17B and surface regions 19 having a higher oxygen content than the inner region of semiconductor laminate 14B are formed.

[0038] The semiconductor device 10B is fabricated by the following steps. First, a stack is prepared, which includes a semiconductor stack 14B having an n-side group III nitride semiconductor layer 11B, a p-side group III nitride semiconductor layer 13, and an active layer 22 disposed between the n-side group III nitride semiconductor layer 11B and the p-side group III nitride semiconductor layer 13, and an electrode layer disposed on the p-side group III nitride semiconductor layer. Dry etching is performed from the surface of the electrode layer to at least the middle of the n-side group III nitride semiconductor layer 11B. This dry etching forms a ridge 25B including the p-side group III nitride semiconductor layer 13, the active layer 22, and a part of the n-side group III nitride semiconductor layer 11B. The side surface 17B of the ridge 25 is cleaned by wet processing, and the wet-processed surface is oxidized.

[0039] When a transparent metal oxide is used for the electrode layer, the electrode layer and the semiconductor laminate 14B may be processed by RIE using a common mask. This provides the electrode 15 and the ridge 25 including the pn junction. When the semiconductor device 10B is used as a semiconductor laser, the ridge 25 extends in the Z direction, which is the resonance direction, and the side surface 17B becomes the side wall of the ridge. The width of the ridge 25 is, for example, the width that forms a lateral single mode waveguide. A relatively narrow waveguide width is required to form a lateral single mode waveguide, and it may be difficult to ensure a contact area between the electrode 15 and the p-side III nitride semiconductor layer 13. With the above-mentioned configuration, the width of the electrode 15 can be made larger than the width of the p-side III nitride semiconductor layer 13, and a sufficient contact area can be obtained. This reduces the contact resistance and allows efficient current injection. The width that forms the lateral single mode waveguide may be, for example, 0.5 μm or more and 1.5 μm or less.

[0040] The layer structure of the second embodiment may be provided with the periodic structure shown in Fig. 3. In this case, the semiconductor device 10B has periodic recesses along the resonance direction (Z direction) that reach partway through the n-side III nitride semiconductor layer 11B, and the inner walls of the recesses serve as side walls. After the wet processing, the semiconductor device is placed in an oxygen-containing atmosphere for a predetermined time, thereby increasing the oxygen content in the surface regions of the inner walls of the minute recesses and reducing the leakage current.

[0041] 7 is a schematic diagram of a semiconductor device 10C as a modification of the second embodiment. The semiconductor device 10C in the diagram of the modification is used as a ridge-type semiconductor laser. The semiconductor device 10C includes a semiconductor stack 14C using Group III nitrides and an electrode 15 provided on the upper surface of the semiconductor stack 14C. The semiconductor stack 14C includes an n-side Group III nitride semiconductor layer 11C, a p-side Group III nitride semiconductor layer 13C, and an active layer 22 disposed between the n-side Group III nitride semiconductor layer 11C and the p-side Group III nitride semiconductor layer 13C.

[0042] The n-side III nitride semiconductor layer 11C includes an n-side contact layer 111, an n-side cladding layer 112, and an n-side guide layer 113. The p-side III nitride semiconductor layer 13C includes a p-side guide layer 131 and a p-side contact layer 132. A light-transmitting metal oxide electrode 15 is provided on the p-side contact layer 132. The semiconductor device 10C has a ridge 25C including from the surface of the p-side contact layer 132 to a middle of the n-side cladding layer 112, and a side surface 17C of the ridge 25C penetrates the pn junction, i.e., the interface between the p-side guide layer 131 and the active layer 22.

[0043] 7, a common mask can also be used to dry etch from the electrode 15 to partway through the n-side cladding layer 112. After the dry etching, the side surface 17C of the ridge 25C is cleaned by wet processing, so that the side surface 17C is recessed slightly inward from the outer periphery of the electrode 15. Then, by placing the semiconductor laminate 14C in an oxygen-containing atmosphere for a predetermined time, a surface region 19 having a higher oxygen content than the inner region of the semiconductor laminate 14C is obtained. The surface region 19 can reduce the leakage current at the side surface 17C that penetrates the pn junction.

[0044] <Third embodiment> 8A and 8B are diagrams showing the steps of manufacturing a semiconductor device 10D according to the third embodiment. The semiconductor device 10D according to the third embodiment has an undoped group III nitride semiconductor layer 120D and an active layer 22 between a p-side group III nitride semiconductor layer 130D and an n-side group III nitride semiconductor layer 110D. The undoped group III nitride semiconductor layer 120D is located between the p-side group III nitride semiconductor layer 130D and the active layer 22. In FIG. 8A, a stack 200D is prepared, which includes a group III nitride semiconductor stack 140D and an electrode layer 150 disposed on the semiconductor stack 140D. The semiconductor stack 140D is formed by vapor phase growth such as MOCVD or PVD. The electrode layer 150 is formed of a transparent metal oxide on the surface of the semiconductor stack 140D.

[0045] The semiconductor laminate 140D includes an n-side group III nitride semiconductor layer 110D, a p-side group III nitride semiconductor layer 130D, an undoped group III nitride semiconductor layer 120D disposed between the n-side group III nitride semiconductor layer 110D and the p-side group III nitride semiconductor layer 130D, and an active layer 22 disposed between the undoped group III nitride semiconductor layer 120D and the n-side group III nitride semiconductor layer 110D. The n-side group III nitride semiconductor layer 110D includes an n-side contact layer 111, an n-side cladding layer 112, and an n-side guide layer 113. The p-side group III nitride semiconductor layer 130D includes an electron block layer 133, a p-side guide layer 131, and a p-side contact layer 132.

[0046] The active layer 22 is formed of, for example, a single quantum well or multiple quantum wells. Impurities may be added to the barrier layers constituting the quantum wells. The undoped III-nitride semiconductor layer 120D has a barrier layer 121. The barrier layer 121 is not intentionally doped with impurities during the film formation process. The barrier layer 121 may be provided as a last barrier of the active layer 22.

[0047] In FIG. 8B, the laminate 200D is processed by a dry process to form a side surface 17D that reaches at least halfway through the barrier layer 121. As shown in FIG. 2A, the electrode layer 150 and a part of the semiconductor laminate 140D may be RIE-processed using a common mask. By RIE, the electrode 15 having a predetermined shape, the p-side group III nitride semiconductor layer 13D, and the undoped group III nitride semiconductor layer 12D are obtained. The n-side group III nitride semiconductor layer 110D in FIG. 8A is used as the n-side group III nitride semiconductor layer 11D of the semiconductor device 10D in FIG. 8B. In this state, the side surface 17D that reaches at least halfway through the barrier layer 121 is exposed from the surface of the p-side group III nitride semiconductor layer 13D. The barrier layer 121 becomes the undoped group III nitride semiconductor layer 12D. By cleaning the exposed side surface 17D by wet processing, the damaged layer on the exposed surface is removed, and the side surface 17D is recessed slightly inward from the outer periphery of the electrode 15.

[0048] After the wet treatment, the entire structure is placed in an oxygen-containing atmosphere for a predetermined time, so that the oxygen content in the side surface 17D and the surface region 19 becomes higher than that in the internal region. Finally, an n-side electrode electrically connected to the n-side contact layer 111 is provided to obtain the semiconductor device 10D. The semiconductor device 10D functions as a ridge-type semiconductor laser. The width of the ridge formed by the p-side group III nitride semiconductor layer 13D and a part of the undoped group III nitride semiconductor layer 12D is, for example, a width that defines a lateral single-mode waveguide.

[0049] During operation of semiconductor device 10D, free electrons may diffuse into barrier layer 121, but surface region 19 reduces leakage current along side 17D in semiconductor device 10D, improving WPE.

[0050] Although the above description has been based on a specific configuration example, the present disclosure is not limited to the above-mentioned configuration example. Each embodiment or modification can be combined with each other. For example, periodic recesses that reach halfway through the undoped III-nitride semiconductor layer 12D may be provided along the resonance direction (Z direction) of the semiconductor device 10D in FIG. 8B. This can reduce the leakage current along the side surface that penetrates the pn junction.

[0051] Embodiments of the present disclosure may include, for example, the following configurations. (Section 1) preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the undoped III-nitride semiconductor layer from a surface of the electrode layer to at least a portion of the undoped III-nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; A method for manufacturing a semiconductor device, comprising: (Section 2) The wet treatment is surface cleaning using an alkaline etchant. Item 1. A method for manufacturing a semiconductor device according to item 1. (Section 3) the m-plane of the Group III nitride semiconductor crystal is exposed by the wet treatment; Item 1 or 2. A method for producing a semiconductor device according to item 1 or 2. (Section 4) The oxidation step includes leaving the structure after the wet treatment in an atmosphere containing oxygen for a predetermined period of time. Item 4. A method for manufacturing a semiconductor device according to any one of items 1 to 3. (Section 5) The electrode layer is formed of a light-transmitting metal oxide, In the dry etching, a common mask is used to etch from the surface of the electrode layer to at least a portion of the undoped Group III nitride semiconductor layer. Item 5. A method for manufacturing a semiconductor device according to any one of items 1 to 4. (Section 6) the stacked body includes an active layer or a light absorbing layer disposed between the n-side Group III nitride semiconductor layer and the undoped Group III nitride semiconductor layer, The dry etching forms a ridge structure of a laser resonator, periodic recesses of the laser resonator, or pixel separation grooves of a light receiving element. Item 6. A method for manufacturing a semiconductor device according to any one of items 1 to 5. (Section 7) The semiconductor element is a semiconductor laser element, The oxidation step includes leaving the structure after the wet treatment in an oxygen-containing atmosphere at a temperature of 100° C. or less for a predetermined period of time. Item 7. A method for producing a semiconductor element according to item 6. (Section 8) preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the n-side Group III nitride semiconductor layer from a surface of the electrode layer to at least a portion of the n-side Group III nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; A method for manufacturing a semiconductor device, comprising: (Section 9) a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the undoped Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region located inside the surface region. Semiconductor element. (Section 10) The side surface of the semiconductor laminate is located inside the outer periphery of the electrode. Item 10. The semiconductor element according to item 9. (Section 11) a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the n-side Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region located inside the surface region. Semiconductor element. (Section 12) the semiconductor laminate has a ridge extending in a resonance direction, the side surface being a ridge side surface, The width of the ridge is a width that forms a lateral single mode waveguide. Item 12. The semiconductor element according to item 11. (Section 13) The semiconductor laminate has periodic recesses, and the side surface is an inner wall of the recesses. Item 12. The semiconductor element according to item 11. (Section 14) The side surface of the semiconductor laminate is located inside the outer periphery of the electrode. Item 14. The semiconductor element according to any one of items 11 to 13. (Section 15) The electrode includes a light-transmitting metal oxide. Item 14. The semiconductor element according to any one of items 11 to 13. [Explanation of symbols]

[0052] 10, 10A, 10B, 10C, 10D Semiconductor elements 11, 11B, 11C, 11D n-side group III nitride semiconductor layer 12, 12D Undoped III-nitride semiconductor layer 13, 13C, 13C p-side III-nitride semiconductor layer 14, 14B, 14C Semiconductor laminate 15 electrodes 17, 17B, 17C, 17D side 19 Surface area 25, 25C Ridge 150 electrode layer 200, 200D laminate

Claims

1. preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the undoped III-nitride semiconductor layer from a surface of the electrode layer to at least a portion of the undoped III-nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; A method for manufacturing a semiconductor device, comprising:

2. The wet treatment is surface cleaning using an alkaline etchant. The method for manufacturing a semiconductor device according to claim 1 .

3. the m-plane of the Group III nitride semiconductor crystal is exposed by the wet treatment; The method for manufacturing a semiconductor device according to claim 1 .

4. The oxidation step includes leaving the structure after the wet treatment in an atmosphere containing oxygen for a predetermined period of time. The method for manufacturing a semiconductor device according to claim 1 .

5. The electrode layer is formed of a light-transmitting metal oxide, In the dry etching, a common mask is used to etch from the surface of the electrode layer to at least a portion of the undoped Group III nitride semiconductor layer. The method for manufacturing a semiconductor device according to claim 1 .

6. the stacked body includes an active layer or a light absorbing layer disposed between the n-side Group III nitride semiconductor layer and the undoped Group III nitride semiconductor layer, The dry etching forms a ridge structure of a laser resonator, periodic recesses of the laser resonator, or pixel separation grooves of a light receiving element. The method for manufacturing a semiconductor device according to claim 1 .

7. The semiconductor element is a semiconductor laser element, The oxidation step includes leaving the material in an oxygen-containing atmosphere at a temperature of 100° C. or less for a predetermined period of time. The method for manufacturing a semiconductor device according to claim 6 .

8. preparing a semiconductor stack having an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer, and an electrode layer disposed on the p-side Group III nitride semiconductor layer; dry etching a portion of the n-side Group III nitride semiconductor layer from a surface of the electrode layer to at least a portion of the n-side Group III nitride semiconductor layer; cleaning the exposed surface of the laminate exposed by the dry etching with a wet process; oxidizing the wet-treated surface; A method for manufacturing a semiconductor device, comprising:

9. a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an undoped Group III nitride semiconductor layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the undoped Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region located inside the surface region. Semiconductor element.

10. The side surface of the semiconductor laminate is located inside the outer periphery of the electrode. The semiconductor device according to claim 9.

11. a semiconductor laminate including an n-side Group III nitride semiconductor layer, a p-side Group III nitride semiconductor layer, and an active layer disposed between the n-side Group III nitride semiconductor layer and the p-side Group III nitride semiconductor layer; an electrode disposed on the p-side Group III nitride semiconductor layer; Equipped with the semiconductor laminate has a side surface that extends from a surface of the p-side Group III nitride semiconductor layer to at least a portion of the n-side Group III nitride semiconductor layer, The side surface and a surface region up to a predetermined distance from the side surface have a higher oxygen content than an internal region located inside the surface region. Semiconductor element.

12. the semiconductor laminate has a ridge extending in a resonance direction, the side surface being a ridge side surface, The width of the ridge is a width that forms a lateral single mode waveguide. The semiconductor device according to claim 11.

13. The semiconductor laminate has periodic recesses, and the side surface is an inner wall of the recesses. The semiconductor device according to claim 11.

14. The side surface of the semiconductor laminate is located inside the outer periphery of the electrode. The semiconductor device according to any one of claims 11 to 13.

15. The electrode includes a light-transmitting metal oxide. The semiconductor device according to any one of claims 11 to 13.

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