Semiconductor device

Abstract

To provide a semiconductor device including a boost circuit that generates a high voltage capable of testing.SOLUTION: A semiconductor device 11 is a switching device 19 including a first switching circuit 19b, in which the first switching circuit 19b includes: a switching device including MIS transistors 27c and 27d connected in series from the first terminal to the second terminal; a boost circuit 13 capable of generating a plurality of boost voltages from a power supply voltage; an inner line 36 connected to the second terminal of the first switching circuit 19b; an electrode 15 connected to the first terminal of the first switching circuit 19b via an external line; a first level shift circuit 21b connected to the boost circuit 13, which makes the first switching circuit 19b conductive in a voltage application mode and makes the first switching circuit 19b non-conductive in an internal boost mode and a monitor mode; and a well voltage generating circuit 23 for supplying a well voltage to a back gate of the MIS transistor 27c of the first switching circuit 29b.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a test operation of a semiconductor device including an internal boost circuit that generates a high voltage. [Background technology]

[0002] Patent Document 1 discloses a multi-step pulse generating circuit for a flash memory device, which simplifies the circuit configuration and reduces the area of ​​the element by fixing the high voltage generated by a positive charge pump circuit and varying the potential of a reference voltage compared with the high voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-159283 A Summary of the Invention [Problem to be solved by the invention]

[0004] An electrically rewritable non-volatile memory requires a high voltage for rewriting, specifically, a voltage higher than the operating voltage of a normal semiconductor device. In a user's environment, this high voltage is generated by an internal boost circuit. However, in manufacturing such a semiconductor device, the manufacturer wants to inspect the electrical characteristics of the non-volatile memory and the characteristics of the internal boost circuit, such as a charge pump. Specifically, inspecting the characteristics of the internal boost circuit includes checking the boost voltage of the charge pump, and inspecting the electrical characteristics of the non-volatile memory includes changing the stored contents of the non-volatile memory using the charge pump or a voltage applied from the outside.

[0005] An object of the present invention is to provide a semiconductor device including a boost circuit that generates a high voltage, which enables a test operation. [Means for solving the problem]

[0006] A semiconductor device according to a first aspect of the present invention is a semiconductor device having an internal boost mode, a monitor mode, and a voltage application mode, the semiconductor device comprising: a switch including one or a plurality of switch circuits, each of the switch circuits including a first terminal and a second terminal, and a first MIS transistor and a second MIS transistor connected in series in a direction from the first terminal to the second terminal, a back gate of the second MIS transistor being connected to a first shared node of the first MIS transistor and the second MIS transistor connected in series, the switch including a first switch circuit as one of the switch circuits; and a boost circuit capable of generating a plurality of boost voltages from a power supply voltage (VDC15), the plurality of boost voltages including a first boost voltage (VPP) and one or a plurality of intermediate boost voltages, the first boost voltage being provided from a first output of the boost circuit, an absolute value of the first boost voltage (VPP) being greater than an absolute value of the intermediate boost voltage and an absolute value of the power supply voltage (VDC15). a boost circuit, the absolute value of which is less than the absolute value of the first boost voltage (VPP) and the absolute value of the intermediate boost voltage; an internal line connected to the second terminal of the first switch circuit; a first level shift circuit connected to the first terminal of the boost circuit via a first line and configured to supply the intermediate boost voltage to a gate of the first MIS transistor of the first switch circuit in the voltage application mode and to supply the first boost voltage in the internal boost mode and the monitor mode; a well voltage generation circuit connected to the boost circuit and having an output configured to provide a well voltage to a back gate of the first MIS transistor of the first switch circuit via a well line; and a third MIS transistor having an electrode connected to an external line, a gate configured to receive the intermediate boost voltage, a back gate and a source connected to the first terminal of the first switch circuit, and a drain connected to the external line. Effect of the Invention

[0007] According to the above aspect, it is possible to perform a test operation in a semiconductor device including a boost circuit that generates a high voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a semiconductor device according to the present embodiment. [Diagram 2] FIG. 2 is a diagram showing a switch circuit of the semiconductor device according to this embodiment. [Diagram 3] FIG. 3 is a diagram showing a level shifter of the semiconductor device according to this embodiment. [Figure 4] FIG. 4 is a diagram illustrating a schematic connection of the switch circuit of the semiconductor device according to the present embodiment. [Diagram 5] FIG. 5 is a diagram illustrating an operation of the semiconductor device according to the present embodiment in a voltage application mode. [Figure 6] FIG. 6 is a diagram illustrating an outline of the operation of the semiconductor device according to the present embodiment in the monitor mode. [Figure 7] FIG. 7 is a diagram illustrating an operation of the semiconductor device according to this embodiment in the internal boost mode. [Figure 8] FIG. 8 is a diagram showing circuit connections in the semiconductor device according to this embodiment. [Figure 9] FIG. 9 is a diagram showing a circuit similar to the switch circuit of the semiconductor device according to this embodiment. [Figure 10] FIG. 10 is a diagram showing the relationship between five potential levels, the first boosted voltage VPP, the second boosted voltage VPPMH, the third boosted voltage VPPML, the power supply voltage VDC15, and the ground potential (0 volts). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. In the following description, identical or similar parts will be marked with "similar" and duplicated description will be omitted.

[0010] Fig. 1 is a block diagram showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Fig. 2 is a diagram showing a switch circuit of the semiconductor device according to an embodiment of the present invention. Fig. 3 is a diagram showing a level shifter of the semiconductor device according to an embodiment of the present invention.

[0011] The semiconductor device 11 includes an internal boost circuit 13, which is called a charge pump, and an electrically rewritable non-volatile memory 17. The non-volatile memory 17 may include a semiconductor memory element such as a flash memory, an EPROM, or an EEPROM. The semiconductor device 11 may also include electrodes 15, such as electrode pads, a switch 19, a level shifter 21, and a well voltage generating circuit 23. The semiconductor device 11 further includes a control circuit 30 that controls an operation mode.

[0012] When the monitor mode and / or the voltage application mode are additionally provided to the semiconductor device 11, these additional modes should not interfere with the internal boost mode. Specifically, when the monitor mode is provided, this should be done so as not to interfere with the internal boost mode. When the voltage application mode is provided, this should be done so as not to interfere with the internal boost mode. In order to avoid the mutual interference, for example, the semiconductor device 11 of the present disclosure is used.

[0013] The boost circuit 13 is configured to generate a first boosted voltage (VPP) and one or more intermediate boosted voltages from a power supply voltage (VDC15). Specifically, the boost circuit 13 can generate a first boosted voltage (VPP), a second boosted voltage (VPPMH), and a third boosted voltage (VPPML). The first boosted voltage (VPP), the second boosted voltage (VPPMH), and the third boosted voltage (VPPML) are provided to a first output, a second output, and a third output of the boost circuit 13, respectively. These voltages are supplied via a supply line. Here, the absolute value of the first boosted voltage (VPP) is greater than the absolute value of the second boosted voltage (VPPMH). The absolute value of the second boosted voltage (VPPMH) is greater than the absolute value of the third boosted voltage (VPPML). The absolute value of the third boosted voltage (VPPML) is greater than the absolute value of the power supply voltage. The term "high voltage" refers to both positive and negative voltages. The first boost voltage (VPP), the second boost voltage (VPPMH), the third boost voltage (VPPML), and the power supply voltage (VDC15) are connected to a first line 31, a second line 32, a third line 33, and a fourth line 34, respectively.

[0014] An exemplary boost circuit 13 includes a series and / or parallel connection of one or more capacitors and one or more MIS transistors.

[0015] The boost circuit 13 operates, for example, to power the electrically rewritable non-volatile memory 17 connected to the internal line 36. In the following description, the exemplary boost circuit 13 generates a positive high voltage.

[0016] The level shifter 21 is configured to control the opening and closing of the switch 19 .

[0017] The semiconductor device 11 further includes a control circuit 30. The control circuit 30 is configured to generate signals that define at least the following modes, specifically, an internal boost mode, a monitor mode, and a voltage application mode, in the semiconductor device 11, and to operate the boost circuit 13 in these modes.

[0018] In the internal boost mode, a signal (H) is applied to the logic input TEST_INT, and a signal (L) is applied to the logic input TEST_MON. These signals cause the logic input TEST_EXT to become a signal (L). In this mode, the internal boost circuit 13 is operated, and no voltage is applied from the outside to the electrode 15. The control circuit 30 also controls the boost circuit 13 to operate in the internal boost mode, the monitor mode, and the voltage application mode.

[0019] In the monitor mode, the output voltage of the internal boost circuit 13 is monitored. In this case, a signal (L) is applied to the logic input TEST_INT, and a signal (H) is applied to the logic input TEST_MON. These signals cause the logic input TEST_EXT to become a signal (L). In this mode, the internal boost circuit 13 is operated, and the output voltage of the boost circuit 13 is monitored at the electrode 15.

[0020] In the voltage application mode, a signal (L) is applied to the logic input TEST_INT and a signal (L) is applied to the logic input TEST_MON. These signals cause the logic input TEST_EXT to become a signal (H). In this mode, the internal boost circuit 13 is operated and a voltage is applied to the electrode 15 from the outside.

[0021] Specifically, the semiconductor device 11 can have, for example, an internal boost mode, a monitor mode, and a voltage application mode. In the internal boost mode, the memory contents of the nonvolatile memory 17 are changed by power supply from the boost circuit 13. The change in memory contents is performed as an operation such as writing or erasing. In the monitor mode, the boost voltage of the boost circuit 13 is output to the electrode 15, and the voltage of the electrode 15 is measured using an external device. In the voltage application mode, an external voltage is applied to the electrode 15 from a tester or an external power source to change the memory contents of the nonvolatile memory 17 or perform other operations. These modes are examples, and the present disclosure is not limited to the semiconductor device 11 providing all of these modes, specifically the internal boost mode, the monitor mode, and the voltage application mode, and any one or more of these modes can be provided.

[0022] The exemplary semiconductor device 11 can be constructed using complementary MIS transistors, with a p-type MIS transistor and an n-type MIS transistor each having a source (S), a drain (D), a gate (G), and a back gate (B). While "S", "D", "G", and "B" are attached to the electrodes of the transistor symbols in the drawings, "S" and "D" do not specify the direction of current flow, but should be understood as merely identifying electrodes to identify the connections of the transistors.

[0023] In the exemplary semiconductor device 11, the p-type MIS transistor is formed in an N-well, and the back gate (B) of the p-type MIS transistor is the N-well. Specifically, a p-type MIS transistor can be given its own dedicated N-well by providing a separate N-well for the p-type MIS transistor.

[0024] The well voltage generation circuit 23 outputs a first boost voltage (VPP) to the well line WELL. Specifically, the well voltage generation circuit 23 supplies the first boost voltage (VPP) as a well voltage to the N wells of some p-type MIS transistors of the switch 19 and the level shifter 21. The first boost voltage (VPP) is a voltage greater than the second boost voltage (VPPMH) and the third boost voltage (VPPML), and prevents the N well from being forward biased with respect to the source (S) and drain (D) of the p-type transistor.

[0025] The switch 19 may include one or more switch circuits 27 as shown in FIG.

[0026] In the switch 19, each of the switch circuits 27 includes a first terminal 27b, a second terminal 27c, a first MIS transistor 27d, and a second MIS transistor 27e. The first MIS transistor 27d and the second MIS transistor 27e are connected in series from the first terminal 27b to the second terminal 27c. A back gate (B) of the second MIS transistor 27e is connected to a first shared node SN1 of the first MIS transistor 27d and the second MIS transistor 27e connected in series. In the switch circuit 27, the back gate (B) of the first MIS transistor 27d receives a first boost voltage (VPP) from the well voltage generating circuit 23. A gate (G) of the second MIS transistor 27e receives a third boost voltage (VPPML) from the boost circuit 13. The switch circuit 27 may further include a third terminal 27f connected to the gate (G) of the first MIS transistor 27d.

[0027] The level shifter 21 may include one or more level shift circuits 29, as shown in Fig. 3. The level shift circuit 29 receives a first boost voltage (VPP), a second boost voltage (VPPMH), a third boost voltage (VPPML), and a power supply voltage (VDC15) via a first line 31, a second line 32, a third line 33, and a fourth line 34. The level shift circuit 29 has a mode terminal 29b for receiving a mode signal MODE that defines the operation of the level shift circuit 29. The level shift circuit 29 has an output 29c for providing an output signal LVSOUT in response to the mode signal MODE. The high level of the output signal LVSOUT may be the first boost voltage (VPP), and the low level of the output signal LVSOUT may be, for example, the third boost voltage (VPPML).

[0028] 4 is a diagram showing a schematic connection of a switch circuit of the semiconductor device according to the present embodiment. In the semiconductor device 11, the electrode 15 is connected to a fifth line 35 (external line). The non-volatile memory 17 is connected to an internal line 36.

[0029] The exemplary switch 19 may include a first switch circuit 19b, a second switch circuit 19c, and a third switch circuit 19d as the switch circuits 27. The first switch circuit 19b is connected between the fifth line 35 and the internal line 36. The second switch circuit 19c is connected between the first line 31 and the fifth line 35. The third switch circuit 19d is connected between the internal line 36 and the first line 31.

[0030] Specifically, the first terminal 27b of the first switch circuit 19b is connected to the fifth line 35 via the third MIS transistor 41. The second terminal 27c of the first switch circuit 19b is connected to the internal line 36. The first terminal 27b of the second switch circuit 19c is connected to the first line 31. The second terminal 27c of the second switch circuit 19c is connected to the fifth line 35. The first terminal 27b of the third switch circuit 19d is connected to the first line 31. The second terminal 27c of the second switch circuit 19c is connected to the internal line 36.

[0031] An exemplary level shifter 21 may include a first level shift circuit 21b, a second level shift circuit 21c, and a third level shift circuit 21d, as shown in Figures 1 and 3. The first level shift circuit 21b, the second level shift circuit 21c, and the third level shift circuit 21d control the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d, respectively. The first level shift circuit 21b, the second level shift circuit 21c, and the third level shift circuit 21d generate a first control signal Sn5, a second control signal Sn1, and a third control signal Sn1, respectively, as shown in Figure 1.

[0032] In this embodiment, each of the first level shift circuit 21b, the second level shift circuit 21c, and the third level shift circuit 21d may have the circuit structure of the level shift circuit 29, and performs an operation of changing the voltage level in response to a mode signal MODE received at a mode terminal 29b. Therefore, each of the first control signal Sn5, the second control signal Sn1, and the third control signal Sn1 may have the first boost voltage (VPP) as a high level (H) and the third boost voltage (VPPML) as a low level (L).

[0033] The relationship between the level shift circuit 29 and the operation modes is as follows. Operation modes: voltage application mode, monitor mode, internal boost mode First level shift circuit 21b: L, H, H Second level shift circuit 21c: H, L, H Third level shift circuit 21d: H, H, L

[0034] The first MIS transistor 27d in each of the switch circuits 19b, 19c, and 19d becomes conductive when receiving a low level, and becomes non-conductive when receiving a high level.

[0035] The exemplary semiconductor device 11 may include a third MIS transistor 41. The third MIS transistor 41 has a gate (G) connected to the third line 33, a back gate (B) and a source (S) connected to the first terminal 27b of the first switch circuit 19b, and a drain (D) connected to the fifth line 35.

[0036] The exemplary semiconductor device 11 further includes a mitigation circuit 43, which may include a fourth MIS transistor 45. The fourth MIS transistor 45 has a gate (G) and a drain (D) connected to the first terminal 27b of the first switch circuit 19b, and a source (S) connected to the third line 33. A back gate (B) of the fourth MIS transistor 45 is connected to the well line WELL. A drain (D) of the fourth MIS transistor 45 is connected to the back gate (B) and the source (S) of the third MIS transistor 41.

[0037] The fourth MIS transistor 45 is so-called diode-connected. A back gate (B) of the fourth MIS transistor 45 receives a first boost voltage (VPP) from the well voltage generating circuit 23. A source (S) of the fourth MIS transistor 45 is connected to the third line 33 and receives a third boost voltage (VPPML). When the gate (G) and drain (D) of the fourth MIS transistor 45 are not supplied with power from the fifth line 35 via the third MIS transistor 41, the fourth MIS transistor 45 supplies power to the first terminal 27b of the first switch circuit 19b and the back gate (B) and source (S) of the third MIS transistor 41.

[0038] The operation of the level shifter 21 and the switch 19 shown in FIG. 1 is as follows.

[0039] In the internal boost mode (logic input TEST_INT:H, logic input TEST_MON:L, logic input TEST_EXT:L), the first level shift circuit 21b provides the first boost voltage VPP to the output n5. The second level shift circuit 21c provides the first boost voltage VPP to the output n1. The third level shift circuit 21d provides the third boost voltage VPPML to the output n3.

[0040] The first MIS transistor 27d of the first switch circuit 19b enters a weak inversion region in response to the first boost voltage VPP on its gate (G). The first MIS transistor 27d of the second switch circuit 19c enters a weak inversion region in response to the first boost voltage VPP on its gate (G). The first MIS transistor 27d of the third switch circuit 19d enters a strong inversion region in response to the third boost voltage VPPML on its gate (G).

[0041] In the voltage application mode (logic input TEST_INT: L, logic input TEST_MON: L, logic input TEST_EXT: H), the first level shift circuit 21b provides the third boost voltage VPPML to the output n5. The second level shift circuit 21c provides the first boost voltage VPP to the output n1. The third level shift circuit 21d provides the first boost voltage VPP to the output n3.

[0042] The first MIS transistor 27d of the first switch circuit 19b enters a strong inversion region in response to the third boost voltage VPPML on its gate (G). The first MIS transistor 27d of the second switch circuit 19c enters a weak inversion region in response to the first boost voltage VPP on its gate (G). The first MIS transistor 27d of the third switch circuit 19d enters a weak inversion region in response to the first boost voltage VPP on its gate (G).

[0043] In the monitor mode (logic input TEST_INT: L, logic input TEST_MON: H, logic input TEST_EXT: L), the first level shift circuit 21b provides the first boosted voltage VPP to the output n5. The second level shift circuit 21c provides the third boosted voltage VPPML to the output n1. The third level shift circuit 21d provides the first boosted voltage VPP to the output n3.

[0044] The first MIS transistor 27d of the first switch circuit 19b enters a weak inversion region in response to the first boost voltage VPP on its gate (G). The first MIS transistor 27d of the second switch circuit 19c enters a strong inversion region in response to the third boost voltage VPPML on its gate (G). The first MIS transistor 27d of the third switch circuit 19d enters a weak inversion region in response to the first boost voltage VPP on its gate (G).

[0045] 5 is a diagram illustrating the operation of the semiconductor device according to the present embodiment in a voltage application mode. In FIG. 5, the voltage propagation (arrow ARW1) in the voltage application mode and the voltages of the main nodes are shown. In the voltage application mode, an external voltage VPP_EXT is applied to the electrode 15.

[0046] The external voltage VPP_EXT may be a value not exceeding the first boost voltage VPP. The external voltage VPP_EXT is in a range lower than the first boost voltage VPP and higher than the potential obtained by adding the absolute value of the threshold voltage VTP of the P-type MIS transistor to the third boost voltage VPPML. After the desired first boost voltage VPP is achieved by the operation of the boost circuit 13, the external application is performed, and after the external application is terminated, the operation of the boost circuit 13 is stopped. The external voltage VPP_EXT is applied to the internal line 36 via the first switch circuit 19b.

[0047] The first level shift circuit 21b supplies the third boost voltage (VPPML) to the gate (G) of the first MIS transistor 27d of the first switch circuit 19b in the voltage application mode. In response to this, the first MIS transistor 27d of the first switch circuit 19b is conductive. The second level shift circuit 21c supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the second switch circuit 19c in the voltage application mode. The first MIS transistor 27d of the second switch circuit 19c is non-conductive. The third level shift circuit 21d supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the third switch circuit 19d in the voltage application mode. The first MIS transistor 27d of the third switch circuit 19d is non-conductive.

[0048] The second MIS transistors 27e of the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d are turned on in response to the third boosted voltage (VPPML) applied to their gates (G). The voltage of the shared node SN1 of the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d becomes the external voltage VPP_EXT through the second MIS transistors 27e in each switch circuit.

[0049] The external voltage VPP_EXT is applied to the gate (G) and drain (D) of the fourth MIS transistor 45 of the mitigation circuit 43 via the third MIS transistor 41 .

[0050] The second switch circuit 19c prevents the external voltage VPP_EXT from being transmitted from the internal line 36 to the first line 31. The third switch circuit 19d prevents the external voltage VPP_EXT from being transmitted from the fifth line 35 to the first line 31.

[0051] The boost circuit 13 is operating, and the well voltage generation circuit 23 supplies the first boost voltage VPP to the well line WELL. In the first MIS transistor 27d of the first switch circuit 19b, the back gate (B) is not forward biased with respect to the source (S) of the external voltage VPP_EXT.

[0052] In the first MIS transistor 27d of the second switch circuit 19c and the third switch circuit 19d, the back gate (B) is not forward biased with respect to the drain (D) of the external voltage VPP_EXT.

[0053] According to the semiconductor device 11, in the first switch circuit 19b, the first MIS transistor 27d receives the third boost voltage (VPPML) from the first level shift circuit 21b at its gate (G) in the voltage application mode. The gate (G) of the second MIS transistor 27e of the first switch circuit 19b receives the third boost voltage (VPPML). In the voltage application mode, the first switch circuit 19b is made conductive by the control of the first level shift circuit. Also, the third MIS transistor 41 receives the third boost voltage (VPPML) on the third line 33 at its gate (G) and is made conductive. The third MIS transistor 41 and the first switch circuit 19b can supply the external voltage VPP_EXT applied to an electrode 15 such as a pad electrode to the internal line 36. On the other hand, the first MIS transistors 27d of the second switch circuit 19c and the third switch circuit 19d are controlled by the second level shift circuit 21c and the third level shift circuit 21d, respectively, and receive the first boost voltage (VPP) at their gates (G) in the voltage application mode. In the voltage application mode, the second switch circuit 19c and the third switch circuit 19d are non-conductive.

[0054] 6 is a diagram illustrating the operation of the semiconductor device according to the present embodiment in the monitor mode. In FIG. 6, the voltage propagation (arrow ARW2) in the monitor mode and the voltages of the main nodes are shown. In the monitor mode, the first boost voltage VPP from the boost circuit 13 is provided to the electrode 15 as the monitor voltage VPP_INT.

[0055] The first level shift circuit 21b supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the first switch circuit 19b in the monitor mode. The first MIS transistor 27d of the first switch circuit 19b is finally turned off. The second level shift circuit 21c supplies the third boost voltage (VPPML) to the gate (G) of the first MIS transistor 27d of the second switch circuit 19c in the monitor mode. In response to this, the first MIS transistor 27d of the second switch circuit 19c is turned on. The third level shift circuit 21d finally supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the third switch circuit 19d in the monitor mode, except for a transitional period. The first MIS transistor 27d of the third switch circuit 19d is finally turned off.

[0056] The first switch circuit 19b, the second switch circuit 19c, and the second MIS transistor 27e of the third switch circuit 19d are turned on in response to the application of the third boost voltage (VPPML) to their gates (G). The voltage of the shared node SN1 of the first switch circuit 19b and the third switch circuit 19d becomes equal to or higher than the third boost voltage (VPPML) due to the delay in turning off the first MIS transistor 27d in each switch circuit.

[0057] The monitor voltage VPP_INT is applied to the gate (G) and drain (D) of the fourth MIS transistor 45 of the mitigation circuit 43 via the third MIS transistor 41.

[0058] In the first switch circuit 19b, the first MIS transistor 27d is non-conductive, preventing the first boost voltage VPP from being transmitted from the fifth line 35 to the internal line 36. In the third switch circuit 19d, the first MIS transistor 27d is non-conductive, preventing the first boost voltage VPP from being transmitted from the first line 31 to the internal line 36. In the monitor mode, a voltage according to the operating conditions of the non-volatile memory 17 is applied to the internal line 36. An example of a voltage according to the operating conditions is a high impedance state.

[0059] The boost circuit 13 is operating, and the well voltage generation circuit 23 supplies the first boost voltage VPP to the well line WELL. In the first MIS transistor 27d and the fourth MIS transistor 45 of the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d, their back gates (B) receive the first boost voltage VPP.

[0060] The third MIS transistor 41 is conductive and transmits the monitor voltage VPP_INT from the fifth line 35 to the first terminal 27b of the first switch circuit 19b and to the mitigation circuit 43. The monitor voltage VPP_INT is also applied to the gate (G) and drain (D) of the fourth MIS transistor 45 of the mitigation circuit 43.

[0061] 7 is a diagram illustrating the operation of the semiconductor device according to this embodiment in the internal boost mode. In FIG. 7, the voltage propagation (arrow ARW3) in the internal boost mode and the voltages of the main nodes are shown. In the internal boost mode, the first boost voltage VPP from the boost circuit 13 is provided to the internal line 36.

[0062] The first level shift circuit 21b finally supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the first switch circuit 19b in the internal boost mode. The first MIS transistor 27d of the first switch circuit 19b is finally non-conductive. The second level shift circuit 21c finally supplies the first boost voltage (VPP) to the gate (G) of the first MIS transistor 27d of the second switch circuit 19c in the monitor mode. The first MIS transistor 27d of the second switch circuit 19c is finally non-conductive. The third level shift circuit 21d supplies the third boost voltage (VPPML) to the gate (G) of the first MIS transistor 27d of the third switch circuit 19d in the internal boost mode. The first MIS transistor 27d of the third switch circuit 19d is conductive.

[0063] The first switch circuit 19b, the second switch circuit 19c, and the second MIS transistor 27e of the third switch circuit 19d are conductive in response to the third boost voltage (VPPML) applied to their gates (G). The voltage of the shared node SN1 of the first switch circuit 19b and the third switch circuit 19d becomes the first boost voltage VPP through the second MIS transistor 27e in each switch circuit.

[0064] The first boost voltage VPP is applied to the internal line 36 and the second terminal 27c of the first switch circuit 19b via the third switch circuit 19d. The first terminal 27b of the second switch circuit 19c receives the first boost voltage VPP from the first line 31.

[0065] In the first switch circuit 19b, the first MIS transistor 27d is non-conductive, preventing the first boosted voltage VPP from being transmitted from the internal line 36 to the fifth line 35. In the second switch circuit 19c, the first MIS transistor 27d is non-conductive, preventing the first boosted voltage VPP from being transmitted from the first line 31 to the fifth line 35.

[0066] The boost circuit 13 is operating, and the well voltage generation circuit 23 supplies the first boost voltage VPP to the well line WELL. In the first MIS transistor 27d of the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d, the back gate (B) receives the first boost voltage VPP.

[0067] The mitigation circuit 43 generates a voltage (VPPML-ABS(VTP)) at the gate (G) and drain (D) of the fourth MIS transistor 45. Here, "ABS(VTP)" means the absolute value of the threshold voltage VTP of a p-type MIS transistor. This voltage is applied to the first terminal 27b of the first switch circuit 19b and the source (S) and back gate (B) of the third MIS transistor 41. At this time, the gate (G) of the third MIS transistor 41 receives the third boost voltage VPPML, so that the third MIS transistor 41 is non-conductive.

[0068] FIG. 8 is a diagram showing circuit connections in the semiconductor device according to this embodiment.

[0069] The semiconductor device 11 may further include one or more mitigation circuits 47 (47b, 47c, 47d). The mitigation circuits 47 (47b, 47c, 47d) may be connected to at least one of the shared nodes SN1 of the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d. Referring to FIG. 8, the first mitigation circuit 47b (47), the second mitigation circuit 47c (47), and the third mitigation circuit 47d (47) are connected to the first switch circuit 19b, the second switch circuit 19c, and the third switch circuit 19d, respectively. The mitigation circuits 47 (47b, 47c, 47d) may include p-type MIS transistors (51, 53, 55), respectively. The exemplary mitigation circuit 47 may have the same circuit connection and operation as the mitigation circuit 43 with respect to the respective p-type MIS transistors (51, 53, 55).

[0070] When the fifth line 35 connected to the electrode 15 is disconnected from the internal line 36, the shared node SN1 of the first switch circuit 19b is charged via the mitigation circuit 47b to a potential that is lower than the third boosted voltage VPPML by the absolute value of the threshold voltage VTP of the p-type MIS transistor.

[0071] When the fifth line 35 connected to the electrode 15 is connected to the internal line 36, the shared node SN1 of the first switch circuit 19b becomes a relay point for the connection between the fifth line 35 and the internal line 36 and receives an externally applied voltage. The potential of the shared node SN1 of the first switch circuit 19b is not transmitted to the third line 33 via the first mitigation circuit 47b.

[0072] When the first line 31 from the boost circuit 13 is connected to the fifth line 35 which is connected to the electrode 15, the shared node SN1 of the second switch circuit 19c becomes a relay point for the connection of the first line 31 and the fifth line 35 and receives the first boosted voltage VPP. The potential of the shared node SN1 of the second switch circuit 19c is not transmitted to the third line 33 via the second mitigation circuit 47c.

[0073] When the first line 31 from the boost circuit 13 is disconnected from the fifth line 35, the shared node SN1 of the second switch circuit 19c is charged to a potential that is lower than the third boosted voltage VPPML by the absolute value of the threshold voltage VTP of the p-type MIS transistor via the second mitigation circuit 47c.

[0074] When the first line 31 from the boost circuit 13 is disconnected from the internal line 36, the shared node SN1 of the third switch circuit 19d is charged to a potential that is lower than the third boosted voltage VPPML by the absolute value of the threshold voltage VTP of the p-type MIS transistor via the third mitigation circuit 47d.

[0075] When the first line 31 from the boost circuit 13 is connected to the internal line 36, the shared node SN1 of the third switch circuit 19d becomes a relay point for the connection of the first line 31 and the internal line 36 and receives the first boosted voltage VPP. The potential of the shared node SN1 of the third switch circuit 19d is not transmitted to the third line 33 via the third mitigation circuit 47d.

[0076] The concept of withstand voltage violation will be explained.

[0077] 9 is a diagram showing a circuit similar to the switch circuit of the semiconductor device according to the present embodiment. Referring to Fig. 9, two transistors (28c, 28d), for example, p-type transistors, are connected in series between a first boost voltage VPP and a ground voltage (GND).

[0078] The gate (G) of the transistor faces the back gate (B) via a gate insulating film. The gate insulating film is located between the semiconductor region of the back gate (B) and the gate (G). The semiconductor regions of the source (S) and drain (D) are adjacent to both sides of the semiconductor region of the back gate (B) (the region directly under the gate insulating film).

[0079] The potential difference between the gate (G) and source (S) is applied to a portion of the gate insulating film, and the potential difference between the gate (G) and drain (D) is applied to a portion of the gate insulating film. Furthermore, when a channel (strong inversion state, weak inversion state) is formed directly below the gate insulating film, the potential of the channel is any voltage within the potential difference between the source (S) and drain (D). Furthermore, when no channel is formed directly below the gate insulating film, the gate oxide film is subjected to the potential difference between the back gate (B) and gate (G).

[0080] For this reason, in order to avoid a breakdown voltage violation, a thick gate oxide film capable of withstanding a large voltage is provided for transistors that handle a large voltage such as the first boost voltage VPP. The characteristics of a transistor with a thick gate oxide film do not satisfy the operating speed required for a circuit that operates with a normal power supply voltage. Therefore, transistors with a variety of gate oxide thicknesses (thick gate oxide film and thin gate oxide film) have been provided for semiconductor devices.

[0081] FIG. 10 shows five potential levels, a first boosted voltage VPP, a second boosted voltage VPPMH, a third boosted voltage VPPML, a power supply voltage VDC15, and a ground potential (0 volts).

[0082] In a transistor with a thin gate oxide film, if the potential difference between the back gate (B) and the gate (G), the potential difference between the gate (G) and the source (S), and the potential difference between the gate (G) and the drain (D) are within the ranges of the three potential differences VD1, VD2, and VD3 in FIG. 10, respectively, the thin gate oxide film transistor can operate without violating the breakdown voltage.

[0083] This is the concept of breakdown voltage violation. Specifically, referring to FIG. 9 again, in the p-type transistor 28c, the voltage of the source (S) is the first boost voltage VPP. The voltage applied to the gate (G) without breakdown voltage violation is up to the third boost voltage VPPML. When the gate (G) is the first boost voltage VPP, the voltage applied to the source (S) without breakdown voltage violation is up to the third boost voltage VPPML. Also, in the p-type transistor 28d, the voltage of the gate (G) is the third boost voltage VPPML. When the gate (G) is the third boost voltage VPPML, the voltage applied to the source (S) without breakdown voltage violation is the first boost voltage VPP, and the voltage applied to the drain (D) without breakdown voltage violation is 0 volts. Also, the range where breakdown voltage violation does not occur is expanded to a potential difference obtained by adding the absolute value of the threshold voltage VTP of the p-type MIS transistor to the above potential difference.

[0084] When potential differences VD1, VD2, and VD3 are applied between the source (S) and gate (G) of the p-type MIS transistor, the channel of the p-type MIS transistor is in a strong inversion state. Similarly, when potential differences VPP-VPPMH, VPPMH-VPPML, VPPML-VDC15, and VDC15-0 are applied between the source (S) and gate (G) of the p-type MIS transistor, the channel of the p-type MIS transistor is in a strong inversion state. In addition, when the source (S) and back gate (B) of the p-type MIS transistor receive the first boost voltage VPP, if the first boost voltage VPP is applied to the gate (G) of the p-type MIS transistor, the channel of the p-type MIS transistor is in a weak inversion state.

[0085] The level shifter 21, for example the first level shift circuit 21b, can provide a voltage signal of the first boost voltage VPP or the third boost voltage VPPML for the value of the output n5 in response to the logic input TEST_MON. The well voltage generation circuit 23 provides the power supply voltage VDC15 during non-boosting when the boost circuit 13 is not operating, and provides the first boost voltage VPP during boosting.

[0086] The series connection of p-type transistors shown in FIG. 9 is replaced with a series connection of n-type transistors, and the concept of breakdown voltage violation is similarly applied.

[0087] The level shifter 21 is connected to a first line 31, a second line 32, a third line 33, and a fourth line 34. The voltages provided through these lines are used to make the level shifter 21 compliant with the breakdown voltage violation concept.

[0088] According to the concept of breakdown voltage violation, the operation of the semiconductor device 11 will be described with reference to FIGS.

[0089] Internal boost mode (TEST_INT:H, TEST_MON:L, TEST_EXT:L)

[0090] The first MIS transistor 27d and the second MIS transistor 27e of the third switch circuit 19d are both turned on, and the first boosted voltage VPP is applied from the first line 31 to the internal line 36, thereby preventing the third switch circuit 19d from violating the withstand voltage limit.

[0091] The shared node SN1 of the second switch circuit 19c rises to a voltage at which the second MIS transistor 27e becomes non-conductive, for example, approximately the third boosted voltage VPPML, due to a delay in the rising edge of the output n1 of the second level shift circuit 21c for the gate (G) of the first MIS transistor 27d of the second switch circuit 19c. This makes it possible to avoid a breakdown voltage violation of the first MIS transistor 27d.

[0092] Since the gate (G) of the second MIS transistor 27e of the first switch circuit 19b receives the third boost voltage VPPML, the shared node SN1 of the first switch circuit 19b receives the first boost voltage VPP from the internal line 36 via the second MIS transistor 27e. This makes it possible to avoid a breakdown voltage violation of the second MIS transistor 27e of the first switch circuit 19b.

[0093] Since no external voltage is applied to the electrode 15, the potential of the fifth line 35 is 0 volts or higher. The fourth MIS transistor 45 of the mitigation circuit 43 raises the potential of the first terminal 27b of the first switch circuit 19b and the source (S) and back gate (B) of the third MIS transistor 41 to a potential that is lower than the third boost voltage VPPML by the threshold voltage (VTP) of the fourth MIS transistor 45 (p-type transistor). This makes it possible to avoid a breakdown voltage violation of the first MIS transistor 27d of the first switch circuit 19b.

[0094] Since no voltage is applied to the electrode 15 from the outside, the potential of the fifth line 35 is 0 volts or more. In the third MIS transistor 41, the gate (G) receives the third boost voltage VPPML, and the drain (D) receives a voltage of 0 volts or more. The source (S) and back gate (B) have a potential that is lower than the third boost voltage VPPML by the threshold voltage (VTP) of the fourth MIS transistor 45 (p-type transistor). This makes it possible to avoid a breakdown voltage violation of the third MIS transistor 41.

[0095] In the fourth MIS transistor 45, the source (S) receives the third boost voltage VPPML, and the back gate (B) receives the first boost voltage VPP from the well line WELL. The gate (G) and drain (D) are at a potential lower than the third boost voltage VPPML by the threshold voltage (VTP) of the fourth MIS transistor 45 (p-type transistor). This makes it possible to avoid a breakdown voltage violation of the fourth MIS transistor 45.

[0096] Monitor mode (TEST_INT:L, TEST_MON:H, TEST_EXT:L)

[0097] The second switch circuit 19b is conductive. The electrode 15 is connected to the first line 31 via the second switch circuit 19b. The first terminal 27b, the second terminal 27c, and the shared node SN1 of the second switch circuit 19b become the first boost voltage VPP. This makes it possible to avoid a violation of the withstand voltage of the second switch circuit 19b.

[0098] The drain (D) of the third MIS transistor 41 receives the monitor voltage (first boosted voltage VPP) from the fifth line 35. A breakdown voltage violation of the third MIS transistor 41 can be avoided.

[0099] The shared node SN1 of the third switch circuit 19d rises to a voltage at which the second MIS transistor 27e becomes non-conductive, for example, to about the third boost voltage VPPML, due to a delay in the rise of the control signal Sn3 of the third level shift circuit 21d for the gate (G) of the first MIS transistor 27d of the third switch circuit 19d. This makes it possible to avoid a violation of the withstand voltage of the first MIS transistor 27d.

[0100] Furthermore, the drain (D) of the second MIS transistor 27e of the third switch circuit 19d is connected to the internal line 36, and the potential of the internal line 36 is equal to or higher than 0 volts. This makes it possible to avoid a breakdown voltage violation of the second MIS transistor 27e.

[0101] In the first switch circuit 19b, the shared node SN1 rises to a potential that is lower than the third boosted voltage VPPML by the threshold voltage (VTP) of the fourth MIS transistor 45 (p-type transistor) due to a delay in the rise of the control signal Sn5 of the first level shift circuit 21b for the gate (G) of the first MIS transistor 27d of the first switch circuit 19b to the first boosted voltage (VPP).This makes it possible to avoid a breakdown voltage violation of the first MIS transistor 27d.

[0102] In the first switch circuit 19b, the voltages of the source (S) and back gate (B) of the second MIS transistor 27e are equal to the voltage of the shared node SN1, so that the second MIS transistor 27e receives the third boost voltage VPPML at its gate (G) and becomes non-conductive. In addition, the drain (D) of the second MIS transistor 27e is connected to the internal line 36, and the potential of the internal line 36 is 0 volts or higher. This makes it possible to avoid a breakdown voltage violation of the second MIS transistor 27e.

[0103] External application mode (TEST_INT:L, TEST_MON:L, TEST_EXT:H)

[0104] The first MIS transistor 27d, the second MIS transistor 27e, and the third MIS transistor 41 of the first switch circuit 19b receive the third boost voltage VPPML at their gates (G) and are all conductive. This makes it possible to avoid a breakdown voltage violation of the first MIS transistor 27d, the second MIS transistor 27e, and the third MIS transistor 41.

[0105] In the second switch circuit 19c, the shared node SN1 is connected to the fifth line 35 via the second MIS transistor 27e, and the shared node SN1 of the third switch circuit 19d is connected to the internal line 36 via the second MIS transistor 27e. The first terminal 27b of the second switch circuit 19c and the first terminal 27b of the third switch circuit 19c receive the first boost voltage VPP from the first line 31. The gates (G) of the second switch circuit 19c and the third switch circuit 19d receive the control signal Sn1 and the control signal Sn3, respectively, and the values ​​of the control signal Sn1 and the control signal Sn3 are the first boost voltage VPP. This makes it possible to avoid a breakdown voltage violation in the second switch circuit 19c and the third switch circuit 19d.

[0106] The semiconductor device 11 based on the concept of withstand voltage violation can avoid the withstand voltage violation by a circuit using only transistors (i.e., low-withstand voltage elements) having a lower withstand voltage than the high-withstand voltage elements, without using transistors (i.e., high-withstand voltage elements) having a withstand voltage against the output voltage of the boost circuit 13, for example, the first boost voltage VPP. However, the semiconductor device 11 can be composed of only high-withstand voltage elements, or can be composed of both high-withstand voltage elements and low-withstand voltage elements.

[0107] Therefore, the semiconductor device 11 can be configured using at least one of a high-voltage element and a low-voltage element.

[0108] The semiconductor device 11 can provide exemplary modes, such as an internal boost mode, a monitor mode, and a voltage application mode. The voltage that can be applied externally ranges from the first boost voltage VPP to a voltage higher than the third boost voltage VPPML by the threshold voltage VTP of the p-type transistor. This eliminates the need to provide special electrode pads and a test circuit for the same, and the chip area can be reduced. In addition, since the range of voltages that can be applied externally is wide, the test time can be reduced. Furthermore, since separate electrodes for monitoring and external application are not required, the number of terminals can be reduced.

[0109] According to this embodiment, a test operation can be performed in a semiconductor device including a boost circuit that generates a high voltage.

[0110] This embodiment has various aspects.

[0111] A semiconductor device according to a first aspect of the present embodiment is a semiconductor device having an internal boost mode, a monitor mode, and a voltage application mode, the semiconductor device including a switch including one or a plurality of switch circuits, each of the switch circuits including a first terminal and a second terminal, and a first MIS transistor and a second MIS transistor connected in series in a direction from the first terminal to the second terminal, a back gate of the second MIS transistor is connected to a first shared node of the first MIS transistor and the second MIS transistor connected in series, the switch including a first switch circuit as one of the switch circuits, and a boost circuit capable of generating a plurality of boost voltages from a power supply voltage, the plurality of boost voltages including a first boost voltage and one or a plurality of intermediate boost voltages, the first boost voltage being provided from a first output of the boost circuit, an absolute value of the first boost voltage being greater than an absolute value of the intermediate boost voltage, and an absolute value of the power supply voltage being greater than an absolute value of the first boost voltage a boost circuit, the absolute value of which is less than the absolute value of a voltage and the absolute value of the intermediate boosted voltage; an internal line connected to the second terminal of the first switch circuit; a first level shift circuit, connected to the first output of the boost circuit via a first line, and configured to supply the intermediate boosted voltage to a gate of the first MIS transistor of the first switch circuit in the voltage application mode and to supply the first boosted voltage in the internal boost mode and the monitor mode; a well voltage generation circuit, connected to the boost circuit and having an output configured to provide a well voltage via a well line to a back gate of the first MIS transistor of the first switch circuit; and a third MIS transistor, the third MIS transistor having an electrode connected to an external line, a gate configured to receive the intermediate boosted voltage, a back gate and a source connected to the first terminal of the first switch circuit, and a drain connected to the external line.

[0112] In a semiconductor device of a second aspect according to the first aspect, the switch includes a second switch circuit as one of the switch circuits, the first terminal of the second switch circuit is connected to the first line and the second terminal of the second switch circuit is connected to the external line, and the semiconductor device further includes a second level shift circuit connected to the boost circuit and configured to supply the intermediate boost voltage to a gate of the first MIS transistor of the second switch circuit in the monitor mode and to supply the first boost voltage in the internal boost mode and the voltage application mode.

[0113] In a semiconductor device of a third aspect according to the first aspect or the second aspect, the switch includes a third switch circuit as one of the switch circuits, the first terminal of the third switch circuit is connected to the first line and the second terminal of the third switch circuit is connected to the internal line, and the semiconductor device can further include a third level shift circuit connected to the boost circuit and configured to supply the intermediate boost voltage to a gate of the first MIS transistor of the third switch circuit in the internal boost mode and to supply the first boost voltage in the monitor mode and the voltage application mode.

[0114] A semiconductor device according to a fourth aspect of the present invention may further include a mitigation circuit including a fourth MIS transistor having a backgate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the backgate and the source of the third MIS transistor.

[0115] A semiconductor device of a fifth aspect according to any one of the first to fourth aspects further includes a first mitigation circuit connected to the first shared node of the first switch circuit, and the first mitigation circuit may include a fifth MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the first switch circuit.

[0116] The semiconductor device of a sixth aspect according to the second aspect further includes a second mitigation circuit connected to the first shared node of the second switch circuit, and the second mitigation circuit may include a sixth MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the second switch circuit.

[0117] The semiconductor device of a seventh aspect according to the third aspect further includes a third mitigation circuit connected to the first shared node of the third switch circuit, and the third mitigation circuit may include a seventh MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the third switch circuit.

[0118] The semiconductor device according to an eighth aspect of the present invention may further include an electrically rewritable nonvolatile memory connected to the internal line.

[0119] In a semiconductor device according to a ninth aspect in accordance with any one of the first to eighth aspects, the boost circuit may include a plurality of capacitors and a plurality of MIS transistors connected in series and / or in parallel.

[0120] A semiconductor device of a tenth aspect according to any one of the first to ninth aspects may further include a control circuit configured to operate the boost circuit in the internal boost mode, the monitor mode, and the voltage application mode.

[0121] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0122] REFERENCE SIGNS LIST 11 semiconductor device, 13 boost circuit, 15 electrode, 17 non-volatile memory, 19 switch, 19b first switch circuit, 19c second switch circuit, 19d third switch circuit, 21 level shifter, 21b first level shift circuit, 21c second level shift circuit, 21d third level shift circuit, 23 Well voltage generating circuit, 27...switching circuit, 27b...first terminal, 27c...second terminal, 27d...first transistor, 27e...second transistor, 29...level shifting circuit, 29b...mode terminal, 29c...output, 30...control circuit, 31...first line, 32...second line, 33...third line, 34...fourth line, 35... 5th line, 36 internal line, 43 mitigation circuit, 45 transistor, 47 mitigation circuit, 47b first mitigation circuit, 47c second mitigation circuit, 47d third mitigation circuit, LVSOUT output signal, MODE mode signal, Sn1 first control signal, Sn3 second control signal, Sn5 second control signal, TEST_EXT, TEST_INT, TEST_MON logic input, VD1, VD2, VD3 potential difference, VDC15 power supply voltage, VPP first boost voltage, VPPMH second boost voltage, VPPML third boost voltage, VPP_EXT external voltage, VPP_INT monitor voltage, VTP threshold voltage, WELL well line, SN1 shared node.

Claims

1. A semiconductor device having an internal boost mode, a monitor mode, and a voltage application mode, a switch including one or more switch circuits, each of the switch circuits including a first terminal and a second terminal, and a first MIS transistor and a second MIS transistor connected in series in a direction from the first terminal to the second terminal, a back gate of the second MIS transistor being connected to a first shared node of the first MIS transistor and the second MIS transistor connected in series, the switch including a first switch circuit as one of the switch circuits; a boost circuit capable of generating a plurality of boosted voltages from a power supply voltage, the plurality of boosted voltages including a first boosted voltage and one or more intermediate boosted voltages, the first boosted voltage being provided from a first output of the boost circuit, an absolute value of the first boosted voltage being greater than an absolute value of the intermediate boosted voltage, and an absolute value of the power supply voltage being less than the absolute value of the first boosted voltage and the absolute value of the intermediate boosted voltage; an internal line connected to the second terminal of the first switch circuit; a first level shift circuit connected to the first output of the boost circuit via a first line, configured to supply the intermediate boosted voltage to a gate of the first MIS transistor of the first switch circuit in the voltage application mode and to supply the first boosted voltage in the internal boost mode and the monitor mode; a well voltage generating circuit having an output connected to the boost circuit and configured to provide a well voltage via a well line to a back gate of the first MIS transistor of the first switch circuit; An electrode connected to an external line; a third MIS transistor having a gate configured to receive the intermediate boosted voltage, a back gate and a source connected to the first terminal of the first switch circuit, and a drain connected to the external line; Equipped with Semiconductor device.

2. the switching device includes a second switch circuit as one of the switch circuits; the first terminal of the second switch circuit is connected to the first line; the second terminal of the second switch circuit is connected to the external line; the semiconductor device further includes a second level shift circuit connected to the boost circuit and configured to supply the intermediate boosted voltage to a gate of the first MIS transistor of the second switch circuit in the monitor mode and to supply the first boosted voltage to the gate of the first MIS transistor in the internal boost mode and the voltage application mode.

2. The semiconductor device according to claim 1.

3. the switching device includes a third switch circuit as one of the switch circuits; the first terminal of the third switch circuit is connected to the first line; the second terminal of the third switch circuit is connected to the internal line; The semiconductor device includes: a third level shift circuit connected to the boost circuit and configured to supply the intermediate boosted voltage to a gate of the first MIS transistor of the third switch circuit in the internal boost mode and to supply the first boosted voltage to a gate of the first MIS transistor in the monitor mode and the voltage application mode; 2. The semiconductor device according to claim 1.

4. a relaxation circuit including a fourth MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the back gate and the source of the third MIS transistor; Further preparations:

4. The semiconductor device according to claim 3.

5. a first mitigation circuit connected to the first shared node of the first switch circuit; the first mitigation circuit includes a fifth MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the first switch circuit; 2. The semiconductor device according to claim 1.

6. a second mitigation circuit connected to the first shared node of the second switch circuit; the second mitigation circuit includes a sixth MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the second switch circuit; 3. The semiconductor device according to claim 2.

7. a third mitigation circuit connected to the first shared node of the third switch circuit; the third mitigation circuit includes a seventh MIS transistor having a back gate connected to the output of the well voltage generation circuit, a source configured to receive the intermediate boosted voltage, and a gate and a drain connected to the first shared node of the third switch circuit; 4. The semiconductor device according to claim 3.

8. The internal line is connected to the nonvolatile memory.

2. The semiconductor device according to claim 1.

9. the boost circuit includes a plurality of capacitors and a plurality of MIS transistors connected in series and / or in parallel; 2. The semiconductor device according to claim 1.

10. a control circuit configured to operate the boost circuit in the internal boost mode, the monitor mode, and the voltage application mode; 2. The semiconductor device according to claim 1.

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