Driving device of bridge circuit

Abstract

To provide a driving device of a bridge circuit, capable of reducing a dead time even in the case it is adopted to a high voltage and a large current system.SOLUTION: In a driving device 4, a remaining dead time detection part 12 detects a delay time from a timing when a gate voltage Vgs of power elements 1 and 2 constructing upper and lower arms of a bridge circuit to a timing when a drain-source inter voltage Vds is stood as a remaining dead time. A minimum residual dead time calculation part 15 determines whether or not a switching of an own arm is performed on any one of a driving side and a rectification side as compared with a threshold value in the delay time, and selects the delay time detected on the rectification side. A Vgs advance amount calculation part 16 and a pseud Vgs signal generation part 17 sets a control amount on the basis of the delay time selected by the minimum residual dead time calculation part, and output a pseud Vds signal which is dropped at a timing that is earlier by a set control amount to an arm side that is opposite to the own arm. A driving part on the arm side that is opposite turns on the arm in accordance with the pseud Vds signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit for driving power elements that constitute a bridge circuit. [Background technology]

[0002] For example, in inverters and converters that configure a bridge circuit with power elements such as MOSFETs as the upper and lower arms and drive them alternately, a dead time is provided to simultaneously turn off the upper and lower arms to prevent them from being turned on at the same time. During this dead time, the diode built into the MOSFET or connected in parallel with it conducts, resulting in greater losses than when the MOSFET is on. Therefore, it is desirable to shorten the dead time as much as possible.

[0003] For example, Patent Document 1 discloses a configuration in which the gate-off of the upper and lower arms is detected mutually, and the ON timing of the own arm is generated by the logical AND of the gate-off detection signal and the drive signal, using the OFF of the opposing arm as a trigger to eliminate the need to add dead time to the drive signals for the upper and lower arms, and the dead time is shortened to a level that does not cause a short circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-97348 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, assuming that the configuration of Patent Document 1 is applied to a high-voltage / high-current system, such as inverter control in an electric vehicle (EV), the following problems arise. The upper and lower arms in such a high-voltage / high-current system are insulated from each other. A digital isolator such as a photocoupler or a magnetic coupler is generally used for signal transmission between the insulated arms, so a delay time occurs. Therefore, the arm cannot be driven until an off detection signal arrives from the opposing arm, and this transmission delay time remains as a dead time. In addition, depending on the gate capacitance of the connected power element and the driving voltage and driving current capacity of the driver, the driving delay time from when the gate of the power element starts to be driven until the threshold voltage Vth is exceeded also remains as a dead time. Therefore, under certain circuit conditions, a dead time of about 500 nsec remains in addition to the above-mentioned transmission delay time.

[0006] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a bridge circuit driver that can further shorten the dead time even when applied to a high voltage / high current system. [Means for solving the problem]

[0007] According to the bridge circuit driving device of claim 1, the delay time detection unit (12) detects the delay time from the timing when the drive signal applied to the conduction control terminals of the power elements (1, 2) constituting the upper and lower arms of the bridge circuit falls to the timing when the voltage between the conduction terminals of the power elements rises. Note that the power elements are semiconductor elements capable of switching a relatively large amount of power, constituting a power conversion circuit such as the above-mentioned inverter.

[0008] A delay time selection unit (15) compares the delay time with a threshold value to determine whether switching of the own arm has been performed on the drive side or the rectification side, and selects the delay time detected on the rectification side. A pseudo drive signal output unit (16, 17, 24) sets a control amount based on the delay time selected by the delay time selection unit, and outputs a pseudo drive signal that falls at a timing earlier than the set control amount to the arm side opposite to the own arm. A drive unit on the opposite arm side turns on the arm in response to the pseudo drive signal.

[0009] That is, the drive unit corresponding to each arm can turn on its own arm at a timing determined by the pseudo drive signal input from the opposing arm, that is, at a timing earlier than the drive signal input from the upper control unit, thereby making it possible to shorten the dead time. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a functional block diagram showing the configuration of a driver for a bridge circuit according to a first embodiment. [Diagram 2] Flowchart showing the process of the drive device [Diagram 3] Timing chart showing remaining dead time detection process [Figure 4] Timing chart showing the process of shortening the remaining dead time [Diagram 5] Waveform diagram showing the drive signals and gate voltage Vgs of the upper and lower arms when the remaining dead time is not shortened [Figure 6] Waveform diagram showing the drive signals and gate voltage Vgs of the upper and lower arms when performing the remaining dead time shortening process [Figure 7] FIG. 2 is a functional block diagram showing the configuration of a driver for a bridge circuit according to a second embodiment. [Figure 8] Flowchart showing the process of the drive device DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) As shown in Fig. 1, the drive device of this embodiment drives, for example, upper and lower arms of one phase constituting a three-phase inverter, that is, a bridge circuit. Each arm is configured such that power elements 1 and 2, such as N-channel MOSFETs, are connected between DC power supply lines 3P and 3N. Gate voltages Vgs are applied to the gates, which are the conduction control terminals of the power elements 1 and 2, by drive units 4P and 4N of the drive device 4. A drive signal from an inverter control unit 5 is input to the drive units 4P and 4N via insulating units 6P and 6N. The insulating units 6P and 6N are, for example, photocouplers or magnetic couplers.

[0012] The configurations of the drivers 4P and 4N corresponding to the power elements 1 and 2 are symmetrical, so the power element 1 will be described below. The drive signal is input to the driver 8 via the AND gate 7 and also to the pseudo Vgs signal generator 17. The driver 8 outputs a gate voltage Vgs to the gate of the power element 1. A series circuit of capacitors 9a and 9b is connected in parallel to the power element 1. The non-inverting input terminal of the comparator 10 is connected to the gate of the power element 1, and the non-inverting input terminal of the comparator 11 is connected to the common connection point of the capacitors 9a and 9b. The inverting input terminals of the comparators 10 and 11 are respectively supplied with reference voltages Vg-Ref and Vd-Ref. The output terminals of the comparators 10 and 11 are connected to the input terminals of the remaining dead time detector 12.

[0013] The remaining dead time detection unit 12 counts the difference between the falling timing of the gate voltage Vgs and the rising timing of the drain-source voltage Vds of the power element 1, and detects the dead time when the level of the gate voltage Vgs changes from the ON side to the OFF side. The dead time detected here may be called the "remaining dead time." The remaining dead time detection unit 12 corresponds to a delay time detection unit.

[0014] A drive / rectification determination unit 13 and a counter 14 are disposed downstream of the remaining dead time detection unit 12. The drive / rectification determination unit 13 determines whether the switching of the power element 1 has been detected on the drive side or the rectification side depending on whether the remaining dead time obtained by the detection unit 12 is equal to or greater than a threshold value or less than a threshold value. Then, the drive / rectification determination unit 13 outputs the remaining dead time obtained in the case of the rectification side to the next stage. The counter 14 continuously performs a counting operation equivalent to one electrical angle cycle of the inverter.

[0015] A minimum remaining dead time calculation unit 15 is disposed after the drive / rectification determination unit 13 and the counter 14. For each electrical angle cycle counted by the counter 14, the minimum remaining dead time calculation unit 15 selects the minimum remaining dead time among the remaining dead times acquired in the case of the rectification side within each cycle. Then, the minimum remaining dead time calculation unit 15 outputs the selected remaining dead time to the Vgs advance amount calculation unit 16 in the next stage. The minimum remaining dead time calculation unit 15 corresponds to a delay time selection unit.

[0016] The Vgs advance amount calculation unit 16 determines the amount of advance of the timing for changing the level of the gate voltage Vgs from the OFF side to the ON side, that is, the dead time reduction control amount, on the power element 2 side, which is the opposing arm, from the minimum remaining dead time acquired from the minimum remaining dead time calculation unit 15. Details of this process will be described later.

[0017] The next stage pseudo Vgs signal generating unit 17 receives the dead time reduction control amount to generate a pseudo Vgs signal, and outputs the signal to the AND gate 7 on the driver 4N side via the insulating unit 18P. When both the drive signal input from the inverter control unit 5 and the pseudo Vgs signal input from the driver 4N become high level, the AND gate 7 of the driver 4P sets the signal to be output to the driver 8 to high level. The Vgs advance amount calculating unit 16 and the pseudo Vgs signal generating unit 17 correspond to a pseudo drive signal output unit.

[0018] Next, the operation of this embodiment will be described. As shown in Fig. 2, when the drive device 4 starts the dead time reduction control, first, the remaining dead time detection unit 13 starts detecting the remaining dead time (S1). That is, the difference between the falling timing of the gate voltage Vgs and the rising timing of the drain-source voltage Vds is counted to detect the remaining dead time at each switching time (S2). The detected value of the remaining dead time is stored in memory (S3). Until one electrical angle period is counted by the counter 14 (S4; No), the process returns to step S2 and continues detecting the remaining dead time.

[0019] As shown in Fig. 3, when the lower arm is switched to the drive side and the upper arm is switched to the rectification side, the remaining dead time detected for the upper arm is relatively long and the remaining dead time detected for the lower arm is relatively short. On the other hand, when the upper arm is switched to the drive side and the lower arm is switched to the rectification side, the above relationship is reversed. Therefore, if the detected remaining dead time length is determined by a threshold value set midway between the two, it can be determined whether the switching of the own arm is to the drive side or the rectification side. Note that Fig. 3 shows a case where the remaining dead time shortening process described later is not performed.

[0020] When one period of the electrical angle is counted (S4; Yes), the minimum remaining dead time calculation unit 15 excludes the remaining dead time values ​​detected when switching is performed on the drive side from the remaining dead time values ​​stored in the memory. In other words, it selects the minimum value from the remaining dead time values ​​detected when switching is performed on the rectification side, and outputs it to the Vgs advance amount calculation unit 16 (S5). Next, the remaining dead time is started to be shortened (S7), but as a preparation for this, the Vgs advance amount calculation unit 16 counts the time from the falling edge of the drive signal input to the own arm to the falling edge of the gate voltage Vgs of the own arm (S6). Therefore, although not shown in FIG. 1, the above drive signal and the output signal of the comparator 10 are input to the Vgs advance amount calculation unit 16.

[0021] The Vgs advance amount calculation unit 16 determines the control amount for shortening the dead time, with the remaining dead time value selected in step S5 as the maximum shortening amount. That is, it is determined within the range of "control amount"≦"maximum shortening amount" (S8). The pseudo Vgs signal generation unit 17 generates a pseudo Vgs signal that falls at a timing earlier by the determined control amount (S9). Then, it transmits the generated pseudo Vgs signal to the driver on the opposing arm side (S10). Then, on the opposing arm side, the gate voltage Vgs rises earlier in response to the pseudo Vgs signal, and the remaining dead time is shortened (S11).

[0022] FIG. 4 shows a state in which the gate voltage Vgs rises earlier by the remaining dead time by mutually transmitting pseudo Vgs signals between the upper and lower arms, as compared to the timing chart shown in FIG. 3, and as a result, the dead time is shortened. FIG. 5 and FIG. 6 show enlarged waveforms when the upper arm is turned on and the lower arm is turned off. FIG. 5 shows a case in which control for shortening the dead time is not performed as in this embodiment. In contrast, as shown in FIG. 6, in this embodiment, the pseudo Vgs signal transmitted from the lower arm side to the upper arm side and the pseudo Vgs signal transmitted from the lower arm side to the upper arm side cause the gate voltage Vgs on the opposing arm side to rise earlier, thereby shortening the dead time.

[0023] As described above, according to this embodiment, in the drive device 4, the remaining dead time detection unit 12 detects the delay time from the timing when the gate voltage Vgs applied to the gates of the power elements 1 and 2 constituting the upper and lower arms of the bridge circuit falls to the timing when the drain-source voltage Vds rises as the remaining dead time.

[0024] A minimum remaining dead time calculation unit 15 compares the delay time with a threshold value to determine whether the switching of the own arm was performed on the drive side or the rectification side, and selects the delay time detected on the rectification side. A Vgs advance amount calculation unit 16 and a pseudo Vgs signal generation unit 17 set a control amount based on the delay time selected by the minimum remaining dead time calculation unit 15, and output a pseudo Vds signal that falls at a timing earlier than the set control amount to the arm side opposite the own arm. A drive unit on the opposite arm side turns on the arm in response to the pseudo Vds signal.

[0025] That is, the driving units 4P, 4N corresponding to each arm can turn on their own arms at a timing determined by the pseudo Vgs signal input from the opposing arm side, that is, at a timing earlier than the driving signal input from the upper control unit. This makes it possible to shorten the dead time. For the same conditions as the configuration with a dead time of about 500 nsec described above, it is possible to shorten the dead time to about 100 nsec, since only the dead time detection error and clock error are involved.

[0026] Furthermore, the Vgs advance amount calculation unit 16 sets the control amount in the dead time reduction control within a range equal to or less than the selected delay time as a limit value, thereby making it possible to reduce the dead time while avoiding the occurrence of a short circuit between the upper and lower arms.

[0027] Second embodiment Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted, and the different parts will be described. A driving device 21 of the second embodiment shown in Fig. 7 includes a voltage detection unit 22 that detects a voltage Vdc between the DC power supply lines 3P and 3N, and a temperature detection unit 23 that detects a temperature Tpd of the power elements 1 and 2. The voltage Vdc and the temperature Tpd detected by these are input to a Vgs advance amount calculation unit 24 that replaces the Vgs advance amount calculation unit 16.

[0028] Next, the operation of the second embodiment will be described. In the process of the second embodiment shown in Fig. 8, steps S12 and S13 are executed instead of step S5 shown in Fig. 2 of the first embodiment. In step S12, a specified value of the dead time is determined based on the operating environment such as the detected voltage Vdc and temperature Tpd. In the following step S13, when the selected remaining dead time value falls below the specified value determined in step S12, the Vgs advance amount calculation unit 24 adjusts the selected remaining dead time value so that it exceeds the specified value.

[0029] As described above, according to the second embodiment, the voltage detection unit 22 detects the voltage Vdc of the DC power supply, and the temperature detection unit 23 detects the temperature Tpd of the power elements 1, 2. The Vgs advance amount calculation unit 24 determines a specified value of the dead time based on the operating environment such as the detected voltage Vdc and temperature Tpd, and when the value of the remaining dead time selected by the minimum remaining dead time calculation unit 15 falls below the determined specified value, adjusts it so that it exceeds the specified value. This makes it possible to shorten the dead time while avoiding the occurrence of a short circuit in the upper and lower arms, even if the value of the remaining dead time detected based on the voltage Vdc, temperature Tpd, etc. fluctuates.

[0030] (Other embodiments) The power element is not limited to an N-channel MOSFET. In the second embodiment, only either the voltage detection unit 22 or the temperature detection unit 23 may be provided, and the specified value may be determined based on only either the voltage Vdc or the temperature Tpd. The bridge circuit is not limited to one that constitutes a three-phase inverter, and may be one that constitutes a single half-bridge circuit or an H-bridge circuit. Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0031] In the drawing, 1 and 2 indicate power elements, 12 indicates a remaining dead time detection section, 13 indicates a drive / rectification determination section, 14 indicates a counter, 15 indicates a small remaining dead time detection section, and 16 indicates a Vgs advance amount calculation section.

Claims

1. It drives the conduction control terminals of two power elements (1, 2) connected in series to form the upper and lower arms of a bridge circuit. a delay time detection unit (12) that detects a delay time from a timing at which a drive signal applied to the conduction control terminal falls to a timing at which a voltage between the conduction terminals of the power element rises; a delay time selection unit (15) that compares the delay time with a threshold value to determine whether the switching of the own arm has been performed on the drive side or the rectification side, and selects the delay time detected on the rectification side; a pseudo drive signal output unit (16, 17, 24) that sets a control amount based on the delay time selected by the delay time selection unit, and outputs a pseudo drive signal that falls at a timing earlier than the set control amount to an arm opposite to the arm itself; a drive unit (8) provided on the opposing arm side and turning on the opposing arm in response to the pseudo drive signal.

2. 2. The bridge circuit drive device according to claim 1, wherein the pseudo drive signal output unit increases the control amount when any of the delay times detected over one electrical angle period falls below a specified value.

3. The device is provided with either or both of a voltage detection unit (22) for detecting the voltage of a power supply and a temperature detection unit (23) for detecting the temperature, 3. The bridge circuit driver according to claim 2, wherein the pseudo drive signal output section sets the specified value in accordance with the voltage or the temperature.

4. 4. The bridge circuit drive device according to claim 2 or 3, wherein the pseudo drive signal output unit (24) sets, as the control variable, a delay time that is equal to or greater than the specified value and is the shortest among delay times detected over one electrical angle period.

5. 2. The bridge circuit drive device according to claim 1, wherein the pseudo drive signal output unit (16) sets the control amount within a range equal to or less than the selected delay time, the control amount being set as a limit value.

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