Driving device of bridge circuit

Abstract

To provide a driving device of a bridge circuit, capable of reducing a dead time also near a zero cross point of a current.SOLUTION: A driving side / rectification side determination part 38 determines whether or not a switching of a power element as a driving objet is performed onto any one of a driving side and a rectification side on the basis of a direction of a current flowing to between an output terminal of a bridge circuit formed by power elements 1 and 2 and a load. An ON side DT detection part 22 detects and stores a delay time between a timing when a level of a voltage Vds of the power element is changed and a timing when a level of the voltage Vgs is changed when the switching is performed on the rectification side. A timing adjustment part 7 adjusts the timing when the level of the driving signal is changed so as to be earlier by a delay time to be detected.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an apparatus for driving power elements that form a bridge circuit. [Background technology]

[0002] For example, in inverters and converters that configure a bridge circuit with power elements such as MOSFETs as the upper and lower arms and drive them alternately, a dead time is provided to simultaneously turn off the upper and lower arms to prevent them from being turned on at the same time. During this dead time, the diode built into the MOSFET or connected in parallel with it conducts, resulting in greater losses than when the MOSFET is on. Therefore, it is desirable to shorten the dead time as much as possible.

[0003] For example, Patent Document 1 discloses a configuration in which the gate-off of the upper and lower arms is detected mutually, and the ON timing of the own arm is generated by the logical AND of the gate-off detection signal and the drive signal, using the OFF of the opposing arm as a trigger to eliminate the need to add dead time to the drive signals for the upper and lower arms, and the dead time is shortened to a level that does not cause a short circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-97348 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, assuming that the configuration of Patent Document 1 is applied to a high-voltage / high-current system, such as inverter control in an electric vehicle (EV), the following problems arise. The upper and lower arms in such a high-voltage / high-current system are insulated from each other. A digital isolator such as a photocoupler or magnetic coupler is generally used for signal transmission between the insulated arms, which causes a delay time. Therefore, the arm cannot be driven until an off detection signal arrives from the opposing arm, and this transmission delay time remains as a dead time. In addition, depending on the gate capacitance of the connected power element and the drive voltage and drive current capacity of the driver, the drive delay time from when the gate of the power element starts to be driven until the threshold voltage Vth is exceeded also remains as a dead time.

[0006] In inverter control, the switching of one upper and lower arms includes the driving side switching that passes current through the load, and the rectification side switching that synchronously rectifies the current that flows when the opposing driving side arm is turned off. In conventional technology, the dead time can only be detected and controlled on the rectification side, and a fixed dead time is used on the driving side. Therefore, the dead time cannot be shortened near zero current where the upper and lower arm switching switches between the driving side and the rectification side, and there is a current region where the conduction loss due to the diode connected in parallel to the power element cannot be reduced.

[0007] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a bridge circuit driver that can shorten the dead time even near the zero crossing point of the current. [Means for solving the problem]

[0008] According to the bridge circuit driving device of claim 1, the driving side / rectification side determination unit (36) determines whether the switching of the power element (1, 2) to be driven is performed on the driving side or the rectification side based on the direction of the current flowing between the output terminal of the bridge circuit and the load. The power element is a semiconductor element that constitutes a power conversion circuit such as the above-mentioned inverter and is capable of switching a relatively large amount of power. The delay time detection unit (22) detects and stores the delay time between the timing when the level of the voltage between the conduction terminals of the power element changes and the timing when the level of the drive signal applied to the conduction control terminal changes when switching is performed on the rectification side. The timing adjustment unit (7) adjusts the timing of changing the level of the drive signal so as to be advanced by the detected delay time.

[0009] That is, the delay time detected and stored when the switching of the power element is performed on the rectification side is also applied when the switching is performed on the drive side. This allows the timing adjustment unit to adjust the timing for changing the level of the drive signal even when the switching of the power element is switched between the drive side and the rectification side. This makes it possible to shorten the dead time even near the zero crossing point of the current. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a driver for a bridge circuit according to a first embodiment. [Diagram 2] Timing chart showing the operation of the Δt-ΔV conversion unit [Diagram 3] 1 is a timing chart showing the operation of a timing adjustment unit; [Figure 4] 1 is a flow chart showing the circuit operation of the driving device. [Diagram 5] FIG. 5 is a waveform diagram showing how the rise timing of the voltage Vgs is adjusted according to the control shown in FIG. 4. [Figure 6] Timing chart when lower arm switching is on the rectification side [Figure 7]Timing chart when upper arm switching is on the rectification side [Figure 8] Timing chart showing a longer period including FIG. 6 and FIG. 7 [Figure 9] A simplified timing chart showing the changes in the drive side / rectifier side of the upper and lower arms in response to changes in load current. [Figure 10] FIG. 11 is a diagram showing the configuration of a driver for a bridge circuit according to a second embodiment. [Figure 11] Timing chart showing the operation of the start / stop circuit DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) As shown in Fig. 1, the drive device of this embodiment drives, for example, upper and lower arms of one phase constituting a three-phase inverter, that is, a bridge circuit. Each arm is configured such that power elements 1 and 2, such as N-channel MOSFETs, are connected between DC power supply lines 3P and 3N. Gate voltages Vgs are applied to the gates, which are the conduction control terminals of the power elements 1 and 2, by drive units 4P and 4N of the drive device 4. A drive signal from an inverter control unit 5 is input to the drive units 4P and 4N via insulating units 6P and 6N. The insulating units 6P and 6N are, for example, photocouplers or magnetic couplers.

[0012] The configurations of the drivers 4P and 4N corresponding to the power elements 1 and 2, respectively, are symmetrical, so the power element 1 will be described below. The drive signal is input to an on-timing adjustment unit 7. The on-timing adjustment unit 7 includes a series circuit of a current source 8, a P-channel MOSFET 9, an N-channel MOS 10, and a current source 11, which are connected between a power supply (not shown) and a circuit ground. The gates of the FETs 9 and 10 are commonly connected, and the drive signal is input to the gates via a NOT gate 12. The drains of the FETs 9 and 10 are commonly connected, and the drains are connected to a non-inverting input terminal of a comparator 13 and an inverting input terminal of a comparator 14. The drains are also connected to ground via a capacitor 15.

[0013] An output signal of the sample-and-hold circuit 16 is applied to the inverting input terminal of the comparator 13. A reference voltage is applied to the non-inverting input terminal of the comparator 14. The output signals of the comparators 13 and 14 are input to one of the input terminals of the AND gates 17 and 18, and a drive signal is input to the other of the input terminals. The other input terminal of the AND gate 18 is negative logic. The other terminals of the AND gates 17 and 18 are connected to the set terminal S and reset terminal R of an RS flip-flop 19, respectively. An output terminal Q of the RS flip-flop 19 is connected to an input terminal of a driver 20. The driver 20 outputs a gate voltage Vgs to the gate of the power element 1.

[0014] A series circuit of capacitors 21a and 21b is connected in parallel to the power element 1. An ON-side DT detection unit 22, which corresponds to a delay time detection unit, includes comparators 23 and 24. The non-inverting input terminal of the comparator 23 is connected to the gate of the power element 1, and the non-inverting input terminal of the comparator 24 is connected to the common connection point of the capacitors 21a and 21b. Reference voltages Vg-Ref and Vd-Ref are respectively applied to the inverting input terminals of the comparators 23 and 24. The output terminal of the comparator 23 is connected to the negative input terminal of the phase comparator 25. The output terminal of the comparator 24 is connected to the positive input terminal of the phase comparator 25 via a NOT gate 26. In the following, the dead time may be referred to as "DT".

[0015] The negative output terminal of the phase comparator 25 is connected to one of the input terminals of an AND gate 28 included in the offset adjustment unit 27, and is also connected to an input terminal of a polarity determination unit 29 corresponding to a short circuit determination unit. The output terminal of the comparator 23 is connected to the other input terminal of the AND gate 28 via a one-shot pulse output unit 30.

[0016] The Δt-ΔV conversion unit 31 includes a series circuit of a current source 32, FETs 33 and 34, and a current source 35, which are configured in the same manner as the input unit of the on-timing adjustment unit 7, and a capacitor 36. The gate of the FET 33 is connected to the output terminal of the AND gate 28, and the gate of the FET 34 is connected to the positive output terminal of the phase comparator 25. The drains of the FETs 33 and 34 are connected to the input terminals of the sample-and-hold circuit 16. A reset signal is provided to the sample-and-hold circuit 16 from the polarity determination unit 29.

[0017] The polarity determination unit 29 determines the polarity of the dead time detected by the comparators 23 and 24 based on the signal at the negative output terminal of the phase comparator 25. The comparator 24 and the phase comparator 25 correspond to a level change detection unit. Here, the "polarity of the dead time" is defined as follows. When the detected dead time is obtained as the time from the falling edge of the drain-source voltage Vds, which is the voltage between the conductive terminals, to the rising edge of the gate-source voltage Vgs, the polarity is "positive". Conversely, when the detected dead time is obtained as the time from the rising edge of the gate-source voltage Vgs to the falling edge of the drain-source voltage Vds, the polarity is "negative".

[0018] Furthermore, the polarity determination unit 29 determines that a short circuit has occurred in the upper and lower arms if the polarity of the dead time is negative and the length of the dead time is equal to or greater than a threshold value. In this case, it outputs a forced OFF signal to the driver 20 to stop driving the power element 1 or 2.

[0019] As shown in FIG. 2, if the polarity of the dead time of the power element 1 or 2 is "positive", the Δt-ΔV conversion unit 31 detects the time Δt from the fall of the drain-source voltage Vds to the rise of the gate-source voltage Vgs as the actual dead time; actual DT. A high-level pulse having a time width corresponding to the actual DT is output from the positive output terminal A of the phase comparator 25. If the polarity of the dead time is "negative", the Δt-ΔV conversion unit 31 detects the time Δt from the rise of the gate-source voltage Vgs to the fall of the drain-source voltage Vds as the actual dead time; actual DT. A low-level pulse having a time width corresponding to the actual DT is output from the negative output terminal B. The one-shot pulse output unit 30 outputs a high-level signal by default. Then, a low-level one-shot pulse is output a certain time after the rise of the gate-source voltage Vgs.

[0020] The capacitor 36 is discharged by the current source 35 while the output terminal A indicates a high level. After the output terminal A changes to a low level, while the one-shot pulse output section 30 is outputting a high-level signal, the terminal voltage of the capacitor 36 does not change. The capacitor 36 is The phase comparator 25 also corresponds to a correction unit.

[0021] The voltage output by Δt-ΔV conversion unit 31 indicates a value according to the length of the actual DT. As shown in FIG. 2, when the actual DT is longer than the target dead time; target DT, i.e., the shortest allowable dead time, the output voltage of Δt-ΔV conversion unit 31 is adjusted so that the actual DT approaches the target DT through the action of Δt-ΔV conversion unit 31. The amount by which the output voltage of Δt-ΔV conversion unit 31 drops according to the pulse width Δt of output A of phase comparator 25 corresponds to ΔV. When (actual DT=target DT), the pulse width of output A and the pulse width of the one-shot pulse output by one-shot pulse output unit 30 become equal.

[0022] A current sensor 37 is disposed on the wiring connecting the common connection point of the power elements 1 and 2 and a load (not shown). An output signal of the current sensor 37 is input to a drive side / rectifier side determination unit 38. An output signal of the drive side / rectifier side determination unit 38 is provided to the sample-and-hold circuits 16 and phase comparator 25 of the drive units 4P and 4N via insulating units 39P and 39N.

[0023] A drive side / rectification side determination unit 38 determines, based on the direction of the current detected by the current sensor 37, whether the switching of the power elements 1, 2 is performed on the drive side or the rectification side, as follows. Current direction: Common connection point → Load, Power element 1: Drive side / Power element 2: Rectification side Current direction: Load → Common connection point, Power element 1: Rectification side / Power element 2: Driving side If it is the rectification side, a timing control ON signal is output to the corresponding drive section, and if it is the rectification side, a timing control OFF signal is output to the corresponding drive section.

[0024] As shown in Fig. 3, the input section of the timing adjustment section 7 generates a trapezoidal wave according to the input drive signal. The levels of the rising and falling sections of the trapezoidal wave are compared with the output voltage of the Δt-ΔV conversion section 31 sampled and held by the sample-and-hold circuit 16 as a threshold. If the polarity of the detected dead time is positive, the output voltage of the sample-and-hold circuit 16 decreases and the threshold decreases. Therefore, the signal input to the driver 20 rises earlier. On the other hand, if the polarity of the detected dead time is negative, the output voltage of the sample-and-hold circuit 16 increases and the threshold increases. As a result, the signal input to the driver 20 changes to rise later.

[0025] Next, the operation of this embodiment will be described. As shown in Fig. 4, the driving units 4P and 4N set an initial value of the dead time from the rising edge of the driving signal to the rising edge of the gate-source voltage Vgs; initial DT, as an initial setting (S1). Then, dead time reduction control is started (S2). Then, it is determined whether the power element to be driven is on the rectification side (S3). If it is on the rectification side (Yes), the phase comparator 25 detects the dead time (S4). At that time, the value of the load current is also detected.

[0026] If the polarity of the detected dead time is positive (S5; Yes), it is determined whether the current value and dead time detected this time are smaller than the values ​​stored in the previous process (S6). If the result is "No," the process returns to step S4. On the other hand, if the result is "Yes," the rising timing of the voltage Vgs at that time is stored (S7). Then, the on-timing adjustment unit 7 changes the rising timing of the voltage Vgs so that the detected dead time approaches the target dead time (S8). Then, a drive signal is output to the driver 20 so that the gate of the power element is turned on according to the stored timing (S9). Then, the process proceeds to step S3.

[0027] If the polarity of the detected dead time is negative and the answer is "No" in step S5, it is determined whether the length of the dead time is equal to or less than the short circuit determination threshold (S10). If the length is equal to or less than the short circuit determination threshold and the answer is "Yes", the process proceeds to step S8. If the length exceeds the short circuit determination threshold and the answer is "No", the driver 20 stops turning on the power element. Then, the on-drive timing is initialized (S10) and the process proceeds to step S3. If the arm itself is the driving side and the answer is "No" in step S3, the power element 2 is turned on based on the dead time detected on the rectification side (S12). FIG. 5 shows a state in which the rise timing of the voltage Vgs on the driving side and the rectification side is adjusted as a result of the above control.

[0028] Fig. 6 shows a case where the switching of the power element 2 in the lower arm is on the rectification side, and the switching of the power element 1 in the upper arm is on the drive side. At this time, for the power element 2, the dead time is detected and control for shortening the dead time is executed, and the power element 2 is turned on. Fig. 7 shows a case where the switching of the power element 2 in the lower arm is on the drive side, and the switching of the power element 1 in the upper arm is switched to the rectification side. At this time, the power element 2 is turned on by the dead time stored as a result of the dead time shortening control executed on the rectification side.

[0029] Fig. 8 shows how detection and reduction control of dead time is performed for each arm in response to switching of the lower arm to the drive side / rectification side in response to a change in the load current. Fig. 9 shows, in a simplified manner, how the execution state of the dead time reduction control is switched in response to the load current that changes in a sinusoidal manner.

[0030] As described above, according to this embodiment, in the drive device 4, the drive side / rectification side determination unit 38 determines whether the switching of the power element to be driven is performed on the drive side or the rectification side based on the direction of the current flowing between the load and the output terminal of the bridge circuit consisting of the power elements 1 and 2. The ON side DT detection unit 22 detects and stores the delay time between the timing when the level of the voltage Vds of the power element changes and the timing when the level of the voltage Vgs changes when switching is performed on the rectification side. The timing adjustment unit 7 adjusts the timing to change the level of the drive signal so as to advance it by the detected delay time.

[0031] That is, the delay time detected and stored when the switching of the power elements 1 and 2 is performed on the rectification side is also applied when the switching is performed on the drive side. This allows the timing adjustment unit 7 to adjust the timing for changing the level of the drive signal even when the switching of the power elements is switched between the drive side and the rectification side. This makes it possible to shorten the dead time even near the zero crossing point of the current, and reduce the conduction loss due to the diodes or body diodes connected in parallel to the power elements 1 and 2.

[0032] Furthermore, the polarity determination unit 29 determines the occurrence of a short circuit in which a through current flows between the power element of the own arm and the power element of the opposing arm when the power element of the own arm is turned on. The on-timing adjustment unit 7 shortens the dead time within a range in which the short circuit occurrence is not determined by the short circuit determination unit 29 and so that the current flowing when the power element of the own arm is turned on is smaller than a threshold value. This allows adjustment to the shortest dead time possible to avoid the occurrence of a short circuit.

[0033] In addition, the short circuit determination unit 29 determines that a short circuit has occurred if the length of the dead time during which the polarity becomes negative is equal to or greater than a threshold value, as the timing at which the level of the voltage Vgs changes is earlier than the timing at which the level of the voltage Vds changes, and if it determines that a short circuit has occurred, it stops driving the power element 1 or 2.

[0034] Furthermore, Δt-ΔV conversion section 31 of timing adjustment section 7 generates a voltage ΔV according to the dead time Δt. Triggered by a change in the level of voltage Vds detected by comparator 24, phase comparator 25 reduces the input voltage by voltage ΔV. By adding the action of the one-shot pulse output by one-shot pulse output section 30 to this action, it is possible to adjust actual DT to be equal to target DT.

[0035] Second embodiment In the following, the same parts as those in the first embodiment are denoted by the same reference numerals and their explanations are omitted, and only the different parts are explained. As shown in Fig. 10, a drive device 41 in the second embodiment is configured by adding a start / stop circuit 42 to the drive device 4. A drive signal is input to the start / stop circuit 42, and the start / stop circuit 42 outputs a start / stop signal to the comparators 23 and 24 and the phase comparator 25.

[0036] 11, the start / stop circuit 42 keeps the start / stop signal at high level for a certain period of time from the rising edge of the start signal, and then changes it to low level. The comparators 23 and 24 and the phase comparator 25 operate during the period when the start / stop signal indicates a high level, and stop operating during the period when the start / stop signal indicates a low level. Therefore, the dead time is detected during the period when the start / stop signal indicates a high level.

[0037] That is, the dead time may be detected during the period related to the fall of the voltage Vds and the period related to the rise of the voltage Vgs. For the other periods, the dead time detection may be stopped by the start / stop signal, thereby avoiding the influence of noise.

[0038] (Other embodiments) The power element is not limited to an N-channel MOSFET. The off-timing of the power elements may be controlled in a similar manner, or both the on-timing and the off-timing may be controlled. The bridge circuit is not limited to one that constitutes a three-phase inverter, and may be one that constitutes a single half-bridge circuit or an H-bridge circuit. Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0039] In the drawing, 1 and 2 indicate power elements, 4 indicates a drive device, 7 indicates an on-timing adjustment unit, 22 indicates an on-side DT detection unit, 23 and 24 indicate comparators, 25 indicates a phase comparator, 27 indicates an offset adjustment unit, 29 indicates a polarity detection unit, 31 indicates a Δt-ΔV conversion unit, and 38 indicates a drive side / rectification side determination unit.

Claims

1. The power element driving circuit drives the conduction control terminal of one of two power elements (1, 2) connected in series to form the upper and lower arms of a bridge circuit. a drive side / rectification side determination unit (36) that determines whether switching of the power element is performed on the drive side or the rectification side based on the direction of a current flowing between the output terminal of the bridge circuit and a load; a delay time detection unit (22) that detects and stores a delay time between a timing at which a voltage level between the conduction terminals of the power element changes and a timing at which a level of a drive signal applied to the conduction control terminal changes when the switching is performed on the rectification side; and a timing adjustment unit (7) that adjusts the timing of changing the level of the drive signal so as to advance it by the delay time.

2. a short circuit determination unit (29) for determining the occurrence of a short circuit in which a through current flows between the power element of the opposing arm when the power element is turned on, 2. The bridge circuit driving device according to claim 1, wherein the on-timing adjustment unit shortens the delay time to a range in which the occurrence of the short circuit is not determined by the short circuit determination unit and such that a current flowing through the power element when the power element is turned on is smaller than a threshold value.

3. the short circuit determination unit determines that the short circuit has occurred if a delay time during which the polarity becomes negative due to a timing at which the level of the drive signal changes in response to the timing at which the level of the voltage between the conductive terminals changes is equal to or greater than a threshold value; 3. The bridge circuit driver according to claim 2, wherein the driving of the power elements is stopped when the occurrence of the short circuit is determined.

4. 2. The bridge circuit driver according to claim 1, wherein the timing adjustment section performs the adjustment for either one of a case where the power element is turned on and a case where the power element is turned off.

5. The timing adjustment unit includes a Δt-ΔV conversion unit (31) that generates a voltage ΔV corresponding to the delay time Δt; a level change detection unit (24) for detecting a change in the level of the voltage between the conductive terminals; 2. The bridge circuit driver according to claim 1, further comprising a correction section (25) that reduces the value of the voltage ΔV by a fixed value using the change in the level as a trigger.

6. a start signal output unit (42) that outputs a start signal for a certain period of time from the timing when the level of the drive signal rises; The bridge circuit driver according to claim 1 , wherein the delay time detector detects the delay time during a period in which the start signal is output.

Images