Wiring circuit board and manufacturing method of wiring circuit board

Abstract

To provide a wiring circuit board capable of reducing occurrence of a transmission loss while improving a degree of freedom in design of wiring, and a manufacturing method of a wiring circuit board.SOLUTION: A first via part 110 is formed within a through hole 11 of a first insulation layer 10. A first terminal part 120 and a plurality of first wiring parts 130 are formed on the first insulation layer 10. The first terminal part 120 includes: a first end face and a second end face which are mutually turned in opposite directions in a lamination direction DL of a wiring circuit board; and a cylindrical outer peripheral surface connecting an outer edge of the first end face with an outer edge of the second end face. The first end face is in contact with the first insulation layer 10 and the first via part 110, and the second end face is a face to which a terminal of an electrical element is connected. A thickness of the first terminal part 120 is larger than a thickness of the first wiring part 130. The outer peripheral surface of the first terminal part 120 is formed flat in the lamination direction DL.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wired circuit board and a method for manufacturing the wired circuit board. [Background technology]

[0002] For example, a wired circuit board is used to transmit and receive electrical signals between a plurality of electronic components. Among wired circuit boards, there is a multilayer wired circuit board having a multilayer structure in which a plurality of wires are formed on a plurality of laminated insulating layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-202249 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a multilayer wiring circuit board, vias are formed penetrating one or more insulating layers to ensure electrical conduction between the insulating layers. In order to expand the range of possible electrical conduction in the stacking direction of the multilayer wiring circuit board, multiple vias may be formed so as to be continuous in the stacking direction. For example, the wiring board described in Patent Document 1 includes many via conductors (stacked via conductors) in which two vias are stacked.

[0005] As described above, a configuration in which multiple vias are stacked (hereinafter referred to as a via series) improves the degree of freedom of wiring inside a printed circuit board. However, each of the multiple vias is usually formed integrally with a land or pad for connecting other electrical conductive paths (vias or terminals, etc.) on the via. Therefore, the via series is likely to have a complex shape. The complexity of the shape of a signal transmission path such as vias and wiring causes a large transmission loss in the transmission path.

[0006] An object of the present invention is to provide a wired circuit board and a method for manufacturing the wired circuit board that can reduce the occurrence of transmission loss while improving the degree of freedom in wiring design. [Means for solving the problem]

[0007] A wired circuit board according to one aspect of the present invention has a laminated structure made of a plurality of layers, and to which an electrical element is connected, and includes: a first insulating layer having a first through hole; a first via portion formed in the first through hole; a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion; a first wiring portion formed on the first insulating layer; and a second insulating layer, wherein the first terminal portion has a first end face and a second end face having a common shape and facing in opposite directions to each other in a lamination direction of the wired circuit board, and a second wiring portion formed on the first insulating layer such that an outer edge of the first end face and an outer edge of the second end face are connected to each other. the first end face is a surface that contacts the first insulating layer and the first via portion, the second end face is a surface to which a terminal of the electrical element will be connected, the second insulating layer is formed on the first insulating layer to cover the outer circumferential surface of the first terminal portion and the first wiring portion while exposing at least a portion of the second end face, a distance between the first end face and the second end face of the first terminal portion in the stacking direction is greater than a thickness of the first wiring portion in the stacking direction, and the outer circumferential surface of the first terminal portion is formed flat in the stacking direction.

[0008] A wired circuit board according to another aspect of the present invention has a laminated structure made of a plurality of layers, and to which electrical elements are connected, and includes a first insulating layer having a first through hole, a first via portion formed in the first through hole, a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion, a first wiring portion formed on the first insulating layer, and a second insulating layer formed on the first insulating layer so as to expose a portion of the first terminal portion and cover the remaining portion of the first terminal portion and the first wiring portion. and a second insulating layer formed on the first insulating layer as described above, wherein the first wiring portion has a third end face and a fourth end face having a common band shape and facing opposite directions in a stacking direction of the wired circuit board, and a pair of side faces extending in the stacking direction so as to connect both sides of the third end face and both sides of the fourth end face, respectively, a thickness of the first wiring portion in the stacking direction is greater than a thickness of the first terminal portion, and each of the pair of side faces of the first wiring portion is formed flat in the stacking direction.

[0009] According to yet another aspect of the present invention, there is provided a method for manufacturing a wired circuit board having a laminated structure made of a plurality of layers, to which electrical elements are connected, the method including the steps of: forming a resist film made of a photosensitive material on one surface of a first insulating layer having a through hole; removing a first portion of the resist film that overlaps the through hole of the first insulating layer in a plan view by photolithography after the formation of the resist film to form a first opening; filling a conductor inside the through hole of the first insulating layer after the formation of the first opening to form a via portion, and filling a partial region of an internal space of the first opening of the resist film with a conductor to form a terminal lower layer portion on the via portion; and after forming the lower-layer terminal portion, removing a second portion of the resist film that is separated from the through hole of the first insulating layer in a planar view by photolithography to form a second opening; after forming the second opening, forming an upper-layer terminal portion on the lower-layer terminal portion by filling a conductor into the remaining area of ​​the internal space of the first opening of the resist film, and forming a wiring portion on the first insulating layer by filling a conductor into the internal space of the second opening of the resist film; after forming the upper-layer terminal portion and the wiring portion, removing the resist film remaining on the first insulating layer; and after removing the resist film, forming a second insulating layer on the first insulating layer. Effect of the Invention

[0010] According to the present invention, it is possible to improve the degree of freedom in wiring design while suppressing a decrease in transmission loss. [Brief description of the drawings]

[0011] [Figure 1] 1A and 1B are a schematic side view and a partially enlarged plan view of a rewiring substrate according to a first embodiment; [Diagram 2] 2 is a cross-sectional view taken along line AA in the partially enlarged plan view of FIG. [Diagram 3] 3 is a partial enlarged view of a first terminal portion in FIG. 2. [Figure 4] FIG. 2 is a schematic side view showing an example of a roll-to-roll apparatus used in the manufacturing process of a rewiring substrate. [Diagram 5] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 6] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 7] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 8] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 9] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 10] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 11] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 12] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 13] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 14] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 15] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 16] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 17] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 18] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 19] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 20] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 21] 1. FIG. 4 is a schematic cross-sectional view for explaining a first example of a method for manufacturing the rewiring board of FIG. [Figure 22] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 23] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Figure 24] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 25] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Figure 26] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Figure 27] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Figure 28] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Figure 29] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 30] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 31] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 32] 1. FIG. 4 is a schematic cross-sectional view for explaining a second example of the method for manufacturing the rewiring board of FIG. [Diagram 33] FIG. 11 is a cross-sectional view of a rewiring substrate according to a second embodiment. [Diagram 34] FIG. 11 is a cross-sectional view showing an example of a rewiring substrate according to another embodiment. [Diagram 35] FIG. 11 is a cross-sectional view showing another example of a rewiring substrate according to another embodiment. [Diagram 36]FIG. 11 is a cross-sectional view showing still another example of a rewiring substrate according to another embodiment. [Figure 37] FIG. 11 is a cross-sectional view showing an example of a printed circuit board according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a wired circuit board and a method for manufacturing the wired circuit board according to an embodiment of the present invention will be described with reference to the drawings. As an example of a wired circuit board, a rewired board will be described. The rewired board is disposed between an electronic component such as a semiconductor element and another wired circuit board such as a rigid printed wiring circuit board (hereinafter abbreviated as a rigid board), and serves to convert the pitch between the fine pattern of the electronic component and the coarse pattern of the other wired circuit board. The rewired board is also called an interposer board.

[0013] 1. First embodiment <1> Basic structure of rewiring board FIG. 1 is a schematic side view and a partially enlarged plan view of a rewiring substrate according to a first embodiment. The upper part of FIG. 1 shows a configuration example in which a rewiring substrate 1 is disposed between a semiconductor element 700 and a rigid substrate 800. The rewiring substrate 1 has a first surface 1A and a second surface 1B facing in opposite directions. In the configuration example of FIG. 1, the second surface 1B of the rewiring substrate 1 is connected to the rigid substrate 800 using a plurality of solder balls. In addition, a semiconductor element 700 is mounted on the first surface 1A of the rewiring substrate 1 using a plurality of solder balls.

[0014] At the bottom of Fig. 1, a partially enlarged plan view of the rewiring substrate 1 is shown in a balloon drawn from a part (part framed by a dotted line) of the rewiring substrate 1 shown at the top of Fig. 1. Fig. 2 is a cross-sectional view taken along line AA in the partially enlarged plan view of Fig. 1. The basic configuration of the rewiring substrate 1 will be described based on the partially enlarged plan view of Fig. 1 and the partially enlarged cross-sectional view of Fig. 2.

[0015] The rewiring substrate 1 according to the present embodiment has a laminated structure made up of multiple layers. In the following description, the direction in which multiple layers are laminated in the rewiring substrate 1 is referred to as the lamination direction DL. The lamination direction DL is generally perpendicular to the multiple layers constituting the rewiring substrate 1, and can also be referred to as the thickness direction of the rewiring substrate 1. In FIG. 1 and certain figures following FIG. 2, the lamination direction DL is indicated by an arrow pointing from the second surface 1B of the rewiring substrate 1 to the first surface 1A.

[0016] 2, the rewiring substrate 1 includes a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a metal support 90. The rewiring substrate 1 also includes a first via portion 110, a first terminal portion 120, two first wiring portions 130, a second via portion 210, a second terminal portion 220, and two second wiring portions 230.

[0017] The metal support 90 is a plate-like member made of metal, and is formed of, for example, stainless steel. The metal support 90 may be formed of any of copper, copper alloy, aluminum, titanium, or an alloy containing iron and nickel, instead of stainless steel. The metal support 90 has a higher rigidity than the multiple insulating layers (10, 20, 30, 40). The metal support 90 is located approximately at the center of the rewiring substrate 1 in the stacking direction DL, and has a first support surface 91 and a second support surface 92 that face in opposite directions in the stacking direction DL. The metal support 90 further has a through hole 93 that extends in the stacking direction DL from the first support surface 91 to the second support surface 92. In this embodiment, the through hole 93 has a circular shape in a plan view seen in the stacking direction DL (see the balloon in FIG. 1). The through hole 93 may be formed in an elliptical shape in a plan view, or may have a polygonal shape. The thickness of the metal support 90 is not less than 10 μm and not more than 100 μm.

[0018] The first insulating layer 10 is made of a photosensitive material and is laminated on the first support surface 91 of the metal support 90. The first insulating layer 10 covers the first support surface 91 and also covers the inner circumferential surface of the through hole 93 of the metal support 90. The thickness of the first insulating layer 10, more specifically, the thickness of the portion of the first insulating layer 10 located on the first support surface 91, is 3 μm or more and 20 μm or less. The first insulating layer 10 also has a through hole 11 extending in the lamination direction DL. The through hole 11 of the first insulating layer 10 is formed so as to pass through the inside of the through hole 93 of the metal support 90, and has a circular shape in a plan view (see the balloon in FIG. 1).

[0019] A first via portion 110 is formed so as to fill the inside of the through hole 11 of the first insulating layer 10. The first via portion 110 is made of a metal material having electrical conductivity. The first via portion 110 has a circular shape in a plan view (see the balloon in FIG. 1), and its diameter is 10 μm or more and 200 μm or less.

[0020] A first terminal portion 120 and two first wiring portions 130 are formed on the first insulating layer 10. The first terminal portion 120 is made of a metal material having electrical conductivity. The first terminal portion 120 overlaps the first via portion 110 in a plan view (see the balloon in FIG. 1) and is directly connected to the first via portion 110. The first terminal portion 120 also includes a terminal lower layer portion 121 and a terminal upper layer portion 122. The terminal lower layer portion 121 and the terminal upper layer portion 122 are layered in this order on the first insulating layer 10.

[0021] The thickness of the first terminal portion 120 is greater than the thickness of the two first wiring portions 130 described below, and is between 1 μm and 15 μm. The first terminal portion 120 has a circular shape in a plan view (see the balloon in FIG. 1) and a diameter between 20 μm and 300 μm. The shape of the first terminal portion 120 will be described in detail later.

[0022] Each of the two first wiring parts 130 is made of a metal material having electrical conductivity. As shown in the balloon in Fig. 1, the two first wiring parts 130 are formed on the first insulating layer 10 so as to be adjacent to each other with a gap therebetween in a plan view and to extend in parallel in one direction. In the example of Figs. 1 and 2, the two first wiring parts 130 are spaced apart from the first terminal part 120 on the first insulating layer 10.

[0023] The thickness of the two first wiring parts 130 is 3 μm or more and 10 μm or less. Moreover, the width d1 (FIG. 2) of each of the two first wiring parts 130 is less than 15 μm, and the distance d2 (FIG. 2) between the two first wiring parts 130 is less than 15 μm. This allows multiple wirings to be designed at high density on the first insulating layer 10. It is preferable that the width d1 of each of the two first wiring parts 130 is 2 μm or less, and the distance d2 between the two first wiring parts 130 is 2 μm or less. In this case, multiple wirings can be designed at high density on the first insulating layer 10.

[0024] The second insulating layer 20 is made of a photosensitive material and is laminated on the first insulating layer 10 as shown in FIG. 2. The second insulating layer 20 covers the other parts of the first terminal parts 120 while exposing a part of the first terminal parts 120, and covers the two first wiring parts 130. In the example of FIG. 2, one surface of the second insulating layer 20 exposed in the direction of the arrow of the lamination direction DL constitutes the first surface 1A of the rewiring substrate 1. The thickness of the second insulating layer 20 is 3 μm or more and 20 μm or less. The terminals of the semiconductor element 700 (FIG. 1) are connected to the parts of the first terminal parts 120 that are not covered by the second insulating layer 20 via solder balls.

[0025] The third insulating layer 30 is made of a photosensitive material and is laminated on the second support surface 92 of the metal support 90. In FIG. 2, the third insulating layer 30 covers the second support surface 92 from below and covers the portion of the first insulating layer 10 located in the through hole 93 of the metal support 90. The thickness of the third insulating layer 30 is 3 μm or more and 20 μm or less. The third insulating layer 30 has a through hole 31 extending in the lamination direction DL. The through hole 31 of the third insulating layer 30 overlaps with the through hole 11 of the first insulating layer 10 in a plan view and has the same shape as the through hole 11 in a plan view (see the balloon in FIG. 1).

[0026] The second via portion 210 is formed so as to fill the inside of the through hole 31 of the third insulating layer 30. The second via portion 210 is made of a metal material having electrical conductivity, overlaps the first via portion 110 in a plan view, and has the same shape as the first via portion 110 in a plan view (see the balloon in FIG. 1). The second via portion 210 is also directly connected to the first via portion 110.

[0027] A second terminal portion 220 and two second wiring portions 230 are formed on the third insulating layer 30. The second terminal portion 220 is made of a metal material having electrical conductivity. The second terminal portion 220 overlaps the second via portion 210 in a plan view (see the balloon in FIG. 1) and is directly connected to the second via portion 210. The second terminal portion 220 has a shape that is basically symmetrical to the first terminal portion 120 with respect to a plane perpendicular to the stacking direction DL. Therefore, the second terminal portion 220 includes a terminal lower layer portion 221 and a terminal upper layer portion 222 that respectively correspond to the terminal lower layer portion 121 and the terminal upper layer portion 122 of the first terminal portion 120. The terminal lower layer portion 221 and the terminal upper layer portion 222 are stacked on the third insulating layer 30 in this order.

[0028] Each of the two second wiring parts 230 is made of a metal material having electrical conductivity. As shown in the balloon in Fig. 1, the two second wiring parts 230 are formed on the third insulating layer 30 so as to be adjacent to each other with a gap therebetween in a plan view and to extend in parallel in one direction. In Figs. 1 and 2, the two second wiring parts 230 are spaced apart from the second terminal part 220 on the third insulating layer 30.

[0029] The thickness of the two second wiring parts 230 is smaller than the thickness of the second terminal part 220, and is 3 μm or more and 10 μm or less. The width of each of the two second wiring parts 230 is less than 15 μm, similar to the width d1 of the first wiring part 130. The distance between the two second wiring parts 230 is less than 15 μm, similar to the distance d2 between the two first wiring parts 130. The thickness and width of the second wiring part 230 may be the same as the thickness d1 and width d2 of the first wiring part 130, or may be different. The distance between the two second wiring parts 230 may be the same as the distance d2 between the two first wiring parts 130, or may be different.

[0030] The fourth insulating layer 40 is made of a photosensitive material and is laminated on the third insulating layer 30 as shown in FIG. 2. In FIG. 2, the fourth insulating layer 40 exposes a part of the second terminal portion 220 from below, covers the other part of the second terminal portion 220, and covers the two second wiring portions 230. In the example of FIG. 2, one surface of the fourth insulating layer 40 exposed in the direction opposite to the arrow of the lamination direction DL constitutes the second surface 1B of the rewiring substrate 1. The thickness of the fourth insulating layer 40 is 3 μm or more and 20 μm or less. The terminal of the rigid substrate 800 (FIG. 1) is connected to the part of the second terminal portion 220 that is not covered by the fourth insulating layer 40 via a solder ball.

[0031] Here, for example, photosensitive polyimide is used as the photosensitive material constituting the above-mentioned multiple insulating layers (10, 20, 30, 40). Note that the first insulating layer 10 may be formed of other photosensitive resins (acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, polyvinyl chloride resin, or other photosensitive resins) instead of photosensitive polyimide.

[0032] Moreover, each of the above-mentioned via portions (110, 210), terminal portions (120, 220), and wiring portions (130, 230) is formed by growing a plating layer on a seed layer by electrolytic plating. In this case, the seed layer is made of, for example, a chromium thin film and a copper thin film. Alternatively, the seed layer is made of a copper thin film. Alternatively, the seed layer may contain either nickel or palladium. Meanwhile, the plating layer is formed of a metal or an alloy containing one or more of copper, gold, silver, platinum, lead, tin, nickel, cobalt, indium, rhodium, chromium, tungsten, ruthenium, and the like. In this embodiment, the plating layer is copper.

[0033] <2> Details of the shape of the first terminal portion 120 The shape of the first terminal portion 120 of the rewiring substrate 1 in Fig. 2 will be described in detail. Fig. 3 is a partial enlarged view of the first terminal portion 120 in Fig. 2. As shown in Fig. 3, the first terminal portion 120 according to this embodiment has a first end face 123 and a second end face 124 that face in opposite directions to each other in the stacking direction DL. The first end face 123 and the second end face 124 have a common shape (circular in this example).

[0034] The first end face 123 is a face in contact with the first insulating layer 10 and the first via portion 110. The second end face 124 is a face to which a terminal of the semiconductor element 700 is to be connected. In the example of FIG. 3, an opening 21 is formed in a part of the second insulating layer 20 constituting the first face 1A such that a part of the second end face 124 is exposed on the second insulating layer 20.

[0035] Furthermore, the first terminal portion 120 has a tubular (in this example, cylindrical) outer peripheral surface 125 extending in the stacking direction DL so as to connect the outer edge of the first end face 123 when viewed in a plane and the outer edge of the second end face 124 when viewed in a plane.

[0036] As described above, first terminal portion 120 has a configuration in which terminal lower layer portion 121 and terminal upper layer portion 122 are laminated, and the thickness of first terminal portion 120 is greater than the thickness of first wiring portion 130. Here, as shown by the thick dotted line in Fig. 3, if a step is formed in outer peripheral surface 125 between terminal lower layer portion 121 and terminal upper layer portion 122 in the lamination direction DL, transmission loss due to the shape of first terminal portion 120 is likely to occur.

[0037] Therefore, the outer peripheral surface 125 of the first terminal portion 120 according to this embodiment is formed flat in the stacking direction DL, as shown by the thick solid line in Fig. 3. That is, on the outer peripheral surface 125 of the first terminal portion 120, no step is formed in the stacking direction DL between the terminal lower layer portion 121 and the terminal upper layer portion 122. This reduces the occurrence of transmission loss in the first terminal portion 120.

[0038] In the rewiring substrate 1 according to the present embodiment, the second terminal portion 220 has a shape that is basically symmetrical to the first terminal portion 120 with respect to a plane perpendicular to the stacking direction DL. Thus, like the first terminal portion 120, the second terminal portion 220 also has an outer peripheral surface that extends in the stacking direction DL, and the outer peripheral surface is formed flat in the stacking direction DL. Therefore, the occurrence of transmission loss in the second terminal portion 220 is reduced.

[0039] <3> First Example of Manufacturing Method of Rewiring Substrate 1 In the present embodiment, the rewiring substrate 1 is manufactured by, for example, a roll-to-roll method. Fig. 4 is a schematic side view showing an example of a roll-to-roll apparatus used in the manufacturing process of the rewiring substrate 1.

[0040] 4, the roll-to-roll apparatus 500 includes an unwinding section 501, a winding section 502, and a plurality of processing sections 510, 520, .... First, a roll (unwinding roll) R1 around which a long metal support 90 is wound is prepared and set in the unwinding section 501 of the roll-to-roll apparatus 500.

[0041] The metal support 90 is unwound from a prepared unwinding roll R1. The unwound metal support 90 is taken up by another roll (take-up roll) R2 set in a winding section 502, as indicated by the dotted arrow in FIG.

[0042] In the roll-to-roll apparatus 500, a plurality of processing sections 510, 520, ... are arranged between two rolls (R1, R2) in a line along the moving direction of the metal support 90. The plurality of processing sections 510, 520, ... respectively form the above-mentioned plurality of insulating layers (10, 20, 30, 40), the plurality of via sections (110, 210), the plurality of terminal sections (120, 220), and the plurality of wiring sections (130, 230) on the long metal support 90 moving between the two rolls (R1, R2). As a result, a plurality of rewiring substrates 1 are formed on the metal support 90 wound up on the winding roll R2. The manufacturing method of the rewiring substrate 1 will be described in detail below.

[0043] 5 to 21 are schematic cross-sectional views for explaining a first example of a method for manufacturing the rewiring substrate 1 of Fig. 1. The schematic cross-sectional views shown in Fig. 5 to 21 correspond to the schematic cross-sectional views of the portion of the rewiring substrate 1 of Fig. 1 shown in Fig. 2.

[0044] As described above, a supply roll R1 (FIG. 4) around which the metal support 90 is wound is prepared, and the metal support 90 is unwound from the supply roll R1. As shown in FIG. 5, a carrier film 98 is attached to the second support surface 92 of the unwound metal support 90.

[0045] 6, a through hole 93 extending from the first support surface 91 to the second support surface 92 is formed in a predetermined portion of the metal support 90. This through hole 93 is formed, for example, by forming an etching resist having an opening corresponding to the through hole 93 on the first support surface 91 and etching the metal support 90.

[0046] Next, as shown in FIG. 7, a first insulating layer 10 is formed on a first support surface 91 of the metal support 90. Specifically, the first insulating layer 10 is formed, for example, as follows. First, a photosensitive polyimide solution (varnish) is applied onto the first support surface 91 so as to cover the entire first support surface 91 of the metal support 90. At this time, the photosensitive polyimide solution is also filled into the through hole 93 of the metal support 90. Thereafter, the applied photosensitive polyimide solution is exposed to light and developed. As a result, as shown in FIG. 7, a first insulating layer 10 is formed on the first support surface 91 of the metal support 90. The first insulating layer 10 further covers the inner circumferential surface of the through hole 93 of the metal support 90, and has a through hole 11 inside the through hole 93 that exposes one surface of the carrier film 98 onto the first insulating layer 10. Instead of applying a solution of photosensitive polyimide onto first supporting surface 91, first insulating layer 10 may be formed by attaching a carrier film made of photosensitive polyimide.

[0047] 7, a seed layer is formed on the exposed portion of the first insulating layer 10 and the portion of the carrier film 98 exposed in the through hole 11. In the figures subsequent to FIG. 7, the seed layer is basically omitted.

[0048] Next, as shown in FIG. 8, a layer of plating resist 80 is formed on the first insulating layer 10. At this time, the plating resist 80 is formed so as to fill the through holes 11 of the first insulating layer 10. Specifically, the plating resist 80 is formed, for example, as follows. First, a solution (varnish) of a positive photosensitive resin is applied onto the first insulating layer 10. After the solution spreads over the entire surface of the first insulating layer 10 and fills the through holes 11, the solution is dried. As a result, the components of the solution are hardened, and the plating resist 80 is formed. Note that the plating resist 80 may be formed by attaching a dry film resist made of a positive photosensitive resin instead of applying a solution of a photosensitive resin onto the first insulating layer 10.

[0049] Next, as shown in FIG. 9, a portion of the plating resist 80 overlapping the through hole 11 of the first insulating layer 10 in a plan view is irradiated with exposure light corresponding to the photosensitive resin of the plating resist 80. Thereafter, the plating resist 80 is developed. If the plating resist 80 is made of a positive photosensitive resin, the exposed portion dissolves in a developer. Thereby, as shown in FIG. 10, a first opening 81 is formed by photolithography in a portion of the plating resist 80 overlapping the through hole 11 of the first insulating layer 10 in a plan view (a portion where the first terminal portion 120 in FIG. 2 should be formed). In addition, the plating resist 80 in the through hole 11 of the first insulating layer 10 is removed.

[0050] In the state of FIG. 10, a seed layer is formed inside and at the bottom of the through hole 11. Also, a seed layer is formed on the portion of the first insulating layer 10 overlapping the first opening 81. Electrolytic plating is performed using these seed layers. As a result, as shown in FIG. 11, the inside of the through hole 11 of the first insulating layer 10 is filled with a conductor (copper in this example), and a first via portion 110 is formed. Also, a partial region of the internal space of the first opening 81 of the plating resist 80 is filled with a conductor (copper in this example), and a terminal lower layer portion 121 is formed on the first via portion 110.

[0051] Next, as shown in Fig. 12, exposure light corresponding to the photosensitive resin of the plating resist 80 is irradiated to a portion of the plating resist 80 that is separated from the through hole 11 of the first insulating layer 10 in a plan view. In the example of Fig. 12, exposure light is irradiated to two portions of the plating resist 80 that are separated by a predetermined distance from the first opening 81. Thereafter, the plating resist 80 is developed. Thereby, as shown in Fig. 13, two second openings 82 are formed by photolithography in the portions of the plating resist 80 that are separated from the through hole 11 of the first insulating layer 10 in a plan view (portions where the two first wiring portions 130 in Fig. 2 should be formed).

[0052] In the state of FIG. 13, the end face of the terminal lower layer 121 is exposed inside the first opening 81. A seed layer is also formed in a portion of the first insulating layer 10 overlapping the two second openings 82. Electrolytic plating is performed using the terminal lower layer 121 and the seed layer. Thereby, as shown in FIG. 14, a conductor (copper in this example) is filled in the remaining region of the internal space of the first opening 81 of the plating resist 80, and a terminal upper layer 122 is formed on the terminal lower layer 121. Also, a conductor (copper in this example) is filled in a partial region of the internal space of the two second openings 82 of the plating resist 80, and two first wiring portions 130 are formed.

[0053] Next, as shown in FIG. 15, the plating resist 80 is peeled off from the first insulating layer 10. The plating resist 80 in this example is made of a positive-type photosensitive resin. Therefore, the plating resist 80 is peeled off, for example, by irradiating the entire plating resist 80 remaining on the first insulating layer 10 with exposure light and developing the exposed plating resist 80. When the plating resist 80 is formed of a dry film resist made of a positive-type photosensitive resin, the plating resist 80 can be removed by exposing and developing the entire plating resist 80 as in the above example. Thereafter, a seed layer (not shown) formed on the first insulating layer 10 and in a portion where the first terminal portion 120 and the two first wiring portions 130 are not formed is removed by etching.

[0054] Next, as shown in Fig. 16, a second insulating layer 20 is formed on the first insulating layer 10 so as to cover the first terminal portion 120 and the two first wiring portions 130. At this time, an opening 21 is formed in the second insulating layer 20 so as to expose a part of the first terminal portion 120. This completes the configuration formed on the first support surface 91 of the metal support 90 of the rewiring substrate 1 of Fig. 1. This causes the carrier film 98 to be peeled off from the second support surface 92 of the metal support 90.

[0055] Next, a structure to be formed on a second support surface 92 of the metal support 90 is produced in substantially the same manner as the structure to be formed on the first support surface 91 of the metal support 90. In Figures 17 to 21, cross-sectional views of an intermediate body of the rewiring substrate 1 are shown in a state inverted in the stacking direction DL with respect to the cross-sectional views of Figures 5 to 16.

[0056] First, as shown in FIG. 17, a third insulating layer 30 is formed on the second support surface 92 of the metal support 90. The third insulating layer 30 is formed, for example, in the same manner as the formation of the first insulating layer 10, by applying a solution of photosensitive polyimide on the second support surface 92, exposing the solution, and developing it. The third insulating layer 30 formed in this example has a through hole 31 that exposes the first via portion 110 on the third insulating layer 30. Note that, like the example of the first insulating layer 10, the third insulating layer 30 may be formed by attaching a carrier film made of photosensitive polyimide instead of applying a solution of photosensitive polyimide on the second support surface 92. Thereafter, as shown by a thick solid line in FIG. 17, a seed layer is formed on the exposed portion of the third insulating layer 30 and the portion of the first via portion 110 exposed in the through hole 31.

[0057] Next, as shown in FIG. 18, a layer of plating resist 70 is formed on the third insulating layer 30. At this time, the plating resist 70 is formed so as to fill the through holes 31 of the third insulating layer 30. The material of the plating resist 70 may be the same as the material of the plating resist 80 described above, or may be a material different from the material of the plating resist 80. When the material of the plating resist 70 is the same as the material of the plating resist 80, the plating resist 70 is formed on the third insulating layer 30 by the same method as the formation of the plating resist 80 on the first insulating layer 10, for example.

[0058] Next, exposure light corresponding to the photosensitive resin of the plating resist 70 is irradiated to a portion of the plating resist 70 in Fig. 18 that overlaps with the through hole 11 of the first insulating layer 10 in a plan view. The plating resist 70 is also developed. As a result, as shown in Fig. 19, a third opening 71 is formed by photolithography in a portion of the plating resist 70 that overlaps with the through hole 11 of the first insulating layer 10 in a plan view (a portion where the second terminal portion 220 in Fig. 2 should be formed).

[0059] Furthermore, electrolytic plating is performed using the seed layer exposed in the internal space of the third opening 71. As a result, the inside of the through hole 31 of the third insulating layer 30 is filled with a conductor (copper in this example), and the second via portion 210 is formed. Furthermore, a partial region of the internal space of the third opening 71 of the plating resist 70 is filled with a conductor (copper in this example), and the terminal lower layer portion 221 is formed on the second via portion 210.

[0060] Next, exposure light corresponding to the photosensitive resin of the plating resist 70 is irradiated to a portion of the plating resist 70 that is separated from the through hole 11 of the first insulating layer 10 in a plan view. The plating resist 70 is developed. As a result, as shown in FIG. 20, two fourth openings 72 are formed by photolithography in a portion of the plating resist 70 that is separated from the through hole 11 of the first insulating layer 10 in a plan view (a portion where the two second wiring parts 230 in FIG. 2 should be formed). In addition, electrolytic plating is performed using the terminal lower layer part 221 exposed in the third opening 71 and the seed layer exposed in the two fourth openings 72. As a result, the terminal upper layer part 222 is formed on the terminal lower layer part 221 in the third opening 71. In addition, two second wiring parts 230 are formed in the two fourth openings 72 of the plating resist 70.

[0061] 21, the plating resist 70 is stripped from the third insulating layer 30, and the seed layer (not shown) exposed on the third insulating layer 30 is removed by etching. Finally, a fourth insulating layer 40 is formed on the third insulating layer 30, thereby completing the rewiring substrate 1 of FIG. 1. The fourth insulating layer 40 is formed by the same method as the method for forming the second insulating layer 20 on the first insulating layer 10.

[0062] <4> Second Example of Manufacturing Method of Rewiring Substrate 1 In addition to the first example of the manufacturing method described above, the rewiring substrate 1 can also be manufactured according to a second example described below. FIGS. 22 to 32 are schematic cross-sectional views for explaining the second example of the manufacturing method of the rewiring substrate 1 of FIG. 1. The schematic cross-sectional views shown in FIGS. 22 to 32 correspond to the schematic cross-sectional views of the part of the rewiring substrate 1 of FIG. 1 shown in FIG. 2, similarly to FIGS. 5 to 21. In short, the second example of the manufacturing method of the rewiring substrate 1 is basically the same as the first example of the manufacturing method of the rewiring substrate 1, except that the carrier film 98 of FIG. 5 is not used. In the second example, the rewiring substrate 1 is also manufactured by the roll-to-roll method.

[0063] The specific contents will be described. First, the metal support 90 is unwound from a unwinding roll around which the metal support 90 is wound. Next, as shown in FIG. 22, a first insulating layer 10 having through holes 11 is formed on a first support surface 91 of the unwound metal support 90. As in the first example of the manufacturing method of the rewiring board 1, the first insulating layer 10 is formed, for example, by applying a solution of photosensitive polyimide on the first support surface 91, exposing the solution in a predetermined pattern, and developing it. In this example, the first insulating layer 10 may also be formed by attaching a carrier film made of photosensitive polyimide instead of applying a solution of photosensitive polyimide on the first support surface 91.

[0064] After the first insulating layer 10 is formed, a seed layer (not shown) is formed on the exposed portion of the first insulating layer 10 and the portion of the first support surface 91 exposed in the through hole 11. Next, as shown in FIG. 23, a layer of plating resist 80 is formed on the first insulating layer 10. Also, as shown in FIG. 24, a portion of the plating resist 80 that overlaps with the through hole 11 of the first insulating layer 10 in a plan view is exposed. Thereafter, the plating resist 80 is developed, and a first opening 81 (FIG. 25) is formed in the plating resist 80. Also, the plating resist 80 in the through hole 11 of the first insulating layer 10 is removed.

[0065] 25, a conductor (copper in this example) is filled into the through hole 11 of the first insulating layer 10 by electrolytic plating to form a first via portion 110. A conductor (copper in this example) is also filled into a partial region of the internal space of the first opening 81 of the plating resist 80 to form a terminal lower layer portion 121 on the first via portion 110.

[0066] 26, a portion of the plating resist 80 different from the through holes 11 of the first insulating layer 10 in a plan view is exposed to light. This portion corresponds to the two first wiring portions 130 (FIG. 2) of the rewiring substrate 1. Thereafter, the plating resist 80 is developed, and two second openings 82 are formed in the plating resist 80.

[0067] 27, the remaining regions of the internal space of the first openings 81 of the plating resist 80 are filled with a conductor (copper in this example) by electrolytic plating, and the terminal upper layer portion 122 is formed on the terminal lower layer portion 121. This completes the first terminal portion 120 consisting of the terminal lower layer portion 121 and the terminal upper layer portion 122. In addition, a conductor (copper in this example) is filled in partial regions of the internal space of the two second openings 82 of the plating resist 80, and two first wiring portions 130 are formed.

[0068] Next, the plating resist 80 is peeled off from the first insulating layer 10. Also, the exposed seed layer (not shown) is removed by etching. Furthermore, as shown in FIG. 28, a second insulating layer 20 is formed on the first insulating layer 10 so as to cover the first terminal portion 120 and the two first wiring portions 130. At this time, an opening 21 is formed in the second insulating layer 20 so that a part of the first terminal portion 120 is exposed. This completes the configuration formed on the first support surface 91 of the metal support 90 of the rewiring substrate 1 of FIG. 1. Then, a part of the metal support 90 that overlaps with the first via portion 110 in a plan view is removed by etching. As a result, a through hole 93 is formed in the metal support 90.

[0069] Next, a structure is prepared that is to be formed on the second support surface 92 of the metal support 90. In Figures 29 to 32, cross-sectional views of an intermediate body of the rewiring substrate 1 are shown in a state inverted in the stacking direction DL with respect to the cross-sectional views of Figures 22 to 28.

[0070] First, as shown in Fig. 29, a third insulating layer 30 is formed on a second support surface 92 of a metal support 90. The third insulating layer 30 of this example is formed so as to cover the entire second support surface 92 and the inner peripheral surface of a through hole 93. The third insulating layer 30 has a through hole 31 that exposes the first via portion 110 on the third insulating layer 30. The method of forming the third insulating layer 30 is basically the same as the method of forming the first insulating layer 10.

[0071] After the third insulating layer 30 is formed, a seed layer (not shown) is formed on the exposed portion of the third insulating layer 30 and on the portion of the first via portion 110 exposed in the through hole 31. Next, as shown in FIG. 30, a layer of plating resist 70 is formed on the third insulating layer 30. At this time, the plating resist 70 is formed so as to fill the through hole 31 of the third insulating layer 30. The formation of the plating resist 70 on the third insulating layer 30 is performed in basically the same manner as the formation of the plating resist 80 on the first insulating layer 10.

[0072] Thereafter, the second via portion 210, the second terminal portion 220, and the two second wiring portions 230 are formed as shown in Fig. 31 by the same procedure as the procedure for forming the first via portion 110, the first terminal portion 120, and the two first wiring portions 130 described with reference to Figs. 24 to 27. That is, exposure and development are repeated twice, and electrolytic plating is performed each time development is performed. Thereby, the second via portion 210, the second terminal portion 220, and the two second wiring portions 230 are formed.

[0073] Next, as shown in FIG. 32, the plating resist 70 is peeled off from the third insulating layer 30. Also, the exposed seed layer (not shown) is removed by etching. Finally, a fourth insulating layer 40 (FIG. 1) is formed on the third insulating layer 30 so as to cover the second terminal portion 220 and the two second wiring portions 230. This completes the rewiring substrate 1 of FIG. 1. Thus, according to the second example of the method for manufacturing the rewiring substrate 1, the carrier film 98 (FIG. 5) used in the first example is not necessary.

[0074] <5> Advantages of the First Embodiment (a) In a rewiring board, the thickness of the wiring portion is determined, for example, according to the required impedance value. Meanwhile, in a rewiring board, the height position of the exposed portion of the terminal portion may be limited within a specific range depending on the shape of the electronic component connected to the rewiring board. As a result, when the wiring portion and the terminal portion are formed on a common insulating layer, the thickness required for the terminal portion may be larger than the thickness required for the wiring portion.

[0075] In the rewiring substrate 1 according to the first embodiment, the thickness of the first terminal portion 120 formed on the first insulating layer 10 is greater than the thickness of the plurality of first wiring portions 130 formed on the first insulating layer 10. Therefore, according to the configuration of the rewiring substrate 1 described above, the height position of the exposed portion of the first terminal portion 120, i.e., the second end face 124 of the first terminal portion 120, can be easily set in a relatively wide range regardless of the thickness of the first wiring portion 130. In addition, in this case, in a rewiring substrate having a laminated structure, it is also possible to form the terminal portion so as to straddle a plurality of layers. Therefore, the degree of freedom in designing the wiring in the rewiring substrate 1 is improved. Furthermore, the outer peripheral surface 125 of the first terminal portion 120 has no step in the lamination direction DL. As a result, transmission loss caused by the shape of the first terminal portion 120 is unlikely to occur. As a result, the degree of freedom in designing the wiring can be improved while reducing the occurrence of transmission loss.

[0076] (b) As described above, the first terminal portion 120 has a circular shape in a plan view. In this case, the outer peripheral surface 125 of the first terminal portion 120 has a cross section perpendicular to the stacking direction DL that includes a curve and has no corners. As a result, the first terminal portion 120 has no steps in the circumferential direction, and transmission loss due to the shape of the first terminal portion 120 is less likely to occur.

[0077] (c) The rewiring substrate 1 includes a metal support 90. In this case, the multiple insulating layers (10, 20, 30, 40), the multiple via portions (110, 210), the multiple terminal portions (120, 220), and the multiple wiring portions (130, 230) are reinforced by the metal support 90, which has high rigidity. This improves the reliability of the rewiring substrate 1. In addition, the handleability of the rewiring substrate 1 is improved.

[0078] Furthermore, the metal support 90 has a higher thermal conductivity than the multiple insulating layers (10, 20, 30, 40). Therefore, when the semiconductor element 700 is mounted on the rewiring substrate 1, the metal support 90 easily receives heat generated by the semiconductor element 700. Therefore, the metal support 90 functions as a heat dissipation member for the semiconductor element 700.

[0079] (d) In the above-described rewiring substrate 1, a circuit including a plurality of wirings is formed on the first support surface 91 of the metal support 90, and a circuit including a plurality of wirings is also formed on the second support surface 92 of the metal support 90. This further improves the degree of freedom in the design of the wiring.

[0080] (e) According to the above-mentioned manufacturing method of the rewiring substrate 1, the first terminal portion 120 and the first wiring portion 130 having different thicknesses are formed using one plating resist 80. Also, the second terminal portion 220 and the second wiring portion 230 having different thicknesses are formed using one plating resist 70. Therefore, it is not necessary to form a plurality of resist films in order to form a plurality of conductor layers having different thicknesses on each of the first insulating layer 10 and the third insulating layer 30. This prevents an increase in the number of manufacturing steps of the rewiring substrate 1.

[0081] (f) In the above-described method for manufacturing the rewiring board 1, when the plating resists 70, 80 are formed of a dry film resist, voids are likely to occur when the plating resists 70, 80 are formed if the surface on which they are to be formed has irregularities. In contrast, when the plating resists 70, 80 are formed by applying a solution of a photosensitive resin and curing the solution, voids are unlikely to occur even if the surface on which they are to be formed has irregularities. Therefore, in order to reduce the occurrence of voids, it is preferable that the plating resists 70, 80 are formed by applying a solution of a photosensitive resin and curing the solution.

[0082] Even when the plating resists 70, 80 are formed of dry film resists, in the above-described method for manufacturing the rewiring board 1, each of the plating resists 70, 80 formed on one surface is exposed and developed multiple times. Therefore, the number of times a resist film is formed on one surface is reduced relative to the number of times exposure and development are performed. As a result, the occurrence of a large number of voids due to repeated formation of a resist film is suppressed compared to the case where a resist film is formed each time exposure and development are performed.

[0083] 2. Second embodiment The rewiring board according to the second embodiment will be described with respect to differences from the rewiring board 1 according to the first embodiment. Fig. 33 is a cross-sectional view of the rewiring board according to the second embodiment. The cross-sectional view of Fig. 33 corresponds to the cross-sectional view of the rewiring board 1 according to the first embodiment in Fig. 2.

[0084] In the rewiring board 1 of Fig. 33, configurations corresponding to the first terminal portion 120 and the first wiring portion 130 of Fig. 2 are shown as a first terminal portion 140 and a first wiring portion 150, respectively. Also, configurations corresponding to the second terminal portion 220 and the second wiring portion 230 of Fig. 2 are shown as a second terminal portion 240 and a second wiring portion 250, respectively.

[0085] In this embodiment, the thickness of the two first wiring parts 150 formed on the first insulating layer 10 is greater than the thickness of the first terminal part 140 formed on the first via part 110. Specifically, the first terminal part 140 in FIG. 33 has the same thickness as the terminal lower layer part 121 (FIG. 2) in the first embodiment. On the other hand, each of the two first wiring parts 150 in FIG. 33 includes a wiring lower layer part 151 and a wiring upper layer part 152. The wiring lower layer part 151 and the wiring upper layer part 152 are laminated and formed in this order on the first insulating layer 10. The wiring lower layer part 151 has the same thickness as the first terminal part 140.

[0086] In Fig. 33, an enlarged view of one of the two first wiring parts 150 and its vicinity is shown in a balloon. As shown in the balloon in Fig. 33, the first wiring part 150 according to the second embodiment has a third end face 153 and a fourth end face 154 that face in opposite directions in the stacking direction DL. The third end face 153 and the fourth end face 154 have a common shape (a band shape in this example).

[0087] The third end face 153 is a face in contact with the first insulating layer 10. The fourth end face 154 is a face that is spaced apart from the first insulating layer 10 and is located in the vicinity of the first face 1A. Furthermore, the first wiring portion 150 has a pair of side faces 155 extending in the stacking direction DL so as to connect both sides of the third end face 153 and both sides of the fourth end face 154, respectively.

[0088] A pair of side surfaces 155 of the first wiring portion 150 according to the present embodiment are formed flat in the stacking direction DL, as shown by a thick solid line in Fig. 33. That is, on the pair of side surfaces 155 of the first wiring portion 150, no step is formed in the stacking direction DL between the wiring lower layer portion 151 and the wiring upper layer portion 152. This reduces the occurrence of transmission loss in the first wiring portion 150, compared to a case in which a step is formed in the stacking direction DL between the wiring lower layer portion 151 and the wiring upper layer portion 152.

[0089] In the rewiring substrate 1 according to the present embodiment, the second wiring portion 250 has a shape that is basically symmetrical to the first wiring portion 150 with respect to a plane perpendicular to the stacking direction DL. Thus, like the first wiring portion 150, the second wiring portion 250 also has a pair of side surfaces extending in the stacking direction DL, and the pair of side surfaces are formed flat in the stacking direction DL. Therefore, the occurrence of transmission loss in the second wiring portion 250 is reduced.

[0090] Furthermore, in the rewiring substrate 1 of FIG. 33, the thickness of each of the multiple wiring portions (150, 250) is greater than the thickness of the multiple terminal portions (140, 240). In this case, the cross-sectional area of ​​the multiple wiring portions (150, 250) can be increased, making it easier to design the wiring while taking into consideration a reduction in resistance value. That is, the degree of freedom in the design of the wiring in the rewiring substrate 1 is improved. As a result, in the rewiring substrate 1 according to the second embodiment as well, the occurrence of transmission loss can be reduced while the degree of freedom in the design of the wiring is improved.

[0091] The rewiring substrate 1 according to the second embodiment can be manufactured, for example, as follows: First, a plating resist 80 is formed on the first insulating layer 10 according to the steps shown in Figs.

[0092] Next, each portion of plating resist 80 where first wiring portion 150 is to be formed is irradiated with exposure light and developed. A lower wiring layer portion 151 is formed in a partial region of the internal space of each opening formed by the development.

[0093] Next, a portion of the plating resist 80 where the first terminal portion 140 is to be formed is irradiated with exposure light and developed. A first via portion 110 is formed in the through hole 11 of the first insulating layer 10 opened by the development, and a first terminal portion 140 is formed in a partial region of the internal space of the newly formed opening. Also, a wiring upper layer portion 152 is formed in the remaining region of the internal space of the previously formed opening. As a result, a first wiring portion 150 consisting of a wiring lower layer portion 151 and a wiring upper layer portion 152 is formed.

[0094] Next, the plating resist 80 is removed from the first insulating layer 10 and the exposed seed layer is removed according to the process shown in Fig. 15. Furthermore, the second insulating layer 20 is formed on the first insulating layer 10 according to the process shown in Fig. 16.

[0095] Thereafter, multiple insulating layers (30, 40), a second via portion 210, a second terminal portion 240 and a second wiring portion 250 are formed on a second support surface 92 of the metal support 90 in a procedure basically similar to that used to form multiple insulating layers (10, 20), a first via portion 110, a first terminal portion 140 and a first wiring portion 150 on the first support surface 91.

[0096] 3. Other embodiments (a) The rewiring substrate 1 in the above embodiment may be configured so that the second end surface 124 of the first terminal portion 120 exposed through the opening 21 of the second insulating layer 20 is exposed flush with the first surface 1A.

[0097] FIG. 34 is a cross-sectional view showing an example of a rewiring substrate 1 according to another embodiment. The cross-sectional view of FIG. 34 corresponds to the cross-sectional view of the rewiring substrate 1 according to the first embodiment in FIG. 2. As shown in FIG. 34, in the rewiring substrate 1, an opening 21 is formed on the first surface 1A to expose the second end surface 124 of the first terminal portion 120 flush with the first surface 1A. In other words, in the rewiring substrate 1 of FIG. 34, the height position of one surface (first surface 1A) of the second insulating layer 20 in the stacking direction DL coincides with the height position of the exposed end surface (second end surface 124) of the first terminal portion 120. This allows the mounting surface of the semiconductor element 700 in the rewiring substrate 1 to be flat.

[0098] Also, an opening 41 is formed on the second surface 1B to expose one end surface of the second terminal portion 220 flush with the second surface 1B. In other words, in the rewiring substrate 1 of FIG. 34, the height position of one surface (second surface 1B) of the fourth insulating layer 40 in the stacking direction DL coincides with the height position of the exposed end surface of the second terminal portion 220. This allows the connection surface of the rewiring substrate 1 to the rigid substrate 800 to be flat.

[0099] (b) In the rewiring substrate 1 according to the above embodiment, a portion of the conductor electrically connecting the first terminal portion 120 and the second terminal portion 220 arranged on either side of the metal support 90 may be made of the same metal as the metal support 90.

[0100] Fig. 35 is a cross-sectional view showing another example of the rewiring substrate 1 according to another embodiment. The cross-sectional view of Fig. 35 corresponds to the cross-sectional view of the rewiring substrate 1 according to the first embodiment in Fig. 2. As shown in Fig. 35, in the rewiring substrate 1, a via conductor 190 made of the same metal as the metal support 90 is provided inside a through hole 93 of the metal support 90. A first via portion 110 is formed on one end face of the via conductor 190 in the stacking direction DL, and a second via portion 210 is formed on the other end face of the via conductor 190.

[0101] When producing the rewiring substrate 1 in FIG. 35, a part of the metal support 90 in an initial state can be formed as the via conductor 190 when forming the through hole 93 in the metal support 90. This eliminates the need to fill the inside of the through hole 93 with a conductor by plating or the like. This makes it possible to easily form an electrical conductive path in the through hole 93 of the metal support 90. Furthermore, the occurrence of defects such as voids in the through hole 93 can be reduced.

[0102] (c) The rewiring substrate 1 according to the above embodiment includes the metal support 90, but the present invention is not limited thereto. FIG. 36 is a cross-sectional view showing yet another example of the rewiring substrate 1 according to another embodiment. The cross-sectional view of FIG. 36 corresponds to the cross-sectional view of the rewiring substrate 1 according to the first embodiment in FIG. 2. As shown in FIG. 36, the rewiring substrate 1 does not need to be provided with the metal support 90. In the rewiring substrate 1 of FIG. 36, a first terminal portion 120 and two first wiring portions 130 are formed on one surface of the first insulating layer 10. In addition, a second terminal portion 220 and two second wiring portions 230 are formed on the other surface of the first insulating layer 10. Electrical conduction between the first terminal portion 120 and the second terminal portion 220 is ensured by the first via portion 110. According to this configuration, the rewiring substrate 1 can be made thinner. In addition, the flexibility of the rewiring substrate 1 can be improved.

[0103] (d) The above embodiment is an example in which the present invention is applied to a rewiring board, but the present invention may be applied to other wiring circuit boards in which a plurality of insulating layers and a plurality of conductor layers are laminated. Fig. 37 is a cross-sectional view showing an example of a wiring circuit board according to another embodiment. The wiring circuit board 2 in Fig. 37 has the same configuration as the rewiring board 1 in Fig. 2, except that the third insulating layer 30 and the second terminal portion 220, etc. are not formed on the second support surface 92 of the metal support 90.

[0104] Even in such a configuration, since outer peripheral surface 125 of first terminal portion 120, which has a thickness greater than that of first wiring portion 130, is formed flat, the same effects as those of the above embodiment can be obtained.

[0105] (e) In the rewiring substrate 1 according to the above embodiment, the metal support 90 may be replaced with a resin support having higher rigidity than the insulating layers (10, 20, 30, 40).

[0106] (f) In the rewiring substrate 1 according to the above embodiment, the first terminal portion 120 and the second terminal portion 220 have a circular shape in a plan view, but the present invention is not limited to this. Each of the first terminal portion 120 and the second terminal portion 220 may have a shape other than a circle (an ellipse or a polygon) in a plan view.

[0107] (g) The rewiring board 1 according to the above embodiment has a configuration in which two insulating layers (10, 20) are laminated on the first support surface 91 of the metal support 90 and two insulating layers (30, 40) are laminated on the second support surface 92, but the present invention is not limited to this. The rewiring board 1 may have a configuration in which one insulating layer or three or more insulating layers are laminated on the first support surface 91. The rewiring board 1 may also have a configuration in which one insulating layer or three or more insulating layers are laminated on the second support surface 92.

[0108] (h) In the rewiring substrate 1 according to the above embodiment, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 are each made of a photosensitive material, but the present invention is not limited to this. At least one of the multiple insulating layers (10, 20, 30, 40) may be made of a non-photosensitive material. For example, at least one of the multiple insulating layers (10, 20, 30, 40) may be made of a thermosetting material. As the thermosetting material, polyimide resin, acrylic resin, epoxy resin, polyamide resin, polybenzoxazole resin, polyvinyl chloride resin, or the like can be used.

[0109] (i) In the above embodiment, the rewiring substrate 1 is manufactured by a roll-to-roll method, but the present invention is not limited to this. The rewiring substrate 1 may be manufactured by a method other than the roll-to-roll method. For example, the rewiring substrate 1 may be manufactured by a sheet-by-sheet method in which a single sheet is sequentially processed. In this case, the rewiring substrate 1 may be a rigid substrate that does not have flexibility.

[0110] (j) In one roll-to-roll apparatus 500 used in the above embodiment, all steps for fabricating the rewiring substrate 1 are performed. That is, one roll-to-roll apparatus 500 includes a plurality of processing sections (510, 520, ...) respectively corresponding to all steps for fabricating the rewiring substrate 1. However, the present invention is not limited to this.

[0111] The multiple steps for producing the rewiring substrate 1 may be performed by multiple roll-to-roll devices. For example, the first half of the series of steps for producing the rewiring substrate 1 may be performed by one roll-to-roll device, and the second half of the steps may be performed by another roll-to-roll device. Also, the multiple steps for producing the rewiring substrate 1 may be performed using three or more roll-to-roll devices. Furthermore, only some of the multiple steps for producing the rewiring substrate 1 may be performed by a roll-to-roll device.

[0112] 4. Correspondence between each component of the claims and each part of the embodiment Below, examples of the correspondence between each component of the claims and each element of the embodiment will be described, but the present invention is not limited to the following examples. Various other elements having the configuration or function described in the claims can also be used as each component of the claims.

[0113] In the above embodiment, the semiconductor element 700 and the rigid substrate 800 are examples of electrical elements, the rewiring substrate 1 and the wired circuit substrate 2 are examples of wired circuit substrates, the through hole 11 in the first insulating layer 10 is an example of a first through hole and a through hole, the first insulating layer 10 is an example of a first insulating layer, the first via portion 110 is an example of a first via portion and a via portion, and the first terminal portions 120, 140 are examples of a first terminal portion.

[0114] In addition, the first wiring portion 130, 150 is an example of a first wiring portion, the second insulating layer 20 is an example of a second insulating layer, the first end face 123 is an example of a first end face, the second end face 124 is an example of a second end face, the outer peripheral surface 125 is an example of an outer peripheral surface, the first surface 1A is an example of an exposed surface, and the opening 21 is an example of an opening.

[0115] In addition, the metal support 90 is an example of a metal support, the first support surface 91 is an example of a first support surface, the second support surface 92 is an example of a second support surface, the through hole 31 in the third insulating layer 30 is an example of a second through hole, the third insulating layer 30 is an example of a third insulating layer, the second via portion 210 is an example of a second via portion, and the second terminal portion 220 is an example of a second terminal portion.

[0116] In addition, the second wiring portion 230 is an example of a second wiring portion, the fourth insulating layer 40 is an example of a fourth insulating layer, the through hole 93 of the metal support 90 is an example of a third through hole, and the portion of the first via portion 110 located inside the through hole 93 of the metal support 90 or the via conductor 190 is an example of a via conductor.

[0117] In addition, first wiring portion 130 is an example of a third wiring portion and a wiring portion, third end face 153 is an example of a third end face, fourth end face 154 is an example of a fourth end face, a pair of side faces 155 is an example of a pair of side faces, plating resist 80 is an example of a resist film, first opening 81 is an example of a first opening, terminal lower layer portion 121 is an example of a terminal lower layer portion, second opening 82 is an example of a second opening, and terminal upper layer portion 122 is an example of a terminal upper layer portion.

[0118] 5. Summary of the embodiment (1) The printed circuit board according to paragraph 1 is A printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, a first insulating layer having a first through hole; a first via portion formed in the first through hole; a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion; a first wiring portion formed on the first insulating layer; a second insulating layer; The first terminal portion is a first end surface and a second end surface having a common shape and facing in opposite directions in a lamination direction of the wired circuit board; a cylindrical outer peripheral surface extending in the stacking direction so as to connect an outer edge of the first end surface and an outer edge of the second end surface; the first end face is a face in contact with the first insulating layer and the first via portion, the second end surface is a surface to which a terminal of the electrical element is to be connected; the second insulating layer is formed on the first insulating layer to cover the outer peripheral surface of the first terminal portion and the first wiring portion while exposing at least a portion of the second end surface; a distance between the first end surface and the second end surface of the first terminal portion in the stacking direction is greater than a thickness of the first wiring portion in the stacking direction; The outer circumferential surface of the first terminal portion is formed flat in the stacking direction.

[0119] In a wired circuit board, the thickness of the wiring portion is determined according to the required impedance value. Meanwhile, in a wired circuit board, the height position of the exposed portion of the terminal portion may be limited within a specific range according to the shape of other electronic components connected to the wired circuit board. As a result, when the wiring portion and the terminal portion are formed on a common insulating layer, the thickness required for the terminal portion may be larger than the thickness required for the wiring portion.

[0120] In the above-mentioned wired circuit board, the thickness of the first terminal portion formed on the first insulating layer is greater than the thickness of the first wiring portion formed on the first insulating layer. As a result, the height position of the exposed portion of the first terminal portion, i.e., the second end face of the first terminal portion, can be easily set in a relatively wide range regardless of the thickness of the first wiring portion. In addition, in this case, it is also possible to form the first terminal portion so as to straddle a plurality of layers in a wired circuit board having a laminated structure. Therefore, the degree of freedom in designing the wiring in the wired circuit board is improved. Furthermore, there is no step in the lamination direction on the outer peripheral surface of the first terminal portion. As a result, transmission loss due to the shape of the first terminal portion is unlikely to occur. As a result, it is possible to reduce the occurrence of transmission loss while improving the degree of freedom in designing the wiring.

[0121] (2) In the printed circuit board according to the first aspect, The outer circumferential surface of the first terminal portion may have a cross section perpendicular to the stacking direction that includes a curve and has no corners.

[0122] In this case, since there is no step in the circumferential direction, transmission loss due to the shape of the first terminal portion is less likely to occur.

[0123] (Item 3) In the wired circuit board according to item 1 or 2, the second insulating layer has an exposed surface facing in a direction opposite to the first insulating layer in the stacking direction; The exposed surface may have an opening through which the second end surface of the first terminal portion is exposed and flush with the exposed surface.

[0124] In this case, the connection surfaces of the electrical elements on the printed circuit board can be made flat.

[0125] (Item 4) In the wired circuit board according to any one of items 1 to 3, The printed circuit board is The semiconductor device may further include a metal support that supports the first insulating layer, the first via portion, the first terminal portion, the first wiring portion, and the second insulating layer.

[0126] In this case, the first insulating layer, the first via portion, the first terminal portion, the first wiring portion, and the second insulating layer are reinforced by the metal support having high rigidity. Therefore, the reliability of the wiring circuit board is improved. In addition, the handling property of the wiring circuit board is improved.

[0127] Furthermore, the metal support has a higher thermal conductivity than the insulating layer, and therefore, when an electrical component is mounted on the wiring circuit board, the metal support is more likely to receive heat generated by the electrical component, and therefore, the metal support functions as a heat dissipation member for the electrical component.

[0128] (5) In the printed circuit board according to the fourth aspect, the metal support has a first support surface and a second support surface facing in opposite directions in the stacking direction; the first insulating layer is formed on the first support surface; The printed circuit board is a third insulating layer having a second through hole and formed on the second support surface such that the second through hole overlaps with the first through hole of the first insulating layer in a plan view; a second via portion formed in the second through hole so as to overlap with the first via portion in a plan view; a second terminal portion formed on the third insulating layer so as to overlap the second via portion in a plan view and directly connected to the second via portion; a second wiring portion formed on the third insulating layer; a fourth insulating layer formed on the third insulating layer so as to cover a remaining portion of the second terminal portion and the second wiring portion while exposing a portion of the second terminal portion; the metal support has a third through hole between the first via portion and the second via portion, A via conductor may be provided inside the third through hole to electrically connect the first via portion and the second via portion.

[0129] In this case, since wiring circuits can be formed on both the first support surface and the second support surface of the metal support, the degree of freedom in wiring design is further improved.

[0130] (Item 6) In the printed circuit board according to item 5, The via conductor may be made of the same metal as the metal support.

[0131] In this case, since a part of the metal support can be formed as a via conductor, there is no need to fill the third through hole with the via conductor by plating or the like. Therefore, an electrical conductive path can be easily formed in the third through hole of the metal support. Also, the occurrence of defects such as voids in the via conductor can be reduced.

[0132] (Item 7) In the wired circuit board according to any one of items 1 to 6, The printed circuit board is Further comprising a third wiring portion formed on the first insulating layer; the first wiring portion and the third wiring portion are disposed adjacent to each other on the first insulating layer; The width of each of the first wiring portion and the third wiring portion is less than 15 μm; The distance between the first wiring portion and the third wiring portion may be less than 15 μm.

[0133] In this case, the wiring can be designed with high density.

[0134] (Item 8) The wired circuit board according to item 8 is A printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, a first insulating layer having a first through hole; a first via portion formed in the first through hole; a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion; a first wiring portion formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the remaining portion of the first terminal portion and the first wiring portion while exposing a portion of the first terminal portion; The first wiring portion is a third end surface and a fourth end surface having a common band shape and facing in opposite directions in a lamination direction of the wiring circuit board; a pair of side surfaces extending in the stacking direction so as to connect both sides of the third end surface and both sides of the fourth end surface, a thickness of the first wiring portion in the stacking direction is greater than a thickness of the first terminal portion, Each of the pair of side surfaces of the first wiring portion is formed flat in the stacking direction.

[0135] In the wired circuit board, the thickness of the first wiring portion is greater than the thickness of the first terminal portion. In this case, the cross-sectional area of ​​the first wiring portion can be increased, making it easier to design the wiring while taking into consideration the reduction of the resistance value. That is, the degree of freedom in designing the wiring in the wired circuit board is improved. Furthermore, the pair of side surfaces of the first wiring portion have no steps in the stacking direction. This makes it difficult for transmission loss due to the shape of the first wiring portion to occur. As a result, it is possible to reduce the occurrence of transmission loss while improving the degree of freedom in designing the wiring.

[0136] (Item 9) A method for producing a printed circuit board according to item 9 includes: A method for manufacturing a printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, comprising the steps of: forming a resist film made of a photosensitive material on one surface of a first insulating layer having a through hole; after forming the resist film, removing a first portion of the resist film that overlaps with the through hole of the first insulating layer in a plan view by photolithography to form a first opening; after forming the first opening, forming a via portion by filling a conductor inside the through hole of the first insulating layer, and forming a terminal lower layer portion on the via portion by filling a partial region of an internal space of the first opening of the resist film with a conductor; after forming the via portion and the terminal lower layer portion, removing a second portion of the resist film that is spaced from the through hole of the first insulating layer in a plan view by photolithography to form a second opening; forming an upper terminal layer on the lower terminal layer by filling a conductor into a remaining region of an internal space of the first opening of the resist film after the second opening is formed, and forming a wiring portion on the first insulating layer by filling a conductor into the internal space of the second opening of the resist film; removing the resist film remaining on the first insulating layer after forming the terminal upper layer portion and the wiring portion; and forming a second insulating layer on the first insulating layer after removing the resist film.

[0137] According to the method for manufacturing the wired circuit board, the conductor is sequentially filled into the first opening formed in one resist film to form the lower terminal layer and the upper terminal layer. As a result, a terminal portion consisting of the lower terminal layer and the upper terminal layer is formed. The upper terminal layer of the terminal portion is formed together with the wiring portion. Therefore, the thickness of the terminal portion can be made larger than the thickness of the wiring portion. As a result, the height position of the exposed portion of the terminal portion can be easily set in a relatively wide range regardless of the thickness of the wiring portion. In addition, in this case, in a wired circuit board having a laminated structure, it is also possible to form the terminal portion so as to straddle multiple layers. Therefore, the degree of freedom in designing the wiring in the wired circuit board is improved.

[0138] Furthermore, the lower terminal layer and the upper terminal layer are formed within the first opening formed by a single photolithography process. Therefore, the inner peripheral surface of the first opening is formed flat in the stacking direction, and the outer peripheral surface of the terminal is also formed flat. In this case, the outer peripheral surface of the terminal has no steps in the stacking direction. This makes it difficult for transmission loss to occur due to the shape of the terminal. As a result, it is possible to reduce transmission loss while improving the freedom of wiring design.

[0139] Moreover, according to the above-mentioned method for manufacturing a wired circuit board, a plurality of conductor layers (terminal parts and wiring parts) having different thicknesses are formed using one resist film. Therefore, it is not necessary to form a plurality of resist films in order to form a plurality of conductor layers having different thicknesses on the first insulating layer. This prevents an increase in the number of manufacturing steps for the wired circuit board.

[0140] Furthermore, when a resist film is formed, voids are likely to occur if the surface on which the resist film is to be formed has unevenness. In the above-mentioned method for producing a wired circuit board, since it is not necessary to form the resist film multiple times, the occurrence of a large number of voids due to repeated formation of the resist film is suppressed. [Explanation of symbols]

[0141] 1...Rewiring board, 1A...First surface, 1B...Second surface, 2...Wiring circuit board, 10...First insulating layer, 11, 31, 93...Through hole, 20...Second insulating layer, 21, 41...Opening, 30...Third insulating layer, 40...Fourth insulating layer, 70, 80...Plating resist, 71...Third opening, 72...Fourth opening, 81...First opening, 82...Second opening, 90...Metal support, 91...First support surface, 92...Second support surface, 98...Carrier film, 110...First via portion, 120, 140...First terminal portion, 121, 221...Lower terminal layer portion, 122, 222 ...terminal upper layer portion, 123...first end face, 124...second end face, 125...outer surface, 130, 150...first wiring portion, 151...wiring lower layer portion, 152...wiring upper layer portion, 153...third end face, 154...fourth end face, 155...side surface, 190...via conductor, 210...second via portion, 220, 240...second terminal portion, 230, 250...second wiring portion, 500...roll device, 501...unwinding portion, 502...winding portion, 510, 520...processing portion, 700...semiconductor element, 800...rigid substrate, DL...stacking direction, R1...unwinding roll, R2...winding roll

Claims

1. A printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, a first insulating layer having a first through hole; a first via portion formed in the first through hole; a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion; a first wiring portion formed on the first insulating layer; a second insulating layer; The first terminal portion is a first end surface and a second end surface having a common shape and facing in opposite directions in a lamination direction of the wired circuit board; a cylindrical outer peripheral surface extending in the stacking direction so as to connect an outer edge of the first end surface and an outer edge of the second end surface, the first end face is a face in contact with the first insulating layer and the first via portion, the second end surface is a surface to which a terminal of the electrical element is to be connected; the second insulating layer is formed on the first insulating layer to cover the outer peripheral surface of the first terminal portion and the first wiring portion while exposing at least a portion of the second end surface; a distance between the first end surface and the second end surface of the first terminal portion in the stacking direction is greater than a thickness of the first wiring portion in the stacking direction; The outer peripheral surface of the first terminal portion is formed flat in the stacking direction.

2. The printed circuit board according to claim 1 , wherein the outer circumferential surface of the first terminal portion has a cross section perpendicular to the stacking direction that includes a curve and has no corners.

3. the second insulating layer has an exposed surface facing in a direction opposite to the first insulating layer in the stacking direction; 3. The printed circuit board according to claim 1, wherein the exposed surface has an opening through which the second end surface of the first terminal portion is exposed and flush with the exposed surface.

4. 3. The wired circuit board according to claim 1, further comprising a metal support supporting said first insulating layer, said first via portion, said first terminal portion, said first wiring portion and said second insulating layer.

5. the metal support has a first support surface and a second support surface facing in opposite directions in the stacking direction; the first insulating layer is formed on the first support surface; The printed circuit board is a third insulating layer having a second through hole formed on the second support surface such that the second through hole overlaps with the first through hole of the first insulating layer in a plan view; a second via portion formed in the second through hole so as to overlap with the first via portion in a plan view; a second terminal portion formed on the third insulating layer so as to overlap the second via portion in a plan view and directly connected to the second via portion; a second wiring portion formed on the third insulating layer; a fourth insulating layer formed on the third insulating layer so as to cover a remaining portion of the second terminal portion and the second wiring portion while exposing a portion of the second terminal portion; the metal support has a third through hole between the first via portion and the second via portion, The printed circuit board according to claim 4 , wherein a via conductor is provided inside said third through hole for electrically connecting said first via portion and said second via portion.

6. The printed circuit board according to claim 5 , wherein the via conductor is made of the same metal as the metal support.

7. A third wiring portion is formed on the first insulating layer, the first wiring portion and the third wiring portion are disposed adjacent to each other on the first insulating layer; each of the first wiring portion and the third wiring portion has a width of less than 15 μm; 3. The printed circuit board according to claim 1, wherein the distance between the first wiring portion and the third wiring portion is less than 15 [mu]m.

8. A printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, a first insulating layer having a first through hole; a first via portion formed in the first through hole; a first terminal portion formed on the first insulating layer so as to overlap the first via portion in a plan view and directly connected to the first via portion; a first wiring portion formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the remaining portion of the first terminal portion and the first wiring portion while exposing a portion of the first terminal portion; The first wiring portion is a third end surface and a fourth end surface having a common band shape and facing in opposite directions to each other in a lamination direction of the wired circuit board; a pair of side surfaces extending in the stacking direction so as to connect both sides of the third end surface and both sides of the fourth end surface, a thickness of the first wiring portion in the stacking direction is greater than a thickness of the first terminal portion, A wired circuit board, wherein each of the pair of side surfaces of the first wiring portion is formed flat in the stacking direction.

9. A method for manufacturing a printed circuit board having a laminated structure composed of a plurality of layers and to which electrical elements are connected, comprising the steps of: forming a resist film made of a photosensitive material on one surface of a first insulating layer having a through hole; after forming the resist film, removing a first portion of the resist film that overlaps with the through hole of the first insulating layer in a plan view by photolithography to form a first opening; after forming the first opening, forming a via portion by filling a conductor inside the through hole of the first insulating layer, and forming a terminal lower layer portion on the via portion by filling a partial region of an internal space of the first opening of the resist film with a conductor; after forming the via portion and the terminal lower layer portion, removing a second portion of the resist film that is spaced from the through hole of the first insulating layer in a plan view by photolithography to form a second opening; forming an upper terminal layer on the lower terminal layer by filling a conductor into a remaining region of an internal space of the first opening of the resist film after the second opening is formed, and forming a wiring portion on the first insulating layer by filling a conductor into the internal space of the second opening of the resist film; removing the resist film remaining on the first insulating layer after forming the terminal upper layer portion and the wiring portion; and forming a second insulating layer on the first insulating layer after removing the resist film.

Images