Semiconductor storage device and manufacturing method of semiconductor storage device

Abstract

To improve manufacturability of a semiconductor storage device.SOLUTION: A semiconductor storage device of an embodiment includes a multi-layered body and a plurality of contacts. The multi-layered body includes a plurality of gate electrode layers. The plurality of contacts include a first contact, a second contact, and a third contact. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer, and a third gate electrode layer. The second gate electrode layer is on a first side with respect to the first gate electrode layer, and the third gate electrode layer is on the first side with respect to the second gate electrode layer. The multi-layered body includes a first conductive protruding part protruding from the first gate electrode layer toward the first contact, and a second conductive protruding part protruding from the third gate electrode layer toward the third contact. The first contact is in contact with the first protruding part. The second contact is in contact with the second gate electrode layer. The third contact is in contact with the second protruding part.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that includes a stack in which a plurality of gate electrode layers and a plurality of insulating layers are alternately stacked one by one, and a plurality of contacts provided on the stack. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0242131 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment aims to improve the manufacturability of a semiconductor memory device. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a stack and a plurality of contacts. The stack includes a plurality of gate electrode layers and a plurality of insulating layers. The gate electrode layers and the insulating layers are alternately stacked in a first direction. The contacts each extend in the first direction. The stack includes a first region, a second region, and a third region. The first region, the second region, and the third region are arranged in a second direction different from the first direction in the order of the first region, the second region, and the third region. The contacts include a first contact arranged in the first region, a second contact arranged in the second region, and a third contact arranged in the third region. The gate electrode layers include a first gate electrode layer, a second gate electrode layer arranged on a first side in the first direction with respect to the first gate electrode layer, and a third gate electrode layer arranged on the first side with respect to the second gate electrode layer. The stack includes a first conductive protrusion protruding from the first gate electrode layer toward the first contact, and a second conductive protrusion protruding from the third gate electrode layer toward the third contact. The first contact is in contact with the first protruding portion, the second contact is in contact with the second gate electrode layer, and the third contact is in contact with the second protruding portion. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a configuration of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Diagram 3] 1 is a cross-sectional view showing a portion of a semiconductor memory device according to a first embodiment. [Figure 4] 4 is an enlarged cross-sectional view showing the area surrounded by line F4 shown in FIG. 3. [Diagram 5] 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device shown in FIG. 4. [Figure 6] 2 is a cross-sectional view showing a staircase region of the semiconductor memory device according to the first embodiment. [Figure 7]FIG. 4 is an enlarged cross-sectional view showing a part of the staircase region of the first embodiment. [Figure 8A] 3A to 3C are diagrams illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 8B] 3A to 3C are diagrams illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a staircase region of a semiconductor memory device according to a modified example of the first embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a staircase region of a semiconductor memory device according to a second embodiment. [Figure 11A] 6A to 6C are diagrams for explaining a manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 11B] 6A to 6C are diagrams for explaining a manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 11C] 6A to 6C are diagrams for explaining a manufacturing method of a semiconductor memory device according to a second embodiment. [Figure 12] FIG. 13 is a perspective cross-sectional view showing a staircase region of a semiconductor memory device according to a third embodiment. [Figure 13] 11 is a cross-sectional view showing a staircase region of a semiconductor memory device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor memory device and a manufacturing method of a semiconductor memory device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are given the same reference numerals. Then, duplicated descriptions of those components may be omitted. In the following description, reference numerals with a distinguishing number or letter at the end may be omitted if they do not need to be distinguished from each other.

[0008] In this application, terms are defined as follows: "Parallel", "orthogonal", or "same" may include "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection, but may include electrical connection. That is, "connection" is not limited to a case where multiple elements are directly connected, but may include a case where multiple elements are connected with another element interposed therebetween.

[0009] The +X direction, the -X direction, the +Y direction, the -Y direction, the +Z direction, and the -Z direction are defined as follows. The +X direction is the direction in which the word lines WL described later extend (see FIG. 3). The -X direction is the opposite direction to the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is the direction that intersects (e.g., perpendicular to) the X direction. The +Y direction is the direction in which the bit lines BL extend (see FIG. 3). The -Y direction is the opposite direction to the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is the direction that intersects (e.g., perpendicular to) the X direction and the Y direction. The +Z direction is the direction from the bit lines BL described later toward the stack 40 (see FIG. 3). The -Z direction is the opposite direction to the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the Z direction.

[0010] In the following description, the +Z direction side may be referred to as "upper", and the -Z direction side as "lower". In the following description, the position in the Z direction may be referred to as "height". However, these expressions are for convenience and do not specify the direction of gravity. The Z direction is an example of a "first direction". The +Z direction side is an example of a "first side". The -Z direction side is an example of a "second side". The X direction is an example of a "second direction". In the drawings described below, illustrations of configurations that are not relevant to the description may be omitted.

[0011] (First embodiment) <1. Configuration of Semiconductor Memory Device> 1 is a block diagram showing a part of the configuration of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device, and is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device, and is used as a storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 1). The block BLK is a set of memory cell transistors. The block BLK is used as a data erase unit. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0013] The command register 12 holds a command CMD that the semiconductor memory device 1 receives from the host device. The address register 13 holds address information ADD that the semiconductor memory device 1 receives from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, or the like based on the command CMD held in the command register 12.

[0014] The driver module 15 includes a voltage generating circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. In a read operation, the sense amplifier module 17 determines the data value stored in each memory cell transistor based on the voltage of each bit line, and transfers the determination result to the host device as read data DAT.

[0015] <2. Electrical configuration of memory cell array> Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. Fig. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of (for example, four) strings STR0 to STR3.

[0016] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), one or more drain side select transistors STD, and one or more source side select transistors STS.

[0017] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to one of word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, and retains a data value in a non-volatile manner.

[0018] The drain of the drain side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain side select transistor STD is connected to one end of the memory cell transistors MT0 to MTn connected in series. The control gate of the drain side select transistor STD is connected to one of the drain side select gate lines SGD0 to SGD3. The drain side select transistor STD is electrically connected to the row decoder module 16 via the drain side select gate line SGD. The drain side select transistor STD connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain side select gate line SGD.

[0019] The drain of the source side select transistor STS is connected to the other end of the serially connected memory cell transistors MT0 to MTn. The source of the source side select transistor STS is connected to a source line SL. The control gate of the source side select transistor STS is connected to a source side select gate line SGS. The source side select transistor STS connects the NAND string NS and the source line SL when a predetermined voltage is applied to the source side select gate line SGS.

[0020] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn, respectively. In the same string STR, the control gates of the drain side select transistors STD are commonly connected to the corresponding drain side select gate lines SGD0 to SGD3. The control gates of the source side select transistors STS are commonly connected to the source side select gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in a plurality of strings STR.

[0021] <3. Physical structure of semiconductor memory device> Next, the physical configuration of the semiconductor memory device 1 will be described. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3.

[0022] <3.1 First chip> The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0023] The semiconductor substrate 21 is a substrate that serves as a base for the first chip 2. At least a portion of the semiconductor substrate 21 is a plate-like shape extending along the X direction and the Y direction. The semiconductor substrate 21 is formed of a semiconductor material such as silicon.

[0024] The peripheral circuit 22 is a circuit for operating the above-mentioned memory cell array 11. The peripheral circuit 22 includes one or more of the above-mentioned command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. The peripheral circuit 22 includes, for example, a plurality of transistors 31, a plurality of contacts 32, a plurality of wiring layers 33, and a plurality of vias 34.

[0025] The transistor 31 is provided on the semiconductor substrate 21. The contact 32 is conductive, extends in the Z direction, and contacts the source region, drain region, or gate electrode of the transistor 31. The multiple wiring layers 33 are arranged at multiple heights. Each wiring layer 33 includes multiple wirings 33a extending in the X direction or the Y direction. The vias 34 are electrical connection parts extending in the Z direction within the first chip 2. The multiple vias 34 include, for example, a via 34 that connects two wirings 33a arranged at different heights, and a via 34 that connects the wirings 33a and the pad 24.

[0026] The insulating section 23 covers the plurality of transistors 31, the plurality of contacts 32, the plurality of wiring layers 33, and the plurality of vias 34. The plurality of pads 24 are provided on the surface of the insulating section 23. Each of the pads 24 is electrically connected to a wiring 33a through the via 34.

[0027] <3.2 Second chip> The second chip 3 is an array chip including a memory cell array 11. The second chip 3 has, for example, the memory cell array 11, an insulating section 35, and a plurality of pads 36. Here, the insulating section 35 and the plurality of pads 36 will be described, and the memory cell array 11 will be described later.

[0028] The insulating section 35 covers the memory cell array 11. The multiple pads 36 are provided on the surface of the insulating section 35. Each pad 36 is electrically connected to a wiring (e.g., wiring 81 or wiring 83) included in a wiring section 80 of the memory cell array 11, which will be described later. In this embodiment, the multiple pads 24 of the first chip 2 and the multiple pads 36 of the second chip 3 are faced to each other and bonded together, thereby integrating the first chip 2 and the second chip 3.

[0029] <4. Physical configuration of memory cell array> Next, the physical configuration of the memory cell array 11 will be described. As shown in FIG. 3, the memory cell array 11 has a stack 40, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a plurality of contacts 70 for the conductive layer, and a wiring portion 80.

[0030] <4.1 Laminate> First, the laminate 40 will be described. Fig. 4 is an enlarged cross-sectional view of a region surrounded by line F4 of the semiconductor memory device 1 shown in Fig. 3. The laminate 40 includes a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating portion 43. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately laminated one by one in the Z direction.

[0031] The conductive layers 41 are aligned along the X and Y directions. Each conductive layer 41 includes a conductive material (first material) such as tungsten, molybdenum, or silicon doped with an impurity. The conductive layer 41 is an example of a "gate electrode layer."

[0032] Of the multiple conductive layers 41, one or more (for example, a plurality of) conductive layers 41 located in the lower part function as a drain side selection gate line SGD. The drain side selection gate line SGD is provided in common to the multiple memory pillars MH aligned in the X direction or Y direction. The intersection of the drain side selection gate line SGD and a channel layer 52 (described later) of each memory pillar MH functions as the above-mentioned drain side selection transistor STD.

[0033] Of the multiple conductive layers 41, one or more (for example, a plurality of) conductive layers 41 located at the top function as a source side selection gate line SGS. The source side selection gate line SGS is provided in common to the multiple memory pillars MH aligned in the X direction or Y direction. The intersection of the source side selection gate line SGS and the channel layer 52 of each memory pillar MH functions as the above-mentioned source side selection transistor STS.

[0034] At least a part of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain side selection gate line SGD and the source side selection gate line SGS among the multiple conductive layers 41 functions as a word line WL. The word line WL is provided in common to the multiple memory pillars MH aligned in the X direction and the Y direction. In this embodiment, the intersection of the word line WL and the channel layer 52 of each memory pillar MH functions as a memory cell transistor MT. The memory cell transistor MT will be described in detail later.

[0035] In this embodiment, the multiple conductive layers 41 have different lengths in the X direction. For example, the multiple conductive layers 41 extend farther in the -X direction as the conductive layers 41 are located closer to the +Z direction. As a result, the stack 40 has a staircase region SR in which the ends of the multiple conductive layers 41 are arranged in a staircase shape. The staircase region SR is an example of a connection region in which the multiple contacts 70 and the multiple conductive layers 41 are connected to each other.

[0036] The insulating layer 42 is an interlayer insulating film provided between two conductive layers 41 adjacent to each other in the Z direction, and insulates the two conductive layers 41. The insulating layer 42 extends along the X direction and the Y direction. The insulating layer 42 is formed of, for example, a film containing silicon and oxygen.

[0037] The insulating portion 43 is provided in the staircase region SR and covers the ends of the plurality of conductive layers 41 arranged in a staircase pattern. The insulating portion 43 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4).

[0038] <4.2 Source line> The source line SL is disposed above the stack 40. The source line SL is a conductive layer extending in the X and Y directions. The source line SL includes a conductive material such as tungsten, molybdenum, or silicon doped with impurities.

[0039] <4.3 Memory pillar> The multiple memory pillars MH are aligned in the X and Y directions (see FIG. 3). Each memory pillar MH extends in the Z direction within the stack 40 and penetrates the stack 40. The upper end of each memory pillar MH contacts a source line SL. Meanwhile, the lower end of each memory pillar MH contacts a contact CH, which will be described later.

[0040] Fig. 5 is a cross-sectional view taken along line F5-F5 of the semiconductor memory device 1 shown in Fig. 4. The memory pillar MH has, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap portion 54 (see Fig. 4).

[0041] The memory film 51 is provided on the outer periphery of the channel layer 52. The memory film 51 is located between the multiple conductive layers 41 and the channel layer 52. The memory film 51 includes, for example, a block insulating film 61, a charge trap film 62, and a tunnel insulating film 63.

[0042] The block insulating film 61 is provided between the multiple conductive layers 41 and the charge trap film 62. The block insulating film 61 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 62. The block insulating film 61 is formed in a ring shape and extends in the Z direction. The block insulating film 61 extends over the entire length of the memory pillar MH in the Z direction, for example. The block insulating film 61 is a laminated structure film in which multiple insulating films, such as a film containing silicon and oxygen or a film containing metal and oxygen, are laminated. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 61 may include a high dielectric constant material (high-k material) such as silicon nitride or hafnium oxide.

[0043] The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in a ring shape and extends in the Z direction. The charge trap film 62 extends over the entire length of the memory pillar MH in the Z direction, for example. The charge trap film 62 is a functional film that has a large number of crystal defects (trap levels) and can trap charges in the crystal defects. The charge trap film 62 is formed of a film containing silicon and nitrogen, for example. The portions of the charge trap film 62 adjacent to each word line WL are an example of a "charge storage section" that can store information by accumulating charges.

[0044] The tunnel insulating film 63 is provided between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is, for example, annular along the outer peripheral surface of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 63 extends, for example, over the entire length of the memory pillar MH in the Z direction. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0045] As a result, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Note that the memory film 51 may have a floating gate type charge accumulation portion (floating gate electrode) as the charge accumulation portion instead of the charge trap film 62. The floating gate electrode is formed of, for example, silicon doped with impurities.

[0046] The insulating core 53 is provided inside the channel layer 52. The insulating core 53 fills at least a portion of the inside of the channel layer 52. The insulating core 53 is formed of a film containing silicon and oxygen. A portion of the insulating core 53 is formed in an annular shape along the inner circumferential surface of the channel layer 52. The insulating core 53 may have a space (air gap) inside the insulating core 53. The insulating core 53 extends in the Z direction. For example, the insulating core 53 spans most of the memory pillar MH in the Z direction except for the lower end of the memory pillar MH (see FIG. 4).

[0047] Returning to FIG. 4, the cap portion 54 will now be described. The cap portion 54 is provided below the insulating core 53. The cap portion 54 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 54 may be doped with impurities. The cap portion 54 is disposed on the inner periphery side of the lower end of the memory film 51, and is formed integrally with the channel layer 52. The cap portion 54, together with the lower end of the channel layer 52, forms the lower end of the memory pillar MH. A contact CH contacts the cap portion 54 in the Z direction.

[0048] <4.4 Bit lines> Next, returning to FIG. 3, the bit line BL will be described. The bit line BL is a wiring for selecting one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below the stack 40. The multiple bit lines BL are arranged in the X direction at intervals in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass below the corresponding multiple memory pillars MH.

[0049] When viewed from the Z direction, each bit line BL overlaps with multiple memory pillars MH (see FIG. 6). Each bit line BL is connected to a channel layer 52 of the memory pillar MH via a contact VY and a contact CH. This makes it possible to select an arbitrary memory cell transistor MT from multiple memory cell transistors MT arranged three-dimensionally by combining the word lines WL and the bit lines BL.

[0050] <4.5 Contacts for Conductive Layers> As shown in FIG. 3, the contacts 70 are electrical connection parts that electrically connect the conductive layer 41 and a wiring 83 (described later) included in the wiring part 80. The contacts 70 are arranged, for example, in the staircase region SR of the laminate 40. The contacts 70 extend in the Z direction and, for example, have different lengths in the Z direction. Each contact 70 includes a conductive material such as tungsten, molybdenum, or silicon doped with an impurity. The upper end of each contact 70 is electrically connected to the corresponding conductive layer 41. The lower end of each contact 70 is electrically connected to the wiring 83 through a via 84 (described later).

[0051] <4.6 Wiring section> Next, a description will be given of the wiring section 80. The wiring section 80 is disposed, for example, between the stacked body 40 and the semiconductor substrate 21. The wiring section 80 includes, for example, a plurality of wirings 81, a plurality of vias 82, a plurality of wirings 83, and a plurality of vias 84.

[0052] The wiring 81 is an electrical connection portion that electrically connects the bit lines BL and the pads 36. The multiple wirings 81 are arranged, for example, below the multiple bit lines BL. Each wiring 81 extends, for example, in the X direction or the Y direction. A via 82 that electrically connects the wiring 81 and the bit lines BL is provided between the wiring 81 and the bit lines BL.

[0053] The wiring 83 is an electrical connection portion that electrically connects the contact 70 for the conductive layer and the pad 36. The wiring 83 is electrically connected to the conductive layer 41 through the via 84 and the contact 70 for the conductive layer. A voltage is applied to the wiring 83 to select the conductive layer 41 (the word line WL, the drain side select gate line SGD, or the source side select gate line SGS).

[0054] <5. Configuration of the staircase area> Next, the configuration of the staircase region SR will be described. 6 is an enlarged cross-sectional view of the staircase region SR. For convenience of explanation, in and after FIG. 6, the -Z direction is illustrated as the upper side, and the +Z direction is illustrated as the lower side.

[0055] As shown in Fig. 6, the staircase region SR has, for example, first to fourth regions R1, R2, R3, and R4. These regions are arranged in the -X direction in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4. The first to fourth regions R1, R2, R3, and R4 are, for example, regions obtained by dividing the staircase region SR into four in the X direction. However, the sizes of the first to fourth regions R1, R2, R3, and R4 may be different from each other.

[0056] (1st to 4th group contacts) 6, the contacts 70 each extend in the Z direction and have different lengths in the Z direction. For example, the contacts 70 located closer to the -X direction extend further in the +Z direction. Each contact 70 is an example of a "columnar body."

[0057] The contacts 70 are arranged in first to fourth regions R1, R2, R3, and R4. The contacts 70 include a first group CG1 of contacts 70A, a second group CG2 of contacts 70B, a third group CG3 of contacts 70C, and a fourth group CG4 of contacts 70D.

[0058] The multiple contacts 70A in the first group CG1 are multiple contacts 70 arranged in the first region R1. Among the multiple contacts 70A in the first group CG1, the contacts 70A located closer to the -X direction in the first region R1 extend farther in the +Z direction. One contact 70A included in the multiple contacts 70A in the first group CG1 is an example of a "first contact."

[0059] The multiple contacts 70B in the second group CG2 are multiple contacts 70 arranged in the second region R2. Among the multiple contacts 70B in the second group CG2, the contacts 70B located closer to the -X direction in the second region R2 extend farther in the +Z direction. One contact 70B included in the multiple contacts 70B in the second group CG2 is an example of a "second contact."

[0060] The multiple contacts 70C in the third group CG3 are multiple contacts 70 arranged in the third region R3. Among the multiple contacts 70C in the third group CG3, the contacts 70C located closer to the -X direction in the third region R3 extend farther in the +Z direction. Any one of the multiple contacts 70C in the third group CG3 is an example of a "third contact."

[0061] The multiple contacts 70D in the fourth group CG4 are multiple contacts 70 arranged in the fourth region R4. Among the multiple contacts 70D in the fourth group CG4, the contacts 70D located closer to the -X direction in the fourth region R4 extend farther in the +Z direction. Any one of the multiple contacts 70D in the fourth group CG4 is an example of a "fourth contact."

[0062] (1st to 4th group conductive layers) As shown in FIG. 6, the multiple conductive layers 41 include multiple conductive layers 41A in a first group LG1, multiple conductive layers 41B in a second group LG2, multiple conductive layers 41C in a third group LG3, and multiple conductive layers 41D in a fourth group LG4.

[0063] The multiple conductive layers 41A in the first group LG1 are multiple conductive layers 41 corresponding to the multiple contacts 70A in the first group CG1. In this application, "corresponding" means electrically connected to each other. Among the multiple conductive layers 41A in the first group LG1, the conductive layer 41 located closer to the +Z direction extends farther in the -X direction. One conductive layer 41A included in the multiple conductive layers 41A in the first group LG1 (the conductive layer 41A corresponding to the first contact) is an example of a "first gate electrode layer."

[0064] The multiple conductive layers 41B of the second group LG2 are multiple conductive layers 41 corresponding to the multiple contacts 70B of the second group CG2. The multiple conductive layers 41B of the second group LG2 are arranged on the +Z direction side of the multiple conductive layers 41A of the first group LG1. The multiple conductive layers 41B of the second group LG2 are arranged between the multiple conductive layers 41A of the first group LG1 and the multiple conductive layers 41C of the third group LG3 in the Z direction. One conductive layer 41B included in the multiple conductive layers 41B of the second group LG2 (the conductive layer 41B corresponding to the second contact) is an example of a "second gate electrode layer."

[0065] The multiple conductive layers 41C of the third group LG3 are multiple conductive layers 41 corresponding to the multiple contacts 70C of the third group CG3. The multiple conductive layers 41C of the third group LG3 are arranged on the +Z direction side with respect to the multiple conductive layers 41B of the second group LG2. The multiple conductive layers 41C of the third group LG3 are arranged in the Z direction between the multiple conductive layers 41B of the second group LG2 and the multiple conductive layers 41D of the fourth group LG4. One conductive layer 41C (conductive layer 41C corresponding to the above-mentioned third contact) included in the multiple conductive layers 41C of the third group LG3 is an example of a "third gate electrode layer."

[0066] The conductive layers 41D in the fourth group LG4 are the conductive layers 41 corresponding to the contacts 70D in the fourth group CG4. The conductive layers 41D in the fourth group LG4 are disposed on the +Z direction side with respect to the conductive layers 41C in the third group LG3. One conductive layer 41D included in the conductive layers 41D in the fourth group LG4 (the conductive layer 41D corresponding to the fourth contact) is an example of a "fourth gate electrode layer."

[0067] (Conductive protrusion) As shown in FIG. 6, the laminate 40 has a plurality of first protruding portions 45 and a plurality of second protruding portions 46.

[0068] A plurality of first protrusions 45 are provided in the first region R1. The first protrusions 45 are provided on the surface on the -Z direction side of the end of the conductive layer 41A of the first group LG1, and are conductive protrusions protruding in the -Z direction from the conductive layer 41A. The first protrusions 45 protrude from the conductive layer 41A toward the contact 70A included in the first group CG1 and are in contact with the contact 70A. In other words, the first protrusions 45 are disposed between the conductive layer 41A and the contact 70A in the Z direction, and electrically connect the conductive layer 41A and the contact 70A.

[0069] In this embodiment, the first protrusion 45 is provided on each of the multiple conductive layers 41A in the first group LG1. Each contact 70A included in the multiple contacts 70A in the first group CG1 is in contact with a first protrusion 45 provided on the conductive layer 41A included in the multiple conductive layers 41A in the first group LG1 and corresponding to the contact 70A. In this embodiment, the X-direction width of the -Z-direction end of the first protrusion 45 and the X-direction width of the +Z-direction end of the contact 70A connected to the first protrusion 45 are the same.

[0070] A plurality of second protrusions 46 are provided in the third region R3. The second protrusions 46 are provided on the surface on the -Z direction side of the end of the conductive layer 41C of the third group LG3, and are conductive protrusions protruding in the -Z direction from the conductive layer 41C. The second protrusions 46 protrude from the conductive layer 41C toward the contact 70C of the third group CG3 and are in contact with the contact 70C. In other words, the second protrusions 46 are disposed between the conductive layer 41C and the contact 70C in the Z direction, and electrically connect the conductive layer 41C and the contact 70C.

[0071] In this embodiment, the second protrusion 46 is provided on each of the multiple conductive layers 41C in the third group LG3. Each contact 70C included in the multiple contacts 70C in the third group CG3 is in contact with the second protrusion 46 provided on the conductive layer 41C included in the multiple conductive layers 41C in the third group LG3 and corresponding to the contact 70C. In this embodiment, the X-direction width of the -Z-direction end of the second protrusion 46 and the X-direction width of the +Z-direction end of the contact 70C connected to the second protrusion 46 are the same.

[0072] The first protrusion 45 and the second protrusion 46 are regrown portions formed by, for example, re-growing a material contained in the conductive layer 41. The first protrusion 45 and the second protrusion 46 are formed so as to protrude from the surface of the conductive layer 41 by, for example, selectively re-growing a material contained in the conductive layer 41 by CVD (Chemical Vapor Deposition). The material (first material) contained in the conductive layer 41 and regrown is, for example, tungsten, molybdenum, or silicon doped with impurities, but is not limited thereto. Note that the first protrusion 45 and the second protrusion 46 may be protrusions formed by re-growing by a method other than CVD, or may be protrusions formed by a method other than regrowth. In the following, when the first protrusion 45 and the second protrusion 46 are not distinguished from each other, they are referred to as "protrusion PT".

[0073] On the other hand, no protrusions corresponding to the protrusions PT are provided in the second region R2 and the fourth region R4 of the laminate 40. Therefore, each of the contacts 70B included in the plurality of contacts 70B in the second group CG2 is in contact with a conductive layer 41B included in the plurality of conductive layers 41B in the second group LG2 and corresponding to the contact 70B, without passing through the protrusion. Also, each of the contacts 70D included in the plurality of contacts 70D in the fourth group CG4 is in contact with a conductive layer 41D included in the plurality of conductive layers 41D in the fourth group LG4 and corresponding to the contact 70D, without passing through the protrusion.

[0074] In other words, in the laminate 40, regions (e.g., the first region R1 or the third region R3) in which a plurality of protrusions PT (e.g., a plurality of first protrusions 45 or a plurality of second protrusions 46) are provided and regions (e.g., the second region R2 and the fourth region R4) in which the above protrusions PT are not present are arranged alternately in the X direction.

[0075] 7 is an enlarged cross-sectional view of a portion of the staircase region SR of this embodiment. First, a description will be given of an example of the configuration of the conductive layer 41. The conductive layer 41 includes, for example, a conductive portion 101, a barrier metal film 102, and an insulating film 103.

[0076] The conductive portion 101 is a portion that forms the main portion of the conductive layer 41. The conductive portion 101 extends in a layer shape in the X direction and the Y direction. The conductive portion 101 includes the above-mentioned conductive material (for example, tungsten, molybdenum, or silicon doped with an impurity).

[0077] The barrier metal film 102 is a film for suppressing diffusion of a conductive material contained in the conductive portion 101. The barrier metal film 102 is provided along the surface of the conductive portion 101. For example, the barrier metal film 102 is provided along both the surface on the +Z direction side and the surface on the -Z direction side of the conductive portion 101. The barrier metal film 102 is formed of, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen.

[0078] The insulating film 103 is an insulating film provided on the surface of the conductive layer 41. The insulating film 103 forms a part of the block insulating film 61, for example, at the intersection of the memory pillar MH and the conductive layer 41. The insulating film 103 is located on the opposite side of the barrier metal film 102 from the conductive portion 101. The insulating film 103 is provided along the surface of the barrier metal film 102. For example, the insulating film 103 is provided along both the surface on the +Z direction side and the surface on the -Z direction side of the barrier metal film 102. The insulating film 103 is, for example, but is not limited to, aluminum oxide. Also, the insulating film 103 may be omitted.

[0079] Next, a description will be given of an example of the configuration of the contact 70. The contact includes, for example, a conductive portion 111 and a barrier metal film 112.

[0080] The conductive portion 111 is a portion that forms the main portion of the contact 70. The conductive portion 111 extends in a columnar shape in the Z direction. The conductive portion 111 includes the above-mentioned conductive material (for example, tungsten, molybdenum, or silicon doped with an impurity).

[0081] The barrier metal film 112 is a film for suppressing diffusion of the conductive material contained in the conductive portion 111. The barrier metal film 112 is provided along the surface of the conductive portion 111. For example, the barrier metal film 112 has a peripheral surface portion 112a extending in the Z direction along the peripheral surface of the conductive portion 111, and a bottom surface portion 112b provided along the bottom surface of the conductive portion 111 on the +Z direction side. The barrier metal film 112 forms, for example, the surface of the contact 70. The barrier metal film 112 is formed of, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen.

[0082] 7, the first protrusion 45 is provided between the conductive layer 41A and the contact 70A in the Z direction. Therefore, in a region (first region R1) in which the first protrusion 45 exists, the barrier metal film 112 of the contact 70A and the conductive layer 41A (e.g., the barrier metal film 102 of the conductive layer 41A) are separated from each other, and a distance L1 exists between the barrier metal film 112 of the contact 70A and the conductive layer 41A. In this embodiment, a part of the first protrusion 45 penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41A and is located inside the conductive layer 41A.

[0083] On the other hand, in a region (second region R2) where the first protrusion 45 does not exist, the contact 70B is in contact with the conductive layer 41B. For example, a part of the contact 70B penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41B and is located inside the conductive layer 41B. In this case, in the region (second region R2) where the first protrusion 45 does not exist, the barrier metal film 112 of the contact 70B and the conductive layer 41B (for example, the barrier metal film 102 of the conductive layer 41B) are in contact with each other.

[0084] Similarly, the second protrusion 46 is provided between the conductive layer 41C and the contact 70C in the Z direction. Therefore, in a region (third region R3) where the second protrusion 46 exists, the barrier metal film 112 of the contact 70C and the conductive layer 41C (e.g., the barrier metal film 102 of the conductive layer 41C) are separated from each other, and a distance L2 exists between the barrier metal film 112 of the contact 70C and the conductive layer 41C. In this embodiment, a part of the second protrusion 46 penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41C and is located inside the conductive layer 41C.

[0085] On the other hand, in a region (fourth region R4) where the second protrusion 46 does not exist, the contact 70D is in contact with the conductive layer 41D. For example, a part of the contact 70D penetrates the insulating film 103 and the barrier metal film 102 of the conductive layer 41D and is located inside the conductive layer 41D. In this case, in the region (fourth region R4) where the second protrusion 46 does not exist, the barrier metal film 112 of the contact 70D and the conductive layer 41D (for example, the barrier metal film 102 of the conductive layer 41D) are in contact with each other.

[0086] As described above, in this embodiment, in a cross section along the X direction and the Y direction (cross section shown in FIG. 7), the shortest distance (e.g., a distance of zero) between the barrier metal film 112 of the contact 70B and the conductive layer 41B is shorter than the shortest distance L1 between the barrier metal film 112 of the contact 70A and the conductive layer 41A, and is shorter than the shortest distance L3 between the barrier metal film 112 of the contact 70C and the conductive layer 41C. Similarly, in a cross section along the X direction and the Y direction, the shortest distance (e.g., a distance of zero) between the barrier metal film 112 of the contact 70D and the conductive layer 41D is shorter than the shortest distance L1 between the barrier metal film 112 of the contact 70A and the conductive layer 41A, and is shorter than the shortest distance L2 between the barrier metal film 112 of the contact 70C and the conductive layer 41C. In other words, for example, when there is a distance between the barrier metal film 112 (for example, the bottom surface portion 112b of the barrier metal film 112) of the contact 70 and the conductive layer 41, it can be said that a protrusion portion PT exists between the contact 70 and the conductive layer 41.

[0087] In the present embodiment, an example in which the contact 70 has the barrier metal film 112 has been described. However, the contact 70 does not have to have the barrier metal film 112. Even in this case, it can be said that the protrusion PT exists between the contact 70 and the conductive layer 41 when the crystal grain state (size of crystal grains or packing density of crystal grains, etc.) is different between the contact 70 and the protrusion PT, impurities (oxygen, etc.) are present at the interface between the contact 70 and the protrusion PT, or the internal impurities are different between the contact 70 and the protrusion PT. From another perspective, it can be said that the protrusion PT exists between the contact 70 and the conductive layer 41 when the crystal grain state (size of crystal grains or packing density of crystal grains, etc.) is different between the conductive layer 41 and the protrusion PT, impurities (oxygen, etc.) are present at the interface between the conductive layer 41 and the protrusion PT, or the internal impurities are different between the conductive layer 41 and the protrusion PT.

[0088] 6. Manufacturing method of semiconductor memory device Next, a method for manufacturing the semiconductor memory device 1 will be described. 8A and 8B are diagrams for explaining a manufacturing method of the semiconductor memory device 1. Note that the following describes a method for forming the staircase region SR. Other parts of the semiconductor memory device 1 can be formed by known methods. Note that, for convenience of explanation, the insulating layer 42 and the insulating portion 43 are shown as one body in Figs. 8A and 8B.

[0089] First, a laminate 40 is formed, which includes a plurality of conductive layers 41, a plurality of insulating layers 42, and an insulating portion 43 (see (ST1) in FIG. 8A). The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately laminated one by one in the Z direction. The conductive layer 41 is an example of a "first layer." The insulating layer 42 is an example of a "second layer." The laminate 40 has first to fourth regions R1, R2, R3, and R4. These regions are arranged in the X direction in the order of the first region R1, the second region R2, the third region R3, and the fourth region R4.

[0090] The laminate 40 is formed, for example, by forming an intermediate laminate in which sacrificial layers and insulating layers 42 are alternately stacked one by one in the Z direction, and then replacing the sacrificial layers with the conductive layers 41. The replacement of the sacrificial layers with the conductive layers 41 is performed, for example, by removing the sacrificial layers from the intermediate laminate by wet etching, and supplying materials for forming the insulating film 103, the barrier metal film 102, and the conductive portion 101 in that order into the space from which the sacrificial layers have been removed, thereby forming the conductive layer 41.

[0091] Next, a mask M is formed so as to cover the laminate 40. Then, a plurality of openings 121 for hole processing are formed in the mask M in regions corresponding to the third region R3 and the fourth region R4 of the laminate 40, for example, by lithography. Then, by performing hole processing in the third region R3 and the fourth region R4 of the laminate 40 through the plurality of openings 121 of the mask M, a plurality of holes 122 each extending halfway in the Z direction of the laminate 40 are formed (see (ST2) in FIG. 8A).

[0092] Next, a plurality of openings 131 for hole processing are formed in the mask M in regions corresponding to the first region R1 and the second region R2 of the laminate 40 by, for example, lithography (see (ST3) in A of FIG. 8).

[0093] Next, holes are drilled in the first region R1 and the second region R2 of the laminate 40 through the multiple openings 131 of the mask M, and the multiple openings 121 of the mask M are used to resume drilling in the third region R3 and the fourth region R4 of the laminate 40. Then, drilling in the first region R1, the second region R2, the third region R3, and the fourth region R4 is stopped when the multiple holes 132 formed in the second region R2 of the laminate 40 and the multiple holes 122 formed in the fourth region R4 do not reach the conductive layer 41 to be connected to among the multiple conductive layers 41, and the multiple holes 132 formed in the first region R1 of the laminate 40 and the multiple holes 122 formed in the third region R3 of the laminate 40 reach the conductive layer 41 to be connected to among the multiple conductive layers 41 (see (ST4) in FIG. 8B).

[0094] Next, a conductive material for the conductive portion 41 is supplied, for example, by CVD, into each of the holes 131 formed in the first region R1 and the holes 121 formed in the third region R3 of the laminate 40, to form a protrusion PT, which is a regrown portion, on the surface of the conductive portion 41 (see (ST5) in FIG. 8B). The protrusion PT is, for example, a conductive portion that forms the first protrusion 45 or the second protrusion 46.

[0095] Next, hole processing is resumed in the first region R1, the second region R2, the third region R3, and the fourth region R4 of the laminate 40 through the multiple openings 121, 131 of the mask M. At this time, multiple first protrusions 45 are present in the first region R1 of the laminate 40, and multiple second protrusions 46 are present in the third region R3. Therefore, the multiple first protrusions 45 and the multiple second protrusions 46 function as stopper layers, and the multiple holes 122, 132 are prevented from being formed deeply in the first region R1 and the third region R3, penetrating the conductive layer 41 to be connected.

[0096] Then, when the plurality of holes 132 formed in the second region R2 of the laminate 40 and the plurality of holes 122 formed in the fourth region R4 reach the conductive layer 41 to which they are to be connected among the plurality of conductive layers 41, the hole processing in the first region R1, the second region R2, the third region R3, and the fourth region R4 is stopped (see (ST6) in FIG. 8B). Thereafter, the materials of the barrier metal film 112 and the conductive portion 111 are sequentially supplied into the plurality of holes 122, 132 to form the contact 70. This completes the formation of the staircase region SR.

[0097] <7. Advantages> As a comparative example, in the hole processing for providing the contact 70, a re-grown portion of tungsten or the like is formed inside the multiple holes corresponding to the conductive layer 41 in the upper half (portion on the -Z direction side) of the multiple conductive layers 41, thereby suppressing the hole penetration into the conductive layer 41 in the upper half of the multiple conductive layers 41. However, in this case, the hole processing in the upper layer portion (portion on the -Z direction side) of the upper half of the multiple conductive layers 41 is difficult, and there is a possibility that the hole penetration will occur in the upper layer portion. For this reason, in the configuration of the above comparative example, it is necessary to increase the film thickness of the re-grown portion in the upper layer portion by, for example, performing multiple re-growth processes. In this case, the manufacturability of the semiconductor memory device is reduced.

[0098] On the other hand, in this embodiment, the semiconductor memory device 1 includes a stacked body 40 and a plurality of contacts 70. The stacked body 40 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one by one in the Z direction. The plurality of contacts 70 each extend in the Z direction. The stacked body 40 includes a first region R1, a second region R2, and a third region R3. The first region R1, the second region R2, and the third region R3 are arranged in the X direction in this order. The plurality of contacts 70 include a first contact 70A arranged in the first region R1, a second contact 70B arranged in the second region R2, and a third contact 70C arranged in the third region R3. The multiple conductive layers 41 include a first conductive layer 41A, a second conductive layer 41B disposed on the +Z direction side of the first conductive layer 41A, and a third conductive layer 41C disposed on the +Z direction side of the second conductive layer 41B. The laminate 40 includes a conductive first protrusion 45 protruding from the first conductive layer 41A toward the first contact 70A, and a conductive second protrusion 46 protruding from the third conductive layer 41C toward the third contact 70C. The first contact 70A is in contact with the first protrusion 45. The second contact 70B is in contact with the second conductive layer 41B. The third contact 70C is in contact with the second protrusion 46.

[0099] According to this configuration, the hole processing for providing the contact 70 can be performed separately for a region including the first region R1 and the second region R2 and a region including the third region R3. Therefore, even if the first protruding portion 45 and the second protruding portion 46 do not have a large thickness, it is possible to prevent the hole from penetrating through the conductive layer 41. This makes it easier to form the first protruding portion 45 and the second protruding portion 46, and improves the manufacturability of the semiconductor memory device 1.

[0100] <8. Variations> Next, a modification of the first embodiment will be described. FIG. 9 is a cross-sectional view showing the staircase region SR of the semiconductor memory device 1A of the modified example of the first embodiment. In this modified example, the contact 70A has an end 70e1 in contact with the first protrusion 45. The end 70e1 is an example of the "first end". On the other hand, the first protrusion 45 has an end 45e1 in contact with the contact 70A. The end 45e1 is an example of the "second end". Here, the hole 132 (see FIG. 8B) for providing the contact 70A may be enlarged in diameter by wet etching, for example, for manufacturing reasons, after the first protrusion 45 is provided. In this case, the width W1 in the X direction of the end 70e1 of the contact 70A is larger than the width W2 in the X direction of the end 45e1 of the first protrusion 45.

[0101] Similarly, the contact 70C has an end 70e1 in contact with the second protrusion 46. Meanwhile, the second protrusion 46 has an end 46e1 in contact with the contact 70C. The hole 122 (see FIG. 8B) for providing the contact 70C may be enlarged in diameter by wet etching, for example, for manufacturing reasons, after the second protrusion 46 is provided. In this case, the width W3 in the X direction of the end 70e1 of the contact 70C is larger than the width W4 in the X direction of the end 46e1 of the second protrusion 46.

[0102] As described above, even if the contact 70 does not have the barrier metal film 112, when the X-direction width W1 of the end 70e1 of the contact 70A is larger than the X-direction width W2 of the end 45e1 of the first protrusion 45, it can be said that the first protrusion 45 exists between the contact 70A and the conductive layer 41A. Similarly, when the X-direction width W3 of the end 70e1 of the contact 70C is larger than the X-direction width W4 of the end 46e1 of the second protrusion 46, it can be said that the second protrusion 46 exists between the contact 70C and the conductive layer 41C.

[0103] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the staircase region SR has six divided regions in the X direction. Note that the configuration other than that described below is the same as the first embodiment.

[0104] 10 is a cross-sectional view showing a semiconductor memory device 1B of the second embodiment. In this embodiment, the staircase region SR has, for example, first to sixth regions R1, R2, R3, R4, R5, and R6. These regions are arranged in the X direction in the order of the first region R1, the second region R2, the third region R3, the fourth region R4, the fifth region R5, and the sixth region R6. The first to sixth regions R1, R2, R3, R4, R5, and R6 are, for example, regions obtained by dividing the staircase region SR into six in the X direction. However, the sizes of the first to sixth regions R1, R2, R3, R4, R5, and R6 may be different from each other.

[0105] (1st to 6th group contacts) The contacts 70 are arranged in the first to sixth regions R1, R2, R3, R4, R5, and R6. The contacts 70 include a first group CG1 of contacts 70A, a second group CG2 of contacts 70B, a third group CG3 of contacts 70C, a fourth group CG4 of contacts 70D, a fifth group CG5 of contacts 70E, and a sixth group CG6 of contacts 70F.

[0106] The contacts 70E in the fifth group CG5 are contacts 70 arranged in the fifth region R5. The contacts 70E in the fifth group CG5 extend farther in the +Z direction as the contacts 70E are located closer to the -X direction in the fifth region R5. One contact 70E included in the contacts 70E in the fifth group CG5 is an example of a "fifth contact."

[0107] The multiple contacts 70F in the sixth group CG6 are multiple contacts 70 arranged in the sixth region R6. Among the multiple contacts 70F in the sixth group CG6, the contacts 70F located closer to the -X direction in the sixth region R6 extend farther in the +Z direction. One contact 70F included in the multiple contacts 70F in the sixth group CG6 is an example of a "sixth contact."

[0108] (1st to 6th Group Conductive Layers) The multiple conductive layers 41 include multiple conductive layers 41A in the first group LG1, multiple conductive layers 41B in the second group LG2, multiple conductive layers 41C in the third group LG3, multiple conductive layers 41D in the fourth group LG4, multiple conductive layers 41E in the fifth group LG5, and multiple conductive layers 41F in the sixth group LG6.

[0109] The conductive layers 41E of the fifth group LG5 are the conductive layers 41 corresponding to the contacts 70E of the fifth group CG5. The conductive layers 41E of the fifth group LG5 are arranged on the +Z direction side of the conductive layers 41D of the fourth group LG4. The conductive layers 41D of the fifth group LG5 are arranged between the conductive layers 41D of the fourth group LG4 and the conductive layers 41F of the sixth group LG6 in the Z direction. One conductive layer 41E included in the conductive layers 41E of the fifth group LG5 (conductive layer 41E corresponding to the fifth contact) is an example of a "fifth gate electrode layer."

[0110] The conductive layers 41F in the sixth group LG6 are the conductive layers 41 corresponding to the contacts 70F in the sixth group CG6. The conductive layers 41F in the sixth group LG6 are disposed on the +Z direction side with respect to the conductive layers 41E in the fifth group LG5. One conductive layer 41F included in the conductive layers 41F in the sixth group LG6 (the conductive layer 41F corresponding to the sixth contact) is an example of a "sixth gate electrode layer."

[0111] (Conductive protrusion) As shown in FIG. 6, the laminate 40 has a plurality of first protruding portions 45, a plurality of second protruding portions 46, and a plurality of third protruding portions 47.

[0112] A plurality of third protrusions 47 are provided in the fifth region R5. The third protrusions 47 are provided on the surface on the -Z direction side of the end of the conductive layer 41E of the fifth group LG5, and are conductive protrusions protruding from the conductive layer 41E in the -Z direction. The third protrusions 47 protrude from the conductive layer 41E toward the contact 70E of the fifth group CG5 and are in contact with the contact 70E. In other words, the third protrusions 47 are disposed between the conductive layer 41E and the contact 70E in the Z direction, and electrically connect the conductive layer 41E and the contact 70E. The third protrusions 47 are regrown portions formed by re-growing a material contained in the conductive layer 41, similar to the first protrusions 45 and the second protrusions 46.

[0113] In this embodiment, the third protrusion 47 is provided on each of the multiple conductive layers 41E in the fifth group LG5. Each contact 70E included in the multiple contacts 70E in the fifth group CG5 is in contact with the third protrusion 47 provided on the conductive layer 41E included in the multiple conductive layers 41E in the fifth group LG5 and corresponding to the contact 70E. Hereinafter, when the first protrusion 45, the second protrusion 46, and the third protrusion 47 are not distinguished from each other, they will be referred to as "protrusion PT."

[0114] (Method of manufacturing semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1B of the second embodiment will be described. 11A to 11C are diagrams for explaining a manufacturing method of a semiconductor memory device 1B according to the second embodiment. For convenience of explanation, the insulating layer 42 and the insulating portion 43 are shown as one body in Fig. 11A to 11C.

[0115] First, similarly to the first embodiment, the laminate 40 is formed (see (ST1) in FIG. 11A). Next, a mask M is formed so as to cover the laminate 40. Then, in the mask M, a plurality of openings 141 for hole processing are formed, for example, by lithography, in regions corresponding to the fifth region R5 and the sixth region R6 of the laminate 40. Then, by performing hole processing in the fifth region R5 and the sixth region R6 of the laminate 40 through the plurality of openings 141 in the mask M, a plurality of holes 142 each extending halfway in the Z direction of the laminate 40 are formed (see (ST2) in FIG. 11A).

[0116] Next, in the mask M, a plurality of openings 131 for hole processing are formed by, for example, lithography in regions corresponding to the third region R3 and the fourth region R4 of the laminate 40 (see (ST3) in FIG. 11A).

[0117] Next, holes are drilled in the third region R3 and the fourth region R4 of the laminate 40 through the multiple openings 131 of the mask M, and hole drilling is resumed in the fifth region R5 and the sixth region R6 of the laminate 40 using the multiple openings 141 of the mask M. Then, holes are drilled in the third to sixth regions R3, R4, R5, and R6 of the laminate 40 through the multiple openings 131 and 141 of the mask M, thereby forming multiple holes 132 and 142 that each extend halfway in the Z direction of the laminate 40 (see (ST4) in FIG. 11B).

[0118] Next, a plurality of openings 121 for hole processing are formed in the mask M in regions corresponding to the first region R1 and the second region R2 of the laminate 40 by, for example, lithography (see (ST5) in FIG. 11B).

[0119] Next, holes are drilled in the first region R1 and the second region R2 of the laminate 40 through the multiple openings 121 of the mask M, and the multiple openings 131 and 141 of the mask M are used to resume drilling holes in the third to sixth regions R3, R4, R5, and R6 of the laminate 40. Then, the drilling of the first to sixth regions R1, R2, R3, R4, R5, and R6 is stopped when the multiple holes 122 formed in the second region R2 of the laminate 40, the multiple holes 132 formed in the fourth region R4, and the multiple holes 142 formed in the sixth region R6 of the laminate 40 do not reach the conductive layer 41 to be connected to, and the multiple holes 122 formed in the first region R1 of the laminate 40, the multiple holes 132 formed in the third region R3, and the multiple holes 142 formed in the fifth region R5 of the laminate 40 reach the conductive layer 41 to be connected to, respectively (see (ST6) in FIG. 11B).

[0120] Next, the conductive material of the conductive portion 41 is supplied, for example, by CVD, into each of the holes 122 formed in the first region R1 of the laminate 40, the holes 132 formed in the third region R3, and the holes 142 formed in the fifth region R5, to form a protrusion PT, which is a regrown portion, on the surface of the conductive portion 41 (see (ST7) in FIG. 11B). The protrusion PT is, for example, a conductive portion that forms the first protrusion 45, the second protrusion 46, or the third protrusion 47.

[0121] Next, hole processing is resumed in the first to sixth regions R1, R2, R3, R4, R5, and R6 of the laminate 40 through the multiple openings 121, 131, and 141 of the mask M. At this time, multiple first protrusions 45 are present in the first region R1 of the laminate 40, multiple second protrusions 46 are present in the third region R3, and multiple third protrusions 47 are present in the fifth region R5. Therefore, the multiple first protrusions 45, the multiple second protrusions 46, and the third protrusion 47 function as stopper layers, and multiple holes 122, 132, and 142 are prevented from being formed deeply through the conductive layer 41 to be connected in the first region R1, the third region R3, and the fifth region R5.

[0122] Then, when the plurality of holes 122 formed in the second region R2 of the laminate 40, the plurality of holes 132 formed in the fourth region R4, and the plurality of holes 142 formed in the sixth region R6 reach the conductive layer 41 to which they are connected among the plurality of conductive layers 41, the hole processing of the first to sixth regions R1, R2, R3, R4, R5, and R6 is stopped (see (ST8) in FIG. 11C). After that, the materials of the barrier metal film 112 and the conductive portion 111 are sequentially supplied into the plurality of holes 122, 132, and 142 to form the contact 70. This completes the formation of the staircase region SR.

[0123] According to this configuration, the reliability of the semiconductor memory device 1B is improved, as in the first embodiment. Furthermore, according to this embodiment, since the number of divisions is greater than that of the first embodiment, even if the first protruding portion 45, the second protruding portion 46, and the third protruding portion 47 are thin, it is possible to suppress the penetration of holes into the conductive layer 41. This makes it easier to form the protruding portions 45, 46, and 47, and improves the manufacturability of the semiconductor memory device 1B.

[0124] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment in that the configuration of the first embodiment is applied to a multi-row staircase type staircase area SR. The configuration other than that described below is the same as the first embodiment.

[0125] 12 is a perspective cross-sectional view showing a staircase region SR of a semiconductor memory device 1C according to a third embodiment. In this embodiment, the conductive layers 41 have a multi-row staircase type staircase region SR. For example, FIG. 12 shows a two-row staircase type staircase region SR as an example of the multi-row staircase type. Note that FIG. 12 shows four conductive layers 41 in each of the regions R1, R2, R3, and R4.

[0126] In the third embodiment, an odd-numbered conductive layer 41 in the Z direction (hereinafter, for convenience of explanation, referred to as "conductive layer 41S") has a first portion 151 and a second portion 152. The first portion 151 and the second portion 152 are aligned in the Y direction in each conductive layer 41S. The length of the second portion 152 in the -X direction is shorter than the length of the first portion 151 in the - direction.

[0127] On the other hand, the conductive layer 41 adjacent to the conductive layer 41S in the +Z direction (hereinafter, for convenience of explanation, referred to as "conductive layer 41T") ​​has a third portion 153 and a fourth portion 154. The third portion 153 and the fourth portion 154 are aligned in the Y direction in each conductive layer 41T. The third portion 153 is located on the +Z direction side of the first portion 151 of the conductive layer 41S. The fourth portion 154 is located on the +Z direction side of the second portion 152 of the conductive layer 41S. The length in the -X direction of each of the third portion 153 and the fourth portion 154 is the same as the length in the -X direction of the first portion 151 of the conductive layer 41S. As a result, the third portion 153 of the conductive layer 41T is covered by the first portion 151 of the conductive layer 41S. On the other hand, the fourth portion 154 of the conductive layer 41T is exposed in the -Z direction without being covered by the second portion 152 of the conductive layer 41S.

[0128] In this embodiment, the multiple contacts 70 include a contact 70S electrically connected to the first portion 151 of the conductive layer 41S and a contact 70T electrically connected to the fourth portion 154 of the conductive layer 41T. The contacts 70S and the contacts 70T are aligned in the Y direction. With this configuration, the length of the staircase region SR in the -X direction can be shortened.

[0129] In this embodiment, a first protrusion 45 is provided between each contact 70S arranged in the first region R1 of the laminate 40 and a first portion 151 of the conductive layer 41S corresponding to the contact 70S. Also, a first protrusion 45 is provided between each contact 70T arranged in the first region R1 of the laminate 40 and a fourth portion 154 of the conductive layer 41T corresponding to the contact 70T.

[0130] Similarly, a second protrusion 46 is provided between each contact 70S arranged in the third region R3 of the laminate 40 and a first portion 151 of the conductive layer 41S corresponding to the contact 70S. In addition, a second protrusion 46 is provided between each contact 70T arranged in the third region R3 of the laminate 40 and a fourth portion 154 of the conductive layer 41T corresponding to the contact 70T.

[0131] On the other hand, in the second region R2 and the fourth region R4 of the laminate 40, there is no protrusion PT between each contact 70S and the first portion 151 of the conductive layer 41S corresponding to the contact 70S, and each contact 70S is in contact with the first portion 151 of the conductive layer 41S. Similarly, in the second region R2 and the fourth region R4 of the laminate 40, there is no protrusion PT between each contact 70T and the fourth portion 154 of the conductive layer 41T corresponding to the contact 70T, and each contact 70T is in contact with the fourth portion 154 of the conductive layer 41T.

[0132] According to this configuration, similarly to the first embodiment, the manufacturability of the semiconductor memory device 1C can be improved. In this embodiment, the two-row staircase type staircase region SR has been described. However, the embodiment is not limited to the above example. For example, the semiconductor memory device 1C may have a multi-row staircase type staircase region SR having three or more rows.

[0133] (Modification) Next, modifications of the first to third embodiments will be described. 13 is a cross-sectional view showing a staircase region SR of a semiconductor memory device 1D according to a modification of the embodiment. Fig. 13 shows a modification corresponding to the configuration of the semiconductor memory device 1 according to the first embodiment. In this modification, the closer the protrusion PT is located in the +Z direction, the greater the thickness of the protrusion PT in the Z direction.

[0134] For example, the multiple protrusions 45 provided in the first region R1 include a protrusion 45-1, a protrusion 45-2, and a protrusion 45-3.

[0135] The protrusion 45-2 is disposed on the +Z direction side compared to the protrusion 45-1. In other words, the conductive layer 41A on which the protrusion 45-2 is provided is located on the +Z direction side of the conductive layer 41A on which the protrusion 45-1 is provided. In this modification, the thickness T2 of the protrusion 45-2 in the Z direction is larger than the thickness T1 of the protrusion 45-1 in the Z direction.

[0136] The protrusion 45-3 is disposed on the +Z direction side compared to the protrusion 45-2. In other words, the conductive layer 41A on which the protrusion 45-3 is provided is located on the +Z direction side of the conductive layer 41A on which the protrusion 45-2 is provided. In this modification, the Z direction thickness T3 of the protrusion 45-3 is larger than the Z direction thickness T2 of the protrusion 45-2.

[0137] Similarly, the multiple protrusions 46 provided in the third region R3 include a protrusion 46-1, a protrusion 46-2, and a protrusion 46-3.

[0138] The protrusion 46-1 is disposed on the +Z direction side compared to the protrusion 45-3 provided in the first region R1. In other words, the conductive layer 41C on which the protrusion 46-1 is provided is located on the +Z direction side of the conductive layer 41A on which the protrusion 45-3 is provided. In this modification, the Z direction thickness T4 of the protrusion 46-1 is greater than the Z direction thickness T3 of the protrusion 45-3.

[0139] The protrusion 46-2 is disposed on the +Z direction side compared to the protrusion 46-1. In other words, the conductive layer 41C on which the protrusion 46-2 is provided is located on the +Z direction side of the conductive layer 41C on which the protrusion 46-1 is provided. In this modification, the Z direction thickness T5 of the protrusion 46-2 is greater than the Z direction thickness T4 of the protrusion 46-1.

[0140] The protrusion 46-3 is disposed on the +Z direction side compared to the protrusion 46-2. In other words, the conductive layer 41C on which the protrusion 46-3 is provided is located on the +Z direction side of the conductive layer 41C on which the protrusion 46-2 is provided. In this modification, the Z direction thickness T6 of the protrusion 46-3 is greater than the Z direction thickness T5 of the protrusion 46-2.

[0141] The above-described configuration is realized, for example, by the fact that the closer the protrusion PT is located in the -Z direction, the more it is removed by etching during processing of the hole 122 or the hole 132. However, the above-described configuration may be realized for a reason other than the above-described etching.

[0142] The configuration of this modification may be applied to the configuration of the second embodiment. In this case, for the multiple protrusions PT included in the first region R1, the third region R3, and the fifth region R5, the protrusions PT located closer to the +Z direction have a larger thickness in the Z direction.

[0143] Some embodiments and modifications have been described above. However, the embodiments and modifications are not limited to the above examples. For example, some of the conductive layers 41 located on the -Z direction side (e.g., some of the conductive layers 41 on the -Z direction side of the multiple conductive layers 41 to which the contact 70A is electrically connected in the first region R1) may not have the protrusion PT. For example, some of the conductive layers 41 located on the -Z direction side of the multiple conductive layers 41 (e.g., some of the conductive layers 41 on the -Z direction side of the multiple conductive layers 41 to which the contact 70A is electrically connected in the first region R1) may have the protrusion PT disappear by being removed by etching during processing of the hole 122 or the hole 132. In addition, some of the multiple conductive layers 41 located on the -Z direction side (for example, some of the multiple conductive layers 41 on the -Z direction side to which the contact 70A is electrically connected in the first region R1) may be over-etched to an extent that they are not pierced when processing the hole 122 or the hole 132, etc., so that the end of the contact 70 on the +Z direction side penetrates into the conductive layer 41.

[0144] According to at least one of the embodiments described above, the semiconductor memory device includes a stacked body and a plurality of contacts. The plurality of stacked bodies include a plurality of gate electrode layers and a plurality of insulating layers. The plurality of contacts include a first contact, a second contact, and a third contact. The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer disposed on a first side with respect to the first gate electrode layer, and a third gate electrode layer disposed on the first side with respect to the second gate electrode layer. The stacked body includes a conductive first protruding portion protruding from the first gate electrode layer toward the first contact, and a conductive second protruding portion protruding from the third gate electrode layer toward the third contact. The first contact is in contact with the first protruding portion. The second contact is in contact with the second gate electrode layer. The third contact is in contact with the second protruding portion. According to such a configuration, it is possible to improve the manufacturability of the semiconductor device.

[0145] Several embodiments have been described above. However, the embodiments are not limited to the above examples. For example, the staircase region SR may be divided into eight or more parts instead of four or six parts.

[0146] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0147] 1, 1A, 1B, 1C...semiconductor memory device, 40...laminated body, 41...conductor layer (gate electrode layer), 41A...first group conductive layer, 41B...second group conductive layer, 41C...third group conductive layer, 41D...fourth group conductive layer, 41E...fifth group conductive layer, 41F...sixth group conductive layer, 42...insulating layer, 45...first protrusion, 46...second protrusion, 47...third protrusion, 70...contact, 70A...first group contact, 70B...second group contact, 70C...third group contact, 70D...fourth group contact, 70E...fifth group contact, 70F...sixth group contact, 122...barrier metal layer of contact, R1...first region, R2...second region, R3...third region, R4...fourth region, R5...fifth region, R6...sixth region.

Claims

1. a stack including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being stacked alternately in a first direction; a plurality of contacts each extending in the first direction; Equipped with the laminate includes a first region, a second region, and a third region, the first region, the second region, and the third region being arranged in this order in a second direction different from the first direction, the first region, the second region, and the third region; the plurality of contacts include a first contact disposed in the first region, a second contact disposed in the second region, and a third contact disposed in the third region; the plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer disposed on a first side in the first direction with respect to the first gate electrode layer, and a third gate electrode layer disposed on the first side with respect to the second gate electrode layer, the stack includes a first conductive protruding portion protruding from the first gate electrode layer toward the first contact, and a second conductive protruding portion protruding from the third gate electrode layer toward the third contact, the first contact is in contact with the first protrusion, the second contact is in contact with the second gate electrode layer; The third contact is in contact with the second protrusion. Semiconductor memory device.

2. When the side opposite to the first side in the first direction is the second side, the plurality of contacts are disposed in the first region and include a first group of a plurality of contacts including the first contact; the plurality of gate electrode layers are disposed on the second side with respect to the second gate electrode layer and include a first group of a plurality of gate electrode layers including the first gate electrode layer; the first protrusion is provided on each of the first group of the plurality of gate electrode layers, Each contact included in the first group of multiple contacts is in contact with the first protrusion provided on a gate electrode layer included in the first group of multiple gate electrode layers and corresponding to the contact.

2. The semiconductor memory device according to claim 1.

3. the plurality of contacts are disposed in the second region and include a second group of a plurality of contacts including the second contact; the plurality of gate electrode layers include a second group of gate electrode layers disposed between the first group of gate electrode layers and the third gate electrode layer and including the second gate electrode layer; Each contact included in the second group of contacts is in contact with a gate electrode layer included in the second group of gate electrode layers and corresponding to the contact.

3. The semiconductor memory device according to claim 2.

4. the plurality of contacts are disposed in the third region and include a third group of a plurality of contacts including the third contact; the plurality of gate electrode layers include a third group of gate electrode layers that is disposed on the first side with respect to the second group of gate electrode layers and includes the third gate electrode layer; the second protrusion is provided on each of the gate electrode layers of the third group, Each contact included in the third group of multiple contacts is in contact with the second protrusion provided on a gate electrode layer included in the third group of multiple gate electrode layers and corresponding to the contact.

4. The semiconductor memory device according to claim 3.

5. the second gate electrode layer has a length in the second direction longer than that of the first gate electrode layer in a connection region where the plurality of contacts and the plurality of gate electrode layers are connected; the third gate electrode layer has a length in the second direction longer than that of the second gate electrode layer in the connection region; 3. The semiconductor memory device according to claim 1.

6. each of the first contact, the second contact, and the third contact includes a barrier metal film; in a cross section along the first direction and the second direction, a shortest distance between the barrier metal film and the second gate electrode layer of the second contact is shorter than a shortest distance between the barrier metal film and the first gate electrode layer of the first contact, and is shorter than a shortest distance between the barrier metal film and the third gate electrode layer of the third contact; 3. The semiconductor memory device according to claim 1.

7. The first contact has a first end in contact with the first protrusion, the first protrusion has a second end in contact with the first end of the first contact; A width of the first end in the second direction is larger than a width of the second end in the second direction.

3. The semiconductor memory device according to claim 1.

8. each of the first gate electrode layer, the second gate electrode layer, and the third gate electrode layer comprises a first material that is tungsten, molybdenum, or silicon; each of the first protrusion and the second protrusion is a regrowth of the first material; 3. The semiconductor memory device according to claim 1.

9. the laminate includes a fourth region and a fifth region, the first region, the second region, the third region, the fourth region, and the fifth region being arranged in the second direction in this order: the first region, the second region, the third region, the fourth region, and the fifth region; the plurality of contacts includes a fourth contact disposed in the fourth region and a fifth contact disposed in the fifth region; the plurality of gate electrode layers include a fourth gate electrode layer disposed on the first side with respect to the third gate electrode layer, and a fifth gate electrode layer disposed on the first side with respect to the fourth gate electrode layer, the stack includes a conductive third protruding portion protruding from the fifth gate electrode layer toward the fifth contact, the fourth contact contacts the fourth gate electrode layer; The fifth contact is in contact with the third protrusion.

3. The semiconductor memory device according to claim 1.

10. forming a laminate including a plurality of first layers and a plurality of second layers, the plurality of first layers and the plurality of second layers being alternately laminated one by one in a first direction, the laminate including a first region, a second region, and a third region, the first region, the second region, and the third region being arranged in a second direction different from the first direction in the order of the first region, the second region, and the third region, the plurality of first layers including a first material; A plurality of holes are formed in the third region, each of the holes extending halfway in the first direction of the laminate; performing hole machining in the first region and the second region while resuming hole machining in the third region, thereby stopping hole machining in the first region, the second region, and the third region in a state in which the plurality of holes formed in the second region do not reach the layers to which they are respectively connected among the plurality of first layers, and the plurality of holes formed in the first region and the plurality of holes formed in the third region have reached the layers to which they are respectively connected among the plurality of first layers; forming a regrowth of the first material within each of the plurality of holes formed in the first region and the plurality of holes formed in the third region; restarting the drilling of the first area, the second area, and the third area; A method for manufacturing a semiconductor memory device comprising the steps of:

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