Circuit design device, circuit design method and circuit design program

Abstract

To provide a circuit design device, circuit design method and circuit design program that can easily design an output circuit in a short time.SOLUTION: A circuit design device 100 according to the present invention has: means that receives an output current Iout of an output circuit from a user for designing an output circuit (a source ground circuit) including a PMOS transistor as a constant current source element, and a NMOS transistor as an amplitude element connected to the constant current source element in series; determination means that determines whether the NMOS transistor satisfies a predetermined Vgs operation condition in a design space of each W value and each L value of the NMOS transistor from a current flowing to the NMOS transistor on the basis of the output current Iout; and selection means that selects candidates of a W value and L value of the PMOS transistor in a design space of each W value and each L value of the PMOS transistor on the basis of candidates of W value and L value of the NMOS transistor determined that the Vgs operation condition is satisfied.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a circuit design device, a circuit design method, and a circuit design program for designing a semiconductor integrated circuit, and more particularly to a method for designing a transistor used in an output circuit (common source circuit). [Background technology]

[0002] As an example of a circuit design device for semiconductor integrated circuits, Patent Document 1 discloses a method for generating circuit cells using a highly versatile template to shorten the design time of a target circuit. The template includes design method information for determining transistor parameters from topology information having a plurality of transistors, process information, and transistor specification information, and a user inputs the process information and transistor specification information using the template. The circuit design device determines transistor parameters according to the input process information and transistor specification information according to the design method information, and automatically generates circuit cells corresponding to the topology based on the determined parameters. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6568980 Summary of the Invention [Problem to be solved by the invention]

[0004] An output circuit included in an operational amplifier or the like is usually composed of a PMOS transistor and an NMOS transistor connected in series between the power supply voltage VDD and GND as shown in Figure 1. The PMOS transistor has a bias voltage VBIAS applied to its gate, causing it to function as a constant current source operating within the saturation region. The NMOS transistor has an input voltage VIN applied to its gate, changing the on-state of the saturation state, thereby controlling the output current and output voltage generated at node N.

[0005] In designing the above output circuit, the designer first adjusts the parameters (gate width W, gate length, drain current Ids, gate voltage Vgs, drain voltage Vds, etc.) of the constant current PMOS transistor based on the required specifications to make it function as a constant current source that operates within the saturation region. Next, the parameters of the NMOS transistor are adjusted based on the required specifications so that the output current and output voltage operate within the saturation region. If this still does not meet the specifications, the designer adjusts the parameters of the PMOS transistor again, changes the amount of current, and repeats the adjustment and trial of the parameters of the NMOS transistor again to search for a solution that meets the specifications.

[0006] However, such a design method imposes a heavy burden on the designer and increases the time required to design the output circuit.

[0007] The present invention is devised to solve such conventional problems, and has an object to provide a circuit design device, a circuit design method, and a circuit design program that enable output circuits to be designed easily in a short amount of time. [Means for solving the problem]

[0008] The electronic device with circuit design function according to the present invention has a means for receiving an output current of the output circuit from a user, for designing a source-grounded output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series to the constant current source element, and a determination means for determining whether or not an operating point of Vgs operating within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current, in a design space including each W value, each L value, and m value of the transistor, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L.

[0009] In one embodiment, the electronic device further includes a priority determination means for determining candidates for the W / L ratio in order of priority when there are a plurality of candidates for the W / L ratio of the transistor determined by the determination means to satisfy the operating point of Vgs operating in a saturation region. In one embodiment, the electronic device further includes a selection means for selecting a W / L ratio of the transistor of the constant current source element based on a current conversion ratio of the amplifying element and the constant current source element, and an adjustment means for adjusting the current conversion ratio. In one embodiment, the determination means includes a calculation means for calculating a steady-state current steadily flowing through the transistor of the output circuit according to an operating state of the transistor and a maximum current which is the sum of the steady-state current and an output current, and determines whether the Vgs voltage which is the operating point of the minimum value of the steady-state current and the maximum current is at a Vgs operating point operating in a saturation region within a range of a determined Vov voltage. In one embodiment, the priority determination means determines the priority of candidates for W / L ratios based on W, L, and m values ​​of a transistor determined to satisfy an operating point of Vgs operating within the predetermined saturation region, based on current consumption and layout area. In one embodiment, the adjustment means adjusts the balance of the current ratio (PN ratio) between a PMOS transistor of the constant current source element and an NMOS transistor of the output circuit, based on the W / L ratio of the transistor determined to satisfy an operating point of Vgs operating within the saturation region and a drain current Ids flowing through a transistor of the output circuit. In one embodiment, the candidates for W / L ratio have a pattern of combinations of W, L, and m values. In one embodiment, the steady current is calculated from various combinations defined by a ratio M of (W / L)×m based on the output current.

[0010] The circuit design method for an electronic device with a circuit design function according to the present invention includes a step of receiving an output current of the output circuit from a user for designing a source-grounded output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series to the constant current source element, and a determination step of determining whether or not an operating point of Vgs operating within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current in a design space including each W value, each L value, and m value of the transistor, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L.

[0011] The circuit design program of the present invention is executed by an electronic device having a circuit design function, and is for designing a source-grounded output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series to the constant current source element, and has a means for receiving an output current of the output circuit from a user, and a determination means for determining whether or not an operating point of Vgs operating within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current, in a design space including each W value, each L value, and m value of the transistor, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L. Effect of the Invention

[0012] According to the present invention, candidate W / L ratios for transistors in an output circuit are determined from the output current of the output circuit received from a user, so that the output circuit can be designed easily and in a short time compared to conventional design methods. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram showing a configuration of an output circuit included in an operational amplifier or the like. [Diagram 2] 1 is a block diagram showing a configuration of a circuit design device according to an embodiment of the present invention; [Diagram 3] FIG. 1 is a diagram illustrating an overview of a circuit design device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram illustrating an example of a design space of a transistor that configures an output circuit. [Diagram 5] 4 is a flow chart showing the overall operation of the circuit design program according to the present embodiment. [Figure 6] 6 is an operational flow showing a procedure for designing the amplifying element shown in FIG. 5. [Figure 7] FIG. 7A is a graph showing the Ids-Vgs characteristics (gm) when the W / L ratio is constant, and FIG. 7B is a diagram for explaining the m value of the transistor according to this embodiment. [Figure 8] 2 is a diagram illustrating an output current Isource and an output current Isink generated in an output circuit. FIG. [Figure 9] FIG. 2 is a diagram illustrating an output current in a state (1) of the output circuit. [Figure 10] FIG. 13 is a diagram illustrating an output current in a state (2) of the output circuit. [Figure 11] FIG. 13 is a diagram illustrating an output current of the output circuit in a state (3). [Figure 12] 1A to 1C are diagrams illustrating the currents 1S, 2S, and 3S that flow through an NMOS transistor when the output circuit is in states (1), (2), and (3). [Figure 13] FIG. 13(A) is a diagram explaining the current value patterns of steady-state currents generated according to each ratio when m value = 4, and FIG. 13(B) is a diagram explaining the current value patterns generated according to each ratio at 2S. [Figure 14] 1 is a graph showing the relationship between the m value and the Ids current. [Figure 15] 1 is a graph showing the relationship between Vov voltage and Ivov current. [Figure 16] 11 is a table showing an example of determining a current value pattern (W / L ratio×m) of an NMOS transistor based on a Vgs operating condition when an output current Iout is 200 uA. [Figure 17] 17 is a diagram showing an example of determining the priority order of the narrowed-down current value patterns shown in FIG. 16. FIG. [Figure 18] 17 is a diagram showing an example of determining the priority order of the narrowed-down current value patterns shown in FIG. 16. FIG. [Figure 19] 4 is an operational flow showing a procedure for designing a constant current element according to the present embodiment. [Figure 20] FIG. 13 is a diagram showing an example of a design result of a PMOS transistor according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention has a function for exploring the design space for concept design (study of feasibility) in a process-independent manner based on upstream design specifications, and designing the constants of the transistors in the circuit. Although the present invention does not particularly limit the circuit to be designed, the following describes the design of the transistor constants of the output circuit (common source circuit) that constitutes an operational amplifier (OP-AMP). EXAMPLES

[0015] An embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a block diagram showing a schematic configuration of a circuit design device of this embodiment. The circuit design device 100 is composed of an electronic device such as a computer, and includes an input unit 110 that receives instructions from a user, an output unit 120 that outputs information related to the circuit design in the form of images and / or sounds, a communication unit 130 that enables wireless or wired communication with the outside, a ROM / RAM 140, a storage unit 150 that stores data, programs, software applications, etc. required for the circuit design, and a controller 160 that controls each unit.

[0016] The input unit 110 includes, but is not limited to, for example, a keyboard, a mouse, a voice input module, etc., and the user inputs information or data required for circuit design. The information input from the input unit 110 is provided to the controller 160. The output unit 120 includes, but is not limited to, a display, a speaker, etc., and outputs various information required for circuit design. The communication unit 130 enables, but is not limited to, connection to external devices or external networks via wireless or wired connection. In one aspect, the communication unit 130 transmits and receives data required for circuit design to and from the cloud server 170.

[0017] The controller 160 includes, but is not limited to, an arithmetic processing device such as a CPU or a GPU, reads the circuit design program stored in the storage unit 150 into the ROM / RAM 140, and executes the circuit design program. The circuit design device 100 of this embodiment uses hardware and software to cause a computer to realize a circuit design.

[0018] 3 is a diagram for explaining an overview of the circuit design device 100 of this embodiment. The circuit design device 100 predicts constant values ​​of transistors in an output circuit used in an operational amplifier or the like. As input conditions, a user inputs an output current Iout and an output amplitude Iamp from an input unit 110. The output current Iout and the output amplitude Iamp are defined by the user according to the circuit characteristics of the operational amplifier.

[0019] Furthermore, the circuit design device 100 can store in the storage unit 160, as circuit design data executed by the circuit design program, a process model of a transistor, a power supply voltage Vd of the transistor, an operating temperature, and ranges (minimum value, maximum value, step width) of a W value (gate width) and an L value (gate length) related to the design space of the transistor. However, some of the circuit design data may be user-definable. For example, the user may be allowed to change the ranges of the power supply voltage, W value, L value, and m value.

[0020] Figure 4 is a diagram illustrating the design space of a transistor. For example, assuming that the parameters of the W value of a transistor are a minimum of 1 um, a maximum of 100 um, and a step width of 0.01 um, and the parameters of the L value are a minimum of 1 um, a maximum of 10 um, and a step width of 0.1 um, the number of combination patterns of the W value and L value of the transistor is 10 6 Therefore, the number of combination patterns of W and L values ​​of PMOS and NMOS transistors that configure the output circuit is 10 12 =(10 6 ) 2 It becomes.

[0021] An output circuit included in an operational amplifier or the like includes, for example, a constant current source element and an amplifying element connected in series to the constant current source element between a power supply voltage VDD and GND, as shown in FIG. 4(B), and generates an output current at a node N connecting the constant current source element and the amplifying element. The constant current element is, for example, a PMOS transistor with VBIAS applied to its gate, and supplies a constant current to an NMOS transistor, which is an amplifying element. The NMOS transistor operates in a saturated state according to an input voltage VIN applied to its gate, and controls the output current generated at the node N. The amplifying element may be a PMOS transistor and the constant current element may be an NMOS transistor, in which case the input of a differential amplifying circuit, which is the input stage of the operational amplifier, is an NMOS transistor. In this example, the amplifying element is described as an NMOS transistor, and the constant current element is described as a PMOS transistor.

[0022] The controller 160 uses the circuit design data input by the user and prepared in the memory unit 160 to predict the constant values ​​of the W value, L value, and m value (m will be described later) of the transistors of the output circuit, predicts candidates for the drain current Ids flowing through the transistors, and calculates the current conversion ratio (PN ratio) between the PMOS transistor and the NMOS transistor as a design reference point. It also makes it possible to predict gm, gd, and gb as small signal parameters of the transistor. These prediction results are output from the output unit 120.

[0023] Next, the details of the circuit design device 100 of this embodiment will be described. FIG. 5 is a flow chart showing the overall operation of the circuit design program executed by the controller 160 of the circuit design device 100 of this embodiment. When the controller 160 receives the output current Iout, output amplitude Iamp, and power supply voltage required for designing the output circuit as user definitions via the input unit 110 (S100), it designs an amplifier element (NMOS transistor) of the output circuit using the user-defined information and circuit design data prepared in advance (S200), then designs a constant current element (PMOS transistor) (S300), and outputs the design results of the amplifier element and the constant current element from the output unit 120 such as a display. It should be noted here that the design of the NMOS transistor, which is the amplifier element, is performed before the design of the PMOS transistor, which is the constant current element, which is different from the conventional design method.

[0024] In the design of an amplifier element, the controller 160 quantitatively determines the steady current Isteady flowing through the output circuit based on the output current Iout input by the user, and predicts the optimum value (W / L ratio) of the NMOS transistor that balances the current consumption and layout area of ​​the output circuit. In the design of a constant current element, the controller 160 automatically determines the current ratio balance (PN ratio) between the NMOS transistor and the PMOS transistor, and predicts the optimum value (W / L ratio) of the PMOS transistor. Furthermore, the controller 160 can cover the solution space of the gate width W, gate length L, and drain current Ids based on the W / L ratio, and predict the small signal parameters gm, gd, and gb. These processes are realized within a set time.

[0025] 6 shows a design method for an amplifying element (NMOS transistor). The controller 160 determines the range of m values ​​with respect to the W / L ratio of the NMOS transistor (210). The m value is an integer and has a relationship of (W / L)×m=(W×m) / L. In other words, the m value is equivalent to the concept of dividing one NMOS transistor into m parallel-connected NMOS transistors.

[0026] Figure 7(A) is a graph showing the Ids-Vgs characteristics of a transistor with a constant W / L ratio. For example, if the W / L ratio is 10, then W / L = 10um / 1um = 20um / 2um = 30um / 3um. As shown in the figure, if the W / L ratio is constant, the Ids-Vgs characteristics are similar and the mutual conductance gm is roughly equal.

[0027] Figure 7(B) shows the current Ids1 flowing through a single transistor when m = 4, and Figure 7(C) shows the current Ids flowing through four transistors connected in parallel when m = 4. The current Ids1 flowing through a single transistor shown in Figure 7(B) is equal to the current Ids2 (Ids1 = Ids2), which is the sum of the currents Ids flowing through the four parallel-connected transistors shown in Figure 7(C). In other words, there is a relationship of (W / L) x m = (W x m) / L.

[0028] The m value replaces a single transistor with m transistors connected in parallel; for example, if the number of transistors connected in parallel is an even number, the transistors can be manufactured symmetrically, and manufacturing variations in the transistors can be suppressed. On the other hand, if the m value is large, the drain current flowing through each transistor is small, but the overall layout area is large. The range (maximum value) of the m value is not particularly limited, but in this example, it is preset in the circuit design data, and for example, m=32 is the maximum value. However, it is also possible for the user to define the range of the m value and input it as the user's input.

[0029] Next, referring to FIG. 6 again, the controller 160 determines the ranges of the W and L values ​​of the NMOS transistor (S220). As shown in FIG. 4, the ranges (minimum, maximum) and step widths of the W and L values ​​define the size and accuracy of the design space. The ranges (minimum, maximum) and step widths of the W and L values ​​are not particularly limited, but in this example, they are set in advance in the circuit design data, for example, the minimum value of the W value is 1 um, the maximum value is 100 um, and the step width is 10 um, and the minimum value of the L value is 1 um, the maximum value is 3 um, and the step width is 1 um. However, it is also possible for the user to define the ranges and step widths of the W and L values ​​and input them as user input.

[0030] Next, the controller 160 generates current value patterns of 1S, 2S, and 3S according to the ratio of the m value to the output current Iout input by the user in the design space of each W value and each L value (S230). 1ST, 2ST, and 3ST represent the total current flowing through the entire NMOS transistor of (W×m) / L according to the state of the output circuit, and 1S, 2S, and 3S represent the current flowing through each individual NMOS transistor. In other words, the relationship is 1S=1ST / m, 2S=2ST / m, and 3S=3ST / m.

[0031] As shown in Fig. 8(A), the current of the output circuit includes the current Isource output from the operational amplifier and the current Isink input to the operational amplifier. The magnitude of the current Isource is equal to the magnitude of the current Isink (Isource = Isink). As shown in Fig. 8(B), the current at which the current Isource is maximum is represented as Imax, and as shown in Fig. 8(C), the current at which the current Isink is minimum is represented as Imin.

[0032] 9 to 11 are diagrams for explaining state transitions of the output circuit. In state (1) shown in FIG. 9, a bias voltage V BIASis applied, the PMOS transistor flows a constant current Isource, and the voltage Vsource from the differential amplifier circuit (the voltage for a half cycle including the lowest operating point, assuming that the output voltage of the differential amplifier circuit is a sine wave) is applied to the gate of the NMOS transistor, the NMOS transistor operates in a saturated state, and a small current flows from node N to GND. When the lowest operating point is applied to the gate of the NMOS transistor, the current flowing through the NMOS transistor is minimized, and the output current generated at node N is maximized Imax.

[0033] Figure 10 shows the transition from state (1) to state (2). In state (2), the current flowing through the PMOS transistor is constant, and there is no change from state (1). In other words, the PMOS transistor passes a constant current Isource. Meanwhile, a voltage at the central operating point of the operational amplifier's sine wave is applied to the gate of the NMOS transistor, and at this time, the NMOS transistor passes a current Isource equal to the current Isource. Therefore, the current Isource generated by the PMOS transistor flows unchanged through the NMOS transistor, resulting in an equilibrium state, and the output current generated at node N becomes zero.

[0034] FIG. 11 shows the transition from state (2) to state (3). In state (3), the current flowing through the PMOS transistor is constant, and there is no change from state (2). In other words, the PMOS transistor passes a constant current Isource. Meanwhile, a half-cycle voltage including the highest operating point of the operational amplifier's sine wave is applied to the gate of the NMOS transistor. When the highest operating point is applied to the gate of the NMOS transistor, the current flowing through the NMOS transistor becomes maximum, and the NMOS transistor passes a current Isink in addition to the current Isourse. In state (3), a sink current Isink (Isource=Isink) is generated in the node N in the opposite direction to the current Isource, and the output current is minimum.

[0035] Figures 12(A), (B), and (C) are diagrams explaining the currents 1S, 2S, and 3S. As shown in Figure 12(A), the current flowing through the NMOS transistor in state (1) is the steady current Isteady, and this steady current Isteady is 1S. In state (1), the gate voltage Vgs is close to the threshold Vth, and control dependent on the W / L of the transistor is difficult, so the steady current Isteady is added to the output circuit, which is realized by operating the NMOS transistor in the strong inversion region (saturation region). It should be noted here that the steady current Isteady flowing through the NMOS transistor in state (1) is treated as a quantitative current.

[0036] As shown in Fig. 12B, in state (2), the steady current Isteady+Isource flowing through the NMOS transistor is 2S. State (2) is an equilibrium state in which the NMOS transistor flows a current equal to the current Isource from the PMOS transistor, and therefore the steady current Isteady and the current Isource flow through the NMOS transistor. Since the current Isource = the output current Iout, 2S = 1S + Isource = 1S + Iout.

[0037] As shown in Figure 12(C), in state (3), the steady-state current Isteady, current Isource, and current Isink flowing through the NMOS transistor are 3S. In state (3), the NMOS transistor also sinks current Isink. Since current Isource = current Isink, 3S = Isteady + Isource + Isink = 1S + Iout × 2.

[0038] In this way, the current flowing through the NMOS transistor can be in one of three states (1), (2), or (3) depending on the gate voltage Vgs, and at these states, 1S, 2S, or 3S currents flow through the NMOS transistor.

[0039] Next, a method for generating the 1S, 2S, and 3S current value patterns will be described. Fig. 13(A) shows a method for generating a steady current Isteady. In this example, W=10um, L=1um, and m=4 are shown.

[0040] The steady-state current Isteady is generated at a rate according to the m value when the output current Iout is set to the maximum current value, and is expressed by the following equation. Isteady=(Iout / m)×n(n=1,2,3,···,m) If m=4, the steady current Isteady is generated in four ratios: 1 / 4, 2 / 4, 3 / 4, and 4 / 4. That is, (Iout / 4)×1, (Iout / 4)×2, (Iout / 4)×3, (Iout / 4)×4.

[0041] If the output current Iout is 100uA and m=4, the steady-state current Isteady has four current value patterns: 25uA, 50uA, 75uA, and 100uA. These current value patterns are the sum of the current flowing through the entire NMOS transistor of (W×m) / L, and are the 1ST current value patterns. Since the current value pattern flowing through a single NMOS transistor is 1ST / m, the 1S current value patterns are 6.25uA, 12.5uA, 18.75uA, and 25uA. Similarly, if m=2, the 1ST current patterns are 50uA and 100uA, and the 1S current patterns are 25uA and 50uA.

[0042] 13B shows an example of generating a current value pattern for 2ST. Since 2S is the output current Iout+steady current, when the output current Iout=100uA and m=4, the four current value patterns for 2ST are 125uA, 150uA, 175uA, and 200uA, and for 2S, they are 31.25uA, 37.5uA, 43.75uA, and 50.0uA.

[0043] By setting the m value, it is possible to cover the detailed relationship between the current Ids and (Vgs-Vth) when W / L is constant. For example, if the m value is 4, four current value patterns can be obtained for one W / L. Ids = K × (W / L) × (Vgs-Vth) 2 (K is a constant), and it is possible to obtain the relationship between four current value patterns and (Vgs-Vth) when W / L is fixed. By varying the magnitude of the m value, it is possible to obtain the relationship between W / L and (Vgs-Vth) in a wide range of design space.

[0044] In this way, the controller 160 generates 1S, 2S, and 3S current value patterns according to the ratio of the m value based on the output current Iout input by the user for each W value and L value in the design space, making it possible to more precisely and quickly predict the operating point of the transistor in the design space.

[0045] Next, the controller 160 determines whether the NMOS transistor satisfies a predetermined Vgs operating condition based on the current flowing through the NMOS transistor, and narrows down or filters the current value patterns (W / L)×m (S240). This narrowing down makes it possible to reduce the number of simulations to be performed in the subsequent processing. The Vgs operating conditions of the transistors are as follows: ·Vgs>Vth: Operation in strong inversion region ·Vds≧Vgs-Vth: Operation within saturation region Vov=Vgs-Vth: Vgs operating range Vov(1S)≧0.1V Vov(3S)≦0.5V

[0046] The reason why Vov (overdrive voltage) is set to 0.1V or more at 1S and 0.5V or less at 3S is to take into consideration the operation in the saturation region of a typical NMOS transistor, but these voltage values ​​are merely an example and are not necessarily limited to these.

[0047] Figure 14 shows the relationship between the m value and the current Ids. As shown in the figure, the larger the m value (number of divisions), the closer the Vgs of the individual transistors is to Vov = 0.1V, and the smaller the current Ids flowing through the individual transistors. In the example shown, when m = 4, m = 8, and m = 16, the voltage Vov is within the range of operating conditions (0.1 to 0.5V), so these current value patterns remain as design candidates. On the other hand, when m = 2, the voltage Vov corresponding to the current Ids exceeds 0.5V, so this current value pattern is excluded from the design candidates.

[0048] If the m value for the output current is known, the current Ids flowing through a single transistor becomes clear. Furthermore, if the range of the current Ids that can flow through a single transistor is known, the optimal m value can be found. FIG. 15 shows the relationship between the voltage Vov and the current Ivov. When the operating range of the voltage Vov is 0.1V to 0.5V, the current Ids at 1S and 3S must be within the range of the current Ivov. In one embodiment, since the current Ids can be reduced if the Vgs at 1S is small at the operating point of the transistor, the operating condition of the voltage Vov at 1S may be set to 0.1V or more and 0.2V or less.

[0049] For example, when the W / L ratio is 10 (W=10um, L=1um), Vth becomes clear, so the voltage Vgs for the operating condition of the voltage Vov of a single transistor, 0.1V to 0.5V, and the upper limit Ivov(max) and lower limit Ivov(min) of the current Ids can be determined. Equations (1) and (2) are used to determine the operating points for 1S and 3S.

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[0050] FIG. 16 shows an example of the judgment result according to the operating conditions of the voltage Vov. Here, an example is shown in which the output current Iout=200uA, the W / L ratio=10, and m=2, 4, 6, 8, and 10. ◯ indicates a current value pattern that satisfies the judgment criterion, and × indicates a current pattern that does not satisfy the judgment criterion. Judgment criterion 1 indicates whether or not the 1S current value pattern satisfies formula (1), and judgment criterion 3 indicates whether or not the 3S current pattern satisfies formula (2). Judgment criterion 2 is not necessarily required, but as described above, it can be judged using formula (1) so that the upper limit for reducing the current Ids at 1S is 0.2V (Vov≦0.2V).

[0051] In order to make a judgment based on the operating conditions of the voltage Vov, the current values ​​[uA] of Ivov01, Ivov02, and Ivov03 are obtained by simulation when Vov = 0.1 V, 0.2 V, and 0.5 V. The simulation is performed for the current value patterns of all the design candidates narrowed down in step S240.

[0052] For example, assume that Ivov01=21 uA when Vov=0.1 V. Then, when m=4, the current value pattern (12.50 uA) of 1S with n (ratio)=1 does not satisfy judgment criterion 1, but the current value patterns of other ratios, n=2, 3, 4, satisfy judgment criterion 1.

[0053] It can be seen that the larger the m value, that is, the larger the number of divisions, the closer it gets to Ivov01. For example, the current value pattern for m=2, n (proportion)=1 that satisfies judgment criterion 1 is 50.00uA, the current value pattern for m=4, n (proportion)=2 is 25.00uA, the current value pattern for m=6, n (proportion)=4 is 22.22uA, and the current value pattern for m=8, n (proportion)=7 is 32.88uA.

[0054] Assume that Ivov02 = 46 uA when Vov = 0.2 V. Then, when m = 4, the current pattern (50.00 uA) of 2S with n (ratio) = 4 does not satisfy criterion 2, but the current value patterns with other ratios, n = 1, 2, 3, satisfy criterion 2.

[0055] Assume that Ivov03=192uA when Vov=0.5V. In this case, the 3S current value pattern with m=2 does not satisfy judgment criterion 3, but all of the 3S current value patterns with other m values ​​satisfy judgment criterion 3. In the overall judgment, a circle is marked to those that satisfy all of judgment criteria 1, 2, and 3. It should be noted that FIG. 16 only illustrates a portion of the current value patterns.

[0056] Next, when multiple design candidates are found by the overall judgment, the controller 160 determines the priority order of them (S250). In the example of FIG. 16, there are seven current value patterns that satisfy the overall judgment. The controller 160 assigns a higher priority to a current value pattern in which the ratio of the steady current Isteady (1ST) to the output current Iout is smaller. Specifically, the controller 160 calculates Ratio=(Iout-Isteady) / Iout. The smaller the ratio of the steady current Isteady, the closer it is to Ratio=1. The ranking shown in FIG. 17 is in descending order of Ratio. Here, the current value pattern when the ratio of m=4 and n=2 has a priority order of 1 and is the first candidate.

[0057] Depending on the magnitude of the output current, 1ST may be the same, i.e. the Ratio may be the same. For example, the current value pattern (200uA) with m=6 and n(ratio)=6 in Fig. 17 and the current value pattern (200uA) with m=8 and n(ratio)=8 in Fig. 17 have the same Ratio (0.0000). In this case, the smaller the m value, the higher the ranking. This is because the larger the m value, the larger the layout area.

[0058] Figure 18 adds the W value, L value, and W / L to the table in Figure 17. The first candidate is W=10um, L=1um, m=4, and the ratio n=2, W / L ratio x 4 = 40.

[0059] After determining the first candidate for the NMOS transistor, the controller 160 next starts designing a PMOS transistor that is a constant current source element (step S300 in FIG. 5). FIG. 19 is an operation flow showing a design method for a constant current element according to this embodiment.

[0060] The controller 160 determines the range of m values ​​of the PMOS transistors (S310). The range of m values ​​may be the same as the range of m values ​​when designing NMOS transistors, or may be different. The range of m values ​​of the PMOS transistors may be included in advance as a default value in the circuit design data, or the default value may be changeable by the user. Here, the m value is a multiple of 2 within the range of 2≦m≦64.

[0061] Next, the controller 160 determines the ranges of W and L values ​​of the PMOS transistor (S320). The ranges of W and L values ​​may be the same as those when designing an NMOS transistor, or may be different. The ranges of W and L may be included in the circuit setting data in advance as default values, or the default values ​​may be changed by the user. Here, as in the design space of the NMOS transistor, the minimum value of W value=1 um, the maximum value=100 um, the step width=10 um, the minimum value of L value=1 um, the maximum value=3 um, and the step width=1 um are used.

[0062] Next, the controller 160 calculates the 2ST current to be passed through the PMOS transistor based on the m value of the first candidate for the NMOS transistor (S330). As shown in the state transition of Fig. 12, the PMOS transistor is a constant current source element that steadily continues to pass the 2ST current regardless of the operating state of the NMOS transistor. In other words, the PMOS transistor always passes the output current Iout and the steady current Isteady.

[0063] 2ST = output current Iout + steady current Isteady, where the output current Iout is defined by the user and the steady current Isteady has already been derived in the design (first candidate) of the NMOS transistor. In the example of FIG. 18, the output current Iout = 200 uA, the steady current Isteady of the first candidate = 100 uA, and 2ST is 300 uA.

[0064] Next, the controller 160 determines whether the PMOS transistor satisfies the predetermined Vgs operating conditions from the current Ids flowing through the PMOS transistor alone (S340). That is, in the combination of the W / L ratios of the PMOS transistors, when a current of 2S flows, it is determined whether the PMOS transistor operates in the saturation region.

[0065] FIG. 20 is a diagram showing an example of the design of a PMOS transistor. In this example, the range of m is 2 ≤ m ≤ 64, the output current Iout = 200 uA defined by the user, and the steady current Isteady of the first candidate obtained from the design of the NMOS transistor = 100 uA. 2ST is 300 uA, and 2S of the transistor alone is shown (2S = 2ST / m). When the m value = 2, 2S of the PMOS transistor alone is 150 uA (300 / 2), when the m value = 4, it is 75 uA (300 / 4), and when the m value = 6, it is 50 uA (300 / 6). It should be noted that only W / L = 10, which is part of the design space, is shown in FIG. 20.

[0066] The Vgs operating conditions are not particularly limited. For example, 0.1 V < Vov ≤ 0.5. This is the same range as that of the NMOS transistor. In one aspect, in order to more precisely distinguish the operating point of Vgs / Ids of the PMOS transistor, it is determined whether the operating conditions are satisfied in each range of 0.1 ≤ Vov < 0.2, 0.2 ≤ Vov < 0.3, 0.3 ≤ Vov < 0.4, and 0.4 ≤ Vov < 0.5.

[0067] The controller 160 calculates, through simulation, the currents Ivov01, Ivov02, Ivov03, Ivov04, and Ivov05 when Vov01 = 0.1V, Vov02 = 0.2V, Vov03 = 0.3V, Vov04 = 0.4V, and Vov05 = 0.5V. This simulation is performed for all combinations of W / L within the design space.

[0068] The controller 160 determines whether the current Ids flowing through the PMOS transistor alone satisfies Ivov01 ≤ Ids < Ivov05. If it is satisfied, it further determines which range of operating conditions among Ivov01 ≤ Ids < Ivov02, Ivov02 ≤ Ids < Ivov03, Ivov03 ≤ Ids < Ivov04, and Ivov04 ≤ Ids < Ivov05 is satisfied. An example of this determination result is shown in FIG. 20. Those satisfying the criteria are marked with a circle.

[0069] Next, the controller 160 selects, as a design candidate, the W / L ratio of the PMOS transistor that satisfies the Vgs operating conditions based on the PN ratio (S350). The PN ratio (current ratio) is the ratio of the current flowing through the NMOS transistor to the current flowing through the PMOS transistor. In this example, the PN ratio is set such that the current flowing through the NMOS transistor and the current flowing through the PMOS transistor are approximately equal, in other words, the source / drain resistance value of the NMOS transistor and the source / drain resistance value of the PMOS transistor are approximately equal. The state where the PN ratio (current ratio) is equal is used as the balance criterion for the current ratio.

[0070] The controller 160 converts the first candidate of the NMOS transistor in terms of the PN ratio and calculates the W / L ratio of the PMOS transistor. As shown in FIG. 18, the first candidate of the NMOS transistor is (W / L ratio) × m = 40. When this is converted in terms of the PN ratio, for the PMOS transistor, (W / L ratio) × m × 3 = 120. In FIG. 20, (W / L ratio) × m = 120 converted in terms of the PN ratio is shown in a thick frame.

[0071] The (W / L ratio) x m value of the PMOS transistor converted with a PN ratio of 3 is defined as the balance criterion for the current ratio of the PMOS transistor and the NMOS transistor. For example, by relating the W / L ratios of the transistors that make up an operational amplifier circuit, it becomes easier to control the design space as a system, so the balance criterion has been established. The balance criterion is indicated by a star in the judgment results in Figure 20.

[0072] If the balance criterion (W / L ratio)×m satisfies the Vgs operating condition, the controller 160 selects it as the first candidate for the PMOS transistor. As shown in the figure, the W / L ratio of the balance criterion satisfies the operating condition, that is, Vgs operating in the saturation region is 0.3V≦Vov<0.4.

[0073] In one embodiment, the controller 160 can have a function of adjusting the PN ratio. Changing the PN ratio means changing the current flowing through the PMOS transistor alone. When considering the characteristics of the entire circuit such as an operational amplifier, it is necessary to change the ratio of the current flowing through the PMOS transistor to the current flowing through the NMOS transistor. Therefore, the controller 160 has a function of changing the PN ratio within a certain range. The controller 160 enables the change of the PN ratio within a range between a predetermined minimum value and a predetermined maximum value. For example, as shown in FIG. 20, the minimum value of the PN ratio is 1.5 and the maximum value is 7, and the PN ratio can be set within this range. Assuming that the controller 160 considers the characteristics of the entire circuit such as an operational amplifier, it selects a W / L ratio×m=80 (W=10, L=1, m=8) with the PN ratio changed to 2 as a design candidate for the PMOS transistor. The user can adjust the PN ratio as necessary.

[0074] The controller 160 appropriately outputs the design results of the NMOS transistors (for example, information on the design results shown in FIG. 18) and the design results of the PMOS transistors (for example, information on the design results shown in FIG. 20) from the output unit 120 such as a display.

[0075] In this way, according to this embodiment, the steady-state current Isteady and the maximum current of 3S flowing through the NMOS transistor are calculated based on the output current Iout input by the user, and it is determined whether the NMOS transistor satisfies the Vgs operating condition from the calculated steady-state current Isteady and the maximum current of 3S, and a (W / L)×m candidate of the PMOS transistor is selected based on the (W / L ratio)×m candidate of the NMOS transistor that satisfies the Vgs operating condition, so that the designer can easily obtain the optimal (W / L)×m of the NMOS transistor and the PMOS transistor of the output circuit by simply inputting at least the output current Iout of the output circuit. This makes it easier to design the output circuit and significantly shortens the design time compared to the conventional design method.

[0076] Furthermore, according to this embodiment, the W / L ratios of the NMOS transistor and the PMOS transistor are resolved in detail by the m value, so that a wide range of design space can be covered with high accuracy to obtain a solution for optimal W and L values ​​of the transistor.

[0077] The features of the circuit design device 100 of this embodiment can be summarized as follows. (1) Quantitatively determine the steady-state current Isteady that flows through the NMOS transistor based on the output current Iout, and output the optimal value (W / L ratio) that balances the current consumption and layout area. This output also includes the operating point judgment result. (2) The current ratio balance (PN ratio) between PMOS transistors and NMOS transistors is automatically determined, and the user can adjust the PN ratio as necessary. (3) Based on the W / L ratio (including the m value), the solution space of the W, L, and m values ​​Ids is covered, and the small signal parameters gm and gd are predicted. (4) Generate flexible combination patterns for the gain, phase margin, and frequency specifications of the entire op-amp circuit. (5) It makes it possible to complete processing within a specified short period of time.

[0078] In the above embodiment, a PMOS transistor is used as the constant current source element and an NMOS transistor is used as the amplifying element, but it is also possible to use an NMOS transistor as the constant current source element and a PMOS transistor as the amplifying element.

[0079] In the above embodiment, the upper limit of the m value of the NMOS transistor is 32, and the upper limit of the m value of the PMOS transistor is 64, but these ranges are only examples and other ranges may be used. Furthermore, in the above embodiment, the m value is used to define the design space of the transistor, but the present invention is not limited to this, and does not necessarily require the m value. The design space may be simply defined by the W value, L value, and step width. Furthermore, the W / L ratio = 10 is used, but the present invention is not limited to this. In the above embodiment, 0.1V ≦ Vov < 0.5V is used as the Vgs operating condition, but this is only an example, and the present invention is not limited to this range, and other ranges can be used for Vov.

[0080] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the gist of the invention described in the claims. [Explanation of symbols]

[0081] 100: Circuit design device 110: Input section 120: Output section 130: Communication section 140:ROM / RAM 150:Storage section 160: Controller

Claims

1. An electronic device having a circuit design function, A means for receiving an output current of the output circuit from a user for designing a source-grounded output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series with the constant current source element; a determination means for determining whether or not a Vgs operating point that operates within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current in a design space including each W value, each L value, and each m value of the transistor, An electronic device, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L.

2. The electronic device further comprises:

2. The electronic device according to claim 1, further comprising a priority determination means for determining, when there are a plurality of candidates for the W / L ratio of a transistor determined by said determination means to satisfy an operating point of Vgs for operation within a saturation region, a priority order determination means for determining the candidates for the W / L ratio in order of priority.

3. The electronic device further comprises: a selection means for selecting a W / L ratio of a transistor of a constant current source element based on a current conversion ratio between the amplifying element and the constant current source element; and an adjusting means for adjusting the current conversion ratio.

4. the determining means includes a calculating means for calculating a steady-state current that steadily flows through a transistor of the output circuit in accordance with an operating state of the transistor and a maximum current that is a sum of the steady-state current and an output current; 2. The electronic device according to claim 1, wherein it is determined whether or not a Vgs voltage that is an operating point of the minimum value and maximum value of the steady-state current is at a Vgs operating point that operates within a saturation region within a range of a determined Vov voltage.

5. 3. The electronic device according to claim 2, wherein the priority determination means determines the priority of candidates for W / L ratios based on W, L, and m values ​​of a transistor determined to satisfy an operating point of Vgs that operates within the predetermined saturation region, based on current consumption and layout area.

6. 4. The electronic device according to claim 3, wherein the adjusting means adjusts a balance of a current ratio (PN ratio) between a PMOS transistor of the constant current source element and an NMOS transistor of the output circuit, based on a W / L ratio of a transistor determined to satisfy an operating point of Vgs operating within a saturation region and a drain current Ids flowing through a transistor of the output circuit.

7. The electronic device according to claim 2 , wherein the candidates for the W / L ratio have a pattern of combinations of W values, L values, and m values.

8. The electronic device according to claim 2 , wherein the steady-state current is calculated from various combinations defined by a ratio n of (W / L)×m based on an output current.

9. A circuit design method for an electronic device having a circuit design function, comprising: A step of receiving an output current of a source-grounded output circuit from a user for designing the output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series with the constant current source element; and determining whether or not a Vgs operating point that operates within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current in a design space including each W value, each L value, and each m value of the transistor, A circuit design method, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L.

10. A circuit design program executed by an electronic device having a circuit design function, A means for receiving an output current of the output circuit from a user for designing a source-grounded output circuit including a MOS transistor as a constant current source element and a MOS transistor as an amplifying element connected in series with the constant current source element; a determination means for determining whether or not a Vgs operating point that operates within a predetermined saturation region is satisfied from a current flowing through a transistor based on the output current in a design space including each W value, each L value, and each m value of the transistor, A circuit design program, wherein the m value is an integer and has a relationship of (W / L)×m=(W×m) / L.

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