Integrated circuit

Abstract

[0032] To propose realization means, which has not been proposed yet, of a composite gate-type logic circuit such as an AOI gate or an OAI gate using a lateral FET represented by a gate around type transistor (GAA) with a small pattern area without sacrificing a rapid characteristics.SOLUTION: [0033] In a plurality of lateral FETs of the same conductivity of a channel part laminated on one another in a longitudinal direction on the same flat surface, the gate signal electrodes of the lateral FETs are laminated in a vertical direction with an insulation film in between and the lateral FETs are connected to one another. It thus becomes possible to achieve increase of speed and reduction of cost of an integrated circuit represented by a logic LSI, using a composite gate-type logic circuit using a gate all around type transistor (GAA) laminated in a longitudinal direction, which has not been realized.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] This relates to an integrated circuit using gate-all-around transistors. [Background technology]

[0002] In the past, LSIs have progressed in accordance with Moore's Law as planar transistors have become increasingly miniaturized, and there has been steady progress in increasing capacity, reducing costs, increasing speed, and reducing power consumption.

[0003] As a result, MPUs, which are representative of logic LSIs, have achieved GHz operation using more than one billion planar transistors, and NAND flash memory, which uses planar transistors and is the memory LSI with the highest capacity, has been increased to 64 Gbit (Reference 1).

[0004] However, miniaturization of this planar transistor is approaching its limit in recent years due to short channel effects and the like.

[0005] In the past, when miniaturization of planar transistors was difficult, circuit methods were used to reduce the number of transistors that constitute the logic circuit, in order to realize inexpensive logic LSIs with small pattern areas. The simplest and most easily understood circuit methods, inverter, NAND, and NOR circuits, have the problem of requiring a large number of transistors. Composite-gate logic circuits overcome this problem, and have the characteristic that any logic circuit can be realized with fewer circuits than the inverter, NAND, and NOR circuits mentioned above, and are currently used as logic circuits to realize logic LSIs.

[0006] On the other hand, in order to solve the problem of the difficulty in miniaturizing planar transistors in the past, proposals have been made on gate-around transistors (hereafter abbreviated as GAA), in which all four sides can be used as channels, and MBCFETs (Multi Bridge Channel FETs), which are made by stacking multiple GAAs vertically and are more suitable for achieving higher speeds than GAA.

[0007] In the future, in order to realize inexpensive logic LSIs with small pattern areas without sacrificing high-speed characteristics, it is desirable to realize composite gate type logic circuits using GAA, but there have been no proposals for this in the past. References 1M. Sako et al., “A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology”, ISSCC Dig. Tech. Papers, 2015. Summary of the Invention Problem that the invention is trying to solve

[0008] So far, no composite gate type logic circuit using GAA with small pattern area has been proposed without sacrificing high speed characteristics.

[0009] This is realized by stacking a plurality of lateral FETs having the same conductivity type of the channel portion vertically at the same position on the same plane, stacking the gate signal electrodes of the plurality of lateral FETs vertically via an insulating film, and connecting the plurality of lateral FETs to each other.

[0010] This invention makes it possible, for the first time, to realize composite-gate logic circuits such as AND·OR·NOT (AOI) and OR·AND·NOT (OAI) using multiple lateral FETs (GAA being a typical example) with the same conductivity type in their channel regions stacked vertically in the same position on the same plane.

[0001] As a result, by reducing the pattern area compared to methods using conventional planar transistors, it will be possible to increase the speed and reduce the cost of integrated circuits, such as logic LSIs, that use vertically stacked gate-all-around transistors (GAA), which was previously not possible. BEST MODE FOR CARRYING OUT THEINVENTION

[0012] A first embodiment of an integrated circuit according to the present invention will now be described with reference to the drawings. [First embodiment] (Configuration of the first embodiment)

[0013] A first embodiment of the present invention will now be described. Figure 1 shows a cross-sectional circuit diagram of an AND / OR / NOT (AOI22) that realizes the inverted signal of AB+CD, which is the inverted signal of the sum of two logical products AB and CD. The bottom of the figure is a silicon substrate, with GAA stacked vertically. To reduce power consumption, it is a composite gate type circuit with a CMOS configuration.

[0014] 4, 5, 6, and 7 indicate input signals A, B, C, and D, respectively; 1 is GND, 2 is VDD, 3 is the output signal, 10-13 are N-type GAA, and 14-17 are P-type GAA. 10 and 11 are stacked vertically to realize the multiplication operation AB, and 12 and 13 are stacked vertically to realize the multiplication operation CD. To realize the multiplication operation, the drain of 11 is vertically connected to the source of 10, and the drain of 13 is vertically connected to the source of 12. If the drain electrodes of 10 and 12 are common, the product sum AB+CD can be realized.

[0015] P-type GAA 14-17 are stacked vertically to realize the inverse sum-and-product operation of the above-mentioned product-and-sum operation. (When product-and-sum operations are realized using N-type to realize a CMOS configuration, it is necessary to realize sum-and-product operations using P-type.) In order to realize the sum-and-product operation, 14 and 15 are connected source to drain, and 16 and 17 are similarly connected source to drain. In order to connect 2 and 3 via GAA, the sources of 16 and 17 are connected to 3, the drains of 16 and 17 to the sources of 14 and 15, and the drains of 14 and 15 to 2.

[0016] In order to make the planar pattern area as small as possible, the N-type GAA and the P-type GAA are stacked, and the sources of 11 and 13 and the sources of 10 and 12 use a common diffusion layer. 10 and 11 are stacked, and 12-17 are stacked. In order to pull out the output 3 to the top and output it, a process step is added and lateral wiring 8 is introduced. This makes it possible to realize the CMOS structure AOI 22, which requires an area equivalent to 8 transistors if it were a planar transistor, with an area equivalent to 1.5 transistors. The pattern area is reduced to about 19%, making it possible to reduce costs. Since the channel width can be increased without increasing the pattern area by stacking the GAA, high-speed performance is not sacrificed by this invention. The above shows the case of the product of two logic elements, but when the number of logic elements is even (AOI44, AOI66, AOI88, etc.), similar stacking and planar layout are possible, which further emphasizes the effect of reducing cost of the present invention.

[0017] FIG. 2 illustrates a first modified example of the first embodiment of the present invention. In Fig. 1, a process step was added and horizontal wiring 8 was introduced to output 3 to the top. The addition of this process step may lead to a slight increase in costs. In Fig. 2, a P-type GAA 18 is newly used to connect the bottom output and the top output 3, eliminating the need for an additional process step.

[0018] FIG. 3 illustrates a second modified example of the first embodiment of the present invention. In Fig. 1, in order to output 3 to the top, a process step was added and horizontal wiring 8 was introduced. This addition of a process step may lead to a slight increase in costs. In Fig. 3, this problem is solved by arranging the N-type GAA and the P-type GAA on different planes.

[0019] A third modification of the first embodiment of the present invention will now be described. Figure 4 shows a cross-sectional circuit diagram of an AND / OR / NOT (AOI33) that realizes the inverted signal ABC+DEF, which is the inverted signal of the sum of two logical products ABC and DEF. The bottom of the diagram is a silicon substrate, with GAA stacked vertically. In an extension of the method of Figure 1, an additional process step has been added and horizontal wiring 8 has been introduced to output 3 to the top, as in Figure 1. Unlike Figure 1, the circuit configuration does not allow the use of a common source diffusion layer, so the pattern area is 25% of that of the conventional planar type.

[0020] A fourth modified example of the first embodiment of the present invention will now be described. Figure 5 shows a cross-sectional circuit diagram of an AND / OR / NOT (AOI33) that realizes the inverted signal ABC+DEF, which is the inverted signal of the sum of two logical products ABC and DEF. The bottom of the figure is a silicon substrate, on which GAAs are stacked vertically. This is an extension of Figure 3, and N-type GAA and P-type GAA are placed on different planes as in Figure 3.

[0021] The fifth modification of the first embodiment of the present invention will now be described. Figure 6 shows a cross-sectional circuit diagram of an AND / OR / NOT (AOI222) that realizes the inverted signal of AB+CD+EF, which is the inverted signal of the sum of three logical products AB, CD, and EF. The bottom of the figure is a silicon substrate, with GAAs stacked vertically. Figure 6 shows an extension of Figure 1, and if the source diffusion layer is shared by three GAAs to reduce the pattern area (shown by dashed line 9 in Figure 6), the pattern area can be reduced to 2 / 12 = 17% compared to the conventional planar type. On the other hand, Figure 7 shows an extension of Figure 3, and similar to Figure 3, the N-type GAA and P-type GAA are placed on different planes.

[0022] A sixth modified example of the first embodiment of the present invention will now be described. Figures 8 and 9 show circuit diagrams seen from the cross section of an AND / OR / NOT (AOI333) that realizes the inverted signal of ABC+DEF+GHI, which is the inverted signal of the sum of three logical products ABC, DEF, and GHI. The bottom of the figure is a silicon substrate, with GAAs stacked vertically. Figure 8 is an extension of the method in Figure 1, where the source diffusion layer is shared by four GAAs to reduce the pattern area (indicated by dashed line 101 in Figure 8). On the other hand, Figure 9 is an extension of the method in Figure 3, where the N-type GAA and P-type GAA are placed on different planes, just like in Figure 3.

[0023] A second embodiment of the present invention will now be described. In the first embodiment, a CMOS circuit configuration was used to achieve low power consumption, but in this embodiment, a dynamic circuit configuration is used which has an even smaller number of transistors and can reduce the pattern area, thereby achieving further cost reduction.

[0024] Figure 10 shows a cross-sectional circuit diagram of a dynamic AND / OR / NOT (AOI333) that realizes the inverted signal of ABC+DEF+GHI, which is the inverted signal of the sum of three logical products ABC, DEF, and GHI. The N-type circuit portion is the same as in the first embodiment, but the load portion has the advantage that it can be configured with a single precharge GAA 19 controlled by a precharge signal PRE (102). 19 can be stacked vertically on many other N-type GAAs other than 19, so the AOI circuit can be realized with the pattern area of ​​a single planar transistor.

[0025] It has been proven that any logic circuit can always be expressed in the sum-product normal form. Therefore, logic circuits realized in logic LSIs do not depend on the number of inputs, and when there is one output, the pattern area can always be reduced to the area of ​​one planar transistor by using the dynamic circuit of the second embodiment. The second embodiment is the first example showing that any logic circuit with one output can be realized with the pattern area of ​​one planar transistor. Effects of the embodiment

[0026] In the present invention, multiple lateral FETs with the same conductivity type of the channel part are stacked vertically at the same position on the same plane, and the gate signal electrodes of the multiple lateral FETs are stacked vertically via an insulating film, and the multiple lateral FETs are connected to each other. As a result, it has become possible for the first time to realize a composite gate type logic circuit such as AOI or OAI using multiple lateral FETs (GAA) with the same conductivity type of the channel part stacked vertically at the same position on the same plane.

[0027] By reducing the pattern area compared to methods using conventional planar transistors, it becomes possible to increase the speed and reduce the cost of integrated circuits, such as logic LSIs, which use composite-gate logic circuits using vertically stacked gate-all-around transistors, something that was not possible previously.

[0028] The pattern area can be set to a value (value for one layer) that is independent of the number of lateral FETs stacked vertically. Therefore, the more layers there are, the cheaper the cost of one lateral FET becomes (in an ideal case, the cost can be reduced to 1 / N by stacking N layers). This effect is prominent in dynamic composite gate type logic circuits using the sum-product normal form. Other Examples Industrial Applicability

[0029] The present invention is not limited to this embodiment. It is also possible to stack different composite gate type logic circuits that operate at different times in the same vertical direction. In that case, further reduction in resistor cost can be achieved. This can also be applied to OAI circuits as well as AOI circuits. As a result, this can be applied to all currently commercialized integrated circuits such as system LSIs, logic LSIs, and FPGAs. [Brief description of the drawings]

[0030] [Figure 1] 1 is a circuit diagram of a first embodiment of a stacked GAA of an integrated circuit according to the present invention, seen from a cross-sectional direction. [Diagram 2] FIG. 1 is a circuit diagram of a first modified example of a stacked GAA of an integrated circuit according to the present invention, viewed from a cross-sectional direction. [Diagram 3]FIG. 11 is a circuit diagram of a second modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, as viewed from the cross-sectional direction. [Figure 4] FIG. 11 is a circuit diagram of a third modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, viewed from the cross-sectional direction. [Diagram 5] FIG. 11 is a circuit diagram of a fourth modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, viewed from the cross-sectional direction. [Figure 6] FIG. 11 is a circuit diagram of a fifth modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, viewed from the cross-sectional direction. [Figure 7] FIG. 13 is a circuit diagram showing a fifth modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, which is close to the second modified example, as viewed from a cross-sectional direction. [Figure 8] FIG. 11 is a circuit diagram of a sixth modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, as viewed from the cross-sectional direction. [Figure 9] FIG. 13 is a circuit diagram showing a sixth modified example of the first embodiment of the stacked GAA of the integrated circuit according to the present invention, which is close to the second modified example, as viewed from a cross-sectional direction. [Figure 10] FIG. 1 is a circuit diagram seen from a cross-sectional direction of a second embodiment (a logic circuit realized in sum-product standard form) of a stacked GAA of an integrated circuit according to the present invention. [Explanation of symbols]

[0031] 1 indicates GND, 2 indicates VDD, and 3 indicates output. The input signal is indicated by A being 4, B being 5, C being 6, D being 7, E being 88, F being 99, G being 92, H being 93, I being 94, and the control signal PRE being 102. Reference numeral 8 denotes horizontal wiring, 9 denotes a source electrode shared by three GAAs, and 101 denotes a source electrode shared by four GAAs. Reference numerals 10-13 indicate N-type GAAs to which input signals are input, and 14-17 indicate P-type GAAs to which input signals are input. Reference numeral 18 denotes a pass-through type GAA, and 19 denotes a GAA for precharging a dynamic circuit.

Claims

1. An integrated circuit comprising a plurality of lateral FETs having the same conductivity type of channel portions vertically stacked at the same position on the same plane, the gate signal electrodes of the plurality of lateral FETs being vertically stacked via an insulating film, and the lateral FETs being vertically connected to each other to realize a composite gate type logic circuit.

2. 2. The integrated circuit according to claim 1, wherein the lateral FET is a gate-around type FET using four sides as a channel, or a plurality of lateral FETs stacked vertically or horizontally.

3. In the integrated circuit of claims 1 and 2, the composite gate type logic circuit is realized by a dynamic circuit realized by a sum-product standard type.

3. An integrated circuit according to claim 1 or 2.

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