Controlling electrostatic charge on masks for extreme ultraviolet lithography

Abstract

To provide devices and processes for managing electrostatic charge on lithographic photomasks for semiconductor fabrication.SOLUTION: The devices include sensors for measuring the electrostatic charge on a lithographic photomask, and charge injectors for modifying the electrostatic charge on a lithographic photomask. The devices are capable of attaching to carriers for lithographic photomasks. The processes include measuring the electrostatic charge on a lithographic photomask, calculating the amount of electrostatic charge to be increased or decreased, and modifying the amount of electrostatic charge.SELECTED DRAWING: Figure 2B

Description

[Technical field]

[0001] The description relates generally to semiconductor processing, and more specifically, the description relates to equipment for extreme ultraviolet (EUV) photolithography, and to devices and methods for control of electrostatic charge on EUV lithography photomasks used in the lithography process. [Background technology]

[0002] Semiconductor chips are critical to intelligent devices and systems, such as personal computers, laptops, tablets, phones, servers, and other consumer and industrial products and systems. The manufacture of semiconductor chips presents multiple challenges that are amplified as devices become smaller and performance demands increase. Challenges include, for example, undesirable material interactions, precision and scaling requirements, power supply requirements, limited fault tolerance, and material and manufacturing costs.

[0003] Extreme ultraviolet (EUV) lithography is an optical lithography technique that uses light in the extreme ultraviolet wavelength range, less than 100 nm and in some applications, for example, less than 13.5 nm, and allows semiconductor device features to be scaled to extremely small dimensions. Lithography is generally used in the semiconductor manufacturing industry to pattern a layer of light-sensitive material, for example, photoresist. To pattern the photoresist, a mask (also called a photomask, lithography mask, or lithography photomask) is used as a template to generate a light pattern that exposes only a portion of the photoresist. Depending on the type of photoresist selected, a subsequent process, for example, exposing the patterned surface to a solvent, removes either the exposed or unexposed sections of the photoresist from the surface of the chip being fabricated. The patterned photoresist can then be used as a template, for example, to deposit material onto the surface of the chip at locations specified by the template, or to etch the surface of the chip. At extremely small feature sizes, the wavelength of light for lithographically patterning photoresist becomes a limiting factor. [Brief description of the drawings]

[0004] The figures are provided to aid in the understanding of the invention. The figures may include diagrams and illustrations of example structures, assemblies, data, methods, and systems. To facilitate the description and understanding of these structures, assemblies, data, methods, and systems, the figures are not exhaustive detailed descriptions. Thus, the figures should not be understood as illustrating the entire boundaries of protection of the structures, assemblies, data, methods, and systems that are possible without departing from the scope of the invention.

[0005] [Figure 1A] FIG. 2 illustrates an exemplary lithographic mask section. [Figure 1B] FIG. 2 illustrates an exemplary lithographic mask section.

[0006] [Figure 2A] FIG. 1 provides an exemplary static charge management device. [Figure 2B] FIG. 1 provides an exemplary static charge management device. [Figure 2C] FIG. 1 provides an exemplary static charge management device.

[0007] [Figure 3A] 1 illustrates an exemplary electrostatic charge management device and carrier for a lithography mask. [Figure 3B] 1 illustrates an exemplary electrostatic charge management device and carrier for a lithography mask. [Figure 3C] 1 illustrates an exemplary electrostatic charge management device and carrier for a lithography mask.

[0008] [Figure 4] FIG. 2 is a flow diagram of an example of a process for managing electrostatic charge on a lithographic mask.

[0009] [Diagram 5] FIG. 1 provides an exemplary computing system that is part of a static charge management system.

[0010] A description of specific details and implementations follows, including diagrams illustrating examples and non-limiting descriptions of implementations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Reference to one or more examples herein should be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the invention. The phrases "one example" or "an example" do not necessarily all refer to the same example or embodiment. Any aspect described can potentially be combined with any other aspect or similar aspect described herein, regardless of whether those aspects are described with respect to the same figure or element.

[0012] The terms "connected" and / or "coupled" can indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more elements are not in direct contact with each other but are instead separated by one or more elements, but still may cooperate or interact with each other, for example physically, magnetically, or electrically.

[0013] The words "first," "second," and similar words do not denote an order, quantity, or importance, but rather are used to distinguish one element from another. The words "a" and "an" herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The terms "follow" or "after" may indicate immediately following or following some other event or events. Other sequences of operations may also be performed according to alternative embodiments. Furthermore, additional operations may be added or removed depending on the particular application.

[0014] Disjunctive language, such as phrases such as "at least one of X, Y, or Z," is generally used to indicate that a certain element or feature can be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, this disjunctive language should not be understood to imply that a particular embodiment requires that at least one of X, at least one of Y, or at least one of Z, respectively, be present.

[0015] The terms chip, die, IC (integrated circuit) chip, IC die, or semiconductor chip are used interchangeably and refer to a semiconductor device that includes an integrated circuit. Chips are manufactured in wafer form, where the wafer contains multiple chips. After manufacturing, the wafer is diced apart to produce the chips.

[0016] The flow diagrams illustrated herein provide examples of sequences of various process actions. The flow diagrams may depict operations performed by software or firmware routines as well as physical operations. Although shown in a particular sequence or order, unless otherwise specified, the order of actions may be modified. Therefore, the illustrated diagrams should be understood as examples only, and processes may be performed in different orders and some actions may be performed in parallel. Additionally, one or more actions may be omitted and not all implementations perform all actions.

[0017] The various components described may be means for performing the described operations or functions. Each component described includes software, hardware, or a combination thereof. Some components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuitry, etc.

[0018] To the extent that various computer operations or functions are described herein, they may be described or defined as software code, instructions, configurations, and / or data. Software content may be provided via a product on which the content is stored, i.e., a non-transitory storage medium, or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium may cause a machine to perform the described functions or operations and includes any mechanism for storing information in a tangible form accessible by a machine (e.g., a computing device), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices). A communication interface includes any mechanism for interfacing, e.g., to a hardwired, wireless, or optical medium, to communicate with another device, e.g., a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc.

[0019] Masks used in EUV lithography can accumulate electrostatic charges on their surfaces despite careful management of the lithography photomasks and the clean rooms in which they are used. These electrostatic charges can be the result of, for example, the use of lithography photomasks during semiconductor manufacturing. Electrostatic charges on EUV lithography photomask surfaces can result in electrostatic discharge-related damage and defects. Electrostatic charges can be transferred between objects through induced electric fields even without contact. Furthermore, electrostatic charges on the mask surface interfere with critical dimension (CD) measurements, such as CD measurements of the mask performed by electron microscopy. It is important not only to be able to quantify the electrostatic charge on the mask, but also to mitigate it.

[0020] 1A-1B provide an example of a section of an EUV lithography photomask, illustrating charge accumulation on the mask surface. An EUV lithography photomask is typically composed of a layer of dielectric material and a layer of conductive material. Lithography photomasks may generally have designs different from those described herein. The inventive examples are useful for lithography photomasks in general, and are not limited to the exemplary lithography photomask provided herein for illustration purposes. Furthermore, the charge distributions shown in FIGS. 1A and 1B are provided for illustration purposes only to show the charge distribution on a lithography photomask, and the actual positive or negative charge distribution within the film structure of a lithography photomask may be more complicated.

[0021] In FIG. 1A, EUV lithography photomask section 100 includes first dielectric layer 105, conductive layer 110, and second dielectric layer 115. Additional layers of lithography photomask section 100 include region 160 comprised of multilayers of, for example, silicon (Si) and molybdenum (Mo), substrate 165 comprised of quartz, and metal layer 170. Multilayer region 160 may include, for example, 30-50 pairs of thin Si and Mo layers. Substrate 165 may include trace amounts of metal elements, such as titanium (Ti). For example, doping titanium in quartz may reduce the thermal expansion coefficient of substrate 165. Mask section 102 shows positive charge accumulated in dielectric layer 105 of structure 100. Exposed dielectric layer 106 in EUV lithography photomask section 102 has a positive charge. Alternatively, depending on conditions, negative charge may build up on the surface dielectric layer 105 and the EUV lithography photomask section 103 may exhibit negative charge build-up within the surface dielectric layer 107 .

[0022] 1B, exemplary EUV lithography photomask section 120 includes a surface metal layer 130, an inner dielectric layer 135, an inner metal layer 140, and a second dielectric layer 145. As in FIG. 1A, additional layers of lithography photomask section 120 may include, for example, region 160 comprised of multiple layers of silicon (Si) and molybdenum (Mo), substrate 165 comprised of quartz, and metal layer 170.

[0023] Lithographic photomask structure 122 shows the accumulation of positive charges on metal layer 133, which is layer 130 of lithographic photomask structure 120. Lithographic photomask structure 123 shows how surface metal layer 130 can store negative charges. In structure 123, surface metal layer 132 illustrates the negative charges.

[0024] In FIG. 1A and FIG. 1B, the EUV mask dielectric layer is, for example, Ta2O5, TaBON, SiO2, Si, and / or photoresist. The material of the conductive layer of the EUV lithography photomask is, for example, Ru, RuN, TaN, TaBN, Ti, TiN, and / or Mo. As can be understood from FIG. 1A-FIG. 1B, the electrostatic charge can be either positive or negative. The lithography photomask may include other numbers or compositions of layers than those shown as examples here. The electrostatic charge generated on the lithography photomask may generally be of various amounts localized within regions of the mask surface. The failure mechanism of the lithography photomask includes charge imbalances in regions of the mask surface. These localized charge imbalances may result in electrostatic discharges that damage the mask.

[0025] 2A-2C illustrate an exemplary device for managing electrostatic charge on a lithography photomask. The lithography photomask may be an EUV lithography mask. In FIG. 2A, the device for managing electrostatic charge includes an electrostatic charge measurement and modification unit 205 and a control unit 210. The control unit 210 may either be physically attached to the electrostatic charge measurement and modification unit 205 as shown in FIG. 2A, or it may be, for example, a part of a computing unit or system (not shown) separate from the electrostatic charge measurement and modification unit 205. Also, the control unit 210 may be coupled to the electrostatic charge measurement and modification unit 205 through a cordless or corded connection. In the case where the charge measurement and modification unit 205 is physically separate from the control unit 210, it may communicate with the control unit 210 through, for example, either a wired or wireless communication connection. Functions performed by the control unit 210 include receiving a static charge measurement input from the static charge measurement and modification unit 205 and causing the static charge measurement and modification unit 205 to modify the static charge on the lithographic photomask by a specified amount. The control unit 210 can also store, output, or store and output values ​​for the charge on the lithographic photomask. Modifying the static charge on the lithographic photomask includes reducing the positive static charge, reducing the negative static charge, increasing the positive static charge, and / or increasing the negative static charge.

[0026] The control unit 210 may include, for example, software, hardware, or a combination of software and hardware, or its functionality may be part of a larger computing system. In some examples, the control unit 210 may include additional intelligence and calculate a value for the amount that the charge needs to be changed to make the lithography photomask perform well, repeatedly and as needed, under selected circumstances, such as during lithography or during mask health analysis (e.g., CD measurement). In some examples, the control unit 210 directs changes to the electrostatic charge value to bring the surface closer to a near zero average electrostatic charge value. In other examples, the control unit 210 directs changes to the average electrostatic charge value to a positive or negative value selected to optimize mask reliability during a selected process. For example, reliability may be that the mask performs repeatably and as needed during a process, and / or reliability may be that the mask increases the overall mask life, such that the mask does not experience catastrophic failure during a process.

[0027] In a further example, the functionality of the control unit 210 may include generating a map of the amount of charge relative to the mask surface, where the map includes mask surface position and charge amount data. The surface position is associated with the amount of charge. The map may be used to modify the charge of one area on the lithographic photomask by a different amount than a second area. The functionality of the control unit 210 may optionally include instructing the electrostatic charge measurement and modification unit 205 to modify the amount of charge on a first area more or less than the amount that the charge should be modified on a second area on the mask surface.

[0028] The control unit 210 may perform all of the above-mentioned functions itself, the control unit 210 may perform a subset of the above-mentioned functions, and / or the control unit 210 may perform additional functions. Some functions may, for example, be performed by the control unit 210 and some functions may be performed by one or more separate computing devices.

[0029] 2B-2C illustrate the electrostatic charge measurement and modification unit 205 rotated with respect to FIG. 2A. FIGS. 2B-2C illustrate possible configurations for the side of the electrostatic charge measurement and modification unit 205 that faces the lithographic photomask and allows modification of the electrostatic charge of the lithographic photomask (not shown). In FIG. 2B, the electrostatic charge measurement and modification unit 205 has a housing 240 that holds a sensor 245 capable of detecting electrostatic charge and a charge injector 250. The sensor 245 is, for example, an electrostatic sensor that monitors the electrostatic charge. The charge injector 250 is, for example, an ionizer, a static charge removal device, or a corona discharge static charge removal device. The housing 240 can have, for example, a shape, size, and configuration that allows it to interface with the lithographic photomask and / or to interface with a carrier for the lithographic photomask.

[0030] 2C illustrates a further example of a static charge measurement and modification unit 205 having multiple sensors 245 and charge injectors 250 both within the housing 240. Although the static charge measurement and modification unit 205 is shown in this example as having the same number of sensors 245 and charge injectors 250, there may be different numbers of each. Additionally, numbers of sensors 245 and charge injectors 250 different from those shown are also possible.

[0031] 3A-3C illustrate an exemplary device for managing electrostatic charge on a lithography photomask associated with a carrier for the lithography photomask. Other types and configurations of lithography mask carriers are possible. The carrier can be, for example, a box, a pod, or other type of enclosure. The carrier protects the lithography mask from environmental challenges. The lithography mask can be an EUV lithography mask and the carrier can be a carrier for the EUV lithography mask. FIG. 3A shows an exemplary charge management device during placement on a carrier for a photolithography mask. FIG. 3B shows an exemplary charge management device positioned to measure and modify charge on a lithography mask (not shown).

[0032] In Figures 3A-3B, the device for managing electrostatic charge on a lithography photomask includes an electrostatic charge measurement and modification unit 305 and a control unit 310. The electrostatic charge measurement and modification unit 305 includes a housing that allows it to interface with a carrier 320 for a lithography photomask. In some examples, a cover (not shown) for the carrier 320 for a lithography photomask is removed and replaced with the device for managing electrostatic charge. In other examples, the device for managing electrostatic charge also includes the carrier 320 for a lithography photomask. The control unit 310 can either be physically attached to the electrostatic charge measurement and modification unit 305 as shown in Figures 3A-3B, or it can be, for example, part of a computing system (not shown) separate from the electrostatic charge measurement and modification unit 305. In the case where the charge measurement and modification unit 305 is physically separate from the control unit 310, it can communicate with the control unit 310, for example, through either a wired communication connection or a wireless communication connection. Functions performed by the control unit 310 include receiving electrostatic charge measurement input from the electrostatic charge measurement and modification unit 305, and causing the electrostatic charge measurement and modification unit 305 to modify the electrostatic charge on the lithographic photomask by a specified amount. The control unit 310 can also store, output, or store and output values ​​for the charge on the lithographic photomask. Characteristics of the control unit 310 include those described with respect to Figures 2A-2C.

[0033] In FIG. 3A-3C, the carrier for the lithography photomask includes a lithography photomask holding mechanism 325. The lithography photomask holding mechanism 325 is optional. Also, the lithography photomask holding mechanism 325 can be optionally more than one holding member into which the lithography photomask can be placed. The lithography photomask holding mechanism 325 can additionally be a support for one or more lithography photomasks. The electrostatic charge measurement and modification unit 305 is either fixed to the lithography photomask carrier 320 or removably attached thereto. When the carrier for the lithography photomask is closed, it can encapsulate the lithography photomask within an interior region. In some examples of FIG. 3B, the lithography photomask is encapsulated and protected from the surrounding environment, including atmospheric contaminants, electrostatic fluctuations, and other types of physical, chemical, and / or electrical harm.

[0034] 3C provides a simplified example of an interior for a carrier 320 for a lithographic photomask. The carrier 320 includes an interior region 330. Although the interior region 330 is shown for the carrier 320 in this example, the electrostatic charge measurement and modification unit 305 may also or instead comprise an interior region capable of receiving all or a portion of a lithographic photomask.

[0035] FIG. 4 provides an exemplary process flow for managing electrostatic charge on a lithography photomask, such as an EUV lithography mask. In FIG. 4, a lithography photomask, such as an EUV lithography mask, for which electrostatic charge assessment and possible modification is desired is selected (400). The electrostatic charge on the lithography photomask is measured (405). Measuring the electrostatic charge optionally includes generating a map of the amount of electrostatic charge relative to the mask surface, where the map includes mask surface location and charge amount data. The measured amount of electrostatic charge is compared to a desired amount of electrostatic charge and a difference is calculated (410). The difference is the amount by which the electrostatic charge should be increased or decreased (410). If the electrostatic charge is the desired amount, i.e., the difference is zero, then no electrostatic charge modification is required (425). If the amount to be increased or decreased is non-zero (415), then the electrostatic charge is increased or decreased to the desired amount (420). The measured electrostatic charge on the lithographic photomask may be positive or negative, and increasing the electrostatic charge increases the amount of positive charge or increases the amount of negative charge. Reducing the electrostatic charge may reduce the amount of positive charge or reduce the amount of negative charge on the surface of the lithographic photomask. Optionally, the map is used to modify the charge of at least one area on the lithographic photomask by a different amount than a second area. For example, if the mask shows that there are multiple areas of high electrostatic charge, multiple areas of medium electrostatic charge, and areas of low electrostatic charge, and the desired result is a mask with near zero or very low electrostatic charge, the electrostatic charge may be reduced more in the high charge areas, reduced less in the medium charge areas, and not reduced at all in the low charge areas. The device according to Figures 2A-2C and 3A-3C may be used to modify the electrostatic charge, for example in the manner described by Figure 4. Optionally, the method of Figure 4 is an iterative process in which after the static charge is first increased or decreased, the static charge is measured again (405), the amount by which the charge should be changed is calculated (410), and the static charge is changed a second time (420). The iterative process may be performed one or more times until the static charge is measured to be at a desired level.

[0036] FIG. 5 illustrates an exemplary computing system that may be used in conjunction with a static charge management device. The computing system may be, for example, a system used to operate equipment in a semiconductor manufacturing facility. For example, instructions for operating the static charge management device or for performing one or more aspects of the process described in FIG. 4 may be stored on and / or executed on the computing system. In this example, the system is communicatively coupled to one or more static charge management devices. The computing system used may include more, different, or fewer features than those described with respect to FIG. 5.

[0037] Computing system 500 includes a processor 510 that provides processing, operational management, and execution of instructions for system 500. Processor 510 may include any type of microprocessor, CPU (Central Processing Unit), GPU (Graphics Processing Unit), processing core, or other processing hardware that provides processing for system 500, or a combination of processors or processing cores. Processor 510 controls the overall operation of system 500 and may be or include one or more programmable general-purpose or special-purpose microprocessors, DSPs, programmable controllers, ASICs, programmable logic devices (PLDs), or the like, or a combination of such devices.

[0038] In one example, system 500 includes an interface 512 coupled to processor 510, which may represent a high-speed or high-throughput interface to system components requiring a higher bandwidth connection, such as memory subsystem 520 or graphics interface component 540, and / or accelerator 542. Interface 512 represents interface circuitry, which may be a stand-alone component or may be integrated onto the processor die. If present, graphics interface 540 interfaces to a graphics component for providing a visual display to a user of system 500. In one example, the display may include a touch screen display.

[0039] Accelerator 542 may be a fixed function or a programmable offload engine that may be accessed or used by processor 510. For example, an accelerator among accelerators 542 may provide a data compression (DC) function, a cryptographic service, such as public key encryption (PKE), a cipher, a hash / authentication function, decryption, or other function or service. In some cases, accelerator 542 may be integrated into a CPU socket (e.g., a connector to a motherboard (or circuit board, printed circuit board, main board, system board, or logic board) that contains a CPU and provides an electrical interface with the CPU). For example, accelerator 542 may include a single or multi-core processor, a graphics processing unit, a logic execution unit, a single or multi-level cache, a functional unit that can be used to independently execute a program or thread, an application specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and a programmable processing element, such as a field programmable gate array (FPGA) or a programmable logic device (PLD). The accelerator 542 may provide multiple neural networks, a CPU, a processor core, a general-purpose graphics processing unit, or the graphics processing unit may be made available for use by artificial intelligence (AI) or machine learning (ML) models.

[0040] The memory subsystem 520 represents the main memory of the system 500 and provides storage for code executed by the processor 510 or data values ​​used in the execution of routines. The memory subsystem 520 may include one or more memory devices 530, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and / or other memory devices, or a combination of such devices. The memory 530 stores and hosts, among other things, an operating system (OS) 532 that provides a software platform for executing instructions in the system 500, and stores and hosts applications 534 and processes 536. In one example, the memory subsystem 520 includes a memory controller 522, which is a memory controller for generating and issuing commands to the memory 530. The memory controller 522 may be a physical part of the processor 510 or a physical part of the interface 512. For example, memory controller 522 may be an integrated memory controller integrated onto circuitry within processor 510 .

[0041] System 500 may also optionally include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, and / or an interface bus. A bus or other signal lines may communicatively or electrically couple components to each other or may communicatively and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) or PCIe (PCI Express) bus, a HyperTransport or Industry Standard Configuration (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or a Firewire bus.

[0042] In one example, the system 500 includes an interface 514, which may be coupled to the interface 512. In one example, the interface 514 represents an interface circuit, which may include stand-alone components and integrated circuits. In one example, a user interface component, or a peripheral component, or both, is coupled to the interface 514. The network interface 550 provides the system 500 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. The network interface 550 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB, or other wired or wireless standard-based or proprietary interface. The network interface 550 may transmit data to devices in the same data center or rack, or to remote devices, which may include transmitting data stored in memory.

[0043] Some examples of network interface 550 are part of or used by an infrastructure processing unit (IPU) or a data processing unit (DPU). An xPU may refer to at least an IPU, a DPU, a GPU, a GPGPU (general purpose computing on graphics processing unit), or other processing unit (e.g., an accelerator device). An IPU or DPU may include a network interface with one or more programmable pipelines or fixed function processors to perform offloading of operations that could be performed by a CPU. An IPU or DPU may include one or more memory devices.

[0044] In one example, system 500 includes one or more input / output (I / O) interfaces 560. I / O interface 560 can include one or more interface components (e.g., audio, alphanumeric, haptic / touch, or other interface connections) through which a user interacts with system 500. Peripheral interface 570 can include additional types of hardware interfaces, such as interfaces to semiconductor manufacturing equipment and / or static charge management devices.

[0045] In one example, the system 500 includes a storage subsystem 580. The storage subsystem 580 includes a storage device 584 that may be or include any conventional medium for storing data in a non-volatile manner, such as one or more magnetic, solid state, and / or optical based disks. The storage 584 may be considered generically as "memory," although the memory 530 is typically the execution or operating memory that provides instructions to the processor 510. The storage 584 is non-volatile, while the memory 530 may include volatile memory (e.g., the value or state of the data is indeterminate if power to the system 500 is interrupted). In one example, the storage subsystem 580 includes a controller 582 that interfaces with the storage 584. In one example, the controller 582 may be a physical part of the interface 512 or the processor 510, or may include circuitry or logic within both the processor 510 and the interface 514.

[0046] A power supply (not shown) provides power to the components of system 500. More specifically, the power supply typically interfaces with one or more power supplies in system 500 to provide power to the components of system 500.

[0047] Exemplary systems may be implemented in various types of computing, smartphones, tablets, personal computers, and network equipment such as switches, routers, racks, and blade servers, such as those used in data center and / or server farm environments.

[0048] In addition to what is described herein, various modifications can be made to the disclosed content and implementation of the present invention without departing from the scope of the present invention. Accordingly, the illustrations and examples herein should be construed in an illustrative sense and not in a limiting sense. The scope of the present invention should be evaluated solely with reference to the claims that follow. [Other possible items] [Item 1] a sensor, wherein said sensor is capable of measuring electrostatic charge on a lithographic photomask; a charge injector, where the charge injector is capable of modifying the electrostatic charge on a lithographic photomask; a housing, wherein the sensor and the charge injector are within the housing; and a control unit, wherein the control unit is capable of causing the sensor to measure the electrostatic charge on the lithographic photomask, capable of storing, outputting, or storing and outputting a value for the charge on the lithographic photomask, and capable of causing the charge injector to modify the charge on the lithographic photomask by a specified amount; An assembly comprising: [Item 2] Item 1. The assembly of item 1, further comprising at least a portion of a carrier for a lithographic photomask, the housing being attached to at least a portion of the carrier for the lithographic photomask. [Item 3] Item 1 , the assembly being capable of being attached to a portion of a carrier for a lithography photomask. [Item 4] Item 2. The assembly of item 1, wherein the lithography photomask is an extreme ultraviolet (EUV) lithography photomask. [Item 5] Item 1, the assembly comprising a plurality of charge injectors. [Item 6] Item 1, the assembly comprising a plurality of sensors. [Item 7] 2. The assembly of claim 1, wherein the control unit is further capable of determining the specified amount from a measurement of electrostatic charge on the lithographic photomask and a selected value for electrostatic charge on the lithographic photomask. [Item 8] a sensor, wherein said sensor is capable of measuring electrostatic charge on a lithography photomask; a charge injector, where the charge injector is capable of modifying the electrostatic charge on a lithographic photomask; a housing, wherein the sensor and the charge injector are within the housing; a control unit, where the control unit is capable of causing the sensor to measure the charge on the lithographic photomask, outputting, or storing and outputting, a value for the charge on the lithographic photomask, and causing the charge injector to modify the charge on the lithographic photomask by a specified amount; and a computing system, wherein the computing system is capable of determining an amount to modify the electrostatic charge on the lithographic photomask based on a selected value for the electrostatic charge and an output value from the control unit, and wherein the computing system is communicatively coupled to the control unit; A system comprising: [Item 9] Item 10. The system of item 8, wherein the computing system is further capable of generating a map of charge amount relative to a lithographic photomask surface, wherein the map includes lithographic photomask surface position and charge amount. [Item 10] Item 10. The system of item 8, further comprising at least a portion of a carrier for a lithographic photomask, the housing being attached to at least a portion of the carrier for the lithographic photomask. [Item 11] Item 9. The system of item 8, wherein the lithography photomask is an extreme ultraviolet (EUV) lithography photomask. [Item 12] 9. The system of claim 8, wherein the system comprises a plurality of charge injectors within the housing. [Item 13] Item 9. The system of item 8, wherein the system comprises a plurality of sensors within the housing. [Item 14] measuring the electrostatic charge on the lithographic photomask; calculating an amount by which the measured electrostatic charge on the lithographic photomask is altered based on a selected amount of electrostatic charge and the measured amount of electrostatic charge; and Varying the amount of electrostatic charge on the lithographic photomask based on the calculated amount. 1. A method for modifying an electrostatic charge on a lithographic photomask, comprising: [Item 15] Item 15. The method of item 14, wherein the lithography photomask is an extreme ultraviolet (EUV) lithography photomask. [Item 16] 15. The method of claim 14, further comprising the step of measuring a second time the electrostatic charge on the lithographic photomask. [Item 17] Item 15. The method of item 14, wherein the amount of static charge on the lithographic photomask is reduced. [Item 18] Item 15. The method of item 14, wherein the amount of electrostatic charge on the lithographic photomask is increased. [Item 19] 15. The method of claim 14, also comprising generating a map of electrostatic charge amount for the lithographic photomask, wherein the map includes lithographic photomask surface position and electrostatic charge amount. [Item 20] 15. The method of claim 14, also including the step of measuring the electrostatic charge on the lithographic photomask a second time and modifying the amount of electrostatic charge on the lithographic photomask based on the calculated amount.

Claims

1. a sensor, wherein the sensor is capable of measuring electrostatic charge on an extreme ultraviolet (EUV) lithography photomask; a charge injector, where the charge injector is capable of modifying the electrostatic charge on an EUV lithography photomask; a housing, wherein the sensor and the charge injector are within the housing; and a control unit, wherein the control unit is capable of causing the sensor to measure the electrostatic charge on the EUV lithography photomask, capable of storing, outputting, or storing and outputting a value for the electrostatic charge on the EUV lithography photomask, and capable of causing the charge injector to modify the electrostatic charge on the EUV lithography photomask by a specified amount. An assembly comprising:

2. The assembly of claim 1 , further comprising at least a portion of a carrier for a lithographic photomask, said housing being attached to at least a portion of said carrier for the lithographic photomask.

3. The assembly of claim 1 , wherein the housing is mountable to a portion of a carrier for a lithography photomask.

4. The assembly of claim 1 , wherein the assembly comprises a plurality of charge injectors.

5. The assembly of claim 1 , wherein the assembly comprises a plurality of sensors.

6. 2. The assembly of claim 1, wherein the control unit is further capable of determining the specified amount from a measurement of electrostatic charge on the lithographic photomask and a selected value for electrostatic charge on the lithographic photomask.

7. a sensor, wherein said sensor is capable of measuring electrostatic charge on a lithography photomask; a charge injector, where the charge injector is capable of modifying the electrostatic charge on a lithographic photomask; a housing, wherein the sensor and the charge injector are within the housing; a control unit, where the control unit is capable of causing the sensor to measure the electrostatic charge on the lithographic photomask, outputting, or storing and outputting, a value for the electrostatic charge on the lithographic photomask, and causing the charge injector to modify the electrostatic charge on the lithographic photomask by a specified amount; and a computing system, wherein the computing system is capable of determining an amount to modify the electrostatic charge on the lithographic photomask based on a selected value for the electrostatic charge and an output value from the control unit, and wherein the computing system is communicatively coupled to the control unit; A system comprising:

8. 8. The system of claim 7, wherein the computing system is further capable of generating a map of charge amount relative to a lithographic photomask surface, wherein the map includes lithographic photomask surface location and charge amount.

9. The system of claim 7 , further comprising at least a portion of a carrier for a lithographic photomask, said housing being attached to at least a portion of said carrier for the lithographic photomask.

10. 8. The system of claim 7, wherein the lithography photomask is an extreme ultraviolet (EUV) lithography photomask.

11. The system of claim 7 , wherein the system comprises a plurality of charge injectors within the housing.

12. The system of claim 7 , wherein the system comprises a plurality of sensors within the housing.

13. measuring the electrostatic charge on the lithographic photomask; calculating an amount by which the measured electrostatic charge on the lithographic photomask is altered based on a selected amount of electrostatic charge and the measured amount of electrostatic charge; and Varying the amount of electrostatic charge on the lithographic photomask based on the calculated amount.

1. A method for modifying an electrostatic charge on a lithographic photomask, comprising:

14. 14. The method of claim 13, wherein the lithography photomask is an extreme ultraviolet (EUV) lithography photomask.

15. 14. The method of claim 13, further comprising the step of measuring the electrostatic charge on the lithographic photomask a second time.

16. The method of claim 13 , wherein altering the amount of electrostatic charge on the lithographic photomask comprises reducing the amount of electrostatic charge on the lithographic photomask.

17. The method of claim 13 , wherein altering the amount of electrostatic charge on the lithographic photomask comprises increasing the amount of electrostatic charge on the lithographic photomask.

18. 14. The method of claim 13, further comprising generating a map of electrostatic charge amount for the lithographic photomask, wherein the map includes lithographic photomask surface location and electrostatic charge amount.

19. 14. The method of claim 13, further comprising measuring the amount of electrostatic charge on the lithographic photomask a second time and modifying the amount of electrostatic charge on the lithographic photomask based on the calculated amount.

20. Apparatus comprising means for carrying out the method according to any one of claims 13 to 19.

21. When executed by the processor, A procedure for measuring electrostatic charge on an extreme ultraviolet (EUV) lithography photomask; calculating an amount by which the measured electrostatic charge on the EUV lithography photomask is altered based on a selected amount of electrostatic charge and the measured amount of electrostatic charge; and modifying the amount of electrostatic charge on the EUV lithography photomask based on the calculated amount. A computer program comprising non-transient instructions for causing a computer to

22. 22. The computer program product of claim 21, wherein modifying the amount of electrostatic charge on the lithographic photomask comprises reducing the amount of electrostatic charge on the lithographic photomask.

23. 22. The computer program product of claim 21, wherein modifying the amount of electrostatic charge on the lithographic photomask comprises increasing the amount of electrostatic charge on the lithographic photomask.

24. 22. The computer program of claim 21, further comprising the step of: measuring the electrostatic charge on the lithographic photomask a second time.

25. 22. The computer program product of claim 21, further comprising: generating a map of electrostatic charge amount for the lithographic photomask, wherein the map includes lithographic photomask surface position and electrostatic charge amount.

26. 26. A machine-readable storage medium storing a computer program according to any one of claims 21 to 25.

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