Level shifter including feedback capacitors

Abstract

The present invention discloses a level shifter including a feedback capacitor, and belongs to the field of integrated circuits. In order to reduce duty cycle loss, the level shifter of the present invention includes a bias circuit, a main circuit and an acceleration module; the bias circuit includes a bandgap reference source and provides a bias current; the main circuit includes an AC path and a DC path, and mirrors the reference current; the acceleration module accelerates signal level switching by charge injection. The present invention can accelerate the level switching of high-speed signals, with extremely low delay and small duty cycle loss.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a level shifter including a feedback capacitor. Background Art

[0002] With the rapid development of generative artificial intelligence and large-scale data centers, the industry has put forward higher requirements for the bandwidth, read and write speed and energy efficiency of memory interfaces. In the fifth-generation standard of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), in order to improve energy efficiency, the chip output power supply voltage has been reduced to 1.1V. To achieve this goal, the multi-voltage domain strategy is generally adopted in the design of the transmitter, that is, the output stage operates in the 1.1V voltage domain, while the previous stage uses a lower voltage to reduce power consumption.

[0003] In advanced semiconductor processes, the withstand voltage of low-voltage metal oxide semiconductor field effect transistors (MOSFETs) is usually less than 1V. If they work directly under a 1.1V power supply, there is a risk of overvoltage, which may cause failure of the device in long-term operation. For this reason, when crossing different voltage domains, the signal must be converted through a level shifter to ensure that the converted level meets the safe operating voltage range of the device. As a bridge between different voltage domains, the performance of the level shifter directly affects the quality of high-speed signal conversion and the final performance of the entire transmitter.

[0004] In DDR high-speed links, maintaining signal integrity is critical to the overall performance of the system. Therefore, the signal needs to have the characteristics of fast response, low latency and minimized duty cycle loss after level conversion. However, this requirement poses a challenge to the design of level shifters, because the signal is prone to duty cycle loss due to level conversion when crossing different voltage domains, and maintaining low latency is also a key problem in the design. Summary of the invention

[0005] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0006] A level shifter including a feedback capacitor includes: a bias circuit and a main circuit; wherein the bias circuit includes: an NMOS tube M1, an NMOS tube M3, a first inverter, and a bandgap reference source; the first end of the bandgap reference source is connected to a second device operating voltage, the second end of the bandgap reference source outputs a reference current to the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M1, and the source of the NMOS tube M1 is connected to the output of the first inverter; the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M1; the power supply end of the first inverter is connected to the first device operating voltage and the first common ground terminal voltage, and the first device operating voltage is used as an input signal; and the main circuit includes: a second inverter, an NMOS tube M4, a feedback capacitor, a resistor, and an NMOS tube group M2 <n:0>, the NMOS tube group M2 <n:0>The NMOS tube group M2 includes N+1 NMOS tubes, where N is a positive integer; the gate of the NMOS tube M3 and the gate of the NMOS tube M4 are both connected to the first device working voltage. <n:0>The gates of the transistors are connected to the gate of the NMOS transistor M1; the first end of the resistor is connected to the second device operating voltage, and the second end of the resistor is connected to the output node; the output node is connected to the drain of the NMOS transistor M4, and the source of the NMOS transistor M4 is connected to the NMOS transistor group M2. <n:0>The drain of the NMOS tube group M2 <n:0>The source is connected to the output terminal of the second inverter; the power supply terminal of the second inverter is connected to the first device operating voltage and the first common ground terminal voltage, and receives an input signal, and the input signal swing is between the first common ground terminal voltage and the first device operating voltage.

[0007] Further, the level shifter including the feedback capacitor further includes: an acceleration module; the acceleration module includes: a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a third inverter and a fourth inverter; the output node is connected to the input end of the third inverter, the input end of the fourth inverter, the gate of the PMOS tube M9 and the gate of the NMOS tube M6; the power supply end of the third inverter and the power supply end of the fourth inverter are both connected to the second device working voltage and the first common ground terminal voltage, the output end of the third inverter is connected to the gate of the PMOS tube M8, and the output end of the fourth inverter is connected to the gate of the PMOS tube M8. The gate of the NMOS tube M7; the source of the PMOS tube M10 is connected to the second device operating voltage, the gate of the PMOS tube M10 is connected to the first enabling signal, the drain of the PMOS tube M10 is connected to the source of the PMOS tube M9, the drain of the PMOS tube M9 is connected to the source of the PMOS tube M8, and the drain of the PMOS tube M8 is connected to the output node; the drain of the NMOS tube M7 is connected to the output node, the source of the NMOS tube M7 is connected to the drain of the NMOS tube M6, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5 is connected to the first common ground terminal voltage, and the gate of the NMOS tube M5 is connected to the second enabling signal.

[0008] Furthermore, the output node leads to an output signal, and the output signal swing is between the second common ground terminal voltage and the second device operating voltage.

[0009] Furthermore, the voltage value of the second device operating voltage is greater than the voltage value of the first device operating voltage; and the voltage value of the second common ground terminal voltage is greater than the voltage value of the first common ground terminal voltage.

[0010] Further, the second enabling signal controls the gate of the NMOS transistor M5 and the first enabling signal controls the gate of the PMOS transistor M10 , which are executed synchronously or independently.

[0011] Furthermore, the NMOS tube group M2 <n:0>The number of NMOS tubes turned on is adjustable.

[0012] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0013] (1) The feedback capacitor can speed up the level switching of high-speed signals, with extremely low delay, which can be as low as picoseconds.

[0014] (2) While the DC path transmits low-frequency signals, it can also reset the initial voltage of the feedback capacitor without the need for an additional reset circuit.

[0015] (3) The acceleration module further accelerates the high-frequency response capability of the level shifter through charge injection.

[0016] (4) When the output signal is VSSH, it will not be affected by changes in temperature or process.

[0017] (5) Through resistors and current mirrors, the high-voltage domain mid-level signal is generated autonomously without the need for an additional voltage regulator, and the structure is simple.

[0018] (6) The duty cycle loss of the output signal is very small, and the present invention can be used to transmit high-speed random signals and clock signals.

[0019] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit diagram of a level shifter including a feedback capacitor according to the present invention;

[0021] Figure 2 It is a schematic diagram of the high-frequency signal waveform of the main circuit of the present invention;

[0022] Figure 3 It is a waveform diagram showing the acceleration module accelerating the transition of the signal waveform. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order.

[0025] Traditional level shifters include high-voltage tubes and inverters that form a positive feedback loop, or high-voltage tubes with diode connections. These solutions have the disadvantages of large delays, slow high-frequency response, and even static power consumption.

[0026] In the present invention, the voltage value of the first device operating voltage (Voltage Drain-to-Drain, VDD) VDDL is V DL , the voltage value of the first common ground terminal voltage (Voltage Source-to-Source, VSS) VSSL is V SL , the voltage value of the second device operating voltage VDDH is V DH , the voltage value of the second common ground terminal voltage VSSH is V SH In addition, the capacitance value of the feedback capacitor in the present invention is C, the capacitance value of the resistor is R, and V DH >V DL , V SH >V SL .

[0027] Figure 1 The circuit diagram of the level shifter including the feedback capacitor of the present invention is shown in FIG. The level shifter includes a bias circuit, a main circuit and an acceleration module.

[0028] The bias circuit includes an N-channel Metal Oxide Semiconductor (NMOS) tube M1, an NMOS tube M3, a first inverter INV1 and a bandgap reference source.

[0029] The first end of the bandgap reference source is connected to VDDH, the second end of the bandgap reference source outputs a reference current IREF to the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M1, the source of the NMOS tube M1 is connected to the output of the first inverter INV1, and the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M1.

[0030] The power supply terminal of the first inverter INV1 is connected to VDDL and VSSL, and VDDL is used as an input signal.

[0031] The main circuit includes a second inverter INV2, an NMOS tube M4, a feedback capacitor, a resistor, and an NMOS tube group M2. <n:0>, where NMOS tube group M2 <n:0>It includes N+1 NMOS tubes, where N is a positive integer. In addition, the resistance value of the resistor is R, and the capacitance value of the feedback capacitor is C.

[0032] The gates of NMOS tube M3 and NMOS tube M4 are both connected to VDDL. <n:0>The gates of are connected to the gate of NMOS tube M1.

[0033] The first end of the resistor is connected to VDDH, and the second end of the resistor is connected to the output node. The output node is connected to the drain of the NMOS tube M4, and the source of the NMOS tube M4 is connected to the NMOS tube group M2. <n:0>The drain of the NMOS tube group M2 <n:0>The source of is connected to the output end of the second inverter INV2.

[0034] The power supply terminal of the second inverter INV2 is connected to VDDL and VSSL, and receives an input signal, wherein the swing of the input signal is VSSL-VDDL.

[0035] Furthermore, the acceleration module includes: a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a third inverter INV3 and a fourth inverter INV4.

[0036] The output node is connected to an input end of the third inverter INV3 , an input end of the fourth inverter INV4 , a gate of the PMOS transistor M9 , and a gate of the NMOS transistor M6 .

[0037] The power supply terminals of the third inverter INV3 and the fourth inverter INV4 are both connected to VDDH and VSSL. The output terminal of the third inverter INV3 is connected to the gate of the PMOS tube M8, and the output terminal of the fourth inverter INV4 is connected to the gate of the NMOS tube M7.

[0038] The source of the PMOS tube M10 is connected to VDDH, the gate of the PMOS tube M10 is connected to the first enabling signal ENP, the drain of the PMOS tube M10 is connected to the source of the PMOS tube M9, the drain of the PMOS tube M9 is connected to the source of the PMOS tube M8, and the drain of the PMOS tube M8 is connected to the output node.

[0039] The drain of the NMOS tube M7 is connected to the output node, the source of the NMOS tube M7 is connected to the drain of the NMOS tube M6, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5 is connected to VSSL, and the gate of the NMOS tube M5 is connected to the second enabling signal ENN.

[0040] In the present invention, the feedback capacitor forms an alternating current (AC) path, and the NMOS tube group M2 <n:0>Together with NMOS tube M4 and resistor, a direct current (DC) path is formed.

[0041] In addition, in the present invention, the source of the PMOS tube M8 is used as the node A, and the source of the NMOS tube M7 is used as the node B; the current flowing into the drain of the NMOS tube M4 is Iout.

[0042] In the present invention, the output signal swing is: VSSH~VDDH.

[0043] Furthermore, NMOS tube group M1 and NMOS tube group M2 <n:0>, NMOS tube group M3 and NMOS tube group M4 are all NMOS tubes with low conduction threshold, and NMOS tube M5, NMOS tube M6, NMOS tube M7, PMOS tube M8, PMOS tube M9 and PMOS tube M10 are all PMOS tubes with high conduction threshold.

[0044] Furthermore, the NMOS tube group M1 and the NMOS tube group M2 <n:0>As current mirrors, NMOS tube group M3 and NMOS tube group M4 are protection tubes to prevent NMOS tube group M1 and NMOS tube group M2 from <n:0>Overpressure.

[0045] Furthermore, the NMOS tube group M2 <n:0>It forms a common-gate amplifier and can control the NMOS tube group M2 through digital code <n:0>The number of NMOS tubes that are turned on; the resistance in the main circuit can be matched with the resistance inside the bandgap reference source, and for example the resistance values ​​of the two are equal or have a specific ratio.

[0046] Furthermore, the first inverter INV1 and the second inverter INV2 are matched to ensure a mirror image relationship between the current provided by the bias circuit and the current of the main circuit.

[0047] The acceleration module in the present invention increases the signal switching speed by injecting charges.

[0048] Optionally, the second enabling signal controls the gate of the NMOS transistor M5 and the first enabling signal controls the gate of the PMOS transistor M10 , which are performed synchronously or independently.

[0049] Figure 2 The AC path in the present invention is used to process high-frequency signals, such as the rising and falling edges of the signal during the switching process, and the AC path is formed through the feedback capacitor, while the low-frequency part is transmitted through the DC path.

[0050] When the input signal is a DC signal VDDL, the NMOS tube group M2 <n:0>The NMOS tube M4 is turned on. At this time, the voltage value of the output signal of the output node Vout=V DH -Iout×R, where V DH is the voltage value of VDDH, Iout is the current flowing into the drain of NMOS tube M4, and R is the resistance value of the resistor.

[0051] Iout also sets the current value flowing through the resistor and NMOS tube M2. By setting Iout, Vout=V SH Since the reference current IREF flows from the bandgap reference source, the product of the current value of the reference current and the internal resistance of the bandgap reference source is constant and is not affected by temperature, process, etc. The resistance in the level shifter matches the internal resistance of the bandgap reference source and flows through the NMOS tube group M2 at the same time. <n:0>The current is obtained by mirroring the reference current IREF, so Iout×R will not be affected by factors such as temperature and process. In other words, in the present invention:

[0052] ;

[0053] Where t is time, d is the differential sign, Iout is the current flowing into the drain of NMOS tube M4, and R is the resistance value of the resistor.

[0054] Therefore, in the present invention, the voltage value Vout of the output signal can be unaffected by changes in temperature, process and other factors, and by adjusting the NMOS tube group M2 <n:0>The number of NMOS tubes turned on can be adjusted to fine-tune Iout to adapt to the change of VDDH, so that the voltage value Vout of the output signal meets the target value.

[0055] On the other hand, when the input signal is a DC VSSL, the voltage value of the output signal of the second inverter INV2 is V DL At this time, the NMOS tube M2 is turned off, and the voltage value of the output node is pulled up to V DH .

[0056] In the initial stage, the voltage value of the input signal is V DL When the output signal voltage is V SH , the charge Q0 stored in the capacitor is: Q0 = (V SH -V SL )×C, where C is the capacitance of the feedback capacitor. By setting the resistance of the resistor and the value of Iout, V SH =V DH -V DL +V SL .

[0057] In the next stage, the voltage value of the input signal changes from V DL Jump to V SL Since the high-frequency component in the jump is directly coupled to the output node through the capacitor, after the AC path reaches the steady state, the voltage value of the output signal at this time is Vout1, and the charge Q1 stored in the capacitor is: Q1= (Vout1-V DL )×C, where C is the capacitance value of the feedback capacitor.

[0058] The signal transmission speed in the AC path is faster than that in the DC path, so when the DC path has not yet responded, there is no charge transfer in the DC path. For the AC path, the charge of the feedback capacitor can be considered to be conserved, so Q1=Q0. So: Vout1=V DL +V SH -V SL =V DH .

[0059] Similarly, for the next stage, the voltage value of the input signal increases from V DL Jump to V SL According to the charge conservation of the front and rear capacitors, we can get: Vout2=V DH -V DL +V SL =V SH , where Vout2 is the voltage value of the updated output signal.

[0060] By analogy, during the high-speed switching of the input signal, the feedback capacitor can achieve fast switching of the output signal, thereby ensuring extremely small duty cycle loss of the output signal.

[0061] Considering the parasitic capacitance at the output node, the voltage swing transmitted by the AC path is reduced. Figure 2 As shown in the figure, when the input signal switches from high level to low level, the output node is quickly pulled up by the AC path. Due to the existence of parasitic capacitance, the signal swing coupled by the AC path cannot reach VDDH, and is pulled up to VDDH by the resistor, that is, the voltage value of the output signal changes from V SH Quickly pull up to V DH Similarly, when the input signal jumps from a high level to a low level, the output signal drops mainly due to the capacitive coupling of the AC path and the pull-down of the NMOS tube.

[0062] Figure 3 It is a waveform diagram of the acceleration module accelerating the jump of the signal waveform. In the present invention, the acceleration module is used to further increase the speed of the output signal jump and improve the overall performance of the level shifter. The acceleration module uses a high-voltage tube to avoid overpressure defects.

[0063] The acceleration module can be enabled by a first enabling signal ENP and a second enabling signal ENN. The NMOS transistor M5 and the PMOS transistor M10 are switch transistors that can be used to independently control the acceleration function of the falling edge or the rising edge.

[0064] When the acceleration module is turned on, in the initial stage, when the input signal is VDDL, the output signal is VSSH. PMOS tube M8 is turned off, PMOS tube M9 is turned on, and the voltage of node A is pulled to V DH , NMOS tube M7 is turned on, NMOS tube M6 is turned off, and the voltage of node B is V SH .

[0065] In the next stage, when the input signal jumps from VDDL to VSSL, the output voltage starts to rise rapidly due to capacitive coupling, the PMOS tube M9 is turned off, and the PMOS tube M8 is turned on.

[0066] The positive charge previously stored in node A begins to be injected into the output node, thereby accelerating the rise of the output node voltage and playing a rising edge acceleration effect. Finally, the voltage of node A and the voltage of the output node are both stable at V DH At the same time, NMOS tube M7 is turned off, NMOS tube M6 is turned on, and the voltage of node B is pulled to V by NMOS tube M6. SL .

[0067] In the next stage, when the input signal jumps from VSSL to VDDL, the voltage of the output node begins to drop, the NMOS tube M6 begins to cut off, the NMOS tube M7 begins to turn on, and the negative charge previously stored in the node B begins to be injected into the output node, thereby accelerating the drop in the voltage of the output node. At the same time, the PMOS tube M9 is turned on, the PMOS tube M8 is turned off, and the node A is precharged to VDDH, in preparation for the subsequent acceleration of the output voltage increase.

[0068] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0069] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A level shifter comprising a feedback capacitor, characterized in that: include: A bias circuit and a main circuit; wherein, The bias circuit comprises: an NMOS tube M1, an NMOS tube M3, a first inverter and a bandgap reference source; The first end of the bandgap reference source is connected to the second device operating voltage, the second end of the bandgap reference source outputs a reference current to the drain of the NMOS tube M3, the source of the NMOS tube M3 is connected to the drain of the NMOS tube M1, and the source of the NMOS tube M1 is connected to the output of the first inverter; The drain of the NMOS tube M1 is connected to the gate of the NMOS tube M1; the power supply terminal of the first inverter is connected to the first device operating voltage and the first common ground terminal voltage, and the first device operating voltage is used as an input signal; and, The main circuit includes: a second inverter, an NMOS tube M4, a feedback capacitor, a resistor, and an NMOS tube group M2 <n:0>, the NMOS tube group M2 <n:0> It includes N+1 NMOS tubes, where N is a positive integer; The gate of the NMOS tube M3 and the gate of the NMOS tube M4 are both connected to the first device working voltage. <n:0> The gates of are connected to the gate of NMOS tube M1; The first end of the resistor is connected to the second device operating voltage, and the second end of the resistor is connected to the output node; the output node is connected to the drain of the NMOS tube M4, and the source of the NMOS tube M4 is connected to the NMOS tube group M2. <n:0>The drain of the NMOS tube group M2 <n:0> A source electrode is connected to an output terminal of a second inverter; The power supply terminal of the second inverter is connected to the first device operating voltage and the first common ground terminal voltage, and receives an input signal, and the input signal swing is between the first common ground terminal voltage and the first device operating voltage.

2. The level shifter comprising a feedback capacitor according to claim 1, characterized in that: The level shifter including the feedback capacitor further includes: an acceleration module; The acceleration module includes: a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a third inverter and a fourth inverter; The output node is connected to the input end of the third inverter, the input end of the fourth inverter, the gate of the PMOS tube M9 and the gate of the NMOS tube M6; The power supply terminal of the third inverter and the power supply terminal of the fourth inverter are both connected to the second device working voltage and the first common ground terminal voltage, the output terminal of the third inverter is connected to the gate of the PMOS tube M8, and the output terminal of the fourth inverter is connected to the gate of the NMOS tube M7; The source of the PMOS tube M10 is connected to the second device operating voltage, the gate of the PMOS tube M10 is connected to the first enabling signal, the drain of the PMOS tube M10 is connected to the source of the PMOS tube M9, the drain of the PMOS tube M9 is connected to the source of the PMOS tube M8, and the drain of the PMOS tube M8 is connected to the output node; The drain of the NMOS tube M7 is connected to the output node, the source of the NMOS tube M7 is connected to the drain of the NMOS tube M6, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M5, the source of the NMOS tube M5 is connected to the first common ground terminal voltage, and the gate of the NMOS tube M5 is connected to the second enabling signal.

3. The level shifter comprising a feedback capacitor according to claim 2, characterized in that: The output node leads to an output signal, and the output signal swing is between the second common ground terminal voltage and the second device operating voltage.

4. The level shifter comprising a feedback capacitor according to claim 1 or 3, characterized in that: The voltage value of the second device operating voltage is greater than the voltage value of the first device operating voltage; The voltage value of the second common ground terminal voltage is greater than the voltage value of the first common ground terminal voltage.

5. The level shifter comprising a feedback capacitor according to claim 4, characterized in that: The second enabling signal controls the gate of the NMOS transistor M5 and the first enabling signal controls the gate of the PMOS transistor M10 , which are executed synchronously or independently.

6. The level shifter comprising a feedback capacitor according to claim 5, characterized in that: The NMOS tube group M2 <n:0> The number of NMOS tubes turned on is adjustable.< / n:0>

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