Semiconductor device

Abstract

To provide a transistor that can be microfabricated.SOLUTION: A semiconductor device includes: an oxide semiconductor layer; first to fourth conductive layers; and first to fourth insulation layers. On the first conductive layer having a recess part, the first insulation layer, the second conductive layer, the second insulation layer, and the third conductive, each having the first open part that is overlapped with the concave part are provided in this order. The third insulation layer is in contact with at least a side surface of the second conductive layer in the first open part. The oxide semiconductor layer is in contact with an upper surface of the third conductive layer and a bottom surface and a side surface of the concave part, and is in contact with the third insulation layer in the first open part. The fourth insulation layer is positioned at the side inner from the oxide semiconductor layer in the first open part. The fourth conductive layer is positioned at the side inner from the fourth insulation layer in the first open part. In a cross-sectional view, the oxide semiconductor layer includes a region that is overlapped with the second conductive layer via the third insulation layer and overlapped with the fourth conductive layer via the fourth insulation layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs (Central Processing Units), memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further increasing the density of integrated circuits. There is also a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] JP 2013-211537 A [Non-patent literature]

[0010] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention [Problem to be solved by the invention]

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, a display device, or a memory device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device, a display device, or a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operation speed. Another object of one embodiment of the present invention is to provide a method for manufacturing the transistor, the semiconductor device, the display device, or the memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0013] One embodiment of the present invention includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, in which the first insulating layer is located over the first conductive layer, the second conductive layer is located over the first insulating layer, the second insulating layer is located over the second conductive layer, and the third conductive layer is located over the second insulating layer, the first conductive layer has a first recess, and the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping with the first recess, and the third insulating layer has a first insulating layer. the oxide semiconductor layer is in contact with at least a side surface of the second conductive layer in the first opening, the oxide semiconductor layer is in contact with an upper surface of the third conductive layer and a bottom surface and side surfaces of the first recess and is in contact with the third insulating layer in the first opening, the fourth insulating layer is located on the inner side of the oxide semiconductor layer in the first opening, and the fourth conductive layer is located on the inner side of the fourth insulating layer in the first opening, and in cross-sectional view, the oxide semiconductor layer has a region overlapping the second conductive layer via the third insulating layer and overlapping the fourth conductive layer via the fourth insulating layer.

[0014] The semiconductor device preferably further includes a fifth insulating layer. In this case, the first conductive layer and the second insulating layer are preferably located on the fifth insulating layer, and the shortest distance from the upper surface of the fifth insulating layer to the upper surface of the first conductive layer that contacts the first insulating layer is longer than the shortest distance from the upper surface of the fifth insulating layer to the lower surface of the fourth insulating layer. Alternatively, the first conductive layer and the fourth conductive layer are preferably located on the fifth insulating layer, and the shortest distance from the upper surface of the fifth insulating layer to the upper surface of the first conductive layer that contacts the first insulating layer is longer than the shortest distance from the upper surface of the fifth insulating layer to the lower surface of the fourth conductive layer.

[0015] It is preferable that the first conductive layer has a fifth conductive layer and a sixth conductive layer on the fifth conductive layer, the sixth conductive layer has a second recess, the first opening overlaps with the second recess, and the oxide semiconductor layer contacts the bottom and side surfaces of the second recess.

[0016] The semiconductor device preferably further includes a sixth insulating layer. In this case, it is preferable that the fourth insulating layer covers the upper surface and side surface of the oxide semiconductor layer on the second insulating layer, the sixth insulating layer is located on the fourth insulating layer and has a second opening at a position overlapping with the first opening, and the fourth conductive layer has a portion overlapping with the oxide semiconductor layer via the fourth insulating layer in the first opening and a portion located in the second opening. Alternatively, it is preferable that the sixth insulating layer is located on the second insulating layer, covers the upper surface and side surface of the oxide semiconductor layer on the second insulating layer and has a second opening at a position overlapping with the first opening, the fourth insulating layer has a portion located in the second opening, and the fourth conductive layer is located inside the fourth insulating layer in the second opening.

[0017] Alternatively, one embodiment of the present invention includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, in which the first insulating layer is located over the first conductive layer, the second conductive layer is located over the first insulating layer, the second insulating layer is located over the second conductive layer, and the third conductive layer is located over the second insulating layer, the first conductive layer has a first recess, and the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping with the first recess, and the third insulating layer is in contact with at least a side surface of the second conductive layer in the first opening, the oxide semiconductor layer is in contact with an upper surface of the third conductive layer and a bottom surface and side surfaces of the first recess, and is in contact with the third insulating layer within the first opening; the fourth insulating layer is located inside the oxide semiconductor layer within the first opening, the fourth conductive layer is located inside the fourth insulating layer within the first opening; the fifth insulating layer is located on the fourth insulating layer and has a second opening reaching the fourth conductive layer at a position overlapping with the first opening, the fifth conductive layer is in contact with the fourth conductive layer within the second opening, and in cross section, the oxide semiconductor layer has a region overlapping with the second conductive layer via the third insulating layer and overlapping with the fourth conductive layer via the fourth insulating layer.

[0018] The semiconductor device preferably further includes a sixth insulating layer. In this case, the first conductive layer and the second insulating layer are preferably located on the sixth insulating layer, and the shortest distance from the upper surface of the sixth insulating layer to the upper surface of the first conductive layer that contacts the first insulating layer is longer than the shortest distance from the upper surface of the sixth insulating layer to the lower surface of the fourth insulating layer. Alternatively, the first conductive layer and the fourth conductive layer are preferably located on the sixth insulating layer, and the shortest distance from the upper surface of the sixth insulating layer to the upper surface of the first conductive layer that contacts the first insulating layer is preferably equal to or longer than the shortest distance from the upper surface of the sixth insulating layer to the lower surface of the fourth conductive layer.

[0019] It is preferable that the first conductive layer has a sixth conductive layer and a seventh conductive layer on the sixth conductive layer, the seventh conductive layer has a second recess, the first opening overlaps with the second recess, and the oxide semiconductor layer contacts the bottom and side surfaces of the second recess.

[0020] In each of the above semiconductor devices, the third insulating layer has a seventh insulating layer in contact with the oxide semiconductor layer and an eighth insulating layer located outside the seventh insulating layer within the first opening, and it is preferable that one of the seventh insulating layer and the eighth insulating layer is an oxide insulating layer and the other is a nitride insulating layer.

[0021] Alternatively, one embodiment of the present invention is a semiconductor device including a first layer and a second layer over the first layer, the second layer including a first memory cell array and a second memory cell array, the first memory cell array including a plurality of first memory cells, the second memory cell array including a plurality of second memory cells, the first layer including a transistor having silicon in a channel formation region, the first memory cell and the second memory cell each including a vertical transistor, the vertical transistor including an oxide semiconductor in a channel formation region, and the first memory cell and the second memory cell having different structures from each other.

[0022] Alternatively, one embodiment of the present invention is a semiconductor device including a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer including a first memory cell array, and the third layer including a second memory cell array, the first memory cell array including a plurality of first memory cells, the second memory cell array including a plurality of second memory cells, the first layer including a transistor having silicon in a channel formation region, the first memory cell and the second memory cell each including a vertical transistor, the vertical transistor including an oxide semiconductor in a channel formation region, and the first memory cell and the second memory cell having different structures from each other.

[0023] Of the first memory cell and the second memory cell, it is preferable that one of them can retain information for a longer period in the absence of power supply to the memory cell than the other.

[0024] Alternatively, one embodiment of the present invention is a semiconductor device including a first layer and a second layer over the first layer, the second layer including a first memory cell array and a second memory cell array, the first memory cell array including a plurality of first memory cells, the second memory cell array including a plurality of second memory cells, the first layer including a transistor having silicon in a channel formation region, the first memory cell including one vertical transistor and one capacitor, the second memory cell including two vertical transistors, and the vertical transistors included in the first memory cell and the second memory cell including each have an oxide semiconductor in a channel formation region.

[0025] Alternatively, one embodiment of the present invention is a semiconductor device including a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer including a first memory cell array, and the third layer including a second memory cell array, the first memory cell array including a plurality of first memory cells, the second memory cell array including a plurality of second memory cells, the first layer including a transistor having silicon in a channel formation region, one of the first memory cell and the second memory cell including one vertical transistor and one capacitor, and the other including two vertical transistors, the vertical transistors included in the first memory cell and the second memory cell including each have an oxide semiconductor in a channel formation region. Effect of the Invention

[0026] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a transistor, a semiconductor device, a display device, or a memory device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device, a display device, or a memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operation speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, display device, or memory device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0028] [Figure 1]1A to 1F are perspective views illustrating configuration examples of a semiconductor device. [Diagram 2] 2A1 and 2A2 are plan views illustrating an example of a semiconductor device, and FIGS. 2B to 2E are cross-sectional views illustrating an example of a semiconductor device. [Diagram 3] FIG. 3 is a cross-sectional view showing an example of a semiconductor device. [Figure 4] 4(A) and 4(B) are cross-sectional views showing an example of a semiconductor device. [Diagram 5] 5(A) and 5(B) are cross-sectional views showing an example of a semiconductor device. [Figure 6] 6A to 6D are cross-sectional views showing an example of a semiconductor device. [Figure 7] 7A to 7C are cross-sectional views showing an example of a semiconductor device. [Figure 8] Fig. 8A is a plan view showing an example of a semiconductor device, and Figs. 8B to 8E are cross-sectional views showing an example of the semiconductor device. [Figure 9] 9(A) and 9(B) are cross-sectional views showing an example of a semiconductor device. [Figure 10] Fig. 10A is a plan view showing an example of a semiconductor device, and Figs. 10B to 10E are cross-sectional views showing an example of the semiconductor device. [Figure 11] 11(A) and 11(B) are cross-sectional views showing an example of a semiconductor device. [Figure 12] Fig. 12A is a plan view showing an example of a semiconductor device, and Figs. 12B to 12E are cross-sectional views showing an example of the semiconductor device. [Figure 13] 13A and 13B are cross-sectional views showing an example of a semiconductor device. [Figure 14] 14A to 14C2 are cross-sectional views showing an example of a semiconductor device. [Figure 15] 15A1 to 15E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 16]16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] 17A to 17F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 18] 18A to 18F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] 19A to 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20] 20A to 20D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 21] 21A to 21D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 22] Fig. 22(A) is a plan view showing an example of a memory device, and Fig. 22(B) and Fig. 22(C) are cross-sectional views showing an example of the memory device. [Diagram 23] 23(A) and 23(B) are cross-sectional views showing an example of a memory device. [Figure 24] 24(A) and 24(B) are cross-sectional views showing an example of a memory device. [Diagram 25] Fig. 25(A) is a plan view showing an example of a memory device, and Fig. 25(B) and Fig. 25(C) are cross-sectional views showing an example of the memory device. [Figure 26] 26(A) and 26(B) are cross-sectional views showing an example of a memory device. [Figure 27] 27(A) and 27(B) are cross-sectional views showing an example of a memory device. [Figure 28] FIG. 28 is a cross-sectional view showing an example of a memory device. [Figure 29] FIG. 29 is a cross-sectional view showing an example of a storage device. [Diagram 30] FIG. 30 is a cross-sectional view showing an example of a storage device. [Diagram 31] FIG. 31 is a cross-sectional view showing an example of a storage device. [Diagram 32] FIG. 32 is a cross-sectional view showing an example of a storage device. [Diagram 33] Fig. 33(A) is a plan view showing an example of a storage device, and Fig. 33(B) is a cross-sectional view showing an example of the storage device. [Diagram 34] FIG. 34 is a cross-sectional view showing an example of a storage device. [Diagram 35] FIG. 35 is a cross-sectional view showing an example of a storage device. [Diagram 36] Fig. 36(A) is a plan view showing an example of a memory device, and Fig. 36(B) is a cross-sectional view showing an example of the memory device. [Figure 37] FIG. 37 is a cross-sectional view showing an example of a storage device. [Figure 38] FIG. 38 is a cross-sectional view showing an example of a memory device. [Figure 39] FIG. 39 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 40] 40A to 40G are diagrams illustrating examples of circuit configurations of memory cells. [Diagram 41] 41A and 41B are perspective views illustrating a configuration example of a semiconductor device. [Diagram 42] FIG. 42 is a block diagram illustrating the CPU. [Diagram 43] 43(A) and 43(B) are perspective views of a semiconductor device. [Diagram 44] 44(A) and 44(B) are perspective views of a semiconductor device. [Diagram 45] 45(A) and 45(B) are diagrams showing various storage devices by hierarchical level. [Figure 46] 46(A) and 46(B) are perspective views showing an example of a display device. [Figure 47] FIG. 47 is a cross-sectional view showing an example of a display device. [Figure 48] FIG. 48 is a cross-sectional view showing an example of a display device. [Figure 49] FIG. 49 is a cross-sectional view showing an example of a display device. [Figure 50] FIG. 50 is a cross-sectional view showing an example of a display device. [Figure 51] 51(A) to 51(C) are diagrams showing configuration examples of a display device. [Figure 52] 52(A) and 52(B) are diagrams showing an example of an electronic component. [Figure 53] Fig. 53(A) to Fig. 53(C) are diagrams showing an example of a mainframe computer. Fig. 53(D) is a diagram showing an example of space equipment. Fig. 53(E) is a diagram showing an example of a storage system applicable to a data center. [Figure 54] 54(A) to 54(F) are diagrams showing examples of electronic devices. [Figure 55] 55(A) to 55(G) are diagrams showing examples of electronic devices. [Figure 56] 56(A) to 56(F) are diagrams showing examples of electronic devices. [Figure 57] Fig. 57(A) is a circuit diagram according to an embodiment, and Fig. 57(B) is a timing chart according to an embodiment. [Figure 58] 58(A) and 58(B) show the measurement results of the read current according to the example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0031] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0033] A transistor is a type of semiconductor element and can realize a function of amplifying a current or voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor, and a transistor having silicon in a channel formation region may be referred to as a Si transistor.

[0035] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0036] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0037] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities may, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V O In some cases, a junction (also referred to as a junction) may be formed.

[0038] In this specification and the like, an oxynitride refers to a material having a composition containing more oxygen than nitrogen, and a nitride oxide refers to a material having a composition containing more nitrogen than oxygen.

[0039] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used to analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in the film. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0040] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0041] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0042] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements having various functions.

[0043] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source in an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0044] In this specification, the term "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0045] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0046] In this specification, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B. Similarly, when it is stated that A contacts B or A overlaps B, at least a part of A contacts B or overlaps B. Therefore, it can be rephrased as A has an area contacting B or A has an area overlapping B, respectively. Similarly, in this specification, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.

[0047] In this specification, a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0048] In this specification and the like, a structure in which light-emitting layers are separately created for light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the material and configuration to be optimized for each light-emitting element, increasing the freedom of material and configuration selection and making it easier to improve brightness and reliability.

[0049] In this specification and the like, holes or electrons may be referred to as "carriers". Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer", a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer", and a hole block layer or an electron block layer may be referred to as a "carrier block layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Also, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0050] In this specification and the like, the light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0051] In this specification and the like, a sacrificial layer (which may also be referred to as a mask layer) is located at least above a light-emitting layer (more specifically, a layer that is processed into an island shape among layers that constitute the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0052] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, a film, or an electrode is divided due to the shape of the surface on which it is formed (for example, a step or the like).

[0053] In addition, in the drawings and the like related to this specification, arrows indicating the X direction, Y direction, and Z direction may be attached. In addition, in this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." In addition, the X direction, the Y direction, and the Z direction are directions that intersect with each other. For example, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other.

[0054] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to Fig. 1. The semiconductor device in this embodiment can function as a memory device.

[0055] 1A to 1F are schematic perspective views showing semiconductor devices. Each of the semiconductor devices shown in FIG. 1A to 1F includes a layer 91 and one or more layers 92 on the layer 91.

[0056] The layer 91 may have, for example, a structure that can be used in a driver circuit 910 (FIG. 39) described later, or a structure that can be used in an arithmetic device 960 (FIG. 42) described later. Specifically, the layer 91 has, for example, a readout circuit. The layer 91 preferably has a transistor having silicon in a channel formation region.

[0057] One layer 92 has at least one type of memory cell array 93. In the following, a description will be given assuming that one memory cell array 93 has one type of memory cell. The memory cell array 93 has one or more memory cells. The memory cell array 93 has, for example, a plurality of memory cells arranged in a matrix. The memory cell array 93 can have a configuration in which a plurality of memory cells are arranged in at least one of the X direction, Y direction, and Z direction.

[0058] A semiconductor device according to one embodiment of the present invention has at least two or more types of memory cell arrays 93. Examples of memory cells that can be used in each memory cell array 93 include a memory cell including one transistor and one capacitor (hereinafter referred to as a 1Tr1C memory cell), a memory cell including two transistors and one capacitor (hereinafter referred to as a 2Tr1C memory cell), and a memory cell including two transistors (hereinafter referred to as a 2Tr0C memory cell). Note that the configuration of a memory cell is not limited thereto, and a combination of two or more transistors (typically two to six transistors) and one or more capacitors (typically one to five capacitors) can be used.

[0059] By having two or more types of memory cells in a semiconductor device, it is possible to select memory cells to be used depending on the application, thereby achieving both high speed reading and writing of the memory device and reduced power consumption of the memory device.

[0060] For example, when reading from the memory cell of 1Tr1C, stored information is erased (also called destructive reading). On the other hand, when reading from the memory cells of 2Tr0C and 2Tr1C, stored information is not erased (also called non-destructive reading). The semiconductor device of one embodiment of the present invention preferably has a plurality of types of memory cells that operate differently from each other in this manner.

[0061] A semiconductor device of one embodiment of the present invention preferably includes at least one of the memory cells shown in Figures 40(A) to 40(G). Here, a memory cell 951 shown in Figure 40(A) is an example of a 1Tr1C memory cell. A memory cell 953 shown in Figure 40(C) and a memory cell 954 shown in Figure 40(D) ​​are examples of a 2Tr1C memory cell. A memory cell 955 shown in Figure 40(E) and a memory cell 956 shown in Figure 40(F) are examples of a 2Tr0C memory cell. Each memory cell will be described in detail later.

[0062] The layer 92 preferably includes a transistor having an oxide semiconductor in a channel formation region. A transistor of one embodiment of the present invention described later uses an oxide semiconductor in a channel formation region and has a small off-state current, and is therefore suitable for a memory cell. As a result, the memory cell becomes substantially nonvolatile. Furthermore, the transistor of one embodiment of the present invention has a high on-state current and a small off-state current, and therefore enables high-speed writing and nondestructive reading. A transistor using an oxide semiconductor in a channel formation region will be described in detail later (see FIGS. 2 to 19, etc.).

[0063] In this specification etc., non-volatile memory refers to a memory that can retain stored information for at least one day, preferably one month or more, more preferably one year or more, and even more preferably ten years or more in a state where no power is supplied to the memory and in an environment of 85° C. Also, in this specification etc., volatile memory refers to a memory other than the above-mentioned non-volatile memory.

[0064] 22 to 32 and the like can be referred to for specific cross-sectional examples of memory cells using a transistor according to one embodiment of the present invention. Here, the memory cells illustrated in FIGS. 22 and 25 are examples of 1Tr1C memory cells. The memory cells illustrated in FIGS. 23, 24, and 26 to 31 are examples of 2Tr0C memory cells. The 2Tr0C memory cells can be used, for example, as high-speed write memory or write mostly memory. The memory cell illustrated in FIG. 32 is an example of a 2Tr1C memory cell. By using an OS transistor in the 2Tr1C memory cell, for example, it is possible to impart a nonvolatile function to a dynamic random access memory (DRAM) and a static random access memory (SRAM). Note that the 1Tr1C memory cell and the 2Tr1C memory cell can be used as a random access memory (RAM). The cross-sectional structures of these memory cells will be described in detail later.

[0065] 22 to 32 include a vertical transistor including an oxide semiconductor for a semiconductor layer. The vertical transistor has high on-state current characteristics, high frequency characteristics, and low off-state current characteristics, and therefore has a substantially nonvolatile function and enables high-speed writing and nondestructive reading.

[0066] Note that the semiconductor device of one embodiment of the present invention has a function of reading data from or writing data to a storage (typically, a high-capacity nonvolatile storage device such as a 3D NAND) that stores data that needs to be stored for a long time and various programs used in a processing device (for details, see FIG. 45 in Embodiment 6 described later). Furthermore, the 3D NAND functions as a read mostly memory due to its characteristics.

[0067] 1(A) and 1(B) each have a layer 92 on a layer 91. The layer 92 of the semiconductor device 81 has a memory cell array 93A and a memory cell array 93B. The layer 92 of the semiconductor device 82 has a memory cell array 93A, a memory cell array 93B, and a memory cell array 93C.

[0068] The memory cell arrays 93A and 93B preferably have memory cells with different circuit configurations. For example, the memory cell array 93A preferably has one of the memory cells 1Tr1C, 2Tr0C, and 2Tr1C, and the memory cell array 93B preferably has another one of the memory cells 1Tr1C, 2Tr0C, and 2Tr1C. Specifically, it is preferable that one of the memory cell arrays 93A and 93B uses a memory cell of 1Tr1C, and the other uses a memory cell of 2Tr0C.

[0069] It is preferable that the memory cell arrays 93A, 93B, and 93C each have a memory cell with a different circuit configuration. For example, it is preferable that the memory cell array 93A has one of the memory cells 1Tr1C, 2Tr0C, and 2Tr1C, the memory cell array 93B has another one of the memory cells 1Tr1C, 2Tr0C, and 2Tr1C, and the memory cell array 93C has the remaining one of the memory cells 1Tr1C, 2Tr0C, and 2Tr1C.

[0070] Alternatively, two or more of the memory cell arrays 93A, 93B, and 93C may have memory cells of the same circuit configuration. Two or more of the memory cell arrays 93A, 93B, and 93C may have memory cells of the same circuit configuration (1Tr1C, 2Tr0C, 2Tr1C, etc.) and may differ from each other in the number, size, etc. of the memory cells. In this way, by using multiple memory cell arrays with different performances and specifications, even if the circuit configuration of the memory cells is the same, it is possible to multi-function the semiconductor device.

[0071] In this way, a semiconductor device in which multiple types of memory cells are combined can be realized by providing two or more types of memory cell arrays 93 in one layer 92. By combining multiple types of memory cells, it is possible to provide a semiconductor device having a function between a write mostly memory and a read mostly memory.

[0072] Note that the semiconductor device of one embodiment of the present invention is suitable for an arithmetic processing device such as a CPU or a GPU (Graphics Processing Unit). Advances in AI (Artificial Intelligence) technology have led to demands for higher performance in CPUs, GPUs, memories, and the like. On the other hand, in AI technology, the same or similar information may be used repeatedly. For this reason, different memories are used depending on the information to be stored. For example, important information that is not to be erased is stored in a memory that can hold the information for a longer period, and the same information, similar information, or information to be temporarily stored is stored in a memory that can hold the information for a relatively short period. In this way, the semiconductor device of one embodiment of the present invention can change the memory cell to be used depending on the application.

[0073] As a method for stacking the layer 92 having the memory cell array and the layer 91, a method of stacking the layer 92 directly on the layer 91 (also called a monolithic stacking method) can be used. The monolithic stacking method is suitable for miniaturization because it has a feature that it is not necessary to align the layer 91 and the layer 92 to connect each layer, or to bond the layer 91 and the layer 92 together. In addition, when the monolithic stacking method is used, for example, assuming that the layer 91 is a processor and the layer 92 is a memory, a so-called on-chip memory configuration can be formed in which the memory is directly formed on the processor. The on-chip memory configuration can speed up the operation of the interface between the processor and the memory. The on-chip memory configuration can reduce the size of the connection wiring, etc., and therefore can also increase the number of connection pins. Increasing the number of connection pins enables parallel operation, and therefore the memory bandwidth (also called memory bandwidth) can be improved.

[0074] Alternatively, a lamination or bonding method may be used in which the layers 91 and 92 are formed on different substrates, the two substrates are laminated, and the two substrates are electrically connected using a through electrode technology such as TSV (Through Silicon Via) or a conductive film bonding technology (Cu-Cu bonding, etc.). The memory cell arrays 93A and 93B may be formed on the same substrate, or may be formed on different substrates. The same applies when there are three or more types of memory cell arrays 93.

[0075] 1(A) and the like, when a single layer 92 has multiple types of memory cell arrays 93, the region is shown as being equally divided, but the present invention is not limited to this. For example, one of memory cell array 93A and memory cell array 93B may occupy a larger area on the top surface of layer 91 than the other. The same applies when there are three or more types of memory cell arrays 93. The outer shape of layer 91 and the outer shape of layer 92 may be the same or different.

[0076] 1C includes two layers, that is, a layer 92 on a layer 91. Specifically, the semiconductor device 83 includes a layer 91, a layer 92a on the layer 91, and a layer 92b on the layer 92a. The layer 92a includes a memory cell array 93A, and the layer 92b includes a memory cell array 93B.

[0077] 1D has three layers, namely, a layer 92 on a layer 91. Specifically, the semiconductor device 84 has a layer 91, a layer 92a on the layer 91, a layer 92b on the layer 92a, and a layer 92c on the layer 92b. The layer 92a has a memory cell array 93A, the layer 92b has a memory cell array 93B, and the layer 92c has a memory cell array 93C.

[0078] In this way, by stacking a plurality of layers 92 each having a different memory cell array 93, a semiconductor device in which a plurality of types of memory cells are integrated can be realized.

[0079] A semiconductor device 85 shown in Fig. 1(E) and a semiconductor device 86 shown in Fig. 1(F) each have two layers, a layer 92 on a layer 91. Specifically, the semiconductor device 85 and the semiconductor device 86 each have a layer 91, a layer 92a on the layer 91, and a layer 92b on the layer 92a. In the semiconductor device 85, the layer 92a has a memory cell array 93A, and the layer 92b has a memory cell array 93B and a memory cell array 93C. In the semiconductor device 86, the layer 92a has the memory cell array 93A and the memory cell array 93B, and the layer 92b has the memory cell array 93C.

[0080] Note that the semiconductor device 83, the semiconductor device 85, and the semiconductor device 86 shown in FIG. 1(C), FIG. 1(E), and FIG. 1(F) can be stacked by various methods. For example, the layer 92a can be formed on the layer 91 by a monolithic stacking method, and the layer 92b can be formed on the layer 92a by a bonding method. Note that the present invention is not limited thereto, and the layers 91, 92a, and 92b may be formed by the same stacking method. Note that the above structure can also be applied to the semiconductor device 84 shown in FIG. 1(D). Specifically, the layers 91, 92a, 92b, and 92c may be formed by the same stacking method or different stacking methods.

[0081] In this manner, a semiconductor device in which a plurality of types of memory cells are combined can be realized by providing two or more types of memory cell arrays 93 in one layer 92 and stacking a plurality of layers 92 each having a different memory cell array 93. By applying the memory cell configuration of one embodiment of the present invention, it is expected that the power consumption can be reduced to 1 / 1000 of that of a conventional memory cell (e.g., a DRAM).

[0082] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0083] (Embodiment 2) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0084] A semiconductor device of one embodiment of the present invention includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers.

[0085] The oxide semiconductor layer functions as a semiconductor layer of a transistor, the first conductive layer functions as one of a source electrode or a drain electrode of the transistor, the third conductive layer functions as the other of the source electrode or the drain electrode of the transistor, and the fourth conductive layer functions as a first gate electrode of the transistor. The fourth insulating layer functions as a first gate insulating layer of the transistor. The second conductive layer functions as a second gate electrode, and the third insulating layer functions as a second gate insulating layer.

[0086] The first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer, and the third conductive layer is located on the second insulating layer, the first conductive layer has a first recess, and the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping the first recess. The third insulating layer contacts the first conductive layer and contacts at least a side surface of the first insulating layer, a side surface of the second conductive layer, and a side surface of the second insulating layer in the first opening. The oxide semiconductor layer contacts an upper surface of the third conductive layer and a bottom surface and a side surface of the first recess, and contacts the third insulating layer in the first opening. The fourth insulating layer is located inside the oxide semiconductor layer in the first opening. The fourth conductive layer is located inside the first opening and on the inner side of the fourth insulating layer.

[0087] In the transistor of one embodiment of the present invention, a first recess is provided in the first conductive layer. As a result, the height of the lower surface of the fourth insulating layer and the height of the lower surface of the fourth conductive layer in the first opening can be made lower than in a case where the first recess is not provided. As a result, a gate electric field can be easily applied to the oxide semiconductor layer, and the electrical characteristics of the transistor can be improved. Here, the height of each surface can be determined, for example, based on the surface on which the transistor is formed.

[0088] In addition, in a cross-sectional view, the oxide semiconductor layer included in the transistor of one embodiment of the present invention has a region that overlaps with the second conductive layer through the third insulating layer and overlaps with the fourth conductive layer through the fourth insulating layer. One of the second conductive layer and the fourth conductive layer functions as a gate, and the other functions as a backgate. The backgate of the transistor makes it easy to control the threshold voltage and can suppress fluctuation in the threshold voltage, thereby improving the electrical characteristics and reliability of the transistor.

[0089] Furthermore, if the parasitic capacitance generated between the source electrode or drain electrode and the gate wiring is large, the operation of the transistor may become slow, and the frequency characteristics of a circuit using the transistor may be degraded.

[0090] Therefore, the transistor of one embodiment of the present invention preferably has a structure in which parasitic capacitance between the third conductive layer and the fourth conductive layer is reduced. In this way, the transistor can operate at high speed. In addition, a semiconductor device with favorable electrical characteristics can be provided.

[0091] For example, the semiconductor device of one embodiment of the present invention preferably further includes a fifth insulating layer. In this case, it is preferable that the fourth insulating layer covers a top surface and a side surface of the oxide semiconductor layer over the second insulating layer, the fifth insulating layer is located over the fourth insulating layer and has a second opening at a position overlapping with the first opening, and the fourth conductive layer has a portion that overlaps with the oxide semiconductor layer in the first opening through the fourth insulating layer and a portion that is located in the second opening. Alternatively, it is preferable that the fifth insulating layer is located over the second insulating layer and covers a top surface and a side surface of the oxide semiconductor layer over the second insulating layer and has the second opening at a position that overlaps with the first opening, the fourth insulating layer has a portion that is located in the second opening, and the fourth conductive layer is located inside the fourth insulating layer in the second opening.

[0092] The fourth conductive layer has a portion that overlaps with the oxide semiconductor layer through the fourth insulating layer in the first opening, and a portion that is located in the second opening. In this case, the gate wiring is disposed on the fifth insulating layer, and the physical distance between the third conductive layer and the gate wiring can be increased. Therefore, the parasitic capacitance generated between the third conductive layer and the gate wiring can be reduced. Note that a part of the fourth conductive layer (a portion located on the fifth insulating layer) may function as the gate wiring, and the gate wiring may be provided on the fifth insulating layer separately from the fourth conductive layer.

[0093] Alternatively, the transistor of one embodiment of the present invention preferably has a structure in which parasitic capacitance between the third conductive layer and the gate wiring is reduced, thereby enabling the transistor to operate at high speed and providing a semiconductor device with favorable electrical characteristics.

[0094] For example, the semiconductor device of one embodiment of the present invention preferably includes a fifth conductive layer and a sixth insulating layer in addition to the oxide semiconductor layer, the first to fourth conductive layers, and the first to fourth insulating layers. In this case, it is preferable that the sixth insulating layer is located over the fourth insulating layer and has a second opening that reaches the fourth conductive layer at a position overlapping with the first opening, and the fifth conductive layer is in contact with the fourth conductive layer in the second opening.

[0095] The fifth conductive layer functions as a gate wiring. Since the fifth conductive layer is disposed on the sixth insulating layer, the physical distance between the third conductive layer and the gate wiring can be increased. Therefore, the parasitic capacitance generated between the third conductive layer and the gate wiring can be reduced.

[0096] Instead of the opening, a groove (slit) may be provided.

[0097] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a height (vertical) component, and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0098] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and thus the occupation area can be significantly reduced as compared with a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0099] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thicknesses of the first insulating layer, the second conductive layer, the second insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupying area and large on-state current can be realized.

[0100] When the channel length of a transistor is shortened, the transistor is likely to be normally on due to the so-called short channel effect (SCE). On the other hand, as described above, the transistor of one embodiment of the present invention has a back gate. Therefore, a normally off transistor can be easily realized by controlling the threshold voltage. That is, the transistor of one embodiment of the present invention has a high on-state current, is normally off, and has high reliability even when miniaturized.

[0101] In addition, since the off-state current of a transistor including an oxide semiconductor is small, when the transistor is used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or is performed very infrequently, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, the memory device can be highly integrated and has low power consumption.

[0102] <Configuration Example 1 of Semiconductor Device> The structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0103] [Transistor 200] FIG. 2(A1) is a plan view of a semiconductor device having a transistor 200. FIG. 2(A2) is a plan view showing an example of arranging a plurality of transistors 200. FIG. 2(B) and FIG. 3 are cross-sectional views taken along dashed lines A1-A2 in FIG. 2(A), respectively. FIG. 3 corresponds to an example of an enlarged view of FIG. 2(B), and shows a configuration example of each layer in more detail. FIG. 2(C) is a cross-sectional view taken along dashed lines A3-A4 in FIG. 2(A). FIG. 2(D) is a cross-sectional view taken along dashed lines A5-A6 in FIG. 2(B) and FIG. 2(C). FIG. 2(D) can also be said to be a cross-sectional view of an XY plane including an insulating layer 280a. FIG. 2(E) is a cross-sectional view taken along dashed lines A7-A8 in FIG. 2(B) and FIG. 2(C). FIG. 2(E) can also be said to be a cross-sectional view of an XY plane including a conductive layer 255. In the plan view of Figure 2(A1), some elements are omitted for clarity, and some elements may also be omitted in the plan views that follow.

[0104] 2A1, 2B to 2E, and 3 include an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, and an insulating layer 280b over the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0105] The transistor 200 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 255 on the insulating layer 280a, a conductive layer 240a on the insulating layer 280b, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, a conductive layer 265a on the insulating layer 250, and a conductive layer 265b on the conductive layer 265a.

[0106] In the following, the conductive layer 220a and the conductive layer 220b may be collectively referred to as the conductive layer 220. Moreover, the conductive layer 240a and the conductive layer 240b may be collectively referred to as the conductive layer 240. Moreover, the conductive layer 265a and the conductive layer 265b may be collectively referred to as the conductive layer 265.

[0107] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 265 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 235 functions as a second gate insulating layer. The conductive layer 265 also functions as a gate wiring. As shown in FIG. 2(A2), the conductive layer 240 and the conductive layer 255 can also function as wirings.

[0108] It is preferable that the conductive layer 265 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode. In this case, the insulating layer 250 functions as a gate insulating layer and the insulating layer 235 functions as a back gate insulating layer. Note that the conductive layer 265 may function as a back gate electrode and the conductive layer 255 may function as a gate electrode.

[0109] The oxide semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and with the conductive layer 265a with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200. One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0110] As shown in FIGS. 2B and 2C, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0111] The conductive layer 220 has a conductive layer 220a and a conductive layer 220b on the conductive layer 220a, and a recess is provided in the conductive layer 220b. In other words, the conductive layer 220 has a recess, the bottom surface of which corresponds to the bottom surface of the recess in the conductive layer 220b, and the side surface of which corresponds to the side surface of the recess in the conductive layer 220b. Specifically, the conductive layer 220b has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. When the opening 290 is formed, the second recess is provided in the conductive layer 220b, and then, when the insulating layer 235 is processed, the first recess is provided in the conductive layer 220b. 2(B) and the like, the side surface of the first recess is aligned with the surface of the insulating layer 235 facing the oxide semiconductor layer 230, and the side surface of the second recess is aligned with the side surface of the insulating layer 280a and the like facing the opening 290. Hereinafter, the first recess and the second recess may be collectively referred to as the recess.

[0112] The opening 290 overlaps with the recess of the conductive layer 220b. Here, the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220b, and the sidewall of the opening 290 includes the side surface of the recess of the conductive layer 220b, the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0113] The opening 290 includes an opening in the insulating layer 280a, an opening in the conductive layer 255, an opening in the insulating layer 280b, an opening in the conductive layer 240a, and an opening in the conductive layer 240b. In other words, an opening in a region where the insulating layer 280a overlaps with the conductive layer 220a is a part of the opening 290, an opening in a region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening 290, an opening in a region where the insulating layer 280b overlaps with the conductive layer 220a is a part of the opening 290, an opening in a region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290, and an opening in a region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290. The shape and size of the opening 290 in a plan view may differ depending on each layer. When the upper surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0114] At least some of the components of the transistor 200 are disposed in the opening 290. Specifically, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265 are disposed such that at least some of them are located in the opening 290.

[0115] The insulating layer 235 has at least a region located between the oxide semiconductor layer 230 and the conductive layer 255. The oxide semiconductor layer 230 contacts the insulating layer 235 in the opening 290.

[0116] 2B and the like, the insulating layer 235 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, and also contacts the side surfaces of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b in the opening 290. The oxide semiconductor layer 230 contacts the bottom and side surfaces of the recess (specifically, the first recess) of the conductive layer 220, the insulating layer 235, and the upper surface of the conductive layer 240b. The insulating layer 250 is located inside the oxide semiconductor layer 230 in the opening 290, and the conductive layer 265a is located inside the insulating layer 250 in the opening 290.

[0117] The insulating layer 235 is provided along at least a part of the sidewall of the opening 290. Moreover, the portions of the oxide semiconductor layer 230 and the insulating layer 250 arranged in the opening 290 are provided so as to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom and the sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. Then, the conductive layer 265a is provided so as to fill at least a part of the recess of the insulating layer 250 reflecting the shape of the opening 290.

[0118] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 290. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 265 in the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller. FIGS. 2B and 2C show an example in which the conductive layer 265 has a two-layer structure, in which only the conductive layer 265a is provided in the opening 290, and the conductive layer 265b over the conductive layer 265a is provided so as to overlap with the opening 290. Note that both the conductive layer 265a and the conductive layer 265b may be located in the opening 290 depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like.

[0119] By providing a recess at a position where the conductive layer 220b overlaps with the opening 290, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 265a in the opening 290 can be made lower than the height of the upper surface of the conductive layer 220b in contact with the insulating layer 280a, with the upper surface of the insulating layer 210 as a reference, as compared to a case where the conductive layer 220b does not have the recess. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 210 is used as a reference. The surface used as a reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which the transistor or semiconductor device is provided may be used as a reference.

[0120] 3, the shortest distance Tc from the upper surface of the insulating layer 210 to the upper surface of the conductive layer 220b that contacts the insulating layer 280a is preferably longer than the shortest distance Ta from the upper surface of the insulating layer 210 to the lower surface of the insulating layer 250. This makes it possible to increase the contact area between the side surface of the conductive layer 220b and the oxide semiconductor layer 230, and to reduce the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. Therefore, it is possible to suppress a decrease in the on-current of the transistor 200 caused by the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. The shortest distance Ta can be determined based on the lower surface of the insulating layer 250 in the opening 290.

[0121] 3, the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the upper surface of the insulating layer 210 to the lower surface of the conductive layer 265a, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, and improves the electrical characteristics of the transistor 200. Furthermore, the gate electric field is also easier to apply to the region of the oxide semiconductor layer 230 that is in contact with the conductive layer 220b, and therefore the on-current of the transistor 200 can be increased. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved. Note that the shortest distance Tb can be determined based on the lower surface of the conductive layer 265a in the opening 290.

[0122] The oxide semiconductor layer 230 contacts the bottom and side surfaces of the recesses of the conductive layer 220b and the upper surface of the conductive layer 240b. The conductive layer 220b has a recess, so that the area of ​​contact between the oxide semiconductor layer 230 and the conductive layer 220b can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced.

[0123] A conductive material containing oxygen is preferably used for the conductive layer 220b, which can reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b.

[0124] When the conductive layer 220 and the conductive layer 240 have a stacked structure, it is preferable to use a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, because this can reduce contact resistance with the oxide semiconductor layer 230. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240b, for example.

[0125] Alternatively, when the conductive layer 220 and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is used for a layer in the stacked structure that is closest to a channel formation region, and the contact resistance with the oxide semiconductor layer 230 can be reduced, thereby shortening the current path between the source and drain, thereby increasing the on-state current of the transistor. For this reason, it is preferable to use a conductive material containing oxygen for the conductive layer 220b and the conductive layer 240a, for example.

[0126] As the conductive material containing oxygen, it is preferable to use a metal oxide having conductivity (also called an oxide conductor).

[0127] FIG. 2B illustrates a structure in which the end of the conductive layer 240a, the end of the conductive layer 240b, and the end of the oxide semiconductor layer 230 are aligned outside the opening 290. As in a manufacturing method example described later, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure in which any of the end of the oxide semiconductor layer 230, the end of the conductive layer 240a, and the end of the conductive layer 240b is located inside or outside the others in the X direction or Y direction may be used.

[0128] The conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. In addition, it is preferable that the conductive layer 240 is not located inside the opening 290 of the insulating layer 280b, etc. In other words, it is preferable that the conductive layer 240 does not have a region in contact with the side surface of the insulating layer 280b in the opening 290. With this configuration, the opening 290 can be formed in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a at once. In addition, when the side surface of the conductive layer 240, the side surface of the insulating layer 280b, the side surface of the conductive layer 255, and the side surface of the insulating layer 280a are aligned in the opening 290, the film thickness distribution of the insulating layer 235, the oxide semiconductor layer 230, etc. provided inside the opening 290 can be made uniform. In addition, it is possible to suppress the insulating layer 235, the oxide semiconductor layer 230, etc. from being divided by a step between the conductive layer 240 and the insulating layer 280b, etc.

[0129] 2B and 2C show a configuration in which the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 are flush (aligned, or approximately aligned), but the present invention is not limited thereto. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280b in the opening 290 may be discontinuous. Also, the inclination of the side surface of the conductive layer 240 in the opening 290 and the inclination of the side surface of the insulating layer 280b in the opening 290 may be different from each other. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side surface of the insulating layer 280b in the opening 290. With such a configuration, the coverage of the oxide semiconductor layer 230 on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when insulating layer 280a and insulating layer 280b each have a multilayer structure, the inclination of the side surface of each layer may be different within opening 290. Similarly, when conductive layer 240 has a multilayer structure, the inclination of the side surface of each layer within opening 290 may be different.

[0130] The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0131] OS transistors have oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. In addition, hydrogen near the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0132] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the region has a high carrier concentration and low resistance due to a high concentration of H or impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions of the OS transistor are preferably n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0133] As described above, the oxide semiconductor layer 230 is provided inside the opening 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located above, so that a current flows in the vertical direction. That is, a channel is formed along the side surface of the opening 290.

[0134] The positional relationship of each layer in the opening 290 will be described with reference to FIG. 2(D) and FIG. 2(E). The insulating layer 235 is in contact with the outer surface of the oxide semiconductor layer 230. The conductive layer 255 surrounds the entire outer periphery of the oxide semiconductor layer 230 via the insulating layer 235. The insulating layer 250 is in contact with the outer surface of the conductive layer 265a. The oxide semiconductor layer 230 surrounds the entire outer periphery of the conductive layer 265a via the insulating layer 250. Thus, the channel formation region of the transistor 200 can be formed on the entire outer surface of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 235). Note that FIG. 2(E) can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0135] The channel length of the transistor 200 can be considered as the distance between the source region and the drain region, that is, the channel length of the transistor 200 can be said to be determined by the thicknesses of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, etc. on the conductive layer 220.

[0136] Since the transistor 200 includes the conductive layer 255 functioning as a back gate, the threshold voltage of the transistor 200 can be controlled by a potential applied to the conductive layer 255. At this time, a portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween is most susceptible to the influence of the conductive layer 255. Thus, in FIG. 3, the oxide semiconductor layer 230 is divided into three regions, a region 230n+, a region 230n-, and a region 230i. The region 230i corresponds to a portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween.

[0137] The region 230n+ is formed in a region in contact with the conductive layer 240b or the conductive layer 220b and in the vicinity thereof in the oxide semiconductor layer 230, and can be called a source region or a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0138] The region 230i is a region in the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 interposed therebetween and overlaps with the conductive layer 265a with the insulating layer 250 interposed therebetween, and can be referred to as a channel formation region. The channel formation region is preferably controlled to be i-type (intrinsic) or substantially i-type by a potential applied to the conductive layer 255.

[0139] The region 230n- is preferably a region having a higher resistance than the region 230n+ and a lower resistance than the region 230i. If there is a high resistance region between the region 230i and the region 230n+, the on-current of the transistor 200 may decrease. By making the region 230n- a relatively low resistance region, the on-current of the transistor 200 may be increased. Note that the region 230n- may also function as a channel formation region.

[0140] As described above, when the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be regarded as the length L1. On the other hand, since the region 230n- is a region with a lower resistance than the region 230i, the channel formation region of the transistor 200 can also be regarded as the region 230i that is controlled by the conductive layer 255 to become a high resistance region. In this case, the channel length of the transistor 200 can be regarded as the length L0 of the region 230i, which is shorter than the length L1. In this case, the length L0 can also be regarded as the effective channel length of the transistor 200.

[0141] When the resistance of the region 230n- is low and the effective channel length of the transistor is short, the transistor is likely to be normally on. On the other hand, the transistor of one embodiment of the present invention has a backgate. By supplying a potential equal to or lower than the source potential or a potential equal to or lower than 0 V (preferably a negative potential) to the backgate, the threshold voltage of the transistor can be shifted in the positive direction and the transistor can be normally off. As a result, the transistor of one embodiment of the present invention can have both a large on-current and a normally off state.

[0142] Note that in the transistor of one embodiment of the present invention, either the conductive layer 255 or the conductive layer 265 may be used as a gate, and either may be used as a back gate. In particular, the transistor of one embodiment of the present invention may have a structure in which the conductive layer 265 is used as a gate and the conductive layer 255 is used as a back gate. When the conductive layer 265, which has a larger region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate, a gate electric field can be applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor.

[0143] In a planar transistor, the channel length is set by the exposure limit of photolithography, but in one embodiment of the present invention, the channel length can be set by the film thicknesses of the insulating layers 280a and 280b. Thus, the channel length of the transistor 200 can be made to have an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, and improves the frequency characteristics.

[0144] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. As a result, the area occupied by the transistor 200 can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Thus, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.

[0145] FIG. 2A2 shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 2A2 shows an example in which 5×5 transistors are arranged in the X and Y directions. As shown in FIG. 2A2, the transistor 200 is provided at an intersection of a conductive layer 265 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 2A2, the diameter of the opening 290 can be smaller than each of the widths of the short sides of the conductive layer 240, the widths of the short sides of the conductive layer 255, and the widths of the short sides of the conductive layer 265. In this way, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0146] As shown in FIG. 2D, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. Thus, a side surface of the conductive layer 265a provided at the center faces a side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, the entire circumference of the oxide semiconductor layer 230 becomes a channel formation region in a plan view. In this case, for example, the channel width of the transistor 200 is determined by the outer periphery of the oxide semiconductor layer 230. That is, it can be said that the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view). In FIGS. 2B to 2E, the width D of the opening 290 is shown, and in FIG. 2E, the channel width W of the transistor 200 is shown. By increasing the width D of the opening 290, the channel width per unit area can be increased, and the on-current can be increased.

[0147] The width D of the opening 290 may vary in the depth direction. Here, in particular, the shortest distance between two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum value of the width of the opening 290 in the conductive layer 255 is used as the width D of the opening 290. Also, the width of the opening 290 at the highest position in the conductive layer 255, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 255, but the method of determining the width D is not particularly limited. For example, the shortest distance between two side surfaces on the opening 290 side of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b can be used as the width D. In addition, the width of opening 290 at the highest position in insulating layer 280a, insulating layer 280b, conductive layer 240a, or conductive layer 240b, the width of opening 290 at the lowest position, the width of opening 290 at the midpoint between these, or the average of these three widths may be used as width D.

[0148] When the opening 290 is formed by using a photolithography method, the width D of the opening 290 is set by the exposure limit of the photolithography. The width D of the opening 290 is set by the film thickness of each of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0149] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0150] As described above, by forming the opening 290 to have a circular shape in a plan view, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230 and the distance between the conductive layer 265a and the oxide semiconductor layer 230 are approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0151] In the present embodiment, the opening 290 is circular in plan view, but the present invention is not limited to this. In plan view, the opening 290 may be, for example, a circle, an ellipse, or other nearly circular shape, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or other polygon with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 2(A1) and the like, the opening 290 is preferably circular in plan view. By making the opening circular, the processing accuracy when forming the opening can be improved, and an opening of a fine size can be formed. In this specification and the like, the circle is not limited to a perfect circle.

[0152] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. FIGS. 2B and 2C show an example in which the conductive layer 220a has a single-layer structure. FIG. 3 shows an example in which the conductive layer 220a has a stacked-layer structure.

[0153] [Oxide semiconductor layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0154] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0155] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a large band gap, the off-current of a transistor can be reduced. Since the off-current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0156] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, the description in Embodiment 3 can be referred to. Detailed description thereof is omitted here.

[0157] In addition, the semiconductor device of this embodiment may be applied to a transistor using another semiconductor material in the channel formation region. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor. Examples of the semiconductor made of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include an organic semiconductor and a nitride semiconductor. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may include impurities as dopants.

[0158] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0159] The semiconductor layer of the transistor may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0160] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to group 16). Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively, MoS 2 ), molybdenum selenide (represented by MoSe2 ), molybdenum tellurium (represented by MoTe 2 ), tungsten sulfide (represented by WS 2 ), tungsten selenide (represented by WSe 2 ), tungsten tellurium (represented by WTe 2 ), hafnium sulfide (represented by HfS 2 ), hafnium selenide (represented by HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (represented by ZrSe 2 ) etc.

[0161] [Insulation layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 235, insulating layer 280a, insulating layer 280b, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for the insulating layer of the semiconductor device.

[0162] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the gate insulating layer, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also becomes possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0163] Examples of materials having a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0164] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with a low relative dielectric constant include silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and silicon oxide to which carbon and nitrogen are added. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0165] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0166] In addition, examples of materials that can have ferroelectricity include metal nitrides having elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. In addition, metal oxides having elements M1 and nitrogen may have ferroelectricity even if they do not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0167] In addition, materials that can have ferroelectricity include SrTaO 2 N, BaTaO 2 Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure 3 etc.

[0168] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0169] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0170] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0171] In this specification, a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0172] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0173] In addition, by adding a Group 3 element (also called IIIa element) in the periodic table to an oxide having one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, and crystals having an orthorhombic crystal structure are easily formed. This is preferable because the proportion of crystals having an orthorhombic crystal structure increases, and the remanent polarization amount can be increased. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide decreases, and ferroelectricity may not be easily expressed. Therefore, the content of the Group 3 element in the oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0174] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the permeation of impurities and oxygen. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for the insulating layer having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0175] Specifically, examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0176] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of an insulating layer that is likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0177] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0178] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0179] In addition, a barrier insulating layer against hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0180] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0181] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atom, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.

[0182] For example, it is preferable to use a silicon nitride film as the insulating layer 210.

[0183] The insulating layer 280a and the insulating layer 280b each preferably have the above-mentioned barrier insulating layer against hydrogen. The insulating layer 280a and the insulating layer 280b are provided so as to surround the oxide semiconductor layer 230. The insulating layer 280a and the insulating layer 280b provided on the outer side of the oxide semiconductor layer 230 have a barrier property against hydrogen, and thus can suppress diffusion of hydrogen into the oxide semiconductor layer 230. For example, the insulating layer 280a and the insulating layer 280b each preferably have one or both of an aluminum oxide film and a silicon nitride film.

[0184] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280a and the insulating layer 280b, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, and an excessive amount of oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230.

[0185] Furthermore, the use of silicon nitride for the insulating layers 280a and 280b can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Thus, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, which can improve the reliability of the transistor 200.

[0186] The insulating layers 280a and 280b each preferably include the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0187] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an atmosphere containing oxygen. In addition, by using a sputtering method in which molecules containing hydrogen are not required for the deposition gas, the hydrogen concentrations in the insulating layers 280a and 280b can be reduced. By depositing at least some of the layers constituting the insulating layers 280a and 280b in this manner, oxygen can be supplied from the insulating layers 280a and 280b to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0188] The concentrations of impurities such as water and hydrogen in the insulating layers 280a and 280b are preferably reduced, so that entry of impurities such as water and hydrogen into a channel formation region of the oxide semiconductor layer 230 can be suppressed.

[0189] Note that the thicknesses of the insulating layers 280a and 280b on the conductive layer 220 affect the channel length of the transistor 200, so the thicknesses of the insulating layers 280a and 280b are set appropriately according to the design value of the channel length of the transistor 200.

[0190] For example, it is preferable to use a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 280a and the insulating layer 280b, respectively. Alternatively, it is preferable to use a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 280a and the insulating layer 280b, respectively. For example, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order as the insulating layer 280a and the insulating layer 280b, respectively.

[0191] The insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0192] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium. Here, in metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, so that they have a high ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, the amorphous structure may be realized by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.

[0193] The function of capturing or fixing a corresponding substance can also be said to have a property that makes it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.

[0194] In the case where the gate insulating layer has a stacked structure, a layer in contact with the oxide semiconductor layer 230 preferably has a function of trapping and fixing hydrogen. This makes it possible to more effectively trap or fix hydrogen contained in the oxide semiconductor layer 230. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For example, hafnium silicate or the like is preferably used as the layer of the insulating layer 250 in contact with the oxide semiconductor layer 230. In addition, the layer preferably has an amorphous structure.

[0195] By making the layer have an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 250 uniform, and it is possible to reduce portions with an extremely thin film thickness, thereby improving the withstand voltage of the insulating layer 250. In addition, it is possible to make the film thickness distribution of the film provided on the insulating layer 250 uniform.

[0196] Moreover, by suppressing the formation of grain boundaries in the layer, leakage current caused by defect levels in the grain boundaries can be reduced, and the insulating layer 250 can function as an insulating film with low leakage current.

[0197] In addition, hafnium oxide is a high dielectric constant (high-k) material, so hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0198] In view of the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0199] In addition, it is preferable to use the above-mentioned barrier insulating layer against hydrogen as the insulating layer 250. By using a barrier insulating layer against hydrogen for the insulating layer 250, it is possible to suppress diffusion of impurities contained in the conductive layer 265 into the oxide semiconductor layer 230. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Furthermore, the insulating layer 250 may have an insulating layer having a structure that is stable against heat, such as silicon oxide or silicon oxynitride.

[0200] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0201] Additionally, insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0202] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0203] The insulating layer 250 preferably has a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 265, and the like. When the insulating layer 250 has a stacked structure, a layer in contact with the conductive layer 240 or the conductive layer 265 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 250, a layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 are preferably barrier insulating layers against oxygen.

[0204] The use of a barrier insulating layer against hydrogen and oxygen for a layer of the insulating layer 250 in contact with the conductive layer 265 can suppress oxidation of the conductive layer 265. In addition, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 265 and causing oxygen vacancies in the oxide semiconductor layer 230.

[0205] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0206] The layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280b. The layer has a barrier property against oxygen, which can prevent the side surface of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0207] Moreover, each layer constituting the insulating layer 250 is preferably a thin film. For example, the insulating layer 250 has a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, so that the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage being constant in the subthreshold region.

[0208] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Each layer constituting the insulating layer 250 may have a region with the above thickness at least in a part thereof.

[0209] In addition, the insulating layer 250 preferably has a three-layer structure in which a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side. Silicon oxide or silicon oxynitride is preferably used as the material with a low relative dielectric constant of the first insulating layer. The first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using an oxide for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230. In addition, by providing the third insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 265, and oxidation of the conductive layer 265 can be prevented. In addition, a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230 can be prevented.

[0210] The insulating layer 250 preferably has a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer made of a material with a low dielectric constant, a second insulating layer having a function of trapping or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side. The first to third insulating layers can have a similar structure to that of the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, which can suppress desorption of oxygen from the oxide semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Since aluminum oxide has a function of trapping or fixing hydrogen, it is suitable for the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side is preferably used.

[0211] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0212] In addition, it is preferable to use a three-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the oxide semiconductor layer 230 side, as the insulating layer 250. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0213] The silicon oxide film of the insulating layer 250 is preferably formed by the PEALD method. The thickness of the silicon oxide film of the insulating layer 250 is preferably 0.7 nm to 3 nm. The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin film formation is possible; film formation is possible on a structure with a high aspect ratio or a surface with a large step; film formation is possible with few defects such as pinholes; film formation is possible with excellent coverage; and film formation is possible at low temperatures. Thus, by using the ALD method, in the transistor of one embodiment of the present invention, the coverage of the insulating layer 250 on the sidewall and bottom surface of the opening 290 can be improved, and the insulating layer 250 with a uniform thickness can be formed. Furthermore, the PEALD method can form a film at a lower temperature by using plasma. Furthermore, by using plasma, the film formation rate can be increased, and productivity can be improved.

[0214] The insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 of two or more types of films, it is possible to impart a plurality of functions to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230. In addition, it is preferable to use the ALD process two or more times in forming the insulating layer 250. For example, the insulating layer 250 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and uniformity of the film thickness of the insulating layer 250. In addition, it is possible to improve productivity by continuously forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0215] Note that the insulating layer 210 may be an insulating layer having a function of trapping or fixing hydrogen. This allows hydrogen in the oxide semiconductor layer 230 to diffuse into the insulating layer 210 through the conductive layers 220a and 220b, and the hydrogen can be trapped or fixed. This allows the hydrogen concentration in the oxide semiconductor layer 230 to be reduced. For example, the insulating layer 210 may have a two-layer structure of a silicon nitride film and a hafnium silicate film over the silicon nitride film.

[0216] The insulating layer 235 may also be referred to as a sidewall, a sidewall insulating layer, or a sidewall protective layer.

[0217] The insulating layer 235 preferably includes an insulating layer having a region containing oxygen that is released by heating, which allows oxygen to be supplied from the insulating layer 235 to the oxide semiconductor layer 230. For example, the insulating layer 235 is preferably made of silicon oxide or silicon oxynitride.

[0218] The insulating layer 235 preferably includes a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, the insulating layer 235 is preferably made of aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide.

[0219] The silicon nitride film of the insulating layer 235 is preferably formed by using the PEALD method, which can improve the coverage of the insulating layer 235 on the sidewall of the opening 290 and form the insulating layer 235 with a uniform thickness.

[0220] Moreover, the insulating layer 235 may be made of the above-mentioned material that may have ferroelectric properties.

[0221] For example, the insulating layer 235 may have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film and a silicon nitride film. In the case of a two-layer structure of a silicon oxide film and a silicon nitride film, it is preferable to provide a silicon oxide film on the oxide semiconductor layer 230 side and a silicon nitride film on the conductive layer 255 side. This makes it possible to efficiently supply oxygen to the oxide semiconductor layer 230 and to suppress the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230. Alternatively, a silicon nitride film may be provided on the oxide semiconductor layer 230 side and a silicon oxide film may be provided on the conductive layer 255 side.

[0222] [Conductive layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 255, conductive layer 265, etc.) of the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0223] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0224] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high electrical conductivity.

[0225] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0226] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0227] Since the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0228] By using a conductive material containing oxygen as the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, IZO (registered trademark), or the like.

[0229] FIG. 3 shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. In this case, it is preferable to use, for example, a conductive material that is not easily oxidized or a conductive material having a function of suppressing the diffusion of oxygen as the conductive layer 220a1, a material with high conductivity as the conductive layer 220a2, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220b. Specifically, it is preferable to use, for example, titanium nitride as the conductive layer 220a1, tungsten as the conductive layer 220a2, and an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 220b. In this case, titanium nitride contacts the insulating layer 210, and the oxide conductor contacts the oxide semiconductor layer 230. In addition, an oxide conductor is used in the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, an oxide conductor has a lower contact resistance with the oxide semiconductor layer 230, and therefore the current path between the source and drain can be shortened, and the on-current of the transistor can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 210, the conductive layer 220 can be prevented from being excessively oxidized by the insulating layer 210. When a metal material (here, tungsten) having a higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0230] 3 shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen as the conductive layer 240b and a material having a higher conductivity than the conductive layer 240b as the conductive layer 240a. Specifically, for example, it is preferable to use an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 240b and tungsten as the conductive layer 240a. Also, ruthenium, titanium nitride, tantalum nitride, or the like may be used as the conductive layer 240a.

[0231] Of the conductive layer 240, the layer that is mainly in contact with the oxide semiconductor layer 230 is the conductive layer 240b. By using an oxide conductor for the conductive layer 240b, the contact resistance with the oxide semiconductor layer 230 can be reduced, which is preferable. In addition, by using a material having a higher conductivity than an oxide conductor for the layer constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased, which is preferable.

[0232] Note that the conductive layer 240a may be formed using a conductive material containing oxygen, and the conductive layer 240b may be formed using a material having higher conductivity than that of the conductive layer 240a. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Thus, the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.

[0233] The conductive layer 255 and the conductive layer 265 are preferably made of a material having high conductivity, such as tungsten. In addition, the conductive layer 255 and the conductive layer 265 are preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen. As described above, examples of the conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255 and the conductive layer 265.

[0234] In addition, the conductive layer 265 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. In addition, the conductive material containing the above-mentioned metal element and nitrogen (for example, titanium nitride, tantalum nitride, etc.) may be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Or, hydrogen mixed in from an outer insulating layer may be captured.

[0235] 3 shows an example in which the conductive layer 265 has a two-layer structure including a conductive layer 265a and a conductive layer 265b over the conductive layer 265a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 265a and tungsten as the conductive layer 265b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 265a and copper as the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0236] The conductive layer 265 may have a stacked structure of three or more layers. For example, the conductive layer 265 may have a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0237] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0238] The conductive layer 255 is preferably made of, for example, tungsten or tantalum nitride.

[0239] [substrate] As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available. Furthermore, there is a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, etc. are available. As the conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. are available. Furthermore, there is a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or insulator is provided on a conductive substrate, etc. are available. Alternatively, these substrates on which elements are provided may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0240] <Configuration Example 2 of Semiconductor Device> The structure of a semiconductor device according to another embodiment of the present invention will be described with reference to FIGS.

[0241] [Transistor 200A] FIG. 4A is a cross-sectional view of a semiconductor device including a transistor 200A.

[0242] FIG. 4A shows an example in which the sidewall of the opening 290 is tapered. By tapering the sidewall of the opening 290, the coverage of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle θ280 of the side surface of the insulating layer 280a in the opening 290 is preferably 45 degrees or more and less than 90 degrees. Specifically, as described above, a taper angle θ280 of 80 degrees or more and less than 90 degrees is preferable because it allows miniaturization or high integration of the semiconductor device. In addition, a taper angle θ280 of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable because it improves the coverage of the film formed in the opening 290.

[0243] Alternatively, for example, the sidewall of the opening 290 may have an inverse tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280a in the opening 290 may be greater than 90 degrees.

[0244] [Transistors 200B, 200C, 200D] Fig. 4B is a cross-sectional view of a semiconductor device including a transistor 200B, Fig. 5A is a cross-sectional view of a semiconductor device including a transistor 200C, and Fig. 5B is a cross-sectional view of a semiconductor device including a transistor 200D.

[0245] The transistors 200B, 200C, and 200D differ from the transistor 200 mainly in that the insulating layer 235 has a two-layer structure and that each of the transistors 200B, 200C, and 200D has an insulating layer 280c and an insulating layer 280d.

[0246] The transistors 200B, 200C, and 200D each include an insulating layer 235a and an insulating layer 235b over the insulating layer 235a. The insulating layer 235a and the insulating layer 235b function as second gate insulating layers of the transistors.

[0247] One of the insulating layer 235a and the insulating layer 235b preferably has an insulating layer having a region containing oxygen that is desorbed by heating. The other of the insulating layer 235a and the insulating layer 235b preferably has a barrier insulating layer against hydrogen.

[0248] This allows oxygen to be supplied from the insulating layer 235a or the insulating layer 235b to the oxide semiconductor layer 230, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0249] For example, it is preferable that one of the insulating layer 235a and the insulating layer 235b is an oxide insulating layer and the other is a nitride insulating layer. Specifically, it is preferable that a silicon nitride film is used for the insulating layer 235a and a silicon oxide film is used for the insulating layer 235b. Alternatively, it is preferable that a silicon oxide film is used for the insulating layer 235a and a silicon nitride film is used for the insulating layer 235b.

[0250] The insulating layer 235 preferably includes a silicon oxide film having a thickness of more than 0 nm and not more than 5 nm. The insulating layer 235 preferably includes a silicon nitride film having a thickness of more than 0 nm and not more than 5 nm. The silicon oxide film and the silicon nitride film are preferably formed by a PEALD method. With such a structure, a gate leakage current from the conductive layer 255 can be prevented in the transistor 200B. The insulating layer 235 includes a silicon nitride film, so that the insulating layer 235 can have a function of blocking hydrogen.

[0251] In the transistor 200B, the insulating layer 235a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 220b, and the insulating layer 235b is provided over the insulating layer 235a. For example, an insulating film to be the insulating layer 235a and an insulating film to be the insulating layer 235b are stacked, and then the two insulating films are processed to form the insulating layer 235a and the insulating layer 235b having the structure shown in FIG. 4B. Therefore, it can be said that this structure can be manufactured relatively easily.

[0252] Transistor 200C shows an example in which insulating layer 235a is provided in contact with the bottom and side surfaces of the recess in conductive layer 220b, and insulating layer 235b is located inside insulating layer 235a within the opening and in contact with the bottom of the recess in conductive layer 220b.

[0253] In the transistor 200D, the conductive layer 220b has a first recess, a second recess located outside the first recess, and a third recess located outside the second recess. The first recess is deeper than the second recess, and the second recess is deeper than the third recess. When forming the opening 290, the third recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235a, the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235b, the first recess is provided in the conductive layer 220b. Therefore, in FIG. 5(B), the side of the first recess is aligned with the surface of insulating layer 235b facing the oxide semiconductor layer 230, the side of the second recess is aligned with the surface of insulating layer 235a facing the insulating layer 235b, and the side of the third recess is aligned with the surface of insulating layer 280a, etc. facing the opening 290.

[0254] Transistor 200D illustrates an example in which insulating layer 235a is provided in contact with the bottom and side surfaces of the third recess of conductive layer 220b, and insulating layer 235b is provided in contact with the bottom and side surfaces of the second recess of conductive layer 220b.

[0255] For example, after the insulating layer 235a is provided on the sidewall of the opening, an insulating film to be the insulating layer 235b is formed and processed, so that the insulating layer 235a and the insulating layer 235b having the structure shown in Fig. 5A or 5B can be formed. Compared to the transistor 200B, the region where the insulating layer 235a is in contact with the oxide semiconductor layer 230 is reduced, and a configuration in which the insulating layer 235b is in contact with the oxide semiconductor layer 230 can be realized.

[0256] In the transistors 200B, 200C, and 200D, the insulating layers 280a and 280b are closer to the channel formation region of the oxide semiconductor layer 230 than the insulating layers 280c and 280d. By using an insulating layer containing oxygen for the insulating layers 280a and 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0257] Each of the insulating layers 280a and 280b preferably has a region with a higher oxygen content than at least one of the insulating layers 280c and 280d. By increasing the oxygen content of the insulating layers 280a and 280b, an i-type region can be easily formed in the oxide semiconductor layer 230.

[0258] It is more preferable to use a film that releases oxygen when heated for each of the insulating layers 280a and 280b. When the insulating layers 280a and 280b release oxygen due to heat applied during the manufacturing process of the transistor, oxygen can be supplied to the oxide semiconductor layer 230. When oxygen is supplied from the insulating layers 280a and 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V in the oxide semiconductor layer 230 can be reduced. O H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0259] In order to improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0260] In particular, when the channel length of a transistor is short, oxygen vacancies in the channel formation region and V O The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by optimizing the amount of oxygen supplied to the oxide semiconductor layer 230 after sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230, a transistor with a short channel length, excellent electrical characteristics, and high reliability can be realized.

[0261] The insulating layer 280a and the insulating layer 280b are preferably formed by a deposition method such as a sputtering method or a plasma enhanced CVD (PECVD) method. In particular, when a sputtering method is used, hydrogen is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the oxide semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor can be stabilized.

[0262] In order to increase the amount of oxygen supplied to the oxide semiconductor layer 230, for example, after the insulating layer 280a or the insulating layer 280b is formed, heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, oxygen may be supplied by forming an oxide film on an upper surface of the insulating layer 280a or the insulating layer 280b by a sputtering method in an oxygen atmosphere. Then, the oxide film may be removed. By performing such treatment, oxygen can be supplied to the insulating layer 280a or the insulating layer 280b, and the amount of oxygen supplied to the oxide semiconductor layer 230 can be increased.

[0263] An insulating layer suitable for the insulating layer 280a and the insulating layer 280b is preferably used for the insulating layer 235 (particularly the insulating layer 235b in contact with the oxide semiconductor layer 230). This enables oxygen to be supplied to the oxide semiconductor layer 230 more efficiently.

[0264] In addition, it is preferable to use a material with a low relative dielectric constant for the insulating layer 280a and the insulating layer 280b. This can reduce the parasitic capacitance generated between the wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 280a and the insulating layer 280b.

[0265] It is preferable to use a barrier insulating layer against oxygen for each of the insulating layers 280c and 280d, which can suppress oxidation of the conductive layers 220 and 240 and prevent the resistance from increasing.

[0266] The insulating layers 280c and 280d may each be a barrier insulating layer against hydrogen. Such a structure is preferable because it can prevent impurities such as hydrogen from diffusing into the oxide semiconductor layer 230.

[0267] In the transistors 200B, 200C, and 200D, it is preferable that the insulating layers 280a and 280b be formed using silicon oxide films, and the insulating layers 280c and 280d be formed using silicon nitride films or aluminum oxide films.

[0268] [Transistor 200E] FIG. 6A is a cross-sectional view of a semiconductor device having a transistor 200E.

[0269] Transistor 200E differs from transistor 200 primarily in that conductive layer 220b includes only one recess.

[0270] A recess may be formed in the conductive layer 220b in one or both of the steps of forming the opening 290 and the step of forming the insulating layer 235. The transistor 200 shows an example in which a recess is formed in the conductive layer 220b in both steps, whereas the transistor 200E shows an example in which a recess is not formed in the conductive layer 220b in the step of forming the opening 290, but is formed in the step of forming the insulating layer 235.

[0271] In the transistor 200E, the insulating layer 235 contacts the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, and the top surface of the conductive layer 220b in the opening 290. The oxide semiconductor layer 230 contacts the bottom surface and the side surface of the recess of the conductive layer 220b.

[0272] When a recess is formed in the conductive layer 220b in at least one of the steps of forming the opening 290 and forming the insulating layer 235, the height of the lower surface of the conductive layer 265a in the opening 290 can be reduced. This makes it easier for a gate electric field to be applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200.

[0273] When a recess is formed in the conductive layer 220b in the process of forming the insulating layer 235, the oxide semiconductor layer 230 can be in contact with the bottom and side surfaces of the recess in the conductive layer 220b, the contact area between the oxide semiconductor layer 230 and the conductive layer 220b is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced, which is preferable.

[0274] [Transistor 200F] FIG. 6B is a cross-sectional view of a semiconductor device having a transistor 200F.

[0275] Transistor 200F differs from transistor 200 primarily in that insulating layer 235 does not cover the sides of conductive layer 240b.

[0276] The insulating layer 235 shown in FIG. 6B is in contact with the bottom surface and side surface of the recess of the conductive layer 220, and is in contact with the side surface of the insulating layer 280a, the side surface of the conductive layer 255, and the side surface of the insulating layer 280b in the opening 290. The insulating layer 235 is in contact with a part of the side surface of the conductive layer 240a, but is not in contact with the side surface of the conductive layer 240b. The insulating layer 235 functions as a second gate insulating layer. Therefore, the insulating layer 235 covers at least the entire side surface of the conductive layer 255 in the opening 290, and electrically insulates the conductive layer 255 from the oxide semiconductor layer 230. The insulating layer 235 may be in contact with one or more of the side surface of the insulating layer 280a, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b in the opening 290, or may cover a part or all of each side surface.

[0277] When at least a part of the side surface of the conductive layer 240b is not covered by the insulating layer 235, the part is in contact with the oxide semiconductor layer 230. This makes it possible to increase the contact area between the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable. Similarly, when the insulating layer 235 does not cover the side surface of the conductive layer 240b and does not cover at least a part of the side surface of the conductive layer 240a, the part is in contact with the oxide semiconductor layer 230. This makes it possible to increase the contact area between the oxide semiconductor layer 230 and the conductive layer 240, and to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, which is preferable.

[0278] [Transistor 200G] FIG. 6C is a cross-sectional view of a semiconductor device having a transistor 200G.

[0279] The transistor 200G differs from the transistor 200 mainly in that the transistor 200G includes an insulating layer 280c, an insulating layer 280d, an insulating layer 280e, and an insulating layer 280f.

[0280] In the transistor 200G, it is preferable to use silicon oxide films as the insulating layers 280a and 280b, and to use silicon nitride films or aluminum oxide films as the insulating layers 280c, 280d, 280e, and 280f. By providing a barrier insulating layer against hydrogen in the insulating layer 280c in contact with the upper surface of the conductive layer 220, the insulating layer 280d in contact with the lower surface of the conductive layer 240, the insulating layer 280e in contact with the lower surface of the conductive layer 255, and the insulating layer 280f in contact with the upper surface of the conductive layer 255, it is preferable to prevent impurities such as hydrogen from diffusing into the oxide semiconductor layer 230.

[0281] Furthermore, for example, when tungsten, tantalum nitride, or the like is used for the conductive layer 255, the conductive layer 255 may be oxidized by using an oxide insulating layer for an insulating layer in contact with the conductive layer 255. For this reason, it is preferable to use silicon nitride films as the insulating layers 280e and 280f above and below the conductive layer 255. This makes it possible to suppress oxidation of the conductive layer 255 and to provide a barrier insulating layer against hydrogen.

[0282] [Transistor 200H] FIG. 6D is a cross-sectional view of a semiconductor device including a transistor 200H.

[0283] Transistor 200H differs from transistor 200 primarily in that the side surface of conductive layer 220 is aligned with the side surfaces of conductive layer 240, insulating layer 280b, conductive layer 255, and insulating layer 280a within opening 290.

[0284] In a cross-sectional view, the width of the conductive layer 220 coincides with the width of the opening 290. With such a configuration, the parasitic capacitance generated between the conductive layer 220 and the conductive layer 240 can be reduced, which is preferable.

[0285] [Transistor 200I] FIG. 7A is a cross-sectional view of a semiconductor device including a transistor 200I.

[0286] Transistor 200I differs from transistor 200 primarily in that insulating layer 235 has a three-layer structure.

[0287] The transistor 200I includes an insulating layer 235a, an insulating layer 235b over the insulating layer 235a, and an insulating layer 235c over the insulating layer 235b. The insulating layers 235a, 235b, and 235c function as a second gate insulating layer of the transistor 200I.

[0288] At least one of the insulating layers 235a, 235b, and 235c preferably has an insulating layer having a region containing oxygen that is desorbed by heating. At least another of the insulating layers 235a, 235b, and 235c preferably has a barrier insulating layer against hydrogen.

[0289] This allows oxygen to be supplied to the oxide semiconductor layer 230 from at least one of the insulating layer 235a, the insulating layer 235b, and the insulating layer 235c, and also prevents hydrogen from diffusing into the oxide semiconductor layer 230, thereby improving the reliability of the transistor.

[0290] For example, it is preferable to use a silicon nitride film for the insulating layer 235a and the insulating layer 235c and a silicon oxide film for the insulating layer 235b. Alternatively, it is preferable to use a silicon oxide film for the insulating layer 235a and the insulating layer 235c and a silicon nitride film for the insulating layer 235b.

[0291] The insulating layer 235 of the three-layer structure in the transistor 200I can be considered as a modified example of the insulating layer 235 of the two-layer structure in the transistor 200B (FIG. 4B). When the insulating layer 235 of the three-layer structure is applied, it is not limited to the configuration shown in the transistor 200I. For example, the insulating layer 235 of the two-layer structure in the transistor 200C (FIG. 5A) or the transistor 200D (FIG. 5B) can also be made to have a three-layer structure.

[0292] [Transistor 200J, 200K] Fig. 7B is a cross-sectional view of a semiconductor device having a transistor 200J. Fig. 7C is a cross-sectional view of a semiconductor device having a transistor 200K.

[0293] The transistor 200J differs from the transistor 200 mainly in that the transistor 200J does not include the conductive layer 265a and the conductive layer 265b and has a conductive layer 265 with a single-layer structure.

[0294] A conductive layer functioning as a gate electrode, like the conductive layer 265 of the transistor 200J, may have a single-layer structure. The conductive layer 265 is preferably provided so as to fill the opening 290.

[0295] Transistor 200K differs from transistor 200 primarily in that both conductive layer 265a and conductive layer 265b are located within opening 290.

[0296] In the transistor 200K, the conductive layer 265b is located within the opening 290. As described above, depending on the diameter of the opening 290 and the thickness of the conductive layer 265a, not only the conductive layer 265a but also the conductive layer 265b may be provided within the opening 290.

[0297] [Transistor 201] FIG. 8(A) is a plan view of a semiconductor device having a transistor 201. FIG. 8(B) is a cross-sectional view taken along dashed lines A1-A2 in FIG. 8(A). FIG. 8(C) is a cross-sectional view taken along dashed lines A3-A4 in FIG. 8(A). FIG. 8(D) is a cross-sectional view taken along dashed lines A5-A6 in FIG. 8(B) and FIG. 8(C). FIG. 8(E) is a cross-sectional view taken along dashed lines A7-A8 in FIG. 8(B) and FIG. 8(C). Note that FIG. 8(D) and FIG. 8(E) have the same configuration as FIG. 2(D) and FIG. 2(E), and therefore detailed description thereof will be omitted.

[0298] 8(A) to 8(E) include an insulating layer 210 over a substrate (not shown), a transistor 201 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, an insulating layer 280b over the insulating layer 280a, an insulating layer 283 over the insulating layer 250, and an insulating layer 285 over the insulating layer 283. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0299] The transistor 201 includes a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 255 on the insulating layer 280a, a conductive layer 240a on the insulating layer 280b, a conductive layer 240b on the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, a conductive layer 265a on the insulating layer 250 and the insulating layer 285, and a conductive layer 265b on the conductive layer 265a.

[0300] In the transistor 201, the stacked structure from the conductive layer 220a to the insulating layer 250 is similar to that of the transistor 200, and therefore detailed description thereof is omitted.

[0301] 8(B) and 8(C), an opening 270 is provided in the insulating layer 283 at a position overlapping with the opening 290, the opening 270 reaching the insulating layer 250. The conductive layer 265a is disposed so that at least a portion thereof is located within the opening 270. Furthermore, the conductive layer 265b may also be disposed so that at least a portion thereof is located within the opening 270. The conductive layer 265a contacts the insulating layer 250 within the opening 270.

[0302] The conductive layer 265a is provided so as to fill at least a portion of the opening 290 and the opening 270 .

[0303] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 290 and the opening 270. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 265 in the opening 290 and the opening 270 as the diameters of the opening 290 and the opening 270 become smaller with the progress of miniaturization of the transistor. FIGS. 8B and 8C show an example in which the conductive layer 265 has a two-layer structure, only the conductive layer 265a is provided in the opening 290, and the conductive layer 265a and the conductive layer 265b are provided in the opening 270. Note that both the conductive layer 265a and the conductive layer 265b may be located in the opening 290 depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like. Furthermore, only the conductive layer 265a may be located in the opening 270 depending on the diameter of the opening 270, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like.

[0304] The portions of the conductive layer 265a and the conductive layer 265b that do not overlap with the opening 290 are mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 283 and the insulating layer 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have overlapping portions without the insulating layer 285 being interposed therebetween.

[0305] 8(B) and 8(C) show an example in which the width of the opening 270 is narrower than the width D of the opening 290. The narrower the width of the opening 270, the narrower the region where the conductive layer 240 and the conductive layer 265 overlap without the insulating layer 285 can be made, and the smaller the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0306] The width of the opening 270 may be larger than the width of the opening 290. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in FIG. 8(C)). Also, for example, the maximum width of the conductive layer 265 is preferably equal to or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 8(E)). This allows the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 without the insulating layer 285 to be sufficiently smaller than the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 via the insulating layer 285, and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be reduced.

[0307] That is, the transistor 201 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0308] In the present embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are similar to the shapes that can be applied to the opening 290 described above.

[0309] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used herein is the maximum width of the opening 270 provided in the insulating layer 283 in a cross-sectional view.

[0310] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. This can suppress diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate therethrough, and thus can be suitably used for the insulating layer 283.

[0311] It is particularly preferable to use silicon nitride formed by a sputtering method as the insulating layer 283. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 283. Furthermore, by forming the insulating layer 283 by a sputtering method, silicon nitride with high density can be formed.

[0312] Alternatively, an insulating layer having a function of trapping or fixing hydrogen may be used as the insulating layer 283. With such a structure, diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230 can be suppressed, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 283, aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.

[0313] Alternatively, the insulating layer 283 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 283 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0314] The insulating layer 285 functions as an interlayer film, and is therefore preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0315] [Transistor 201A] FIG. 9A is a cross-sectional view of a semiconductor device including a transistor 201A.

[0316] 9A shows an example in which the sidewall of the opening 290 has a tapered shape. For details regarding the case in which the sidewall of the opening 290 has a tapered shape, the description of the transistor 200A (FIG. 4A) can be referred to.

[0317] [Transistor 201B] FIG. 9B is a cross-sectional view of a semiconductor device including a transistor 201B.

[0318] The transistor 201B differs from the transistor 201 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, the description of the transistor 200B (FIG. 4B) can be referred to.

[0319] The shape and details of the transistor 201 can be changed in the same manner as the transistor 200. Specifically, the transistor 201 can have the same structure as the transistors 200C to 200K.

[0320] [Transistor 202] FIG. 10(A) is a plan view of a semiconductor device having a transistor 202. FIG. 10(B) is a cross-sectional view taken along dashed lines A1-A2 in FIG. 10(A). FIG. 10(C) is a cross-sectional view taken along dashed lines A3-A4 in FIG. 10(A). FIG. 10(D) is a cross-sectional view taken along dashed lines A5-A6 in FIG. 10(B) and FIG. 10(C). FIG. 10(E) is a cross-sectional view taken along dashed lines A7-A8 in FIG. 10(B) and FIG. 10(C). Note that FIG. 10(D) and FIG. 10(E) have the same configuration as FIG. 2(D) and FIG. 2(E) except that they do not have the conductive layer 265a but have the conductive layer 260, and therefore detailed description thereof will be omitted.

[0321] 10A to 10E includes an insulating layer 210 over a substrate (not shown), a transistor 202 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, an insulating layer 280b over the insulating layer 280a, an insulating layer 283 over the insulating layer 250, an insulating layer 285 over the insulating layer 283, and a conductive layer 265 over the insulating layer 285. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0322] The transistor 202 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 255 over the insulating layer 280a, a conductive layer 240a over the insulating layer 280b, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the conductive layer 265 may be regarded as a component of the transistor 202.

[0323] The conductive layer 260 functions as a gate electrode (first gate electrode) of the transistor 202, and the conductive layer 265 functions as a gate wiring. The conductive layer 260 can be formed using any of the materials that can be used for the conductive layer 265.

[0324] In the transistor 202, the stacked structure from the conductive layer 220a to the oxide semiconductor layer 230 is similar to that of the transistor 200; therefore, detailed description thereof is omitted.

[0325] 10B and 10C, the insulating layer 283 has an opening 270 that reaches the oxide semiconductor layer 230 at a position overlapping with the opening 290. At least some of the components of the transistor 202 are disposed in the opening 270. Specifically, the insulating layer 250 and the conductive layer 260 are disposed such that at least some of them are located in the opening 270. The insulating layer 250 is in contact with the oxide semiconductor layer 230 and the insulating layer 283 in the opening 270.

[0326] The portion of insulating layer 250 that is disposed within opening 270 is provided to reflect the shape of opening 270. Specifically, insulating layer 250 is provided so as to cover the sidewall of opening 270 (the side surface of insulating layer 283). Then, conductive layer 260 is provided so as to fill at least a portion of the recess of insulating layer 250 that reflects the shape of opening 270.

[0327] In the transistor 202, the conductive layer 260 does not overlap with the top surface of the conductive layer 240, so that the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced. As shown in FIGS. 10B and 10C, in a cross-sectional view, the maximum value of the width of the conductive layer 260 is smaller than the width D of the opening 290. When the maximum value of the width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Note that, for example, as shown in FIG. 10B or FIG. 10C, the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0328] 10(B) and 10(C) show an example in which the width of the opening 270 is the same as the width of the opening 290 (same as width D). It is more preferable that the width of the opening 270 is the same as or smaller than the width of the opening 290. This is preferable because the conductive layer 260 does not overlap the upper surface of the conductive layer 240 and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced.

[0329] In the present embodiment, an example in which the conductive layer 260 does not overlap with the upper surface of the conductive layer 240 is mainly shown, but the conductive layer 260 may have a portion overlapping with the upper surface of the conductive layer 240. The smaller the overlapping portion, the smaller the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240, which is preferable. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265 in FIG. 10(C)). Also, for example, the maximum width of the conductive layer 265 is preferably the same as or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 10(E)).

[0330] It is preferable that the height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same. The conductive layer 265 is provided on the insulating layer 285, the insulating layer 283, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other. The insulating layer 283 and the insulating layer 285 are located between the conductive layer 265 and the conductive layer 240. This can increase the physical distance between the conductive layer 265 and the conductive layer 240, and can reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240.

[0331] In other words, the transistor 202 has a structure in which parasitic capacitance between the other of the source electrode and the drain electrode and between the gate electrode and the other of the source electrode and the drain electrode and between the gate wiring are reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0332] [Transistor 202A] FIG. 11A is a cross-sectional view of a semiconductor device including a transistor 202A.

[0333] 11A shows an example in which the sidewall of the opening 290 has a tapered shape. For details regarding the case in which the sidewall of the opening 290 has a tapered shape, the description of the transistor 200A (FIG. 4A) can be referred to.

[0334] [Transistor 202B] FIG. 11B is a cross-sectional view of a semiconductor device including a transistor 202B.

[0335] The transistor 202B differs from the transistor 202 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, the description of the transistor 200B (FIG. 4B) can be referred to.

[0336] The transistor 202 may have a different shape and details, similar to the transistor 200. Specifically, the transistor 202 may have a similar structure to the transistors 200C to 200K.

[0337] [Transistor 203] FIG. 12(A) is a plan view of a semiconductor device having a transistor 203. FIG. 12(B) is a cross-sectional view taken along dashed lines A1-A2 in FIG. 12(A). FIG. 12(C) is a cross-sectional view taken along dashed lines A3-A4 in FIG. 12(A). FIG. 12(D) is a cross-sectional view taken along dashed lines A5-A6 in FIG. 12(B) and FIG. 12(C). FIG. 12(E) is a cross-sectional view taken along dashed lines A7-A8 in FIG. 12(B) and FIG. 12(C). Note that FIG. 12(D) and FIG. 12(E) have the same configuration as FIG. 2(D) and FIG. 2(E) except that they do not have the conductive layer 265a but have the conductive layer 260, and therefore detailed description thereof will be omitted.

[0338] 12A to 12E includes an insulating layer 210 over a substrate (not shown), a transistor 203 over the insulating layer 210, an insulating layer 280a over the insulating layer 210, an insulating layer 280b over the insulating layer 280a, an insulating layer 285 over the insulating layer 250, a conductive layer 265a over the insulating layer 285, and a conductive layer 265b over the conductive layer 265a. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, and the insulating layer 285 function as interlayer films.

[0339] The transistor 203 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, a conductive layer 255 over the insulating layer 280a, a conductive layer 240a over the insulating layer 280b, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. Note that the conductive layer 265a and the conductive layer 265b may each be considered as components of the transistor 203.

[0340] The conductive layer 260 functions as a gate electrode (first gate electrode) of the transistor 203, and the conductive layers 265a and 265b function as gate wirings. The conductive layer 260 can be formed using any of the materials that can be used for the conductive layer 265.

[0341] In the transistor 203, the stacked structure from the conductive layer 220a to the insulating layer 250 is similar to that of the transistor 200, and therefore detailed description thereof will be omitted.

[0342] As shown in FIG. 12B and FIG. 12C, the transistor 203 has a conductive layer 260 over the insulating layer 250. The conductive layer 260 is provided to fill the opening 290. The conductive layer 260 of the transistor 203 can be said to be a conductive layer obtained by modifying the shape of the conductive layer 265a of the transistor 200. The conductive layer 260 does not extend in either the X direction or the Y direction. It is preferable that the width of the conductive layer 260 is narrow in both the X direction and the Y direction. This can reduce the area of ​​a region of the conductive layer 260 that overlaps with the top surface of the conductive layer 240, and can reduce parasitic capacitance generated between the conductive layer 260 and the conductive layer 240.

[0343] 12B and 12C show an example in which the maximum width of the conductive layer 260 is smaller than the width D of the opening 290. In this manner, it is preferable that the maximum width of the conductive layer 260 is equal to or smaller than the width of the opening 290.

[0344] The maximum width of the conductive layer 260 may be larger than the width of the opening 290. For example, the maximum width of the conductive layer 260 is preferably equal to or smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in FIG. 12(C)). Also, for example, the maximum width of the conductive layer 260 is preferably equal to or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 12(E)). This allows the area of ​​the overlapping portion between the conductive layer 260 and the conductive layer 240 to be sufficiently small, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 to be reduced.

[0345] 12(B) and 12(C), the insulating layer 285 has an opening 270 that reaches the conductive layer 260 at a position overlapping the opening 290. The conductive layer 265a is disposed so that at least a portion thereof is located within the opening 270. Furthermore, the conductive layer 265b may also be disposed so that at least a portion thereof is located within the opening 270. The conductive layer 265a contacts the conductive layer 260 within the opening 270. It can also be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other.

[0346] The conductive layer 265a is provided so as to fill at least a portion of the opening 270. Also, the conductive layer 265b may be provided so as to fill a portion of the opening 270.

[0347] In the transistor of one embodiment of the present invention, at least one layer constituting the conductive layer 265 is provided in the opening 270. When the conductive layer 265 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 265 in the opening 270 as the transistor is miniaturized and the diameter of the opening 270 becomes smaller. FIGS. 12B and 12C show an example in which the conductive layer 265 has a two-layer structure and the conductive layer 265a and the conductive layer 265b are provided in the opening 270. Note that depending on the diameter of the opening 270, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like, only the conductive layer 265a may be located in the opening 270.

[0348] The portions of the conductive layer 265a and the conductive layer 265b that do not overlap with the opening 290 are mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layer 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have overlapping portions without the insulating layer 285 being interposed therebetween.

[0349] 12(B) and 12(C) show an example in which the width of the opening 270 is narrower than the width D of the opening 290. The narrower the width of the opening 270, the narrower the region where the conductive layer 240 and the conductive layer 265 overlap without the insulating layer 285 can be made, and the smaller the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0350] The width of the opening 270 may be larger than the width of the opening 290. For example, the width of the opening 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in FIG. 12(C)). Also, for example, the maximum width of the conductive layer 265 is preferably equal to or smaller than the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in FIG. 12(E)). This allows the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 without the insulating layer 285 to be sufficiently smaller than the area of ​​the overlapping portion between the conductive layer 240 and the conductive layer 265 via the insulating layer 285, and the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265 can be reduced.

[0351] That is, the transistor 203 has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0352] [Transistor 203A] FIG. 13A is a cross-sectional view of a semiconductor device including a transistor 203A.

[0353] 13A shows an example in which the sidewall of the opening 290 has a tapered shape. For details regarding the case in which the sidewall of the opening 290 has a tapered shape, the description of the transistor 200A (FIG. 4A) can be referred to.

[0354] [Transistor 203B] FIG. 13B is a cross-sectional view of a semiconductor device including a transistor 203B.

[0355] The transistor 203B differs from the transistor 203 mainly in that the insulating layer 235 has a two-layer structure. For details of the insulating layer 235 having a two-layer structure, the description of the transistor 200B (FIG. 4B) can be referred to.

[0356] The transistor 203 may have a different shape and details, similar to the transistor 200. Specifically, the transistor 203 may have a similar structure to the transistors 200C to 200K.

[0357] [Transistors 203C, 203D] Fig. 14A is a cross-sectional view of a semiconductor device including a transistor 203C, and Fig. 14B is a cross-sectional view of a semiconductor device including a transistor 203D.

[0358] The transistor 203C differs from the transistor 203 mainly in that the transistor 203C does not include the insulating layer 285 but includes an insulating layer 285a and an insulating layer 285b.

[0359] Furthermore, the transistor 203C and the transistor 203D mainly differ from the transistor 203 in that the top surface of the conductive layer 260 is flat.

[0360] In this manner, the upper surface of the conductive layer 260 may be planarized. In addition, it is preferable that the height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 285a are aligned or approximately aligned.

[0361] [Transistor 203E] 14C1 and 14C2 are cross-sectional views of a semiconductor device including a transistor 203E.

[0362] The transistor 203E differs from the transistor 203 mainly in that the conductive layer 260 has a portion overlapping with the top surface of the conductive layer 240b.

[0363] As described above, the conductive layer 260 may have a portion overlapping with the conductive layer 240. On the other hand, it is preferable to separately provide a conductive layer 265 that functions as a gate wiring, and to provide an insulating layer 285 between the conductive layer 265 and the conductive layer 240. This increases the physical distance between the conductive layer 265 and the conductive layer 240, and reduces the parasitic capacitance generated between the gate wiring and the conductive layer 240.

[0364] [Area containing halogen elements, Area containing the first element] In the semiconductor device of one embodiment of the present invention, at least one of the side surface of the insulating layer 280a on the opening 290 side and its vicinity, the side surface of the insulating layer 280b on the opening 290 side and its vicinity, the insulating layer 235, and the oxide semiconductor layer 230 may have a region containing a halogen element.

[0365] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. From the viewpoint of replacing oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.

[0366] The insulating layer 280a, the insulating layer 280b, or the insulating layer 235 has a halogen element, so that the halogen element can be supplied into the oxide semiconductor layer 230. The halogen element (X) becomes a defect (VoX) in which the halogen element enters an oxygen vacancy (Vo) in the oxide semiconductor layer 230, and has a function of generating electrons that serve as carriers. For example, when chlorine (Cl) is used as the halogen element, Cl exists stably in the oxide semiconductor layer 230 (particularly at the interface between the insulating layer 235 and the oxide semiconductor layer 230 and in the vicinity thereof) in the state of VoCl. At this time, Cl can enter the existing Vo or can be substituted for oxygen to become the state of VoCl.

[0367] On the other hand, oxygen substituted with Cl (also referred to as excess oxygen) has a function of trapping electrons. Carrier trapping by oxygen occurs preferentially over carrier generation by VoCl. Thus, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer 235 and the oxide semiconductor layer 230 and in the vicinity thereof. The presence of negative charges in the channel formation region can shift the threshold voltage of the transistor in the positive direction. Thus, even when the transistor has a fine structure or an extremely short channel length, the transistor can be normally off.

[0368] In this manner, the transistor of one embodiment of the present invention can be normally-off not only by controlling the threshold voltage with the back gate but also by using a halogen element.

[0369] In the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 preferably contain an impurity element. The impurity element is preferably a first element. Alternatively, the impurity element is preferably both the first element and hydrogen. The oxide semiconductor layer 230 preferably contains the impurity element particularly in the above-described region 230n+ (see FIG. 3).

[0370] Note that at least one of the conductive layer 240a, the conductive layer 240b, the conductive layer 220a, and the conductive layer 220b may contain an impurity element.

[0371] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0372] The first element is not limited to the above elements, and may be one or more of the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in the rare earth elements.

[0373] By supplying the first element to the source region and the drain region, the first element takes away oxygen from these regions, and oxygen vacancies are generated in these regions. The oxygen vacancies are then bonded to hydrogen in the film to generate carriers, and the resistance of the source region and the drain region can be reduced. This can reduce the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Therefore, the on-current of the transistor can be increased. By increasing the on-current, the operating voltage of the transistor can be reduced. This can reduce the power consumption of the semiconductor device.

[0374] When an element that easily bonds with oxygen is used as the first element, the first element exists in a state of being bonded with oxygen in the semiconductor layer. When an element that bonds with oxygen to be stabilized is used as the first element, the first element in the semiconductor layer exists stably in an oxidized state, so that it is difficult to be desorbed by heat or the like during the manufacturing process of the semiconductor device, and a stable low resistance region can be realized in a state where the electrical resistance is low. For this reason, it is preferable to use an element whose oxide can exist as a solid at 25°C and 1 atm as the first element. Specifically, examples of preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals), and examples of particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0375] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0376] Moreover, hydrogen is suitable as an impurity element because it has a function of bonding with oxygen vacancies in addition to the function of generating oxygen vacancies described above.

[0377] By using both the first element and hydrogen as the impurity elements, the electric resistance of the source region and the drain region in the oxide semiconductor layer 230 can be easily reduced and the low electric resistance can be stably maintained.

[0378] In addition, when both the first element and hydrogen are supplied, the ions generated from the raw material gas can be added without mass separation, which is preferable because it is possible to increase productivity. For example, 2 H 6 By using gas, boron and hydrogen can be supplied as impurity elements. 3 By using gas, phosphorus and hydrogen can be supplied as impurity elements. The method of supplying the impurity elements is not limited to this. For example, a specific element may be added by ionizing the source gas and mass-separating the ions. For example, B 2 H 6 A gas may be used, and boron may be added after mass separation.

[0379] Note that the impurity element may be supplied also to a channel formation region in the oxide semiconductor layer 230. Alternatively, due to the influence of heat applied during a manufacturing process, part of the impurity element contained in the region 230n+ or the region 230n− may diffuse into the channel formation region (region 230i).

[0380] In manufacturing the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 are preferably doped with the impurity element more easily than the channel formation region. Therefore, the impurity element is preferably doped from a direction perpendicular or substantially perpendicular to the top surface of the substrate. At this time, the amount of the impurity element doped is smaller in a surface of the oxide semiconductor layer 230 that is inclined with respect to the top surface of the substrate than in a surface that is parallel or substantially parallel to the top surface of the substrate. That is, the amount of the impurity element doped is larger in the source region and the drain region of the oxide semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source region and the drain region can be preferentially reduced.

[0381] <Example of a method for manufacturing a semiconductor device> Next, a manufacturing method of a semiconductor device of one embodiment of the present invention will be described with reference to Figures 15 to 19. Note that with regard to materials and formation methods of each element, description of parts similar to those described above may be omitted.

[0382] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0383] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0384] CVD methods can also be classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD: Thermal CVD) methods that use heat, photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal Organic CVD) methods based on the source gas used.

[0385] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0386] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0387] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, a film formed by the ALD method may contain more elements such as carbon or chlorine than a film formed by other film formation methods. The amount of these elements can be quantified using XPS or SIMS. Note that, in the method for forming a metal oxide film according to one embodiment of the present invention, the ALD method is used, but since one or both of the following conditions are adopted: a high substrate temperature during film formation and / or an impurity removal treatment is performed, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using the ALD method without applying these conditions.

[0388] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0389] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0390] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0391] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0392] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0393] Furthermore, when processing a thin film constituting a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0394] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0395] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0396] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0397] [Example of a method for manufacturing the transistor 200] An example of a method for manufacturing a semiconductor device including the above-described transistor 200 (see FIGS. 2 and 3) will be described with reference to FIGS.

[0398] First, as shown in Figures 15(A1) and 15(A2), an insulating layer 210 is formed on a substrate (not shown), a conductive layer 220a is formed on the insulating layer 210, a conductive layer 220b is formed on the conductive layer 220a, an insulating layer 280a is formed on the conductive layer 220b, and a conductive layer 255 is formed on the insulating layer 280a.

[0399] Note that after the insulating layer 280a is formed, a planarization treatment is preferably performed to planarize the top surface of the insulating layer 280a. As the planarization treatment, a planarization treatment (also referred to as a CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. Alternatively, a planarization treatment (also referred to as an etch-back treatment) using etching may be performed. By performing the planarization treatment on the insulating layer 280a, the surface on which the conductive layer 255 is to be formed can be flattened, and discontinuity of the conductive layer 255 can be suppressed. Note that the planarization treatment is not necessarily performed, in which case, the manufacturing cost can be reduced.

[0400] Subsequently, as shown in FIG. 15B, an insulating layer 280b is formed over the conductive layer 255, a conductive layer 240a is formed over the insulating layer 280b, and a conductive layer 240b is formed over the conductive layer 240a.

[0401] 15(C), openings 290 are formed in the conductive layer 240b, the conductive layer 240a, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a at positions overlapping with the conductive layer 220a. At this time, a recess is preferably provided in the conductive layer 220b at a position overlapping with the opening 290. By forming the opening 290, a bottom surface and a side surface of the recess of the conductive layer 220b are preferably exposed.

[0402] In order to reduce the size of the transistor and perform fine processing, when forming the opening 290, it is preferable to process a part of the conductive layer 220b, a part of the conductive layer 240a, a part of the conductive layer 240b, a part of the conductive layer 255, a part of the insulating layer 280a, and a part of the insulating layer 280b by anisotropic etching. In particular, processing by a dry etching method is preferable because it is suitable for fine processing. Also, the opening 290 may be formed under different processing conditions depending on the layer. Note that, depending on the materials and processing conditions of the conductive layer 220b, the conductive layer 240a, the conductive layer 240b, the conductive layer 255, the insulating layer 280a, and the insulating layer 280b, the inclination of the side of the recess of the conductive layer 220b, the inclination of the side of the conductive layer 240a, the inclination of the side of the conductive layer 240b, the inclination of the side of the conductive layer 255, the inclination of the side of the insulating layer 280a, and the inclination of the side of the insulating layer 280b may differ from each other.

[0403] Furthermore, by the process of forming the opening 290, etc., a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess of the conductive layer 220b, the side surfaces of the insulating layer 280a, the side surfaces of the insulating layer 280b, the side surfaces of the conductive layer 255, the side surfaces of the conductive layer 240a, and the top and side surfaces of the conductive layer 240b. Examples of the region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from the etching gas used in the dry etching may remain in the region.

[0404] Subsequently, a heat treatment may be performed, for example, at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0405] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 280a, the insulating layer 280b, and the like can be reduced before the oxide semiconductor layer 230 is formed.

[0406] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the insulating layer 280a and the insulating layer 280b as much as possible.

[0407] 15(D), an insulating layer 235 is formed so as to cover the opening 290. The insulating layer 235 is provided in contact with the bottom surface and side surfaces of the recess of the conductive layer 220b, the side surfaces of the insulating layer 280a, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 280b, the side surfaces of the conductive layer 240a, and the top surface and side surfaces of the conductive layer 240b.

[0408] Since the insulating layer 235 is a layer provided inside the opening 290, it is preferably formed by the CVD method or the ALD method, and more preferably by the ALD method, so that the insulating layer 235 can be provided with good coverage.

[0409] 15(E), the insulating layer 235 is processed to expose the upper surface of the conductive layer 240b and to expose the conductive layer 220b at the opening 290. It is preferable that the bottom surface of the recess of the conductive layer 220b is exposed at the opening 290.

[0410] By processing the insulating layer 235 by anisotropic etching, it is possible to remove the region of the insulating layer 235 located on the upper surface of the conductive layer 240b and the region located on the bottom surface of the opening 290, and to leave the insulating layer 235 only on the side surface within the opening 290. It is preferable to process the insulating layer 235 by performing highly anisotropic etching using a dry etching method.

[0411] As shown in FIG. 15(E), when the insulating layer 235 is processed, a part of the conductive layer 220b may be removed to provide a recess in the conductive layer 220b.

[0412] 16A, the oxide semiconductor layer 230 is formed to cover the opening 290. The oxide semiconductor layer 230 is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b.

[0413] The oxide semiconductor layer 230 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0414] The oxide semiconductor layer 230 is preferably formed as a film with a uniform thickness along the bottom and side surfaces of the recesses of the conductive layer 220b, the insulating layer 235, and the upper surface of the conductive layer 240b. By forming the film using the ALD method, a thin film can be formed with good controllability. Therefore, it is preferable to form the oxide semiconductor layer 230 using the ALD method.

[0415] In addition, when the oxide semiconductor layer 230 has high crystallinity, diffusion of impurities in the oxide semiconductor layer 230 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and the reliability can be improved. When the oxide semiconductor layer 230 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.

[0416] When the oxide semiconductor layer 230 is formed by a sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as a sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by a sputtering method, an In-M-Zn oxide target or the like can be used.

[0417] When the oxide semiconductor layer 230 is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in a sputtering gas is set to more than 30% and less than or equal to 100%, preferably greater than or equal to 70% and less than or equal to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in a sputtering gas is set to more than or equal to 1% and less than or equal to 30%, preferably greater than or equal to 5% and less than or equal to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide semiconductor layer can be improved by performing the film formation while heating the substrate.

[0418] For a method for forming an oxide semiconductor layer, the description in Embodiment 3 can be referred to.

[0419] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor layer 230 is not polycrystallized. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and further preferably from 350° C. to 550° C. For details of the heat treatment, see the above description.

[0420] In addition, a gas used in the heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor layer 230 as much as possible.

[0421] In this embodiment, the heat treatment is performed at a temperature of 450° C. for one hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. Such heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor layer 230 and provide a denser and more compact structure. This can increase the crystalline regions in the oxide semiconductor layer 230 and reduce in-plane variations in the crystalline regions in the oxide semiconductor layer 230. Thus, in-plane variations in electrical characteristics of the transistor can be reduced.

[0422] When at least one of the insulating layers 280a, 280b, and 235 contains oxygen, oxygen is preferably supplied by heat treatment from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 230. This can reduce oxygen vacancies and VoH.

[0423] In this manner, oxygen (also referred to as excess oxygen) released by heating from an insulating layer in contact with the oxide semiconductor layer 230 or an insulating layer located near the oxide semiconductor layer 230 may be supplied to the oxide semiconductor layer 230. The excess oxygen has a function of trapping electrons, and thus negative charges are likely to be formed. Thus, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0424] 16B, the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b are processed to expose part of the top surface of the insulating layer 280b. The oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b can be processed using the same mask. This is preferable because the number of masks required to manufacture a semiconductor device can be reduced.

[0425] 16C, an insulating layer 250 is formed to cover the opening 290, and a conductive layer 265a is formed over the insulating layer 250. Further, a conductive layer 265b is formed over the conductive layer 265a. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The conductive layer 265a is preferably provided to fill the opening 290. Note that depending on the diameter of the opening 290, the thickness of the conductive layer 265a, and the like, the conductive layer 265b may also be provided in the opening 290.

[0426] The insulating layer 250 and the conductive layer 265a are each formed in an opening 290 having a large aspect ratio. Therefore, for forming the insulating layer 250 and the conductive layer 265a, it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0427] In this manner, the transistor 200 can be manufactured.

[0428] [Example of a method for manufacturing transistor 201] An example of a method for manufacturing a semiconductor device including the above-described transistor 201 (see FIG. 8) will be described with reference to FIGS. 17A to 17F. Note that detailed description of the same steps as those in the example of a method for manufacturing the transistor 200 will be omitted.

[0429] 15A1 to 16B are performed in the same manner as in the example of the method for manufacturing the transistor 200. Then, as shown in FIG 17A, the insulating layer 250 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230.

[0430] Thereafter, a sacrificial layer 262 is formed on the insulating layer 250. A SOC (Spin On Carbon) film and a SOG (Spin On Glass) film are suitable for the sacrificial layer 262. The sacrificial layer 262 is preferably a two-layer structure of, for example, an SOC film and an SOG film on the SOC film.

[0431] Providing the sacrificial layer 262 in contact with the insulating layer 250 is preferable because damage to the oxide semiconductor layer 230 can be reduced in a manufacturing process of the semiconductor device compared to providing the sacrificial layer 262 in contact with the oxide semiconductor layer 230. On the other hand, providing the sacrificial layer 262 in contact with the oxide semiconductor layer 230 as in an example of a manufacturing method of the transistor 202 described later is preferable because damage to the insulating layer 250 can be reduced in a manufacturing process of the semiconductor device. Note that when the insulating layer 250 has a stacked structure, some layers constituting the insulating layer 250 may be formed before the sacrificial layer 262, and the remaining layers may be formed after removing the sacrificial layer 262.

[0432] Subsequently, as shown in FIG. 17(B), a part of the sacrificial layer 262 is removed. In a region where the sacrificial layer 262 remains, a gate electrode (conductive layer 265a and conductive layer 265b) will be provided in a later step. Therefore, it is preferable that the sacrificial layer 262 has a small portion that overlaps with the upper surface of the conductive layer 240b, and it is more preferable that the sacrificial layer 262 does not overlap with the upper surface of the conductive layer 240b. As shown in FIG. 17(B), it is preferable that the maximum value of the width of the sacrificial layer 262 is shorter than the width D of the opening 290 in a cross-sectional view.

[0433] 17C, an insulating layer 283 is formed so as to cover the insulating layer 250 and the sacrificial layer 262, and an insulating layer 285 is formed on the insulating layer 283. Then, as shown in FIG.

[0434] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240b and the conductive layer 265a can be increased, and the parasitic capacitance generated between the conductive layer 240b and the gate electrode (or gate wiring) can be reduced.

[0435] For example, the insulating layer 285 is preferably a silicon oxide film formed by a sputtering method.

[0436] Here, if the insulating layer 283 is not provided, when a silicon oxide film is formed as the insulating layer 285 by a sputtering method, the sacrificial layer 262 is exposed to plasma containing oxygen, and therefore a part or all of the sacrificial layer 262 may be etched. As described above, depending on the method of forming the insulating layer 285, the shape of the sacrificial layer 262 may be reduced or the sacrificial layer 262 may disappear. For this reason, it is preferable that the insulating layer formed on the sacrificial layer 262 has a stacked structure of the insulating layer 283 and the insulating layer 285, rather than the single insulating layer 285. This provides the effects of expanding the range of materials to be selected for the sacrificial layer 262 and the insulating layer 285, reducing the difficulty of manufacturing a semiconductor device, and the like.

[0437] When an oxide film is used for the insulating layer 283, it is preferable to form it by a method other than the sputtering method, for example, the ALD method. For example, it is preferable to form an aluminum oxide film or a hafnium oxide film as the insulating layer 283 by the ALD method. Alternatively, it is preferable to use a nitride film (such as a silicon nitride film) for the insulating layer 283. This can prevent the sacrificial layer 262 from being unintentionally processed when the insulating layer 283 and the insulating layer 285 are formed.

[0438] Moreover, the insulating layer 283 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, so that the insulating layer 283 can be provided with good coverage even on the side surfaces of the sacrificial layer 262, etc.

[0439] 17(D), a planarization process is performed to expose the upper surface of the sacrificial layer 262, and to planarize the upper surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285. The planarization process is preferably a CMP process. In the planarization process, at least a part of the insulating layer 283 and the insulating layer 285 is removed. Furthermore, a part of the sacrificial layer 262 may be removed.

[0440] Subsequently, the sacrificial layer 262 is removed as shown in Fig. 17(E). There is no particular limit to the method for removing the sacrificial layer 262. For example, the sacrificial layer 262 can be removed by dry etching. Here, as shown in Fig. 17(E), it can be said that the insulating layer 283 has an opening 270 at a position overlapping the opening 290.

[0441] 17(F), a conductive layer 265a is formed to cover the opening 270 and the opening 290. The conductive layer 265a is provided in contact with the insulating layer 250 and the insulating layer 283 in the opening 270 and the opening 290. The conductive layer 265a is preferably provided to fill the opening 290. Furthermore, a conductive layer 265b is formed over the conductive layer 265a. Here, an example is shown in which the conductive layer 265b is provided in the opening 270.

[0442] The conductive layer 265a and the conductive layer 265b are formed in one or both of the openings 290 and 270, which have a large aspect ratio. Therefore, for forming the conductive layer 265a and the conductive layer 265b, it is preferable to use a film formation method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0443] Depending on the diameter of the opening 270, the diameter of the opening 290, the thickness of the conductive layer 265a, and the thickness of the conductive layer 265b, the conductive layer 265b may also be provided in the opening 290. Alternatively, the conductive layer 265a may fill the opening 270, and the conductive layer 265b may not be provided in the opening 270.

[0444] In this manner, the transistor 201 can be manufactured.

[0445] [Example of a method for manufacturing the transistor 202] An example of a method for manufacturing the semiconductor device including the above-described transistor 202 (see FIG. 10) will be described with reference to FIGS. 18A to 18F. Note that detailed description of the same steps as those in the example of the method for manufacturing the transistors 200 and 201 will be omitted.

[0446] 15A1 to 16B are performed in the same manner as in the example of the method for manufacturing the transistor 200. Then, as shown in FIG 18A, a sacrificial layer 262 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230.

[0447] Next, as shown in FIG. 18(B), a part of the sacrificial layer 262 is removed. In the region where the sacrificial layer 262 remains, a gate insulating layer and a gate electrode (insulating layer 250 and conductive layer 260) will be provided in a later step. Therefore, it is preferable that the sacrificial layer 262 has a small portion overlapping with the upper surface of the conductive layer 240b, and it is more preferable that the sacrificial layer 262 does not overlap with the upper surface of the conductive layer 240b. In a cross-sectional view, it is preferable that the width of the sacrificial layer 262 does not exceed the sum of the width D of the opening 290 and twice the thickness of the insulating layer 250 to be formed later. FIG. 18(B) shows an example in which the width of the sacrificial layer 262 is the width D of the opening 290.

[0448] Next, as shown in FIG. 18C, an insulating layer 283 is formed so as to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230, and the sacrificial layer 262, and an insulating layer 285 is formed over the insulating layer 283.

[0449] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240b and the gate wiring (conductive layer 265) can be increased, and the parasitic capacitance generated between the conductive layer 240b and the gate wiring can be reduced.

[0450] Subsequently, as shown in FIG. 18D, a planarization process is performed to expose the upper surface of the sacrificial layer 262, and the upper surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285 are planarized.

[0451] Subsequently, as shown in FIG. 18(E), the sacrificial layer 262 is removed.

[0452] 18(F), an insulating layer 250 is formed to cover the openings 270 and the openings 290, and a conductive layer 260 is formed over the insulating layer 250. Next, a planarization treatment is performed to expose the top surfaces of the insulating layer 283 and the insulating layer 285, and the top surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 283, and the insulating layer 285 are planarized.

[0453] The insulating layer 250 is provided in contact with the oxide semiconductor layer 230 and the insulating layer 283.

[0454] The insulating layer 250 and the conductive layer 260 are respectively formed in the openings 290 and 270, which have a large aspect ratio. Therefore, for forming the insulating layer 250 and the conductive layer 260, it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0455] As the planarization process, a CMP process is suitable. In the planarization process, at least the portions of the conductive layer 260 and the insulating layer 250 that overlap with the upper surface of the insulating layer 285 are removed. This makes it possible to remove the portions of the conductive layer 260 that overlap with the upper surface of the conductive layer 240, and to suppress the occurrence of parasitic capacitance between the conductive layer 260 and the conductive layer 240.

[0456] By using the CMP process to remove the portion of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240, an increase in the number of masks can be suppressed compared to the case where dry etching is used.

[0457] 18(F), it is preferable that the height of the upper surface of insulating layer 285 and the height of the upper surface of conductive layer 260 are the same. Alternatively, one of the height of the upper surface of insulating layer 285 and the height of the upper surface of conductive layer 260 may be higher than the other. The vertical relationship between the heights of the upper surfaces of the two layers can be controlled by the difference in polishing rate between the materials of insulating layer 285 and conductive layer 260.

[0458] 18(F), a conductive layer 265 is formed over the insulating layer 250, the insulating layer 283, the insulating layer 285, and the conductive layer 260. Then, as shown in FIG.

[0459] Between the conductive layer 265 and the conductive layer 240b, the insulating layer 283 and the insulating layer 285 are located. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240b, and to reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240b.

[0460] In the above manner, a semiconductor device of one embodiment of the present invention can be manufactured.

[0461] [Example of a method for manufacturing transistor 203] An example of a method for manufacturing a semiconductor device including the above-described transistor 203 (see FIG. 12) will be described with reference to FIGS. 19A to 19D. Note that detailed description of the same steps as those in the example of a method for manufacturing the transistor 200 will be omitted.

[0462] 15A1 to 16B are performed in a manner similar to the example of a method for manufacturing the transistor 200. Then, as shown in FIG 19A, an insulating layer 250 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230, and a conductive layer 260 is formed over the insulating layer 250.

[0463] The insulating layer 250 and the conductive layer 260 are each formed in an opening 290 having a large aspect ratio. Therefore, for forming the insulating layer 250 and the conductive layer 260, it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0464] It is preferable that the conductive layer 260 has a small portion overlapping with the top surface of the conductive layer 240b, and more preferably does not overlap with the top surface of the conductive layer 240b. This can reduce parasitic capacitance generated between the conductive layer 260 and the conductive layer 240b. Note that like the transistor 203E (see FIGS. 14C1 and 14C2), the conductive layer 260 may have a portion overlapping with the top surface of the conductive layer 240b.

[0465] 19(B), an insulating layer 285 is formed to cover the insulating layer 250 and the conductive layer 260. As shown in FIG.

[0466] By increasing the thickness of the insulating layer 285, the distance between the conductive layer 240b and the conductive layer 265a can be increased, and the parasitic capacitance generated between the conductive layer 240b and the gate wiring can be reduced.

[0467] For example, the insulating layer 285 is preferably a silicon oxide film formed by a sputtering method.

[0468] 19(C), an opening 270 is formed in the insulating layer 285 so as to reach the conductive layer 260. As shown in FIG.

[0469] 19(D), a conductive layer 265a is formed to cover the opening 270, and a conductive layer 265b is formed over the conductive layer 265a. The conductive layer 265a is provided in contact with the conductive layer 260 within the opening 270. The conductive layer 265a and the conductive layer 265b are preferably provided to fill the opening 270.

[0470] The conductive layer 265a and the conductive layer 265b are each formed in an opening 270 having a large aspect ratio. Therefore, for forming the conductive layer 265a and the conductive layer 265b, it is preferable to use a film formation method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.

[0471] Depending on the diameter of the opening 270 and the thickness of the conductive layer 265a, the conductive layer 265a may fill the opening 270, and the conductive layer 265b may not be provided within the opening 270.

[0472] In this manner, the transistor 203 can be manufactured.

[0473] [Method of adding elements] As described above, a region containing a halogen element may be provided in at least one of the insulating layer 280a, the insulating layer 280b, the insulating layer 235, and the oxide semiconductor layer 230. A region containing the first element may be provided in the oxide semiconductor layer 230. A region containing the first element may be provided in at least one of the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b.

[0474] 15C, a halogen element may be supplied to the side surfaces of the insulating layers 280a and 280b at the opening 290. Note that the halogen element may be supplied to one or more of the conductive layers 240a, 240b, 255, 220a, and 220b.

[0475] 15C shows an example in which the sidewall of the opening 290 is perpendicular to the top surface of the substrate. In the semiconductor device of one embodiment of the present invention, the sidewall of the opening 290 is perpendicular or approximately perpendicular to the top surface of the substrate, or has a tapered shape. Therefore, when the halogen element is added perpendicular or approximately perpendicular to the top surface of the substrate, it may be difficult to uniformly supply the halogen element to a desired region.

[0476] Therefore, it is preferable to add the halogen element from a direction tilted at an angle of more than 0 degrees and less than 90 degrees with respect to the upper surface of the substrate. This makes it easy to supply the halogen element to the side surfaces of the insulating layers 280a and 280b at the opening 290. In addition, it is not limited to addition from one direction, but by supplying the halogen element stepwise by changing the angle, it is possible to supply the halogen element more uniformly to the desired region, which is preferable.

[0477] The elements that can be used as the halogen element are as described above.

[0478] The halogen element can be preferably supplied by plasma ion doping or ion implantation, which can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration voltage, dose, etc.

[0479] It should be noted that, for example, the angle at which the halogen element is added can be set within the above range by tilting either or both of the substrate to be processed and the ion irradiation unit of the apparatus.

[0480] The purity of the halogen element to be supplied can be increased by using an ion implantation method in which the source gas is ionized and the ions are added after mass separation, while the productivity can be increased by using a plasma ion doping method in which the source gas is ionized and the ions are added without mass separation.

[0481] The ion implantation device or ion doping device used for supplying the halogen element is also used in the manufacture of Si transistors such as LTPS transistors, so that the existing LTPS manufacturing line equipment can be used and no new capital investment is required, which is preferable, and thus the capital investment cost for manufacturing semiconductor devices can be reduced.

[0482] As the source gas of the halogen element, the above-mentioned gas containing the halogen element can be used. As the gas, either a gas of a simple halogen or a gas of a halide can be used. When fluorine is supplied, typically, F 2 Gas, BF 3 Gas, C. 4 F 6 Gas, C. 5 F 6 Gas, C. 4 F 8 Gas, CF 4 Gas, SF 6 Gas, CHF 3 Gas, CH 2 F 2 Gas, CH 3 F gas, etc. can be used. In addition, when supplying chlorine, typically Cl2 Gas, BCl 3 Gas, SiCl 4 Gas, CCl 4 A gas can be used. A mixed gas obtained by diluting these source gases with hydrogen or a noble gas can also be used. The ion source is not limited to a gas, and a solid or liquid can be heated and vaporized.

[0483] The supply of the halogen element can be controlled by setting conditions such as the acceleration voltage and the dose amount, taking into consideration the composition, density, thickness, and the like of the insulating layer 280a and the insulating layer 280b.

[0484] The method of supplying the halogen element is not limited, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of the plasma treatment, the halogen element can be supplied by generating plasma in a gas atmosphere containing the halogen element to be supplied and performing plasma treatment. As the device for generating the plasma, a dry etching device, an ashing device, a plasma CVD device, a high density plasma CVD device, etc. may be used.

[0485] The halogen element supplying step may be performed while heating the substrate. This makes it possible to repair damage to the insulating layer 280a and the insulating layer 280b caused when the halogen element is added. In other words, the addition of the halogen element to the insulating layer 280a and the insulating layer 280b and the repair of the damage caused by the addition can be performed in parallel.

[0486] The substrate temperature in the halogen element supplying step is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0487] Moreover, after the insulating layer 235 shown in FIG. 15(D) or 15(E) is formed, a halogen element may be supplied to the insulating layer 235 located in the opening 290.

[0488] Then, by forming the oxide semiconductor layer 230 while heating the substrate, a halogen element can be supplied from the insulating layer 280a, the insulating layer 280b, or the insulating layer 235 to the oxide semiconductor layer 230. Furthermore, during heat treatment performed after the oxide semiconductor layer 230 is formed, a halogen element can be supplied from the insulating layer 280a, the insulating layer 280b, or the insulating layer 235 to the oxide semiconductor layer 230.

[0489] In this manner, by adding a halogen element to an insulating layer in contact with the oxide semiconductor layer 230 or an insulating layer located near the oxide semiconductor layer 230, and then supplying the halogen element from the insulating layer to the oxide semiconductor layer 230, it is possible to suppress damage to the channel formation region of the oxide semiconductor layer 230 caused by the addition of the element, and to suppress deterioration of the crystallinity of the channel formation region caused by the addition of the element, etc. Therefore, the reliability of the transistor can be improved.

[0490] 16A or 16B is formed, a halogen element may be supplied to the side surface of the oxide semiconductor layer 230 located in the opening 290. In this case, as shown in FIG.

[0491] After the opening 290 shown in FIG. 15C is formed, an impurity element may be supplied to the top surface of the conductive layer 220b and the top surface of the conductive layer 240b.

[0492] After that, the oxide semiconductor layer 230 is formed and subjected to heat treatment or the like, so that the impurity element can be supplied to the source region and the drain region of the oxide semiconductor layer 230 from the conductive layer 220b and the conductive layer 240b.

[0493] Supplying the impurity element to the oxide semiconductor layer 230 through the conductive layer 220 or the conductive layer 240 can suppress a decrease in crystallinity of the oxide semiconductor layer 230 as compared to the case where the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be suppressed.

[0494] 15C and before the step of forming the conductive layer 265a in FIG. 16C. That is, the impurity element may be supplied to the oxide semiconductor layer 230 after the oxide semiconductor layer 230 is formed. Alternatively, the impurity element may be added to the oxide semiconductor layer 230 through the insulating layer 250.

[0495] By adding an impurity element to the oxide semiconductor layer 230, the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can each be reduced.

[0496] By directly adding the impurity element to the oxide semiconductor layer 230 and then forming the insulating layer 250 over the oxide semiconductor layer 230, damage to the insulating layer 250 due to the addition of the impurity element can be suppressed.

[0497] Alternatively, by supplying the impurity element to the oxide semiconductor layer 230 through the insulating layer 250, a decrease in the crystallinity of the oxide semiconductor layer 230 can be suppressed compared to the case where the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be suppressed.

[0498] Furthermore, if the insulating layer 250 is formed after the impurity element is added, there is a risk of contamination of the inside of a deposition chamber for the insulating layer 250. For this reason, it is preferable to add the impurity element after the insulating layer 250 is formed.

[0499] Here, the thickness of the insulating layer 250 in the direction in which the impurity element is added is greater in a region provided along the side surface of the insulating layer 235 than in a region provided along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b. As a result, the amount of the impurity element added is greater in the region of the oxide semiconductor layer 230 provided along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b than in the region provided along the side surface of the insulating layer 235. In this way, it is possible to suppress the impurity element from entering the channel formation region of the oxide semiconductor layer 230 and to preferentially reduce the resistance of the source region and the drain region.

[0500] The impurity element is preferably added from a direction perpendicular or substantially perpendicular to the upper surface of the substrate. In this case, in the oxide semiconductor layer 230, a surface inclined with respect to the upper surface of the substrate or a perpendicular or substantially perpendicular surface thereof is doped with a smaller amount of the impurity element than a surface parallel or substantially parallel to the upper surface of the substrate. That is, a larger amount of the impurity element is doped in the source and drain regions of the oxide semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.

[0501] The elements that can be used as the impurity elements are as described above.

[0502] The impurity element can be preferably supplied by plasma ion doping or ion implantation, which can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration voltage, dose, etc.

[0503] By using an ion implantation method in which a source gas is ionized and the ions are mass-separated and added, the purity of the supplied impurity element can be increased. When using the ion implantation method, it is preferable to use the first element described above as the impurity element, and it is more preferable to use boron or phosphorus. By using an element that bonds with oxygen to stabilize the impurity element, a stable low resistance region with low electrical resistance can be realized.

[0504] In addition, the productivity can be improved by using a plasma ion doping method in which the raw material gas is ionized and the ions are added without mass separation. When the plasma ion doping method is used, it is preferable to use both the first element and hydrogen as the impurity element, and it is more preferable to use both boron or phosphorus and hydrogen. By using both an element that bonds with oxygen to stabilize it and hydrogen as the impurity element, it is easy to reduce the electrical resistance of the low resistance region and the state in which the electrical resistance is low can be stably maintained.

[0505] The ion implantation device or ion doping device used for supplying the impurity element is also used in the manufacture of Si transistors such as LTPS transistors, so that the existing LTPS manufacturing line equipment can be used and no new capital investment is required, which is preferable, and thus the capital investment cost for manufacturing semiconductor devices can be reduced.

[0506] In the supplying treatment of the impurity element, the treatment conditions are preferably controlled so that the concentration of the impurity element in a portion of the oxide semiconductor layer 230 that overlaps with the top surface of the conductive layer 220b or the top surface of the conductive layer 240b is higher than the concentration of the impurity element in other regions. In this way, the impurity element can be supplied at an optimum concentration to the source and drain regions of the oxide semiconductor layer 230.

[0507] As the source gas of the impurity element, a gas containing the above-mentioned impurity element can be used. When boron is supplied, typically B 2 H 6 Gas, BF 3 Gases, etc. can be used. In addition, when supplying phosphorus, PH 3 In addition, a mixed gas in which these source gases are diluted with hydrogen or a noble gas may be used.

[0508] Other raw gases include CH 4 , N 2 , N.H. 3, AlH 3 , AlCl 3 , SiH 4 , Si 2 H 6 , F 2 , H.F., H. 2 , (C 5 H 5 ) 2 Mg, noble gases, etc. can be used. The ion source is not limited to gas, and a solid or liquid may be heated and vaporized.

[0509] For example, it is preferable to supply boron and hydrogen as the impurity element by using a gas containing boron and hydrogen, in which case the impurity element can be added without mass separation and the resistance of the oxide semiconductor layer 230 can be easily reduced, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.

[0510] In addition, it is preferable to use the same source gas in the halogen element supplying step and the impurity element supplying step, since this can reduce the manufacturing cost. For example, BF 3 By ionizing the gas and mass-separating the ions, fluorine can be supplied as a halogen element, and boron can be supplied as an impurity element.

[0511] The supply of the impurity element can be controlled by setting conditions such as an acceleration voltage and a dose amount in consideration of the composition, density, thickness, and the like of the oxide semiconductor layer 230.

[0512] The method of supplying the impurity element is not limited, and may be, for example, a plasma treatment or a treatment using thermal diffusion by heating. In the case of the plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing the plasma treatment. As the device for generating the plasma, a dry etching device, an ashing device, a plasma CVD device, a high density plasma CVD device, etc. may be used.

[0513] The step of supplying the impurity element is preferably performed while heating the substrate. This makes it possible to repair damage caused when the impurity element is added to the oxide semiconductor layer 230. That is, the addition of the impurity element to the oxide semiconductor layer 230 and the repair of damage caused by the addition can be performed in parallel.

[0514] The substrate temperature in the impurity element supply process is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0515] After the impurity element is supplied, heat treatment may be performed. By performing the heat treatment, damage to the oxide semiconductor layer 230 caused in the step of supplying the impurity element can be repaired.

[0516] By using an element that bonds with oxygen to stabilize the semiconductor device as the impurity element, it is possible to suppress the impurity element from being desorbed due to heat applied during the manufacturing process of the semiconductor device, etc. Therefore, even if a heat treatment is performed after the addition of the impurity element or a film formation process is performed while the substrate is heated, the impurity element is not desorbed and the electrical resistance can be maintained at a low level.

[0517] As described above, the semiconductor device of one embodiment of the present invention has a structure in which a gate electric field is easily applied to the oxide semiconductor, so that the electrical characteristics of the transistor can be improved.

[0518] In addition, the semiconductor device according to one embodiment of the present invention has a structure in which parasitic capacitance between a source electrode or a drain electrode and a gate electrode and between a source electrode or a drain electrode and a gate wiring are reduced, thereby improving the frequency characteristics of a circuit using the semiconductor device.

[0519] In addition, the transistor of one embodiment of the present invention has a back gate. Therefore, the transistor of one embodiment of the present invention can have a structure that has excellent on-state characteristics, a normally-off state, and high reliability even when miniaturized.

[0520] This embodiment mode can be combined with other embodiment modes as appropriate.

[0521] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0522] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0523] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image.

[0524] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the film is formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the film is formed. In the region of the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the film is formed.

[0525] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0526] When an oxide semiconductor layer having a CAAC structure is subjected to electron beam diffraction, spots (bright points) indicating c-axis orientation are observed in the electron beam diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor layer is formed or the normal vector of the surface of the oxide semiconductor layer.

[0527] Furthermore, an FFT pattern obtained by subjecting a TEM image to a Fast Fourier Transform (FFT) process reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0528] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing for each region in the cross-sectional TEM image, and the crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that are high in brightness and are approximately equal distances from the center among the spots observed in the created FFT pattern is taken as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered as a CAAC structure.

[0529] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the layer has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and typically, hexagonal Voronoi regions are observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0530] We will now explain how to create a Voronoi diagram. First, image analysis of a TEM image involves performing FFT processing, then filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT filtered image. Lattice points are extracted from the created FFT filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal region surrounded by the line segments connecting the Voronoi points is defined as the Voronoi region. In this way, a Voronoi diagram can be created.

[0531] In the creation of a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width can be observed as an example of the observation range of the TEM, but the observation range is not limited to this.

[0532] Furthermore, when the distribution of hexagonal lattice orientations is analyzed using lattice points extracted by image analysis of planar TEM images, the difference in hexagonal lattice orientations at the boundary between two structures with different hexagonal lattice orientations is small, the boundary is observed to be blurred, and the two structures appear to be connected in a manner that seems to interpenetrate. In other words, no clear boundary is observed in the CAAC structure.

[0533] The orientation of the hexagonal lattice can be calculated by calculating the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0534] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0535] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and more preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Also, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and more preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Here, element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0536] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms are observed as bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Also, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0537] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium Examples of the metal oxide that can be used include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Examples of the metal oxide that can be used include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0538] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0539] The metal oxide may have one or more kinds of metal elements having a large period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more kinds of metal elements having a large period number in the periodic table in addition to indium. The greater the overlap of the orbits of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of a transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0540] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0541] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0542] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0543] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0544] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using two kinds of film formation methods may be referred to as a hybrid OS.

[0545] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0546] In the formation of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is formed by the first film formation method. In particular, the metal oxide formed at this time preferably has a CAAC structure. For example, a metal oxide formed by a sputtering method is likely to have crystallinity.

[0547] When a metal oxide is formed by using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy given to the substrate by the sputtering particles or the like. There is a concern that the mixed layer may hinder the crystallization of the metal oxide.

[0548] For example, when an insulating layer having silicon, for example silicon oxide, is used as a surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide by using the first film formation method. There is a concern that the crystallization of the metal oxide may be hindered by the mixing of impurities such as silicon into the metal oxide.

[0549] In view of this, in one embodiment of the present invention, before forming a metal oxide by using the first film formation method, a metal oxide is formed by using the second film formation method. That is, after forming a metal oxide as a first layer by using the second film formation method, a metal oxide is formed as a second layer on the first layer by using the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface to be formed as the second film formation method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is the surface to be formed of the oxide semiconductor layer. In addition, since the inclusion of impurities such as silicon in the second layer can be suppressed, the crystallinity can be possibly increased. For example, an atomic layer deposition (ALD) method and a chemical vapor deposition (CVD) method are suitable as the second film formation method because they can suppress damage to a surface to be formed compared to a sputtering method.

[0550] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0551] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0552] The first film formation method includes, for example, a sputtering method, a PLD method, and the like.

[0553] Examples of the second film formation method include the ALD method, the plasma enhanced CVD (PECVD) method, the thermal CVD method, the photo-CVD method, the metal organic CVD (MOCVD) method, and the molecular beam epitaxy (MBE) method. The MBE method is a film formation method for growing a thin film having a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface on which the film is formed. In addition, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that cause less damage to the surface on which the film is formed. Examples of the wet method include the spray coating method.

[0554] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, and then forming a metal oxide as a second layer by using the first film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure.

[0555] In addition, a third layer can be further formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to give crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0556] In addition, the second layer has excellent crystallinity because the effect of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0557] Note that the third layer is a top layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating film when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating film, carrier mobility can be increased when the transistor is on.

[0558] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, forming a metal oxide as a second layer by using the first film formation method, and forming a metal oxide as a third layer by using the second film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure. The ALD method is a film formation method with better coverage than the sputtering method, and the coverage of the oxide semiconductor layer can be improved by using the ALD method as the film formation method for the first layer and the third layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0559] [Method for producing oxide semiconductor layer] The oxide semiconductor layer 230 can be manufactured, for example, by forming an oxide semiconductor 230a on a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor layer 230 is formed, it is preferable to perform heat treatment. By performing the heat treatment, the crystallinity of the oxide semiconductor layer 230 can be improved. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process. The layer 229 is an insulating film, and is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0560] The oxide semiconductor layer 230 can be used as the oxide semiconductor layer 230 included in each transistor described in Embodiment 2. The layer 229 corresponds to one or more of the conductive layer 220, the insulating layer 235, the conductive layer 240, and the like described in Embodiment 2.

[0561] The layer 229 does not have to be crystalline. When the layer 229 has crystallinity, the layer 229 may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer 230.

[0562] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS.

[0563] First, an oxide semiconductor 230a is formed over the layer 229 (FIG. 20A). Then, an oxide semiconductor 230b is formed over the oxide semiconductor 230a (FIG. 20B).

[0564] The oxide semiconductor 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0565] The oxide semiconductor 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 230a is formed, as compared with a deposition method for the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0566] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage to the surface on which the film is formed. When the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described later is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0567] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, after the oxide semiconductor 230a is formed over the layer 229, the oxide semiconductor 230b is formed by a sputtering method. At this time, the oxide semiconductor 230a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed. By forming the oxide semiconductor 230a between the oxide semiconductor 230b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor 230a is to be formed, alloying between a component contained in the oxide semiconductor layer 230 and a component contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0568] With the above structure, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 20(A) and 20(B) show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor 230a.

[0569] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0570] For example, an EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a and is not the main component of the layer (here, layer 229) that will be the surface to be formed becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 230a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will be the surface to be formed and is not the main component of the oxide semiconductor 230a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will be the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0571] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0572] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0573] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0574] By thinning the alloyed region, it becomes possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer 230.

[0575] The CAAC structure near the formation surface may be observed by TEM observation. For example, in a cross-sectional observation of the oxide semiconductor layer 230 by high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed near the formation surface.

[0576] Note that when the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than that of a CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 20A, the oxide semiconductor 230a may have a region with lower crystallinity than the oxide semiconductor 230b.

[0577] After the oxide semiconductor 230a is formed by the ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 230b on the oxide semiconductor 230a by the sputtering method.

[0578] Here, when the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. In addition, when the oxide semiconductor 230b is formed, a minute crystal region may be formed in the mixed layer 231 due to sputtering particles or energy given to the substrate side by the sputtering particles or the like. In a subsequent heat treatment process, the mixed layer 231 or the minute crystal region formed in the mixed layer 231 may become a nucleus, and at least a part of the oxide semiconductor 230a may be crystallized.

[0579] In-Mn-Zn oxide can be used as a target for the sputtering method. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0580] Furthermore, there are cases where a metal oxide having higher crystallinity can be formed as the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as oxygen flow rate ratio) is higher.

[0581] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the transistor is formed. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0582] In forming the oxide semiconductor 230b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In forming the oxide semiconductor 230b by sputtering, the substrate heating temperature is preferably, for example, 100°C to 400°C, and more preferably 200°C to 300°C.

[0583] Through the above steps, as shown in FIG. 20B, an oxide semiconductor 230a can be formed over the layer 229 and an oxide semiconductor 230b can be formed over the oxide semiconductor 230a.

[0584] Next, the oxide semiconductor 230c is formed over the oxide semiconductor 230b (FIG. 20C). Here, the oxide semiconductor 230c is formed by an ALD method. For the formation of the oxide semiconductor 230c by the ALD method, the method for forming the oxide semiconductor 230a can be referred to.

[0585] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially with the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0586] A heat treatment step may then be performed.

[0587] The temperature of the heat treatment can be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the temperature can be 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment can repair the gaps in the crystal parts at the atomic level of the CAAC structure of the oxide semiconductor 230b by the oxide semiconductor 230c (in other words, the crystal molecules formed by the ALD method).

[0588] There is no particular limitation on the heating device used for the heat treatment, and it may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

[0589] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. When the region is formed only below the oxide semiconductor 230c after the ALD process, the heat treatment step may cause the region to expand upward ( FIG. 20D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer in the oxide semiconductor 230c.

[0590] It is also preferable that at least a part of the oxide semiconductor 230a is converted into CAAC by the heat treatment process (FIG. 20(D)). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of the oxide semiconductor 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is large, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0591] Furthermore, because the CAAC process occurs from the top to the bottom of the oxide semiconductor 230a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if t...

Claims

1. a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first insulating layer overlies the first conductive layer; the second conductive layer is located on the first insulating layer; the second insulating layer overlies the second conductive layer; the third conductive layer is located on the second insulating layer; the first conductive layer has a first recess; the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping the first recess; the third insulating layer is in contact with at least a side surface of the second conductive layer within the first opening; the oxide semiconductor layer is in contact with an upper surface of the third conductive layer and a bottom surface and a side surface of the first recess, and is in contact with the third insulating layer within the first opening; the fourth insulating layer is located inside the first opening relative to the oxide semiconductor layer, the fourth conductive layer is located inside the first opening and on the inner side of the fourth insulating layer; a second insulating layer formed on the second conductive layer and a fourth insulating layer formed on the fourth conductive layer, the second insulating layer being sandwiched between the second conductive layer and the fourth conductive layer, the fourth ... fourth conductive layer and the third conductive layer;

2. In claim 1, A fifth insulating layer is provided. the first conductive layer and the second insulating layer are located on the fifth insulating layer; A semiconductor device, wherein the shortest distance from an upper surface of the fifth insulating layer to an upper surface of the first conductive layer that is in contact with the first insulating layer is longer than the shortest distance from the upper surface of the fifth insulating layer to a lower surface of the fourth insulating layer.

3. In claim 1, A fifth insulating layer is provided. the first conductive layer and the fourth conductive layer are located on the fifth insulating layer; a shortest distance from an upper surface of the fifth insulating layer to an upper surface of the first conductive layer that is in contact with the first insulating layer is greater than or equal to a shortest distance from the upper surface of the fifth insulating layer to a lower surface of the fourth conductive layer.

4. In claim 1, the first conductive layer has a fifth conductive layer and a sixth conductive layer on the fifth conductive layer; the sixth conductive layer has a second recess; the first opening overlaps with the second recess; the oxide semiconductor layer is in contact with a bottom surface and side surfaces of the second recess.

5. In claim 1, A sixth insulating layer is provided. the fourth insulating layer covers an upper surface and a side surface of the oxide semiconductor layer on the second insulating layer; the sixth insulating layer is located on the fourth insulating layer and has a second opening at a position overlapping the first opening; the fourth conductive layer has a portion that overlaps with the oxide semiconductor layer in the first opening with the fourth insulating layer interposed therebetween, and a portion that is located in the second opening.

6. In claim 1, A sixth insulating layer is provided. the sixth insulating layer is located on the second insulating layer, covers an upper surface and a side surface of the oxide semiconductor layer on the second insulating layer, and has a second opening at a position overlapping with the first opening; the fourth insulating layer has a portion located within the second opening; The fourth conductive layer is located inside the second opening and closer to the fourth insulating layer.

7. In claim 1, the third insulating layer includes a seventh insulating layer in contact with the oxide semiconductor layer and an eighth insulating layer located outside the seventh insulating layer in the first opening, one of the seventh insulating layer and the eighth insulating layer is an oxide insulating layer, and the other is a nitride insulating layer.

8. In claim 1, a fifth insulating layer and a fifth conductive layer; the fifth insulating layer is located on the fourth insulating layer and has a second opening that reaches the fourth conductive layer at a position overlapping with the first opening; The fifth conductive layer is in contact with the fourth conductive layer within the second opening.

9. a first layer and a second layer on the first layer, the second layer includes a first memory cell array and a second memory cell array; the first memory cell array includes a plurality of first memory cells; the second memory cell array includes a plurality of second memory cells; the first layer has a transistor having silicon in a channel formation region; each of the first memory cell and the second memory cell includes a vertical transistor; the vertical transistor has an oxide semiconductor in a channel formation region, The first memory cell and the second memory cell have different configurations.

10. a first layer, a second layer on the first layer, and a third layer on the second layer; the second layer having a first memory cell array; the third layer includes a second memory cell array; the first memory cell array includes a plurality of first memory cells; the second memory cell array includes a plurality of second memory cells; the first layer has a transistor having silicon in a channel formation region; each of the first memory cell and the second memory cell includes a vertical transistor; the vertical transistor has an oxide semiconductor in a channel formation region, The first memory cell and the second memory cell have different configurations.

11. In claim 9 or 10, A semiconductor device, wherein one of the first memory cell and the second memory cell can retain information for a longer period in a state where no power is supplied to the memory cell than the other of the first memory cell and the second memory cell.

12. a first layer and a second layer on the first layer, the second layer includes a first memory cell array and a second memory cell array; the first memory cell array includes a plurality of first memory cells; the second memory cell array includes a plurality of second memory cells; the first layer has a transistor having silicon in a channel formation region; the first memory cell is composed of one vertical transistor and one capacitance element; The second memory cell is composed of two vertical transistors, a vertical transistor included in the first memory cell and a vertical transistor included in the second memory cell each include an oxide semiconductor in a channel formation region.

13. a first layer, a second layer on the first layer, and a third layer on the second layer; the second layer having a first memory cell array; the third layer includes a second memory cell array; the first memory cell array includes a plurality of first memory cells; the second memory cell array includes a plurality of second memory cells; the first layer has a transistor having silicon in a channel formation region; one of the first memory cell and the second memory cell is composed of one vertical transistor and one capacitance element, and the other is composed of two vertical transistors; a vertical transistor included in the first memory cell and a vertical transistor included in the second memory cell each include an oxide semiconductor in a channel formation region.

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