Oxide semiconductor layer, method for forming the oxide semiconductor layer, semiconductor device, and method for manufacturing the semiconductor device

Abstract

To provide: a transistor with favorable electrical characteristics; a transistor with a high on-state current; a transistor with low parasitic capacitance; or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated.SOLUTION: There is provided a transistor including an oxide semiconductor layer, a semiconductor device, or a memory device. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further increasing the density of integrated circuits. There is also a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] Furthermore, Non-Patent Document 2 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] JP 2013-211537 A [Non-patent literature]

[0011] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 [Non-Patent Document 2] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO:FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp.50-150 Summary of the Invention [Problem to be solved by the invention]

[0012] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Another object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, display device, or memory device. Another object of one embodiment of the present invention is to provide a semiconductor device, display device, or memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operation speed. Another object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, display device, or memory device.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0014] One embodiment of the present invention is an oxide semiconductor layer containing indium, the oxide semiconductor layer having a first region, a second region on the first region, and a third region on the second region, the first region being located at a distance of 0 nm to 3 nm from a surface on which the oxide semiconductor layer is to be formed in a direction substantially perpendicular to the surface, and bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope.

[0015] In the above embodiment, it is preferable that the second region contains zinc, the second region contains crystals, and a c-axis of the crystals is approximately parallel to a normal direction to a surface on which the oxide semiconductor layer is formed.

[0016] In the above aspect, the c-axis orientation rate in the second region is preferably higher than the c-axis orientation rate in the first region.

[0017] In the above aspect, the c-axis orientation rate in the third region is preferably higher than the c-axis orientation rate in the first region.

[0018] In the above aspect, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0019] Another embodiment of the present invention is a method for forming an oxide semiconductor layer by forming a first metal oxide, forming a second metal oxide over the first metal oxide, and forming a third metal oxide over the second metal oxide, in which each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidant, and the second metal oxide is formed by a sputtering method using a sputtering target containing indium.

[0020] In the above embodiment, it is preferable that the sputtering target contains zinc, and the sputtering method is carried out in an atmosphere containing oxygen.

[0021] In the above embodiment, the temperature for heating the substrate in the ALD method is preferably 100° C. or higher and 350° C. or lower.

[0022] In the above embodiment, it is preferable that, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer is formed are confirmed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

[0023] In the above embodiment, it is preferable that no clear boundary is observed between the first metal oxide and the second metal oxide, and no clear boundary is observed between the second metal oxide and the third metal oxide.

[0024] In the above embodiment, it is preferable to perform a heat treatment at 350° C. or higher and 550° C. or lower after forming the third metal oxide on the second metal oxide.

[0025] Alternatively, one embodiment of the present invention includes a transistor over a first insulating layer and a second insulating layer. The transistor includes a first conductive layer over the first insulating layer, a second conductive layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode. The second insulating layer is located between the first conductive layer and the second conductive layer, the second conductive layer is located over the second insulating layer, the second insulating layer and the second conductive layer have a first opening reaching the first conductive layer, the oxide semiconductor layer is in contact with a side surface of the second insulating layer in the first opening and a side surface of the second conductive layer in the first opening, and the gate electrode is formed between the first conductive layer and the second conductive layer. the insulating layer is located on the oxide semiconductor layer; the gate electrode has a region in the first opening that overlaps with the oxide semiconductor layer with the gate insulating layer sandwiched therebetween; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed; and bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region when a cross-section of the oxide semiconductor layer is observed using a transmission electron microscope.

[0026] In addition, in the above aspect, it is preferable that the side surface of the second insulating layer in the first opening has a fourth region that forms an angle with the top surface of the first conductive layer of 75 degrees or more and 90 degrees or less, and that the first region is in contact with the fourth region.

[0027] Alternatively, one embodiment of the present invention includes forming a first insulating layer over a first conductive layer, forming a second conductive layer over the first insulating layer, forming a first opening reaching the first conductive layer by removing a part of the second conductive layer and a part of the first insulating layer to expose a top surface of the first conductive layer, forming a first metal oxide in contact with the top surface of the first conductive layer, a side surface of the first opening of the first insulating layer, a side surface of the first opening of the second conductive layer, and a top surface of the second conductive layer, respectively, and forming a second metal oxide on the first metal oxide. a third metal oxide on the second metal oxide, a second insulating layer in contact with an upper surface of the third metal oxide, and a third conductive layer on the second insulating layer; each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizer, and the second metal oxide is formed by a sputtering method using a sputtering target containing indium.

[0028] In the above embodiment, the third conductive layer is preferably formed by a metal CVD method at a temperature of 250° C. or higher. Effect of the Invention

[0029] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a transistor with large on-state current can be provided. According to another embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to another embodiment of the present invention, a highly reliable transistor, a semiconductor device, a display device, or a memory device can be provided. According to another embodiment of the present invention, a semiconductor device, a display device, or a memory device with low power consumption can be provided. According to another embodiment of the present invention, a memory device with high operation speed can be provided. According to another embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, display device, or memory device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0031] [Figure 1] 1A to 1D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. [Diagram 2] 2A to 2D are cross-sectional views illustrating examples of oxide semiconductors. [Diagram 3] 3A to 3E are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 4] 4A to 4D are diagrams illustrating atomic arrangements of metal oxides according to one embodiment of the present invention. [Diagram 5] 5A to 5D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 6] 6A to 6C are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 7] Fig. 7(A) is a plan view showing an example of a semiconductor device, and Fig. 7(B) and Fig. 7(C) are cross-sectional views showing an example of the semiconductor device. [Figure 8] FIG. 8 is a cross-sectional view showing an example of a semiconductor device. [Figure 9] 9(A) and 9(B) are cross-sectional views showing an example of a semiconductor device. [Figure 10] Fig. 10(A) is a plan view showing an example of a semiconductor device, and Fig. 10(B) and Fig. 10(C) are cross-sectional views showing an example of a semiconductor device. [Figure 11] Fig. 11(A) is a plan view showing an example of a semiconductor device, and Fig. 11(B) is a cross-sectional view showing an example of the semiconductor device. [Figure 12] Fig. 12(A) is a plan view showing an example of a semiconductor device, and Fig. 12(B) is a cross-sectional view showing an example of a semiconductor device. [Figure 13] 13A to 13C are cross-sectional views showing an example of a semiconductor device. [Figure 14] Fig. 14(A) is a plan view showing an example of a semiconductor device, and Fig. 14(B) and Fig. 14(C) are cross-sectional views showing an example of a semiconductor device. [Figure 15] Fig. 15(A) is a plan view showing an example of a semiconductor device, and Fig. 15(B) and Fig. 15(C) are cross-sectional views showing an example of a semiconductor device. [Figure 16] 16A to 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 17] Fig. 17(A) is a plan view showing an example of a memory device, and Fig. 17(B) and Fig. 17(C) are cross-sectional views showing an example of the memory device. [Figure 18] 18(A) and 18(B) are cross-sectional views showing an example of a memory device. [Figure 19] Fig. 19(A) is a plan view showing an example of a storage device, and Fig. 19(B) is a cross-sectional view showing an example of the storage device. [Figure 20] FIG. 20 is a cross-sectional view showing an example of a storage device. [Figure 21] FIG. 21 is a cross-sectional view showing an example of a storage device. [Figure 22] FIG. 22 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 23] 23A to 23H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 24] 24A and 24B are perspective views illustrating a configuration example of a semiconductor device. [Diagram 25] FIG. 25 is a block diagram illustrating the CPU. [Figure 26] 26(A) and 26(B) are perspective views of the semiconductor device. [Figure 27] 27(A) and 27(B) are perspective views of a semiconductor device. [Figure 28] 28(A) and 28(B) are diagrams showing various storage devices by hierarchical level. [Figure 29] 29(A) and 29(B) are perspective views showing an example of a display device. [Diagram 30] FIG. 30 is a cross-sectional view showing an example of a display device. [Diagram 31] FIG. 31 is a cross-sectional view showing an example of a display device. [Diagram 32] 32A to 32C are diagrams showing configuration examples of display devices. [Diagram 33] 33(A) and 33(B) are diagrams showing an example of an electronic component. [Diagram 34] Fig. 34(A) to Fig. 34(C) are diagrams showing an example of a mainframe computer. Fig. 34(D) is a diagram showing an example of space equipment. Fig. 34(E) is a diagram showing an example of a storage system applicable to a data center. [Diagram 35] 35(A) to 35(F) are diagrams showing examples of electronic devices. [Diagram 36] 36A to 36G are diagrams illustrating examples of electronic devices. [Figure 37] 37A to 37F are diagrams showing examples of electronic devices. [Figure 38] FIG. 38 is a circuit diagram used in the circuit simulation. [Figure 39] 39(A) and 39(B) are timing charts explaining the operation of the circuit. [Diagram 40] 40(A) and 40(B) are diagrams showing the Id-Vg characteristics of a transistor. [Diagram 41] 41(A) and 41(B) are diagrams showing the Id-Vg characteristics of a transistor. [Diagram 42] 42(A) and 42(B) are diagrams showing the Id-Vg characteristics of a transistor. [Diagram 43] 43(A) and 43(B) are diagrams showing the Id-Vd characteristics of a transistor. [Diagram 44] 44(A) to 44(C) are diagrams showing orientation mapping. [Diagram 45] 45(A) and 45(B) are diagrams showing a TEM image and an FFT image. [Figure 46] 46(A) and 46(B) are diagrams showing orientation mapping. [Figure 47] 47(A) and 47(B) are diagrams showing a TEM image and an FFT image. [Figure 48] 48(A) and 48(B) are diagrams showing the c-axis orientation rate. [Figure 49] 49(A) and 49(B) are diagrams showing the c-axis orientation rate. [Figure 50] 50(A) to 50(D) are diagrams showing the results of SIMS analysis. [Figure 51] 51(A) and 51(B) are diagrams showing the Id-Vg characteristics of a transistor. [Figure 52] 52(A) and 52(B) are diagrams showing the Id-Vg characteristics of a transistor. [Figure 53] 53A and 53B are diagrams showing the Id-Vg characteristics of a transistor, and the Id-Vd characteristics of a transistor, respectively. [Figure 54] 54A and 54B are diagrams showing the Id-Vg characteristics of a transistor, and the Id-Vd characteristics of a transistor, respectively. [Figure 55] 55A and 55B are diagrams showing the Id-Vg characteristics of a transistor, and the Id-Vd characteristics of a transistor, respectively. [Figure 56] 56(A) and 56(B) are diagrams showing the Id-Vg characteristics of a transistor. [Figure 57] 57(A) and 57(B) are diagrams showing the Id-Vg characteristics of a transistor. [Figure 58] FIG. 58 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 59] FIG. 59 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 60] 60(A) and 60(B) are diagrams showing the results of a circuit simulation. [Figure 61] 61(A) and 61(B) are diagrams showing the results of a circuit simulation. [Figure 62] 62(A) and 62(B) are diagrams showing the results of a circuit simulation. [Figure 63] 63(A) and 63(B) are diagrams showing the results of a circuit simulation. [Figure 64] FIG. 64 is a diagram showing the measurement results of the cutoff frequency. [Figure 65] FIG. 65 shows the results of XPS analysis. [Figure 66] 66(A) and 66(B) are diagrams showing the Id-Vg characteristics and the Ig-Vg characteristics of a transistor. [Figure 67] FIG. 67 is a diagram showing the Id-Vg characteristics and Ig-Vg characteristics of a transistor. [Figure 68] FIG. 68 shows the results of SIMS analysis. [Figure 69] FIG. 69 shows a TEM image. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0033] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0034] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0035] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0036] A transistor is a type of semiconductor element and can realize a function of amplifying a current or voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0037] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor, and a transistor having silicon in a channel formation region may be referred to as a Si transistor.

[0038] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0039] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0040] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities may, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V O In some cases, a junction (also referred to as a junction) may be formed.

[0041] In this specification and the like, an oxynitride refers to a material having a composition containing more oxygen than nitrogen, and a nitride oxide refers to a material having a composition containing more nitrogen than oxygen.

[0042] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used to analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in the film. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0043] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0044] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0045] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements having various functions.

[0046] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source in an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0047] In this specification, the normally-on characteristic refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the normally-off characteristic refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0048] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0049] In this specification, the phrase "top surface shapes are substantially the same" refers to at least a portion of the contours of the stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case, it may also be said that the top surface shapes are substantially the same. In addition, when the top surface shapes are the same or substantially the same, it can also be said that the ends are aligned or substantially aligned, or that the side ends are aligned or substantially aligned.

[0050] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side of the structure and the substrate surface or the surface on which the structure is to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with a slight unevenness.

[0051] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0052] In this specification and the like, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0053] In this specification and the like, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as, A has a region that covers B.

[0054] In this specification and the like, when it is stated that A overlaps with B, at least a portion of A overlaps with B. Therefore, for example, this can be rephrased as saying that A has a region that overlaps with B.

[0055] In this specification, a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0056] In this specification and the like, a structure in which light-emitting layers are separately created for light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the material and configuration to be optimized for each light-emitting element, increasing the freedom of material and configuration selection and making it easier to improve brightness and reliability.

[0057] In this specification and the like, holes or electrons may be referred to as "carriers". Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer", a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer", and a hole block layer or an electron block layer may be referred to as a "carrier block layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Also, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0058] In this specification etc., the light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification etc., the light-receiving element (also called a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification etc., one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0059] In this specification and the like, a sacrificial layer (which may also be referred to as a mask layer) is located at least above a light-emitting layer (more specifically, a layer that is processed into an island shape among layers that constitute the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0060] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like EL layer refers to a state in which the EL layer is physically separated from the adjacent EL layer.

[0061] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (for example, a step or the like).

[0062] In addition, in the drawings and the like related to this specification, arrows indicating the X direction, Y direction, and Z direction may be attached. In addition, in this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." In addition, the X direction, the Y direction, and the Z direction are directions that intersect with each other. For example, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other.

[0063] (Embodiment 1) In this embodiment, an oxide semiconductor layer according to one embodiment of the present invention will be described. The oxide semiconductor layer according to one embodiment of the present invention is preferably used as a semiconductor layer of a transistor. When the oxide semiconductor layer according to one embodiment of the present invention is used as a semiconductor layer of a transistor, the oxide semiconductor layer preferably has a channel formation region. In addition, the oxide semiconductor layer preferably has a source region and a drain region.

[0064] [Oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of the metal oxide having crystallinity include a c-axis aligned crystalline (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0065] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image.

[0066] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface on which the oxide semiconductor layer is formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is formed.

[0067] The polycrystalline structure has crystal grain boundaries. When a heat treatment is performed after forming an oxide semiconductor layer having a polycrystalline structure, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the oxide semiconductor layer, the electric resistance of the oxide semiconductor layer increases. This is because the electric resistance of the minute gap or the minute space is very high, for example, infinite. When an oxide semiconductor layer having a minute gap or a minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In the CAAC structure, a crystal grain boundary is not clearly observed in the ab plane, and therefore a highly reliable semiconductor device can be realized. In addition, since there are few crystal grain boundaries, an energy barrier against carrier conduction in the channel of the transistor is small, and an improvement in on-current is expected.

[0068] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0069] When an oxide semiconductor layer having a CAAC structure is subjected to electron beam diffraction, spots (bright points) indicating c-axis orientation are observed in the electron beam diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor layer is formed or the normal vector of the surface of the oxide semiconductor layer.

[0070] Furthermore, an FFT pattern obtained by performing a Fast Fourier Transform (FFT) process on a TEM image reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0071] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing for each region in the cross-sectional TEM image, and the crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equal distances from the center among the spots observed in the created FFT pattern is set as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably within 90°±20° (70° or more and 110° or less) with respect to the surface on which the oxide semiconductor layer is formed, more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) can be regarded as a CAAC structure.

[0072] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the layer has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and typically, hexagonal Voronoi regions are observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0073] We will now explain how to create a Voronoi diagram. First, image analysis of a TEM image involves performing FFT processing, then filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT filtered image. Lattice points are extracted from the created FFT filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal region surrounded by the line segments connecting the Voronoi points is defined as the Voronoi region. In this way, a Voronoi diagram can be created.

[0074] In the creation of a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width may be observed as an example of the observation range of the TEM, but the observation range is not limited to this.

[0075] Furthermore, when the distribution of hexagonal lattice orientations is analyzed using lattice points extracted by image analysis of planar TEM images, the difference in hexagonal lattice orientations at the boundary between two structures with different hexagonal lattice orientations is small, the boundary is observed to be blurred, and the two structures appear to be connected in a manner that seems to interpenetrate. In other words, no clear boundary is observed in the CAAC structure.

[0076] The orientation of the hexagonal lattice can be calculated from the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0077] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0078] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and more preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Also, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and more preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Here, element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0079] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms arranged in layers are observed as a row of bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Also, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0080] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium Examples of the metal oxide that can be used include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Examples of the metal oxide that can be used include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0081] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0082] The metal oxide may have one or more kinds of metal elements having a large period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more kinds of metal elements having a large period number in the periodic table in addition to indium. The greater the overlap of the orbits of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of a transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0083] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0084] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0085] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0086] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0087] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using two kinds of film formation methods may be referred to as a hybrid OS.

[0088] In the formation of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is formed by the first film formation method. In particular, the metal oxide formed at this time preferably has a CAAC structure. For example, a metal oxide formed by a sputtering method is likely to have crystallinity.

[0089] When a metal oxide is formed by using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy given to the substrate by the sputtering particles or the like. There is a concern that the mixed layer may hinder the crystallization of the metal oxide.

[0090] For example, when an insulating layer having silicon, for example silicon oxide, is used as a surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide by using the first film formation method. There is a concern that the crystallization of the metal oxide may be hindered by the mixing of impurities such as silicon into the metal oxide.

[0091] In view of this, in one embodiment of the present invention, before forming a metal oxide by using the first film formation method, a metal oxide is formed by using the second film formation method. That is, after forming a metal oxide as a first layer by using the second film formation method, a metal oxide is formed as a second layer on the first layer by using the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface to be formed as the second film formation method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is the surface to be formed of the oxide semiconductor layer. In addition, since the inclusion of impurities such as silicon in the second layer can be suppressed, the crystallinity can be possibly increased. For example, an atomic layer deposition (ALD) method and a chemical vapor deposition (CVD) method are suitable as the second film formation method because they can suppress damage to a surface to be formed compared to a sputtering method.

[0092] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0093] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0094] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0095] Examples of the second film formation method include the ALD method, the plasma enhanced CVD (PECVD) method, the thermal CVD method, the photo-CVD method, the metal organic CVD (MOCVD) method, and the molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface on which the film is formed. In addition, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that cause less damage to the surface on which the film is formed. For example, a spray coating method can be used as the wet method.

[0096] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, and then forming a metal oxide as a second layer by using the first film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure.

[0097] A third layer can also be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to have crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by using a film formation method that has higher coverage than the second layer as the third layer, the oxide semiconductor layer can have both high crystallinity and high coverage in the entire layer. Also, for example, by using a film formation method that causes less damage than the second layer as the third layer, damage to the second layer is reduced, and the oxide semiconductor layer can have high crystallinity in the entire layer.

[0098] In addition, the second layer has excellent crystallinity because the effect of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0099] Note that the third layer is the uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor described later. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0100] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, forming a metal oxide as a second layer by using the first film formation method, and forming a metal oxide as a third layer by using the second film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure. The ALD method is a film formation method with better coverage than the sputtering method, and the coverage of the oxide semiconductor layer can be improved by using the ALD method as the film formation method for the first layer and the third layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0101] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using the reactive sputtering method.

[0102] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0103] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of a high substrate temperature condition during film formation and an impurity removal treatment, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.

[0104] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0105] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. In addition, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0106] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0107] [Method for producing oxide semiconductor layer] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS.

[0108] The oxide semiconductor layer 230 can be manufactured, for example, by forming an oxide semiconductor layer 230a on a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor layer 230b on the oxide semiconductor layer 230a by a sputtering method, and forming an oxide semiconductor layer 230c on the oxide semiconductor layer 230b by an ALD method. After the oxide semiconductor layer 230 is formed, it is preferable to perform heat treatment. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process. The layer 229 is an insulating film, and is, for example, an insulating film of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. As the layer 229, a film to be described later as an insulator included in a semiconductor device can be used.

[0109] Alternatively, a conductive film may be used as the layer 229. For example, the oxide semiconductor layer 230 can be formed over a conductive film which functions as an electrode of a semiconductor device.

[0110] The layer 229 does not need to have crystallinity. In other words, the layer 229 may have an amorphous structure. When the layer 229 has crystallinity, the layer 229 may have a crystal structure that has low lattice matching with a metal oxide included in the oxide semiconductor layer 230.

[0111] First, an oxide semiconductor layer 230a is formed over the layer 229 (FIG. 1A). Then, an oxide semiconductor layer 230b is formed over the oxide semiconductor layer 230a (FIG. 1B).

[0112] The oxide semiconductor layer 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0113] The oxide semiconductor layer 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor layer 230a is formed, as compared with the deposition method for the oxide semiconductor layer 230b. Here, the oxide semiconductor layer 230a is formed by an ALD method.

[0114] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage to the surface on which the film is formed. When the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described later is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0115] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, after the oxide semiconductor layer 230a is formed over the layer 229, the oxide semiconductor layer 230b is formed by a sputtering method. At this time, the oxide semiconductor layer 230a is preferably formed by a deposition method that causes little damage to the surface of the layer 229. By forming the oxide semiconductor layer 230a between the oxide semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to the surface of the layer 229, alloying of a component contained in the oxide semiconductor layer 230 and a component contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0116] With the above structure, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 1A and 1B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor layer 230a.

[0117] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0118] For example, an EDX line analysis is performed on the alloyed region and its periphery with the direction perpendicular to the surface of the oxide semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor layer 230a contains In) that is the main component of the oxide semiconductor layer 230a and is not the main component of the layer (here, layer 229) that is the surface to be formed becomes half-value is defined as the depth (position) of the interface between the alloyed region and the oxide semiconductor layer 230a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer 229 and is not the main component of the oxide semiconductor layer 230a becomes half-value is defined as the depth (position) of the interface between the alloyed region and the layer 229. From the above, the thickness of the alloyed region can be calculated.

[0119] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0120] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0121] By setting the thickness t_s2 to a value within the above range, the thickness of the alloyed region can be made thin, and thus the thickness t_s2 can be set to a value within the above range.

[0122] By reducing the thickness of the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer 230.

[0123] The CAAC structure near the formation surface may be observed by TEM observation. For example, in a cross-sectional observation of the oxide semiconductor layer 230 by high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed near the formation surface.

[0124] Alternatively, the CAAC structure near the surface to be formed may be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. The FFT pattern reflects reciprocal lattice space information similar to that of an electron beam diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) with respect to the surface to be formed of the oxide semiconductor layer can be regarded as a CAAC structure.

[0125] When the oxide semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than that of a CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 1A, the oxide semiconductor layer 230a may have a region with lower crystallinity than the oxide semiconductor layer 230b.

[0126] Here, a method of forming an In-M-Zn oxide as the oxide semiconductor layer 230a by the ALD method will be described. The details of the formation of a metal oxide by the ALD method will be described later.

[0127] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 229. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0128] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer in which indium and oxygen are combined by desorbing components other than indium while leaving indium adsorbed on the substrate. Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0129] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0130] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer in which element M and oxygen are combined, while element M is still adsorbed on the substrate, by desorbing components other than element M. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0131] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer of the combined element M and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0132] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, for example, the substrate heating temperature is 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0133] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, forming a layer in which zinc and oxygen are combined. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0134] Next, a layer of indium and oxygen is formed again on the layer of zinc and oxygen by the above-mentioned method. By repeating the above-mentioned method, an In-M-Zn oxide can be formed as the oxide semiconductor layer 230a on the layer 229 by the ALD method.

[0135] In the ALD method, the composition of the film obtained can be controlled by the amount of the raw material gas introduced. For example, in the ALD method, a film of any composition can be formed by adjusting the amount of the raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like. In addition, for example, in the ALD method, a film whose composition changes continuously can be formed by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened by not requiring the time required for transport and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0136] After the oxide semiconductor layer 230a is formed by the ALD method, an In-M-Zn oxide is formed as the oxide semiconductor layer 230b on the oxide semiconductor layer 230a by the sputtering method.

[0137] Here, when the oxide semiconductor layer 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor layer 230a. In addition, when the oxide semiconductor layer 230b is formed, a minute crystal region may be formed in the mixed layer 231 due to sputtering particles or energy given to the substrate side by the sputtering particles or the like. In a subsequent heat treatment process, the mixed layer 231 or the minute crystal region formed in the mixed layer 231 may become a nucleus, and at least a part of the oxide semiconductor layer 230a may be crystallized.

[0138] In-M-Zn oxide can be used as a target for the sputtering method. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0139] Furthermore, there are cases where a metal oxide having higher crystallinity can be formed as the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as oxygen flow rate ratio) is higher.

[0140] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the metal oxide is formed. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0141] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to that of the sputtering target.

[0142] In forming the oxide semiconductor layer 230b by the sputtering method, it is preferable to heat the substrate. In forming the metal oxide, the substrate temperature (stage temperature) may be increased during the formation of the metal oxide to form a metal oxide with high crystallinity. In forming the oxide semiconductor layer 230b by the sputtering method, the substrate heating temperature is preferably 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0143] Through the above steps, as shown in FIG. 1B, an oxide semiconductor layer 230a can be formed over the layer 229 and an oxide semiconductor layer 230b can be formed over the oxide semiconductor layer 230a.

[0144] Next, the oxide semiconductor layer 230c is formed on the oxide semiconductor layer 230b (FIG. 1C). Here, the oxide semiconductor layer 230c is formed by the ALD method. For the formation of the oxide semiconductor layer 230c by the ALD method, the method for forming the oxide semiconductor layer 230a can be referred to.

[0145] When an oxide semiconductor layer 230c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor layer 230b having a CAAC structure by using an ALD method, the oxide semiconductor layer 230c may grow epitaxially with the oxide semiconductor layer 230b as a nucleus. Therefore, when the oxide semiconductor layer 230c is formed, the oxide semiconductor layer 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor layer 230c.

[0146] A heat treatment step may then be performed.

[0147] The temperature of the heat treatment may be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The temperature may be typically 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair gaps in the crystal parts at the atomic level of the CAAC structure of the oxide semiconductor layer 230b by the oxide semiconductor layer 230c (in other words, the crystal molecules formed by the ALD method).

[0148] There is no particular limitation on the heating device used for the heat treatment, and it may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

[0149] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor layer 230c. In addition, when the region having the CAAC structure is formed only below the oxide semiconductor layer 230c after the film formation by the ALD method, the heat treatment step may cause the region having the CAAC structure to expand upward (FIG. 1(D)). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire oxide semiconductor layer 230c.

[0150] In addition, the heat treatment process may further repair the oxide semiconductor layer 230b by the oxide semiconductor layer 230c (in other words, the crystal molecules formed by the ALD method) that fills gaps in the atomic-level crystal parts of the CAAC structure of the oxide semiconductor layer 230b.

[0151] It is also preferable that at least a part of the oxide semiconductor layer 230a is converted into CAAC by the heat treatment process (FIG. 1(D)). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor layer 230a during the deposition of the oxide semiconductor layer 230b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor layer 230a that is converted into CAAC is large, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0152] Furthermore, because the CAAC process is performed from the top to the bottom of the oxide semiconductor layer 230a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor layer 230a can have high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0153] 1A to 1D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 1A to 1D can also be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention. As illustrated in FIG. 1A to 1D, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c each have high crystallinity using the oxide semiconductor layer 230b having high crystallinity as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor layer 230a may be increased by heat treatment during the formation of the oxide semiconductor layer 230b or after the formation of the oxide semiconductor layer 230c. The crystallinity of the oxide semiconductor layer 230c may be increased by heat treatment during the formation of the oxide semiconductor layer 230c or after the formation of the oxide semiconductor layer 230c. Note that the heat treatment has an assisting effect for increasing crystallinity.

[0154] In this manner, in the method for forming a metal oxide film according to one embodiment of the present invention, the highly crystalline oxide semiconductor layer 230b (i.e., CAAC) can be used as a nucleus or seed to increase the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor layer 230a and the oxide semiconductor layer 230c in this case). This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the oxide semiconductor layer 230b as a nucleus or seed to form an oxide semiconductor with high crystallinity. An oxide semiconductor formed using such a film formation method, that is, a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0155] In the entire oxide semiconductor layer 230 including the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, it is preferable that a region having a CAAC structure is widely present throughout the entire layer. FIG. 2A shows the state in which the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c are crystallized. In the oxide semiconductor layer 230a, the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor layer 230b through crystals. In the oxide semiconductor layer 230c, the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor layer 230b through crystals. As a result, the boundary between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b may not be observed. Also, the boundary between the oxide semiconductor layer 230b and the oxide semiconductor layer 230c may not be observed. The oxide semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer 230 may be expressed as a single layer.

[0156] In each of the oxide semiconductor layers 230a, 230b, and 230c, in a region having the CAAC structure, for example, in cross-sectional observation using a high-resolution TEM, bright points aligned parallel to the surface on which the oxide semiconductor layer 230a is formed are confirmed. In addition, it is preferable that the c-axis of the CAAC structure of each of the oxide semiconductor layers 230a, 230b, and 230c is approximately parallel to the normal direction of the surface on which the oxide semiconductor layer 230a is formed.

[0157] Also, a part of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c may not be crystallized. Also, a part of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c may have a region with lower crystallinity than the CAAC structure remaining. The example shown in FIG. 2B shows a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor layer 230a is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface. FIG. 2C shows a state in which the vicinity of the surface in the oxide semiconductor layer 230c is not crystallized, or a region with lower crystallinity than the CAAC structure remains near the surface. FIG. 2D shows a state in which the vicinity of the interface of the oxide semiconductor layer 230a with the layer 229 and the vicinity of the surface of the oxide semiconductor layer 230c are not crystallized, or a region with lower crystallinity than the CAAC structure remains near the interface of the oxide semiconductor layer 230a with the layer 229 and the vicinity of the surface of the oxide semiconductor layer 230c.

[0158] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of a transistor using the oxide semiconductor layer can be suppressed or initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-state current can be increased.

[0159] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0160] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 230, the boundaries between the stacked films of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c may not be visible. In particular, it may be difficult to confirm the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0161] As described above, by using a metal oxide with a high In content for a transistor, the field effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure for a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content for one or both of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, crystals that reflect the crystal orientation of the oxide semiconductor layer 230b are formed, and polycrystallization can be suppressed.

[0162] In addition, it is preferable that the degree of lattice mismatch between the crystals of the oxide semiconductor layer 230b and the crystals of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is small. This allows the oxide semiconductor layer 230a or the oxide semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor layer 230b. At this time, for example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer 230 is formed are confirmed in the oxide semiconductor layer 230a or the oxide semiconductor layer 230c.

[0163] As long as the degree of lattice mismatch between the crystals of the oxide semiconductor layer 230b and the crystals of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is small, the crystal structure of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is not particularly limited. The crystal structure of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0164] [Composition of oxide semiconductor layer] The oxide semiconductor layer 230a preferably has a different composition from the oxide semiconductor layer 230b. The oxide semiconductor layer 230c preferably has a different composition from the oxide semiconductor layer 230b. The oxide semiconductor layer 230a may have the same composition as the oxide semiconductor layer 230c. Alternatively, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may have different compositions.

[0165] As described above, the oxide semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor layer 230b can be formed by, for example, a sputtering method. The oxide semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor layer 230b preferably contains the element M in addition to zinc. By containing the element M in the oxide semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, it is possible to improve the reliability of a transistor to which the oxide semiconductor layer is applied. Specifically, the oxide semiconductor layer 230b may be made of a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0166] The oxide semiconductor layer 230b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0167] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be a metal oxide having a high ratio of In. The oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher ratio of In than the element M. By using a metal oxide having a high ratio of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0168] Alternatively, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be configured to not include the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be configured to include a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0169] Moreover, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be made of a metal oxide having a higher proportion of In than the oxide semiconductor layer 230b.

[0170] For example, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be made of a metal oxide having a higher Ga ratio than the oxide semiconductor layer 230b. For example, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be made of a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the ratio of Ga, for example, the band gaps of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be made larger than that of the oxide semiconductor layer 230b. As a result, the oxide semiconductor layer 230b is sandwiched between the oxide semiconductor layer 230a and the oxide semiconductor layer 230c having a larger band gap, and the oxide semiconductor layer 230b mainly functions as a current path (channel). By sandwiching the oxide semiconductor layer 230b between the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, it is possible to reduce trap levels at the interface of the oxide semiconductor layer 230b and in the vicinity thereof. This makes it possible to realize a buried channel type transistor in which the channel is kept away from the insulating layer interface, and to increase the field effect mobility. In addition, the influence of the interface state that may be formed on the back channel side is reduced, and light deterioration (e.g., negative bias light deterioration) of the transistor can be suppressed, thereby improving the reliability of the transistor.

[0171] Alternatively, one of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be a metal oxide having a higher proportion of In than the oxide semiconductor layer 230b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor layer 230b.

[0172] The oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c may each have a plurality of layers having the above-described compositions stacked together. For example, the oxide semiconductor layer 230c may have a structure in which a metal oxide having a high proportion of Ga is stacked on a metal oxide having a high proportion of In.

[0173] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductor layer 230a and the oxide semiconductor layer 230c are formed using compositions that make it difficult to form a CAAC structure when they are formed as a single layer, crystal growth occurs with the oxide semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c and in a region including the oxide semiconductor layer 230b.

[0174] In particular, even when the oxide semiconductor layers 230a and 230c have a composition with a high In content, the oxide semiconductor layers 230a and 230c can have suitable crystallinity for use as semiconductor layers of transistors. In the oxide semiconductor layer of one embodiment of the present invention, the high In content can improve the on-state characteristics of the transistor, and the CAAC structure with high crystallinity can improve reliability.

[0175] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be made of a metal oxide having the same composition as the oxide semiconductor layer 230b. By using the same composition, CAAC may be easily generated after heat treatment.

[0176] In addition, an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have one or more of a higher dielectric constant, a higher film density, and a higher film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0177] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0178] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0179] [Oxide semiconductor layer of transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0180] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure, in which metal atoms are arranged in a layered manner in a crystal portion in a direction parallel to or approximately parallel to a surface on which the oxide semiconductor layer is formed.

[0181] The case where the oxide semiconductor layer of one embodiment of the present invention is applied to the semiconductor device illustrated in FIG. 7B, FIG. 7C, and the like will be described later. In FIG. 7B and FIG. 7C, the oxide semiconductor layer 230 has metal atoms arranged in a layered manner parallel or substantially parallel to the sidewalls of the opening 290 (the side surfaces of the insulating layer 280 and the conductive layer 240), which are the surfaces where the oxide semiconductor layer 230 is to be formed. It can also be expressed that the ab plane of the CAAC structure is provided in a direction parallel or substantially parallel to the surfaces where the oxide semiconductor layer 230 is to be formed. With such a structure, the ab plane of the CAAC structure can be provided in the direction of current flow in the channel of the transistor 200. This can increase the on-state current of the transistor.

[0182] When the oxide semiconductor layer 230 described with reference to FIG. 1A to FIG. 2D is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In addition, in a transistor used in a finer semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and is preferably 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. In addition, the average thickness of the oxide semiconductor layer 230 in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0183] The thickness of the oxide semiconductor layer 230b is preferably, for example, 200 nm or less. When the oxide semiconductor layer 230b has a layered shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and more preferably 2 nm to 100 nm.

[0184] Alternatively, if the oxide semiconductor layer 230b can function as a crystal nucleus, the oxide semiconductor layer 230b may not exist as a layer but may be an aggregate of island-shaped regions. In such a case, for example, the island-shaped regions of the oxide semiconductor layer 230b exist discretely.

[0185] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c each have a thickness of, for example, preferably 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm. The oxide semiconductor layer 230a is further preferably 0.5 nm to 3 nm.

[0186] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0187] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or shortage of constituent atoms) and impurities.

[0188] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0189] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0190] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0191] In addition, a metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transmission of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of a transistor can be increased.

[0192] [Impurities in oxide semiconductors] Here, the influence of each impurity in an oxide semiconductor will be described.

[0193] It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. O ) and impurities may cause electrical characteristics to fluctuate and reliability to deteriorate. In addition, hydrogen near the oxygen vacancy may cause V O H and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region, V O It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0194] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0195] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0196] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0197] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0198] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0199] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0200] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0201] The crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern by performing FFT processing on the TEM image. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of the electron diffraction pattern.

[0202] By performing FFT processing for each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal part. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0203] The c-axis orientation rate can be calculated by calculating the ratio of c-axis-oriented regions in a map showing crystal orientation. Note that the c-axis-oriented regions are herein defined as regions whose orientation coincides with the c-axis and regions whose difference from the c-axis is preferably within 20°, more preferably within 15°, more preferably within 10°, and even more preferably within 5°. Here, the angle of the c-axis is the angle with respect to the surface on which the oxide semiconductor layer is formed.

[0204] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0205] In addition, when the analysis is performed using a cross-sectional TEM image, the observation range of the cross-sectional TEM image may be, for example, a region having a width of 100 nm in the horizontal direction with the direction perpendicular to the surface on which the oxide semiconductor layer is formed as the vertical direction. Note that the observation range is not limited to this.

[0206] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of a region whose difference from the c-axis is within 20°.

[0207] The c-axis orientation rates of the region formed as the oxide semiconductor layer 230a, the region formed as the oxide semiconductor layer 230b, and the region formed as the oxide semiconductor layer 230c are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1. Here, the c-axis orientation rate is preferably calculated as the ratio of a region whose difference from the c-axis is within 20°, for example.

[0208] After the oxide semiconductor layer 230 is formed, the boundaries between the oxide semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0209] The oxide semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from the top of the layer 229. Each region has a layer shape.

[0210] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation rate of the second region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of the region whose difference with the c-axis is within 20°, for example.

[0211] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 230 .

[0212] Or, the layer thickness in each region may be, for example, approximately the same.

[0213] [Method of producing metal oxides using the ALD method] Here, an example of a method for forming a metal oxide film having a three-layered crystal structure by the ALD method will be described with reference to Figs. 3(A) to 3(E). First, a precursor 611a is introduced into a chamber, and the precursor 611a is adsorbed onto the surface of a substrate 610 (see Fig. 3(A). Hereinafter, this process may be referred to as the first step). Here, as shown in Fig. 3(A), the precursor 611a is adsorbed onto the surface of the substrate 610, and a self-termination mechanism of the surface chemical reaction is activated, so that the precursor 611a is not further adsorbed onto the layer of the precursor 611a on the substrate 610. The appropriate range of the substrate temperature in which the self-termination mechanism of the surface chemical reaction is activated is also called the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and may be, for example, 100°C to 600°C, preferably 200°C to 400°C.

[0214] Next, an inert gas (argon, helium, nitrogen, etc.) is introduced into the chamber to discharge excess precursor 611a and reaction products from the chamber (hereinafter, this step may be referred to as the second step). Instead of introducing an inert gas into the chamber, excess precursor and reaction products may be discharged from the chamber by vacuum evacuation. The second step is also called purging.

[0215] Next, reactant 612a (e.g., oxidant (ozone (O 3 ), oxygen (O 2 ), water (H 2O) and their plasma, radicals, ions, etc.) are introduced into the chamber and reacted with the precursor 611a adsorbed on the surface of the substrate 610, so that some of the components contained in the precursor 611a are desorbed while the constituent molecules of the precursor 611a are still adsorbed on the substrate 610 (see FIG. 3(B). Hereinafter, this step may be referred to as the third step). As a result, a layer of oxide 613a formed by oxidizing a part of the precursor 611a is formed on the surface of the substrate 610.

[0216] Next, excess reactant 612a or reaction products are discharged from the chamber by introducing an inert gas or evacuating (hereinafter, this step may be referred to as a fourth step).

[0217] Next, precursor 611b having a metal element different from precursor 611a is introduced, and the same process as the first step is performed to cause precursor 611b to be adsorbed on the surface of the layer of oxide 613a (see FIG. 3(C)). Here, as shown in FIG. 3(C), the precursor 611b is adsorbed on the layer of oxide 613a, and a self-terminating mechanism of the surface chemical reaction is activated, so that precursor 611b is not further adsorbed on the layer of precursor 611b on substrate 610.

[0218] Next, as in the second step, excess precursor 611b and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

[0219] Next, as in the third step, reactant 612b is introduced into the chamber. Here, reactant 612b may be the same as reactant 612a or may be different (see FIG. 3(D)). As a result, a layer of oxide 613b formed by oxidizing a part of precursor 611b is formed on the layer of oxide 613a.

[0220] Next, as in the fourth step, excess reactant 612b and reaction products are discharged from the chamber by introducing an inert gas or by vacuum evacuation.

[0221] Furthermore, the first to fourth steps can be performed in a similar manner to form a layer of oxide 613c on the layer of oxide 613b. In this manner, by repeatedly performing the steps of forming oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of oxides 613a to 613c is repeated can be formed (see FIG. 3E). In other words, an oxide layer can be formed by performing the first to fourth steps as one set, and by repeating this set, a layered crystal structure in which multiple oxide layers are stacked can be formed.

[0222] The thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.

[0223] In addition, when forming a metal oxide having a layered crystal structure, it is preferable to perform the steps shown in Figures 3(A) to 3(E) while heating the substrate. For example, the substrate temperature may be set to 200°C or higher and 600°C or lower, preferably 300°C or higher and lower than the decomposition temperature of the precursor. When forming a film by the ALD method using multiple precursors of different types, it is preferable to set the substrate temperature to the decomposition temperature of the lowest precursor among the multiple precursors. This allows the multiple precursors used to be adsorbed onto the target (e.g., substrate) without being decomposed during film formation by the ALD method.

[0224] By performing the above-mentioned film formation while heating the substrate in such a temperature range, impurities such as hydrogen and carbon contained in the precursor and reactant can be removed from the metal oxide in each process from step 1 to step 4. For example, carbon in the metal oxide can be removed by CO 2 and CO, and hydrogen in the metal oxide is released as H 2 The metal atoms and oxygen atoms can be released as O. Furthermore, at the same time as the above-mentioned impurities are removed, the rearrangement of metal atoms and oxygen atoms can be caused, and each oxide layer can be arranged in a highly orderly manner. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0225] In order to perform film formation while heating the substrate in the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200° C. or more and 700° C. or less, and more preferably 300° C. or more and 600° C. or less. As a precursor having such a high decomposition temperature, it is preferable to use a precursor formed of an inorganic substance (hereinafter referred to as an inorganic precursor). Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed of an organic substance (hereinafter referred to as an organic precursor), and some of them have an ALD window in the above temperature range. In addition, since inorganic precursors do not contain impurities such as hydrogen or carbon, it is possible to prevent an increase in the concentration of impurities such as hydrogen or carbon in the metal oxide film formed.

[0226] Furthermore, it is preferable to perform a heat treatment after the formation of the metal oxide film. In particular, it is preferable to perform a heat treatment continuously without exposing the film to the outside air after the formation of the film by the ALD method. The heat treatment can be performed under the conditions described in FIG. 1(A) to FIG. 1(D) and the like.

[0227] By carrying out the heat treatment in this way, impurities such as hydrogen and carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO 2 and CO, and hydrogen in the metal oxide is released as H 2 The metal atoms and oxygen atoms can be released as O. Furthermore, at the same time as removing the above impurities, rearrangement of metal atoms and oxygen atoms can be performed, improving the crystallinity. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0228] In addition, after the metal oxide film is formed, it is preferable to perform a microwave treatment in an atmosphere containing oxygen to reduce the impurity concentration in the metal oxide. The impurities include, in particular, hydrogen and carbon. In the above, the metal oxide is subjected to a microwave treatment in an atmosphere containing oxygen, but the present invention is not limited to this. For example, an insulating film, more specifically, a silicon oxide film, located near the metal oxide may be subjected to a microwave treatment in an atmosphere containing oxygen.

[0229] 3A to 3E, a structure in which the oxides 613a to 613c are stacked repeatedly is described, but the present invention is not limited to this. For example, a metal oxide in which a single layer, two layers, or four or more oxide layers are repeatedly formed may be used.

[0230] In addition, unless otherwise specified in this specification and the like, when ozone, oxygen, or water is used as a reactant or an oxidant, these are not limited to a gas or molecular state, but also include a plasma state, a radical state, and an ion state. When forming a film using an oxidant in a plasma state, a radical state, or an ion state, a plasma ALD apparatus described below may be used.

[0231] In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to react the precursor with the oxidizing agent sufficiently. For example, the pulse time for introducing the oxidizing agent may be increased. Alternatively, the oxidizing agent may be introduced multiple times. When the oxidizing agent is introduced multiple times, the same type of oxidizing agent may be introduced, or different types of oxidizing agents may be introduced. For example, water may be introduced into the chamber as a first oxidizing agent, and then the chamber may be evacuated, and ozone or oxygen not containing hydrogen may be introduced into the chamber as a second oxidizing agent, and then the chamber may be evacuated.

[0232] In this way, by repeating the introduction of the oxidizing agent and the introduction of the inert gas (or evacuation) multiple times in a short period of time in the chamber, it is possible to more reliably remove excess hydrogen atoms, carbon atoms, chlorine atoms, etc. from the precursor adsorbed on the substrate surface and expel them from the chamber. Also, by increasing the number of types of oxidizing agents to two, it is possible to remove more excess hydrogen atoms, etc. from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, it is possible to reduce the amount of water, hydrogen, etc. contained in the formed film.

[0233] The ALD method is a film formation method in which precursors and reactants are reacted with each other using thermal energy. The temperature required for the reaction of the precursors and reactants is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., and is 100°C to 600°C, preferably 200°C to 600°C, and more preferably 300°C to 600°C.

[0234] Furthermore, in addition to the above-mentioned precursor and reactant reactions, the ALD method in which a plasma-excited reactant is introduced into the chamber as a third raw material gas is sometimes called the plasma ALD method. In this case, a plasma generating device is provided at the introduction part of the third raw material gas. Inductively Coupled Plasma (ICP) can be used to generate plasma. In contrast, the ALD method in which the precursor and reactant react with thermal energy is sometimes called the thermal ALD method.

[0235] In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeated while a plasma-excited reactant (second reactant) is introduced to form a film. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third raw material gas can be the same material as the oxidizing agent. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizing agent, a nitriding agent may be used as the second reactant. Nitrogen (N 2 ) or ammonia (NH 3 ) can be used. Nitrogen (N 2 ) and hydrogen (H 2 ) can be used as a nitriding agent. 2 ) 5%, hydrogen (H 2 ) 95% mixed gas can be used as the nitriding agent. By conducting film formation while introducing plasma-excited nitrogen or ammonia, nitride films such as metal nitride films can be formed.

[0236] In addition, argon (Ar), helium (He) or nitrogen (N 2 ) may be used. The use of a carrier gas such as argon, helium, or nitrogen is preferable because it facilitates plasma discharge and facilitates the generation of a plasma-excited second reactant. When forming an oxide film such as a metal oxide film using the plasma ALD method, if nitrogen is used as the carrier gas, the nitrogen may be mixed into the film, making it difficult to obtain the desired film quality. In this case, it is preferable to use argon or helium as the carrier gas.

[0237] The ALD method can deposit extremely thin films with uniform thickness and has a high surface coverage even on uneven surfaces.

[0238] Here, the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide will be described with reference to Figures 4(A) to 4(D). In Figures 4(B) and 4(D), atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines. In Figures 4(B) and 4(D), the c-axis direction in the crystal structure of In-M-Zn oxide is represented by an arrow in the figure. Also, the ab-plane direction in the crystal structure of In-M-Zn oxide is perpendicular to the c-axis direction represented by the arrow in Figures 4(B) and 4(D).

[0239] 4A is a diagram showing an oxide 660 having an In-M-Zn oxide formed on a structure 650. Here, the structure refers to an element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate, a conductor such as a gate electrode, a source electrode, and a drain electrode, an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film, a metal oxide, and a semiconductor such as silicon. FIG. 4A shows a case where a surface of the structure 650 on which a film is to be formed is arranged parallel to a substrate (or a base body, not shown).

[0240] Fig. 4(B) is an enlarged view showing the atomic arrangement in the crystal in a region 653 which is a part of the oxide 660 in Fig. 4(A). Here, the composition of the oxide 660 shown in Fig. 4(A) and Fig. 4(B) is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is YbFe 2 O 4 The element M is a metal element having a valence of +3.

[0241] 4B, the crystals of the oxide 660 are formed by repeatedly stacking a layer 621 having indium (In) and oxygen, a layer 631 having an element M and oxygen, and a layer 641 having zinc (Zn) and oxygen in this order. The layer 621, the layer 631, and the layer 641 are arranged substantially parallel to the deposition surface of the structure 650. That is, the ab-plane of the oxide 660 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal direction of the deposition surface of the structure 650.

[0242] As shown in FIG. 4B, each of layers 621, 631, and 641 of the above crystals is composed of one metal element and oxygen, and is arranged with good crystallinity, which can increase the mobility of the metal oxide.

[0243] Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:1:1 is not limited to the structure shown in FIG. 4(B). The order of stacking the layers 621, 631, and 641 may be changed. For example, the layers 621, 641, and 631 may be repeatedly stacked in this order. Alternatively, the layers 621, 631, 641, 621, 641, and 631 may be repeatedly stacked in this order. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M.

[0244] In the above, an example was shown in which an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] was formed. (1+α) M (1-α) O 3 (ZnO) m Crystalline In-M-Zn oxide, represented by (α is a real number greater than 0 and less than 1, and m is a positive number), can similarly have a layered crystal structure. As an example, Figures 4(C) and 4(D) show In-M-Zn oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio].

[0245] Fig. 4(C) is a diagram showing an oxide 662 having an In-M-Zn oxide formed on the structure 650. Fig. 4(D) is an enlarged view showing the atomic arrangement in the crystal in a region 654 which is a part of the oxide 662 in Fig. 4(C).

[0246] 4D, the crystals of the oxide 662 include a layer 622 having indium (In), an element M, and oxygen, a layer 641 having zinc (Zn) and oxygen, and a layer 631 having the element M and oxygen. In the oxide 662, a plurality of layers are repeatedly stacked in the order of the layer 622, the layer 641, the layer 631, and the layer 641. The layer 622, the layer 631, and the layer 641 are arranged approximately parallel to the deposition surface of the structure 650. That is, the ab-plane of the oxide 662 is approximately parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is approximately parallel to the normal direction of the deposition surface of the structure 650.

[0247] 4D, the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:3:4 may have a different structure within the range of the atomic ratio of In:M:Zn=1:3:4. For example, the stacking order of the layers 622, 631, and 641 may be changed. A part of the element M in the layer 631 may be substituted with zinc, and a part of the zinc in the layer 641 may be substituted with the element M. The layer 621 or the layer 631 may be formed instead of the layer 622.

[0248] Next, a method for forming the oxide 660 having the In-M-Zn oxide shown in FIG. 4(A) and FIG. 4(B) will be described in detail with reference to FIG. 5(A) to FIG. 6(C).

[0249] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed on the surface of the structure 650 (see FIG. 5(A)). Here, the source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the precursor having indium, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, or the like can be used.

[0250] In addition, an inorganic precursor not containing a hydrocarbon may be used as the precursor containing indium. A halogen-based indium compound such as indium trichloride, indium tribromide, or indium triiodide may be used as the inorganic precursor containing indium. Indium trichloride has a decomposition temperature of about 500° C. or more and 700° C. or less. Therefore, by using indium trichloride, a film can be formed by the ALD method while heating the substrate at about 400° C. or more and 600° C. or less, for example, at 500° C.

[0251] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0252] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor to remove components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer 621 in which indium and oxygen are combined (see FIG. 5(B)). As the oxidizing agent, ozone, oxygen, water, etc. can be used. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0253] Next, a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto layer 621 (see FIG. 5(C)). The source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. When gallium is used as element M, trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, or the like can be used as a precursor having gallium.

[0254] In addition, an inorganic precursor not containing a hydrocarbon may be used as the precursor containing gallium. A halogen-based gallium compound such as gallium trichloride, gallium tribromide, or gallium triiodide may be used as the inorganic precursor containing gallium. Gallium trichloride has a decomposition temperature of about 550° C. or more and 700° C. or less. Therefore, by using gallium trichloride, a film can be formed by the ALD method while heating the substrate at about 450° C. or more and 650° C. or less, for example, at 550° C.

[0255] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0256] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor to desorb components other than element M while leaving element M adsorbed on the substrate, thereby forming layer 631 in which element M is combined with oxygen (see FIG. 5(D)). At this time, some of the oxygen constituting layer 641 may be adsorbed onto layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0257] Next, a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the layer 631 (see FIG. 6(A)). At this time, a part of a layer 641 in which zinc and oxygen are combined may be formed. The source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor. As the precursor containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc acetate, etc. can be used.

[0258] In addition, an inorganic precursor not containing a hydrocarbon may be used as the zinc-containing precursor. A halogen-based zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide may be used as the zinc-containing inorganic precursor. The decomposition temperature of zinc dichloride is about 450° C. or more and 700° C. or less. Therefore, by using zinc dichloride, a film can be formed by the ALD method while heating the substrate at about 350° C. or more and 550° C. or less, for example, at 450° C.

[0259] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0260] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc is still adsorbed on the substrate, forming a layer 641 in which zinc and oxygen are combined (see FIG. 6(B)). Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0261] Next, the layer 621 is formed again over the layer 641 by the above-described method (see FIG. 6C). By repeating the above-described method, an oxide 660 can be formed over the substrate or the structure.

[0262] The precursors may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. A film formed using a precursor containing a halogen such as chlorine may contain a halogen such as chlorine.

[0263] As described above, by forming the oxide 660 by the ALD method, a metal oxide can be formed in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface. For example, in the oxide semiconductor layer 230 shown in FIG. 7B and FIG. 7C described later, layered crystals can be formed approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulating layer 280. With this structure, the layered crystals of the oxide semiconductor layer 230 are formed approximately parallel to the channel length direction of the transistor 200, and therefore the on-current of the transistor can be increased.

[0264] 5A to 6C are preferably performed while heating the substrate, for example, at a substrate temperature of 200° C. to 600° C., preferably 300° C. to the decomposition temperature of the precursor.

[0265] In order to form a film while heating the substrate in the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200° C. or more and 700° C. or less, and more preferably 300° C. or more and 600° C. or less. As a precursor having such a high decomposition temperature, it is preferable to use an inorganic precursor. In general, inorganic precursors tend to have a higher decomposition temperature than organic precursors, so that the precursor is less likely to be decomposed even if the film is formed while heating the substrate as described above.

[0266] As the inorganic precursor, for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used. As described above, the decomposition temperature of these precursors is about 350° C. or more and 700° C. or less, which is considerably higher than the decomposition temperature of general organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. In this way, when performing film formation by the ALD method using multiple different types of precursors, it is preferable to set the substrate temperature to the decomposition temperature of the lowest precursor among the multiple precursors. In the above example, the substrate temperature may be set within a range in which zinc dichloride, which has the lowest decomposition temperature of the precursor, does not decompose. This allows other indium trichloride and gallium trichloride to be adsorbed to the target (for example, a substrate, etc.) without being decomposed.

[0267] 5A to 6C show an example in which the layer 621 is formed as a layer containing indium, the layer 631 is formed thereon as a layer containing element M, and the layer 641 is further formed thereon as a layer containing zinc, but this embodiment is not limited to this. One of the layer 631 and the layer 641 may be formed, the layer 621 may be formed thereon, and the other of the layer 631 and the layer 641 may be formed thereon. Alternatively, one of the layer 631 and the layer 641 may be formed, the other of the layer 631 and the layer 641 may be formed thereon, and the layer 621 may be formed thereon.

[0268] When forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], the above-mentioned layers 621, 631, and 641 may be formed appropriately according to the atomic ratio. For example, a stack of layers 631 and 641 having the desired number of atoms, number of layers, and thickness may be formed between two layers 621 by repeating the formation of layer 641 multiple times before and after the formation of layer 631 as shown in FIG. 6(A).

[0269] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0270] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0271] A semiconductor device of one embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.

[0272] The first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have an opening that reaches the first conductive layer. The oxide semiconductor layer is in contact with at least a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the opening. The second insulating layer is located over the oxide semiconductor layer in the opening. The third conductive layer overlaps with the oxide semiconductor layer in the opening, with the second insulating layer sandwiched therebetween. Note that the opening is also referred to as an opening.

[0273] The first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer functions as a gate electrode of the transistor, and the second insulating layer functions as a gate insulating layer.

[0274] In this specification, the term "in a cross-sectional view" is used, but may be specifically rephrased as "in a cross-sectional view from the same direction." For example, when explaining the relationship between multiple configurations, the relationship in a cross-sectional view from the same direction is explained. In this case, the relationship between the multiple configurations can be explained using one cross-sectional view.

[0275] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a height (vertical) component, and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0276] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and therefore the occupation area can be significantly reduced as compared with a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0277] In this specification, the term "ends coincide" refers to at least a portion of the contours of stacked layers overlapping in a plan view. For example, this term includes cases where the upper and lower layers are processed using the same mask pattern or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "ends coincide" is also used.

[0278] In general, it may be difficult to clearly distinguish between a "perfect match" and a "substantially match." For this reason, in this specification and elsewhere, "match" may include both a perfect match and a substantially match.

[0279] <Example of semiconductor device configuration> The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 7A to 14C. FIG. 7A is a plan view of a semiconductor device including a transistor 200. FIG. 7B is a cross-sectional view taken along dashed line A1-A2 in FIG. 7A. FIG. 7C is a cross-sectional view taken along dashed line A3-A4 in FIG. 7A. FIG. 9A is a cross-sectional view taken along the XY plane including an insulating layer 280. Note that some elements are omitted in the plan view of FIG. 7A for clarity. Some elements may also be omitted in the subsequent plan views.

[0280] 7A to 7C and 9A includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, and an insulating layer 283 and an insulating layer 285 over the transistor 200. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0281] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The conductive layer 220 and the conductive layer 240 are located at different heights.

[0282] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode.

[0283] A region of the oxide semiconductor layer 230 which is in contact with the conductive layer 220 and the conductive layer 240 preferably functions as a low-resistance region.

[0284] 7(B) and 7(C), an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220. A recess overlapping the opening 290 is provided in the conductive layer 220. The opening 290 and the recess of the conductive layer 220 form a continuous opening. The bottom of the continuous opening becomes the upper surface of the conductive layer 220.

[0285] The sidewalls of the opening 290 are the side surfaces of the insulating layer 280 and the conductive layer 240. The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, an opening in a region where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290, and an opening in a region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290. Note that, among the openings 290, the opening 290 provided in the insulating layer 280 is represented as opening 290a, and the opening 290 provided in the conductive layer 240 is represented as opening 290b.

[0286] At least some of the components of the transistor 200 are disposed inside the opening 290. Specifically, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least some of them are located inside the opening 290. The oxide semiconductor layer 230 contacts an upper surface of the conductive layer 220, a side surface of the insulating layer 280, and a side surface of the conductive layer 240 within the opening 290.

[0287] Moreover, insulating layer 280 has insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Insulating layer 280a has a region in contact with the upper surface of insulating layer 210, a region in contact with the side surface of conductive layer 220, and a region in contact with the upper surface of conductive layer 220. Insulating layer 280c has a region in contact with the lower surface of conductive layer 240.

[0288] The oxide semiconductor layer 230 is provided inside an opening 290 in the insulating layer 280. The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, so that a current flows in a vertical direction. That is, a channel is formed along the sidewall of the opening 290a.

[0289] The oxide semiconductor layer 230 contacts the upper surface of the conductive layer 220 and the side surface of the conductive layer 240 inside the opening 290. The oxide semiconductor layer 230 also contacts a part of the upper surface of the conductive layer 240. In this way, the oxide semiconductor layer 230 contacts not only the side surface but also the upper surface of the conductive layer 240, so that the area of ​​contact between the oxide semiconductor layer 230 and the conductive layer 240 can be made larger than, for example, a case in which the oxide semiconductor layer 230 contacts the side surface of the conductive layer 240 but does not contact the upper surface. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be made smaller.

[0290] The conductive layer 240 has an opening 290b in a region overlapping with the conductive layer 220. The conductive layer 240 is preferably not provided inside the opening 290a of the insulating layer 280. That is, the conductive layer 240 preferably does not have a region in contact with a side surface of the insulating layer 280 in the opening 290a. With this structure, the opening 290b of the conductive layer 240 and the opening 290a of the insulating layer 280 can be formed at the same time. With the structure in which the side surface of the conductive layer 240 in the opening 290b and the side surface of the insulating layer 280 in the opening 290a match or substantially match, the film thickness distribution of the oxide semiconductor layer 230 provided inside the opening 290 can be made uniform. Furthermore, the oxide semiconductor layer 230 can be prevented from being divided by a step between the conductive layer 240 and the insulating layer 280.

[0291] FIG. 9(A) is a cross-sectional view taken along dashed line A1-A2 in FIG. 7(A), which is a modified example of FIG. 7(B). FIG. 9(B) is a cross-sectional view taken along dashed line A3-A4 in FIG. 7(A), which is a modified example of FIG. 7(C). The conductive layer 240 shown in FIG. 9(A) and FIG. 9(B) has a stacked structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. Note that the conductive layer 240 may be a single layer or may have a stacked structure of three or more layers. The details of the conductive layer 240a and the conductive layer 240b will be described later. Note that although the insulating layer 283 and the insulating layer 285 may be omitted in FIG. 9(A) and FIG. 9(B) and the following drawings, it is preferable that the insulating layer 283 and the insulating layer 285 are provided over the transistor 200.

[0292] The conductive layer 260 shown in FIG. 9(A) and FIG. 9(B) has a stacked structure of a conductive layer 260a and a conductive layer 260b over the conductive layer 260a. The conductive layer 260a is preferably formed using a film formation method with high coverage. Furthermore, by reducing the thickness of the conductive layer 260a, the coverage of the sidewall of the opening 290 can be further improved. The conductive layer 260b can be made thicker than the conductive layer 260a. By increasing the thickness of the conductive layer, the resistance of the conductive layer can be reduced. Note that the conductive layer 240 may be a single layer or may have a stacked structure of three or more layers. Details of the conductive layer 260a and the conductive layer 260b will be described later.

[0293] The width of the opening 290 is defined as width D. Width D may vary in the depth direction. For example, it may be the width of the upper end of the opening 290 in the insulating layer 280. Alternatively, it may be the width of the lower end. Alternatively, it may be the width at half the depth of the opening 290 in the insulating layer 280. Alternatively, the width of the opening 290 in the conductive layer 240 may be used.

[0294] The portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed inside the opening 290 are provided to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom and sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. The oxide semiconductor layer 230 is preferably provided so as to contact the sidewall of the insulating layer 280 in the opening 290a. The insulating layer 250 is disposed facing the sidewall of the insulating layer 280 in the opening 290a, with the oxide semiconductor layer 230 sandwiched therebetween.

[0295] The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. By reducing the width D, the transistor 200 can be miniaturized. However, when the width D is reduced, if the aspect ratio of the opening 290 is high, only a part of the laminated structure of the conductive layer 260 may be disposed inside the opening 290 depending on the formation method or thickness of the components disposed inside the opening. Here, an example is shown in which the conductive layer 260a is disposed inside the opening 290, and the conductive layer 260b is not disposed within the opening 290. The conductive layer 260a is preferably formed using a method with high coverage.

[0296] The sidewall of the opening 290 is preferably perpendicular or nearly perpendicular to the top surface of the conductive layer 220. By forming the opening 290 in such a shape, the area occupied by the transistor 200 can be reduced. Thus, the semiconductor device can be miniaturized.

[0297] The film provided inside the opening 290 can be formed using an atomic layer deposition (ALD) method, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, or the like.

[0298] 10(B) shows an example in which the sidewall of the opening 290 has a tapered shape, as compared with FIG. 7(B). The angle θ280 between the top surface of the conductive layer 220 (or the top surface of the insulating layer 210) and the sidewall of the insulating layer 280 of the opening 290 is preferably 90 degrees or an angle close to 90 degrees. For example, the angle θ280 is preferably 75 degrees or more and 90 degrees or less.

[0299] In addition, the angle θ280 may be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees. By tapering the sidewall of the opening 290, the oxide semiconductor layer 230 and the insulating layer 250 can be formed with good coverage.

[0300] In particular, when the sidewall of the opening 290 has a tapered shape, the coverage of the sidewall of the opening 290 can be improved. Therefore, as in the configuration shown in FIG 10(C), not only the thin conductive layer 260a but also the thick conductive layer 260b may be provided in the opening 290.

[0301] The opening 290 may have a tapered shape only at the upper end. In such a case, for example, at least a part of the sidewall of the region having the tapered shape may be covered with the conductive layer 260b. In addition, the opening 290 preferably has a region deeper than the region having the tapered shape, where the sidewall is steeper than the upper end. For example, when the opening 290 has such a shape, the contact area with the conductive layer 240 is increased in the tapered region, so that the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced. In addition, when a part of the insulating layer 280 has a tapered shape, for example, the region may function as a relaxation region of the electric field between the conductive layer 240 and the conductive layer 260.

[0302] It is preferable that the insulating layer 250 has a configuration that has good coverage on the sidewall of the opening 290 and can suppress short circuits between the conductive layer 240 and the conductive layer 260.

[0303] The insulating layer 250 functions as a gate insulating layer of the transistor 200. By making the gate insulating layer thin, it is possible to reduce a gate potential applied during operation of the transistor 200. In addition, it is possible to operate the transistor 200 at high speed.

[0304] 7B and 7C show an example in which the end of the oxide semiconductor layer 230 and the end of the conductive layer 240 coincide with each other outside the opening 290. Note that the present invention is not limited thereto. For example, the semiconductor device shown in FIG. 11A and FIG. 11B is different from that shown in FIG. 7A and FIG. 7B in that the end of the oxide semiconductor layer 230 is located outside the end of the conductive layer 240. By making the end of the oxide semiconductor layer 230 outside the end of the conductive layer 240 and covering the end of the conductive layer 240 with the oxide semiconductor layer 230, the withstand voltage between the conductive layer 240 and the conductive layer 260 can be further increased and the leakage current of the insulating layer 250 located between the conductive layer 240 and the conductive layer 260 can be further reduced in some cases. In addition, as shown in FIG. 12A and FIG. 12B, the end of the oxide semiconductor layer 230 may be located inside the end of the conductive layer 240.

[0305] <OSトランジスタ> The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0306] The oxide semiconductor layer 230 described in the above embodiment can be used as the oxide semiconductor layer 230. The oxide semiconductor layer 230 described in the above embodiment can be formed by stacking the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c. FIG. 8 shows an enlarged view of a part of the cross-sectional view shown in FIG. 7B, and illustrates the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c. Note that in other drawings, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c may be omitted for clarity. The oxide semiconductor layer 230a is in contact with an upper surface of the conductive layer 220, a side surface of a recess of the conductive layer 220, a side surface of an opening 290a of the insulating layer 280, a side surface of an opening 290b of the conductive layer 240, and an upper surface of the conductive layer 240. The oxide semiconductor layer 230b is provided over the oxide semiconductor layer 230a. The oxide semiconductor layer 230c covers the upper surface of the conductive layer 220, the side surfaces of the recesses of the conductive layer 220, the side surfaces of the openings 290a of the insulating layer 280, the side surfaces of the openings 290b of the conductive layer 240, and the upper surface of the conductive layer 240, with the oxide semiconductor layer 230b sandwiched therebetween. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230c. The conductive layer 260 covers the oxide semiconductor layer 230c, with the insulating layer 250 sandwiched therebetween.

[0307] The oxide semiconductor layer 230 is provided in contact with a side surface of the opening 290a of the insulating layer 280. The angle between the side surface of the insulating layer 280 and the upper surface of the conductive layer 220 (or the upper surface of the insulating layer 210) is θ280. Therefore, for example, the direction of the c-axis of the CAAC structure of the oxide semiconductor layer 230 is approximately perpendicular to the angle θ280.

[0308] OS transistors have oxygen vacancies (V O ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. In addition, hydrogen near the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V OH) and generate electrons that serve as carriers. For this reason, when oxygen vacancies are contained in the channel formation region in the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0309] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the region has a high carrier concentration and low resistance due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the OS transistor are preferably n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0310] A region of the oxide semiconductor layer 230 in contact with the insulating layer 280 and its vicinity function as a channel formation region of the transistor 200. One of a region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and a region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0311] When the oxide semiconductor layer 230 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 has a low resistance. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220. Similarly, when the oxide semiconductor layer 230 and the conductive layer 240 come into contact with each other, the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 has a low resistance. This makes it possible to reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0312] 10A, the insulating layer 280 is in contact with the entire outer periphery of the oxide semiconductor layer 230. Thus, the channel formation region of the transistor 200 can be formed on the entire outer periphery of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 280). Note that FIG. 10A can also be considered to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0313] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 7C, the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L is the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0314] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making it difficult to further miniaturize the transistor. However, in the transistor included in the semiconductor device of one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 280. Thus, the channel length of the transistor 200 can be made to be an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is 0.1 nm or more, 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0315] Furthermore, since the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by the thickness of the insulating layer 280 over the conductive layer 220, even when the channel length is set to be long, for example, 60 nm or more, the area occupied by the transistor, specifically, for example, the area of ​​the transistor as viewed from above, is roughly determined by the width of the opening 290. As described later, the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. For example, even when the channel length is set to 150 nm, the width of the opening 290 can be made narrower than 150 nm. That is, the width of the opening can be narrower than the channel length of the transistor, which reduces the area occupied by the transistor and enables high integration of the semiconductor device.

[0316] Note that by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0317] Therefore, the channel length of a transistor included in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0318] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. As a result, the area occupied by the transistor 200 can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Thus, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.

[0319] As shown in FIG. 10A, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Thus, the side surface of the conductive layer 260 provided at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire circumference of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the length of the outer periphery of the oxide semiconductor layer 230 determines the channel width of the transistor 200. That is, it can be said that the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view). In FIG. 7C and FIG. 10A, the width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line. In FIG. 10A, the channel width W of the transistor 200 is indicated by a double-dot chain line arrow. By increasing the width D of the opening 290, the channel width per unit area can be increased, and the on-current can be increased.

[0320] When the opening 290 is formed by using a photolithography method, the width D of the opening 290 is limited by the exposure limit of the photolithography. The width D of the opening 290 is set by the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0321] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0322] In addition, by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0323] In the present embodiment, the opening 290 is circular in plan view, but the present invention is not limited to this. For example, the opening 290 may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in plan view.

[0324] 13A shows an enlarged view of a part of the cross section shown in FIG. 7B. As shown in FIG. 13A, a recess overlapping with the opening 290 is formed in the conductive layer 220, and at least a part of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is formed to fill the recess. With this structure, it is possible to easily apply the gate electric field of the conductive layer 260 up to the vicinity of the conductive layer 220 of the oxide semiconductor layer 230. The recess of the conductive layer 220 is formed, for example, by overetching when the opening 290 is formed.

[0325] 13A, the opening 290 and the recess of the conductive layer 220 form a continuous opening. In this case, for example, the bottom of the continuous opening becomes the upper surface of the conductive layer 220.

[0326] 13B shows an example in which the conductive layer 220 has a three-layer structure of a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b. The bottom surface of a recess in the conductive layer 220 corresponds to the upper surface of the conductive layer 220b, and the side surface of the recess corresponds to the side surface of the conductive layer 220c on the opening 290 side. Here, the shortest distance from the upper surface of the insulating layer 210 to the upper surface of the conductive layer 220c that is in contact with the insulating layer 280 is preferably longer than the shortest distance from the upper surface of the insulating layer 210 to the upper surface of the insulating layer 250. This can reduce the contact resistance between the side surface of the conductive layer 220c and the oxide semiconductor layer 230. As a result, a decrease in the on-current of the transistor 200 can be suppressed.

[0327] Fig. 13C is a modification of Fig. 13B. In Fig. 13C, the bottom surface of the recess of the conductive layer 220 is located above the top surface of the conductive layer 220b. As shown in Fig. 13C, the oxide semiconductor layer 230 is not necessarily in contact with the conductive layer 220a or the conductive layer 220b.

[0328] In addition, there are cases where the conductive layer 220 does not have a recess.

[0329] When the conductive layer 220 is in contact with the side surface of the oxide semiconductor layer 230, the contact area between the conductive layer 220 and the oxide semiconductor layer 230 can be increased, and the contact resistance can be reduced.

[0330] In addition, by having a region where the conductive layer 220 and the conductive layer 260 overlap each other, for example, a gate electric field is easily applied to a channel formation region of the oxide semiconductor layer 230, which can improve the electrical characteristics of the transistor. Furthermore, since a gate electric field is easily applied to a region of the oxide semiconductor layer 230 in contact with the conductive layer 220, for example, the on-current of the transistor can be increased.

[0331] <Modifications of the semiconductor device> In the semiconductor device shown in Figures 14(A) to 14(C), an insulating layer 283 and an insulating layer 285 are provided on an insulating layer 250, the insulating layer 285 has an opening 270, and a conductive layer 260 is provided in the opening 270. Figure 14(A) is a plan view of a semiconductor device having a transistor 200. Figure 14(B) is a cross-sectional view taken along dashed line A1-A2 in Figure 14(A). Figure 14(C) is a cross-sectional view taken along dashed line A3-A4 in Figure 14(A).

[0332] 14B and 14C, the opening 270 overlaps with the opening 290 in a plan view. The conductive layer 260 has a region located in the opening 270 provided in the insulating layer 285 and a region in contact with the top surface of the insulating layer 285. The insulating layer 283 has a region overlapping with the top surface of the conductive layer 240 with the insulating layer 250 and the oxide semiconductor layer 230 sandwiched therebetween, and a region sandwiched between a side surface of the opening 270 and a side surface of the conductive layer 260. The conductive layer 240 and the conductive layer 260 overlap with each other with the insulating layer 285 sandwiched therebetween.

[0333] In the semiconductor device shown in Figures 14(B) and 14(C), the insulating layer 283 and the insulating layer 285 are provided between the conductive layer 240 and the conductive layer 260, and therefore, by making the insulating layer 285 thicker, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced.

[0334] The semiconductor device shown in FIGS. 15(A) to 15(C) has an insulating layer 283 and an insulating layer 285 on an insulating layer 250. The insulating layer 285 has an opening 270, and a conductive layer 260a is provided in the opening 270. FIG. 15(A) is a plan view of a semiconductor device having a transistor 200. FIG. 15(B) is a cross-sectional view taken along dashed line A1-A2 in FIG. 15(A). FIG. 15(C) is a cross-sectional view taken along dashed line A3-A4 in FIG. 15(A).

[0335] In the semiconductor device illustrated in FIG. 15B and FIG. 15C, the opening 270 overlaps with the opening 290 in a plan view. The conductive layer 260a has a region located in the opening 270 provided in the insulating layer 285. The insulating layer 283 has a region overlapping with an upper surface of the conductive layer 240 with the oxide semiconductor layer 230 sandwiched therebetween, and a region sandwiched between a side surface of the opening 270 and a side surface of the conductive layer 260a. It is preferable that the height of the upper surface of the conductive layer 260a and the height of the upper surface of the insulating layer 285 are the same or approximately the same. The conductive layer 260b is provided over the conductive layer 260a, the insulating layer 285, and the insulating layer 283. The conductive layer 240 and the conductive layer 260b overlap with each other with the insulating layer 285 sandwiched therebetween. The conductive layer 260a is not provided in a region outside the opening 270 in a plan view.

[0336] 15B and 15C, the insulating layer 283 and the insulating layer 285 are provided between the conductive layer 240 and the conductive layer 260b, and therefore, by making the insulating layer 285 thicker, the parasitic capacitance between the conductive layer 240 and the conductive layer 260b can be reduced. In addition, the conductive layer 260a is not provided in a region outside the opening 270 in a plan view, and therefore the area overlapping with the conductive layer 240 is small. Therefore, the parasitic capacitance between the conductive layer 260a and the conductive layer 240 can be reduced.

[0337] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Each layer constituting the semiconductor device of this embodiment may have a single layer structure or a multilayer structure.

[0338] [Insulation layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for the insulating layer of the semiconductor device.

[0339] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the permeation of impurities and oxygen. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for the insulating layer having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0340] Specifically, it is preferable to use a barrier insulating layer against impurities such as water and hydrogen, and oxygen.

[0341] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property in which a corresponding substance is difficult to diffuse, a property in which a corresponding substance is difficult to permeate, a property in which the permeability of a corresponding substance is low, a function of suppressing the diffusion of a corresponding substance, or a function of suppressing the permeation of a corresponding substance. Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N 2 O, NO, NO 2 etc.), copper atom, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.

[0342] Examples of the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Other examples include oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0343] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of an insulating layer that is likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0344] Furthermore, for example, as transistors become finer and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a material with a high relative dielectric constant (high-k) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. In addition, it is possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. In addition, by using a material with a high relative dielectric constant as the dielectric layer of a capacitance element, it is possible to make the element have a larger capacitance value. On the other hand, by using a material with a low relative dielectric constant for the insulating layer that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, it is advisable to select a material according to the function of the insulating layer. In addition, a material with a low relative dielectric constant also has a high dielectric strength.

[0345] Examples of materials having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0346] Examples of materials with a low relative dielectric constant include resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with a low relative dielectric constant include silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. Examples of silicon oxides include silicon oxides having vacancies. These silicon oxides may contain nitrogen.

[0347] Furthermore, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be applied to both layers in which a material with a high dielectric constant is preferably used, such as a gate insulating layer, and layers in which a material with a low dielectric constant is preferably used, such as an interlayer film. These materials have a relatively low dielectric constant compared to high-k materials such as hafnium oxide, and therefore may be referred to as materials with a low dielectric constant in this specification and the like.

[0348] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0349] In addition, examples of materials that can have ferroelectricity include metal nitrides having elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. In addition, metal oxides having elements M1 and nitrogen may have ferroelectricity even if they do not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0350] In addition, materials that can have ferroelectricity include SrTaO 2 N, BaTaO 2 Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure 3 etc.

[0351] In the above description, metal oxides and metal nitrides are exemplified as materials that can have ferroelectricity, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0352] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0353] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0354] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer. In addition, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

[0355] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0356] The insulating layer 250 functions as a gate insulating layer of the transistor 200. For the insulating layer 250, a material with a high dielectric constant is preferably used.

[0357] The insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0358] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing magnesium. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium. Here, in metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, so that the ability to capture or fix hydrogen is high. Therefore, these metal oxides preferably have an amorphous structure. For example, the amorphous structure may be realized by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.

[0359] The function of capturing or fixing a corresponding substance can also be said to have a property that makes it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.

[0360] When the insulating layer 250 has a stacked structure, it is preferable to use a layer having a function of trapping and fixing hydrogen as one of the layers (hereinafter referred to as a first insulating layer of the insulating layer 250). When the insulating layer 250 has a stacked structure of two layers, a layer having a function of trapping and fixing hydrogen is used as a layer in contact with the oxide semiconductor layer 230, and when the insulating layer 250 has a stacked structure of three or more layers, a layer having a function of trapping and fixing hydrogen is used as a layer close to the oxide semiconductor layer 230, so that hydrogen contained in the oxide semiconductor layer 230 can be more effectively trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0361] In addition to the first insulating layer, the insulating layer 250 preferably uses a barrier insulating layer against hydrogen as a second insulating layer. Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0362] The insulating layer 250 may be made of, for example, hafnium silicate as the first insulating layer. The insulating layer 250 may preferably have an amorphous structure as the first insulating layer. By making the structure amorphous, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the insulating layer can be improved. This makes the film thickness distribution of the insulating layer uniform, and the extremely thin film thickness portions can be reduced, thereby improving the withstand voltage of the insulating layer. In addition, the film thickness distribution of the film provided on the insulating layer can be made uniform.

[0363] Moreover, by suppressing the formation of grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries, and therefore the insulating layer can function as an insulating film with low leakage current.

[0364] In addition, hafnium oxide is a material with a high dielectric constant, so hafnium silicate can also be a material with a high dielectric constant depending on the silicon content. Therefore, when used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0365] In view of the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the first insulating layer of insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0366] Furthermore, by using a barrier insulating layer against hydrogen as the second insulating layer of the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 260 into the oxide semiconductor layer 230. Silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Here, the second insulating layer is preferably an upper layer of the first insulating layer.

[0367] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0368] Furthermore, the insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride, etc. For example, the insulating layer 250 preferably comprises silicon oxide.

[0369] The insulating layer 250 preferably includes a layer capable of supplying oxygen to the oxide semiconductor layer 230. An oxide can be used as the layer capable of supplying oxygen. When the insulating layer 250 includes silicon oxide or silicon oxynitride, oxygen can be suitably supplied from the insulating layer 250 to the oxide semiconductor layer 230.

[0370] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0371] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 260, etc. When the insulating layer 250 has a stacked structure, each of the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 is preferably a barrier insulating layer against oxygen.

[0372] The layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280. When the layer has a barrier property against oxygen, the side surface of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0373] For example, by using a barrier insulating layer against hydrogen and oxygen for the above-mentioned second insulating layer, it is possible to suppress oxidation of the conductive layer 260. In addition, it is possible to suppress the oxygen contained in the oxide semiconductor layer 230 from diffusing into the conductive layer 260 and the formation of oxygen vacancies in the oxide semiconductor layer 230.

[0374] Examples of the barrier insulating layer against oxygen include oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0375] Hafnium and silicon-containing oxides (hafnium silicate) function as a barrier insulating layer against oxygen, and as mentioned above, they are also excellent insulating layers that can easily achieve an amorphous structure and have the ability to capture or fix hydrogen.

[0376] Furthermore, silicon nitride is an excellent insulating layer that not only functions as a barrier insulating layer against oxygen, but also has high barrier properties against hydrogen, as described above.

[0377] The insulating layer 250 preferably has a two-layer structure in which a first insulating layer having a function of capturing or fixing hydrogen and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.

[0378] As an example, the first insulating layer may be made of an oxide containing one or both of aluminum and hafnium, and the second insulating layer may be made of silicon nitride.

[0379] In addition, it is preferable to use a three-layer structure in which, from the oxide semiconductor layer 230 side, a third insulating layer having a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. The material with a relatively low dielectric constant of the third insulating layer refers to, for example, a material with a lower dielectric constant than any one or more of the other layers in the stacked structure. Here, silicon oxide or silicon oxynitride can be used as the third insulating layer. The third insulating layer is a layer in contact with the oxide semiconductor layer 230. By using an oxide for the third insulating layer, oxygen can be supplied to the oxide semiconductor layer 230. In addition, by providing the second insulating layer, it is possible to suppress the diffusion of oxygen contained in the third insulating layer into the conductive layer 260, and thus to suppress the oxidation of the conductive layer 260. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230.

[0380] As an example, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0381] The insulating layer 250 preferably has a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a third insulating layer made of a material with a relatively low dielectric constant, a first insulating layer having a function of trapping or fixing hydrogen, and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side. The first to third insulating layers can have a similar structure to that of the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, which can suppress desorption of oxygen from the oxide semiconductor layer 230. For example, aluminum oxide is preferably used as the fourth insulating layer. Aluminum oxide has a function of trapping or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.

[0382] As an example, aluminum oxide can be used as the fourth insulating layer, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0383] In particular, the thickness of the insulating layer 250 in a region overlapping with the channel formation region of the oxide semiconductor layer 230 is preferably 0.1 nm to 30 nm, more preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 8.0 nm, and still more preferably 0.5 nm to 7.0 nm.

[0384] In order to miniaturize the transistor, it is preferable that the thickness of each layer constituting the insulating layer 250 is thin. For example, the thickness of each layer constituting the insulating layer 250 is 0.1 nm to 10 nm, or 0.1 nm to 5 nm, or 0.5 nm to 5 nm, or 1 nm to less than 5 nm, or 1 nm to 3 nm. Each layer constituting the insulating layer 250 may have a region with the above thickness in at least a part thereof.

[0385] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0386] In addition, it is preferable to use a three-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the oxide semiconductor layer 230 side, as the insulating layer 250. Specifically, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0387] The silicon oxide film is an insulating film having a relatively low relative dielectric constant compared to other insulating films (typically, a silicon nitride film). The silicon oxide film has a function of supplying oxygen to the oxide semiconductor layer 230 or the like by performing heat treatment or the like. The silicon oxide film of the insulating layer 250 is preferably formed by a PEALD method. The thickness of the silicon oxide film of the insulating layer 250 is preferably 0.7 nm to 3 nm. The hafnium oxide film has a function of capturing hydrogen and fixing hydrogen. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. In particular, it is preferable to reduce the hydrogen concentration in the channel formation region of the oxide semiconductor layer 230. The insulating film containing hafnium may increase the relative dielectric constant of the insulating film.

[0388] The ALD method can deposit atoms one layer at a time, and thus has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. Thus, by using the ALD method, in the transistor of one embodiment of the present invention, the coverage of the insulating layer 250 on the sidewalls and bottom surface of the opening 290 can be improved, and the insulating layer 250 with a uniform thickness can be formed. Furthermore, the PEALD method can form films at lower temperatures by using plasma. Furthermore, by using plasma, the film formation rate can be increased, and productivity can be improved.

[0389] The insulating layer 250 preferably includes an insulating film having a function of extracting hydrogen from the oxide semiconductor layer 230. The silicon oxide film and the hafnium oxide film each have a function of extracting hydrogen from the oxide semiconductor layer 230.

[0390] The insulating layer 250 is preferably formed of two or more different films. By forming the insulating layer 250 of two or more different films, different functions can be imparted to the insulating layer 250. Examples of the different functions include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230. In addition, it is preferable to use the ALD process two or more times in forming the insulating layer 250. For example, the insulating layer 250 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and uniformity of the film thickness of the insulating layer 250. In addition, it is possible to improve productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0391] Note that a silicon oxynitride film can be used instead of the silicon oxide film in the insulating layer 250. A silicon nitride oxide film can be used instead of the silicon nitride film in the insulating layer 250. An oxide containing hafnium and aluminum, an oxide containing hafnium and silicon, or the like can be used instead of the hafnium oxide film in the insulating layer 250.

[0392] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0393] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0394] In addition, a barrier insulating layer against hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0395] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0396] For example, it is preferable to use a silicon nitride film as the insulating layer 210.

[0397] The insulating layer 210 may have a two-layer structure. For example, an insulating layer having a function of trapping or fixing hydrogen can be used as an upper layer of the insulating layer 210. In this manner, hydrogen in the oxide semiconductor layer 230 can be diffused to the upper layer of the insulating layer 210 through the conductive layer 220 and the hydrogen can be trapped or fixed. As a result, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0398] For example, it is preferable to use a silicon nitride film as the lower layer of the insulating layer 210 and an oxide film containing hafnium and silicon (hafnium silicate film) as the upper layer.

[0399] A barrier insulating layer against hydrogen is preferably used for one or more of the insulating layer 283 and the insulating layer 285. This can suppress diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be preferably used for the insulating layer 283.

[0400] It is particularly preferable to use silicon nitride formed by a sputtering method as one or more of the insulating layers 283 and 285. The sputtering method does not require the use of molecules containing hydrogen in a deposition gas, and therefore the hydrogen concentration in the insulating layer 283 can be reduced. Furthermore, by forming the insulating layer 283 by a sputtering method, silicon nitride with high density can be formed.

[0401] Alternatively, an insulating layer having a function of trapping or fixing hydrogen may be used as one or more of the insulating layers 283 and 285. With such a structure, diffusion of hydrogen from above the insulating layers 283 and 285 to the oxide semiconductor layer 230 can be suppressed, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Hafnium silicate, or the like can be used as one or more of the insulating layers 283 and 285.

[0402] Alternatively, the insulating layer 283 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 283 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0403] In addition, the semiconductor device may have a structure in which either the insulating layer 283 or the insulating layer 285 is not provided.

[0404] In addition, for example, a material with a low relative dielectric constant can be used as the insulating layer 285. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0405] The concentration of impurities such as water and hydrogen in the insulating layer 285 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0406] The insulating layer 280 preferably has the above-mentioned barrier insulating layer against hydrogen. The insulating layer 280 is provided so as to surround the oxide semiconductor layer 230. The insulating layer 280 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, and thus can suppress diffusion of hydrogen into the oxide semiconductor layer 230. For example, the insulating layer 280 preferably has a silicon nitride film.

[0407] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, and an excessive amount of oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230.

[0408] Furthermore, the use of silicon nitride for the insulating layer 280 can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Thus, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, which can improve the reliability of the transistor 200.

[0409] The insulating layer 280 preferably includes the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0410] For example, an insulating layer having a region containing excess oxygen can be formed by deposition in an atmosphere containing oxygen using a sputtering method. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a part of the layers constituting the insulating layer 280 in this manner, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0411] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0412] Since the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 200 , the thickness of the insulating layer 280 is appropriately set in accordance with the design value of the channel length of the transistor 200 .

[0413] The insulating layer 280 preferably has a laminated structure of, for example, an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0414] The insulating layer 280b is a layer in contact with a channel formation region of the oxide semiconductor layer 230. When an insulating layer containing oxygen is used as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0415] The insulating layer 280b preferably has a region with a higher oxygen content than at least one of the insulating layer 280a and the insulating layer 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content than each of the insulating layer 280a and the insulating layer 280c. By increasing the oxygen content of the insulating layer 280b, it becomes easier to form an i-type region in the oxide semiconductor layer 230 near the insulating layer 280b.

[0416] It is more preferable that the insulating layer 280b be a film that releases oxygen when heated. When the insulating layer 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor layer 230. When oxygen is supplied from the insulating layer 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V O H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0417] In order to improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0418] As an example, the amount of oxygen molecules released from the insulating layer 280b is 1.0×10 14 molecules / cm 2 That's it, 1.0 x 10 15 molecules / cm 2 The amount of released oxygen molecules can be measured by thermal desorption spectrometry.

[0419] In particular, when the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and V OThe influence of H on the electrical characteristics and reliability is particularly large. Therefore, by optimizing the amount of oxygen supplied to the oxide semiconductor layer 230 after sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230, a transistor with a short channel length, excellent electrical characteristics, and high reliability can be realized.

[0420] The insulating layer 280b is preferably formed by a deposition method such as a sputtering method or a PECVD method. In particular, when a sputtering method is used, hydrogen gas is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the oxide semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.

[0421] In order to increase the amount of oxygen supplied to the oxide semiconductor layer 230, for example, heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen may be performed after the insulating layer 280b is formed. Alternatively, oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the top surface of the insulating layer 280b by a sputtering method. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 280b, and the amount of oxygen supplied to the oxide semiconductor layer 230 can be increased.

[0422] In addition, the amount of oxygen supplied to the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region of the oxide semiconductor layer 230 in contact with the insulating layer 280c is smaller than that to the region of the oxide semiconductor layer 230 in contact with the insulating layer 280b. Therefore, the resistance of the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region of the oxide semiconductor layer 230 in contact with the insulating layer 280c may be reduced. In other words, by adjusting the thickness of the insulating layer 280a, the range of the region that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the region that functions as the other of the source region and the drain region can be controlled. In this way, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the characteristics required for the transistor.

[0423] In addition, it is preferable to use a material with a low relative dielectric constant for the insulating layer 280b, which can reduce the parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 280b.

[0424] It is preferable to use a barrier insulating layer against oxygen for each of the insulating layer 280a and the insulating layer 280c. By providing the insulating layer 280a between the insulating layer 280b and the conductive layer 220, it is possible to prevent the conductive layer 220 from being oxidized and the resistance of the conductive layer 220 from increasing. In addition, by providing the insulating layer 280c between the insulating layer 280b and the conductive layer 240, it is possible to prevent the conductive layer 240 from being oxidized and the resistance of the conductive layer 240 from increasing.

[0425] Alternatively, an insulating layer having a function of trapping or fixing hydrogen may be used as the insulating layer 280a. With such a structure, hydrogen can be prevented from diffusing from below the insulating layer 280a to the oxide semiconductor layer 230, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Thus, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 280a, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon can be used. Alternatively, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 280a. Similarly, an insulating layer having a function of trapping or fixing hydrogen may be used as the insulating layer 280c.

[0426] For example, the insulating layer 280a and the insulating layer 280c can be made of silicon nitride, and the insulating layer 280b can be made of silicon oxide.

[0427] [Conductive layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) of the semiconductor device, it is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium, and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0428] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0429] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high electrical conductivity.

[0430] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0431] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0432] The conductive layer 260 can be made of the above-mentioned metal elements, alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. For example, it is preferable to use a material with high conductivity, such as tungsten. In addition, it is preferable to use a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing oxygen diffusion, as the conductive layer 260. As described above, examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 260.

[0433] In addition, the conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an outer insulating layer may be captured.

[0434] The conductive layer 260 may have a thickness of, for example, 3 nm or more and 500 nm or less. The thickness of the conductive layer 260 may be, for example, equal to or greater than the thickness of the insulating layer 250. By making the conductive layer 260 thicker, the resistance of the conductive layer 260 can be reduced.

[0435] In addition, the conductive layer 260 preferably has a two-layer structure including a conductive layer 260a and a conductive layer 260b over the conductive layer 260a.

[0436] By using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 260a, for example, release of oxygen from the oxide semiconductor layer 230 can be suppressed, and formation of oxygen vacancies in the oxide semiconductor layer 230 can be suppressed.

[0437] In addition, by using a conductive material that is not easily oxidized as the conductive layer 260a, it is possible to suppress, for example, the conductive layer 260a from being oxidized and the conductivity from being reduced due to the release of oxygen from the oxide semiconductor layer 230 or the release of oxygen from the insulating layer 250.

[0438] The material used for the conductive layer 260b preferably has a higher conductivity than the material used for the conductive layer 260a, for example. In addition, by making the conductive layer 260b thicker, the current flowing through the conductive layer 260b can be further increased.

[0439] The conductive layer 260a can be suitably formed along the sidewall of the opening 290 by using a film formation method with high coverage.

[0440] The conductive layer 260a can be, for example, a conductive material containing nitrogen, a conductive material containing oxygen, etc. In addition, the conductive layer 260a can be, for example, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.

[0441] The conductive layer 260a may be made of, for example, a conductive material containing the above-mentioned metal element and nitrogen, such as tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, a nitride containing tantalum and aluminum, or the like.

[0442] Furthermore, the conductive layer 260a can be made of a conductive material containing the aforementioned metal element and oxygen, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.

[0443] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

[0444] In addition, as the conductive layer 260a, materials including titanium, tantalum, ruthenium, and one or more selected from these metal elements are preferable because they are conductive materials that are resistant to oxidation, have a function of suppressing the diffusion of oxygen, or maintain conductivity even when they absorb oxygen.

[0445] The conductive layer 260b may be made of, for example, the above-mentioned metal elements, an alloy containing the above-mentioned metal elements, or an alloy combining the above-mentioned metal elements. For example, tungsten may be used.

[0446] The conductive layer 260a may further have a stacked structure. The conductive layer 260b may further have a stacked structure. When the conductive layer 260a has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260a may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked. When the conductive layer 260b has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260b may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked.

[0447] Since the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0448] By using a conductive material containing oxygen as the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, IZO (registered trademark), or the like.

[0449] When the conductive layer 220 has a three-layer structure of a first conductive layer (e.g., conductive layer 220a), a second conductive layer (e.g., conductive layer 220b), and a third conductive layer (e.g., conductive layer 220c) on the insulating layer 210 in this order, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the first conductive layer, a material with high conductivity as the second conductive layer, and a conductive material containing oxygen as the third conductive layer. Specifically, it is preferable to use titanium nitride as the first conductive layer, tungsten as the second conductive layer, and ITO or ITSO as the third conductive layer. In this case, titanium nitride is in contact with the insulating layer 210, and ITO or ITSO is in contact with the oxide semiconductor layer 230. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. When tungsten, which has high conductivity, is used for the second conductive layer, the conductivity of the conductive layer 220 can be increased.

[0450] Furthermore, when the conductive layer 240 has a two-layer laminated structure (for example, the conductive layer 240a and the conductive layer 240b), it is preferable to use a material having a higher conductivity than the upper layer for the lower layer and a conductive material containing oxygen for the upper layer. Specifically, it is preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride for the lower layer and ITO or ITSO for the upper layer. In this case, ITO or ITSO is in contact with the oxide semiconductor layer 230. With such a structure, the conductive layer 240 can maintain its conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, by using a material having a higher conductivity than the upper layer for the lower layer, it is possible to increase the conductivity of the conductive layer 240.

[0451] In addition, when the conductive layer 240 has a two-layer structure, a material having high conductivity may be used for the upper layer (e.g., the conductive layer 240b) and a conductive material containing oxygen may be used for the lower layer (e.g., the conductive layer 240a). In such a case, for example, the oxide semiconductor layer 230 is in contact with the upper surface of the conductive layer 240a, whereby the contact resistance between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0452] [Oxide semiconductor layer 230] As the oxide semiconductor layer 230, the oxide semiconductor layer 230 described in the above embodiment can be used.

[0453] Hydrogen in the oxide semiconductor reacts with oxygen that bonds to metal atoms to form water, creating oxygen vacancies (V O In addition, defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V OHydrogen may function as a donor and generate electrons that serve as carriers. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a lot of hydrogen tends to have normally-on characteristics (that is, a threshold voltage that has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a lot of hydrogen, the reliability of the transistor may be deteriorated.

[0454] V in the oxide semiconductor layer 230 O It is preferable to reduce H as much as possible and make the oxide semiconductor layer 230 highly intrinsic or substantially highly intrinsic. O In order to obtain an oxide semiconductor with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies. O Stable electrical characteristics can be obtained by using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies is sometimes referred to as oxygen adding treatment.

[0455] The carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0456] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0457] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0458] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0459] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3less than 1×10 18 atoms / cm 3 Less than.

[0460] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0461] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0462] In addition, the semiconductor device of this embodiment may be applied to a transistor using another semiconductor material in the channel formation region. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor. Examples of the semiconductor made of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include an organic semiconductor and a nitride semiconductor. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may include impurities as dopants.

[0463] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0464] The semiconductor layer of the transistor may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0465] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to group 16). Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively, MoS 2 ), molybdenum selenide (represented by MoSe 2 ), molybdenum tellurium (represented by MoTe 2 ), tungsten sulfide (represented by WS 2 ), tungsten selenide (represented by WSe 2 ), tungsten tellurium (represented by WTe 2 ), hafnium sulfide (represented by HfS 2 ), hafnium selenide (represented by HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (represented by ZrSe 2 ) etc.

[0466] [substrate] As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available. Furthermore, there is a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, etc. are available. As the conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. are available. Furthermore, there is a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or insulator is provided on a conductive substrate, etc. are available. Alternatively, these substrates on which elements are provided may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0467] <Example of a method for manufacturing a semiconductor device> A method for manufacturing a semiconductor device will be described with reference to Figures 16(A) to 16(C). Here, as an example, a method for manufacturing a structure shown in Figures 7(A) to 7(C) will be described. Note that, regarding the materials and formation methods of each element, descriptions of parts similar to those described above may be omitted.

[0468] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, or the like.

[0469] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. There is also RF-superimposed DC sputtering, which superimposes RF and DC. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming a film using a conductive target. In addition to forming a conductive film, DC sputtering can also form an insulating film by performing reactive sputtering. Pulsed DC sputtering is mainly used when forming a film of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows control of ion energy during film formation and control of the target side potential. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Also, a high-quality film can be obtained.

[0470] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is performed by self-bias or the like. In addition, long-throw sputtering can form anisotropic film by increasing the distance between the sputtering target and the substrate.

[0471] CVD methods can be classified into PECVD, thermal CVD (TCVD) that uses heat, photo CVD (Photo CVD) that uses light, etc. They can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0472] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0473] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0474] In addition, the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD (Plasma Enhanced ALD) method can be preferable in some cases because it uses plasma and allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In one embodiment of the present invention, a metal oxide film formation method uses an ALD method. However, since the method employs a high substrate temperature condition during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0475] Unlike the film formation method in which particles emitted from a target are deposited, the CVD method and the ALD method are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method with a fast film formation speed or a CVD method. For example, when the metal oxide has a layered structure of a first metal oxide and a second metal oxide, a method of forming a film of the first metal oxide using a sputtering method and forming a film of the second metal oxide on the first metal oxide using an ALD method can be mentioned. For example, when the first metal oxide has a crystal part, the second metal oxide may grow as a crystal with the crystal part as a nucleus.

[0476] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gas. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transport and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0477] In addition, in the ALD method, a film of any composition can be formed by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), etc. In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0478] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0479] Furthermore, when processing a thin film constituting a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0480] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0481] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0482] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0483] First, the conductive layer 220 is formed over the insulating layer 210, the insulating layer 280 is formed over the conductive layer 220, and the conductive layer 240 is formed over the insulating layer 280. Note that the insulating layer 280 here has a three-layer structure of an insulating layer 280a, an insulating layer 280b, and an insulating layer 280c.

[0484] Note that after the insulating layer 280 is formed, a planarization treatment (also referred to as a CMP treatment) using a chemical mechanical polishing (CMP) method is preferably performed to planarize the top surface of the insulating layer 280. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240, which functions as a wiring, is formed can be made flat, and discontinuity of the conductive layer 240 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, the manufacturing cost can be reduced.

[0485] Next, openings 290 are formed in the conductive layer 240 and the insulating layer 280 at positions overlapping the conductive layer 220 (FIG. 16(A)). At this time, recesses are formed in the conductive layer 220 at positions overlapping the openings 290.

[0486] Since the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive layer 240 and a part of the insulating layer 280 by anisotropic etching. In particular, processing by a dry etching method is preferable because it is suitable for fine processing. In addition, the processing may be performed under different conditions depending on the layer.

[0487] Here, it is preferable to use processing conditions that give the side walls of the conductive layer 240 and the insulating layer 280c a tapered shape, and it is also preferable to use processing conditions that give the side walls of the insulating layer 280b a steep shape.

[0488] Furthermore, the insulating layer 280a may be formed using processing conditions that result in a tapered sidewall, or may be formed using processing conditions that result in a steep sidewall.

[0489] Here, by devising the materials of the insulating layers 280c and 280b, it is possible to form the insulating layer 280c in a tapered shape and the insulating layer 280b in a steep shape using the same dry etching conditions.

[0490] Subsequently, a heat treatment may be performed, for example, at 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the heat treatment may be performed at a temperature of 350° C. to 550° C. for a treatment time of 1 minute to 1 hour, or 10 minutes to 30 minutes.

[0491] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230.

[0492] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the insulating layer 280 as much as possible.

[0493] The conductive layer 240 and the insulating layer 280 may be opened using the same mask or different masks.

[0494] Next, the oxide semiconductor layer 230 is formed so as to cover the opening 290. The oxide semiconductor layer 230 is formed in contact with the upper surface of the conductive layer 220, the side surface of the insulating layer 280, and the upper surface and side surface of the conductive layer 240.

[0495] The oxide semiconductor layer 230 can be formed by stacking a plurality of layers. Here, the oxide semiconductor layer 230 is formed by depositing a first layer, a second layer, and a third layer in this order.

[0496] It is preferable to use a film formation method for the first layer that causes little damage to the insulating layer 280 and does not cause alloying with the insulating layer 280. For example, it is preferable to form the first layer using an ALD method, a PECVD method, a thermal CVD method, an MOCVD method, an MBE method, or the like.

[0497] Moreover, it is preferable that the oxide semiconductor layer 230 has a high aspect ratio and high coverage on the sidewall and bottom of the opening 290 having a small diameter. Therefore, it is preferable that at least some of the layers formed as the oxide semiconductor layer 230 are formed using a method with excellent coverage. In particular, by using the ALD method, a film with small thickness variation can be formed in the opening 290 along the upper surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0498] In addition, the oxide semiconductor layer 230 preferably has high crystallinity. By increasing the crystallinity of the oxide semiconductor layer 230, diffusion of impurities in the oxide semiconductor layer 230 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and the reliability can be improved. For example, a metal oxide formed by a sputtering method is likely to have high crystallinity. Thus, by forming at least a part of the layers formed as the oxide semiconductor layer 230 by a sputtering method, the oxide semiconductor layer 230 can have crystallinity.

[0499] On the other hand, the sputtering method may have poorer coverage than methods such as the ALD method. Therefore, in consideration of the coverage of the sidewall and bottom of the opening 290, when the sputtering method is used for one layer of the multiple layers formed as the oxide semiconductor layer 230, it is preferable to use a layer formed by a method having excellent coverage in combination with the other layer.

[0500] The above embodiment can be referred to for the method of forming the oxide semiconductor layer 230. First, the oxide semiconductor layer 230a is formed (not shown).

[0501] Next, an oxide semiconductor layer 230b is formed by sputtering (not shown).

[0502] Next, an oxide semiconductor layer 230c (not shown) is formed by ALD.

[0503] Following the formation of the oxide semiconductor layer 230c, heat treatment may be performed. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 can be increased. In particular, the crystallinity of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be increased. For example, the heat treatment conditions and the heat treatment method described in Embodiment 1 can be used for the heat treatment. Furthermore, following the formation of the oxide semiconductor layer 230c, the heat treatment does not necessarily have to be performed. For example, the heat treatment may be performed after the formation of the insulating layer 250, which will be described later. Alternatively, for example, the crystallinity of the oxide semiconductor layer 230 can be increased by using heat generated during the formation of the conductive layer 260, which will be described later.

[0504] Next, the conductive layer 240 and the oxide semiconductor layer 230 are processed into an island shape (FIG. 16B). Here, the conductive layer 240 and the oxide semiconductor layer 230 can be processed at the same time by using the same mask.

[0505] Note that the step of processing the conductive layer 240 into an island shape and the step of processing the oxide semiconductor layer 230 into an island shape may be performed independently. In this case, for example, the step of processing the conductive layer 240 into an island shape and the step of providing the opening 290 in the conductive layer 240 can be performed independently, and the order of the steps does not matter. In addition, the island shape processing and the formation of the opening may be performed at the same time by performing exposure using a mask for processing into a square island shape and exposure using a mask for providing a circular opening, and then performing etching. In addition, exposure using a multi-tone mask (typically a half-tone mask or a gray-tone mask) may be used.

[0506] Subsequently, the insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0507] The heat generated during the formation of the insulating layer 250 may be used to enhance the crystallinity of the oxide semiconductor layer 230. By setting the deposition temperature of the insulating layer to, for example, 250° C. or higher, more preferably 350° C. or higher, the heat generated during the deposition of the insulating layer may enhance the crystallinity of the oxide semiconductor layer 230.

[0508] After the insulating layer 250 is formed, heat treatment may be performed. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 can be increased. In particular, the crystallinity of the oxide semiconductor layer 230c and the oxide semiconductor layer 230b can be increased. After the insulating layer 250 is formed, heat treatment does not necessarily have to be performed.

[0509] When heat treatment is performed, it may be performed at, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the treatment may be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour, or 10 minutes to 30 minutes.

[0510] The gas used in the heat treatment can be nitrogen gas, an inert gas, or an oxidizing gas. For example, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By the heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.

[0511] The heat treatment may be carried out under reduced pressure.

[0512] In addition, in the case where the insulating layer 280 contains oxygen, it is preferable to supply oxygen from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 by heat treatment. O H can be reduced.

[0513] Next, a conductive layer to become the conductive layer 260a is formed over the insulating layer 250. The conductive layer to become the conductive layer 260a is formed so as to cover an upper surface of the conductive layer 220, a side surface of the insulating layer 280, and an upper surface and a side surface of the conductive layer 240, with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. Next, a conductive layer to become the conductive layer 260b is formed.

[0514] The conductive layer 260a and the conductive layer 260b are formed in contact with the insulating layer 250 provided in the opening 290 having a large aspect ratio. Therefore, the conductive layer that becomes the conductive layer 260a and the conductive layer that becomes the conductive layer 260b are preferably formed by a film formation method having good coverage, and more preferably, the ALD method, the metal CVD method, or the like.

[0515] Here, the crystallinity of the oxide semiconductor layer 230 may be improved by using heat generated during deposition of the conductive layer that will become the conductive layer 260. By setting the deposition temperature of the conductive layer that will become the conductive layer 260 to, for example, 250° C. or higher, more preferably 350° C. or higher, the crystallinity of the oxide semiconductor layer 230 may be improved by the heat generated during deposition of the conductive layer. Here, for example, the conductive layer is formed by a metal CVD method using a temperature of 250° C. or higher.

[0516] Next, the conductive layer to be the conductive layer 260b and the conductive layer to be the conductive layer 260a are partly removed using a mask to form the conductive layer 260b and the conductive layer 260a (FIG. 16C).

[0517] Next, the insulating layer 283 is formed over the conductive layer 260. Subsequently, the insulating layer 285 is formed over the insulating layer 283.

[0518] Here, the heat used in forming the insulating layers 283 and 285 can be used to increase the crystallinity of the oxide semiconductor layer 230 in some cases. When the insulating layers are formed at a temperature of, for example, 250° C. or higher, more preferably 350° C. or higher, the heat used in forming the insulating layers can increase the crystallinity of the oxide semiconductor layer 230 in some cases. Here, for example, the insulating layer 283 is formed by an ALD method at a temperature of 250° C. or higher, and then the insulating layer 285 is formed by a sputtering method.

[0519] In the above manner, a semiconductor device of one embodiment of the present invention can be manufactured.

[0520] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0521] (Embodiment 3) In this embodiment, a memory device of one embodiment of the present invention will be described with reference to FIGS. 17 to 21. A semiconductor device of one embodiment of the present invention can be used as a memory device. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0522] <Storage device configuration example 1> The structure of a memory device including a transistor and a capacitor will be described with reference to Figures 17(A) to 17(C). Figure 17(A) is a plan view of a memory device including a transistor 200 and a capacitor 100. Figure 17(B) is a cross-sectional view taken along dashed line A1-A2 in Figure 17(A). Figure 17(C) is a cross-sectional view taken along dashed line A3-A4 in Figure 17(A).

[0523] 17A to 17C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280, and an insulating layer 283 over the memory cell 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 283 function as interlayer films. The conductive layer 110 functions as a wiring.

[0524] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0525] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0526] As shown in FIG. 17(B) and FIG. 17(C), the insulating layer 180 is provided with an opening 190 that reaches the conductive layer 110. At least a part of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region that contacts the upper surface of the conductive layer 110 in the opening 190, a region that contacts the side surface of the insulating layer 180 in the opening 190, and a region that contacts at least a part of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a part of it is located in the opening 190. The conductive layer 120 is disposed so that at least a part of it is located in the opening 190. As shown in FIG. 17(B) and FIG. 17(C), the conductive layer 120 is preferably provided so as to fill the opening 190. The films provided inside the opening 190 are preferably formed using a method with high coverage such as the ALD method. This improves the coverage of the film. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed using an ALD method, a metal CVD method, or the like.

[0527] In the opening 190, the capacitive element 100 has an upper electrode and a lower electrode facing each other with a dielectric sandwiched therebetween, not only on the bottom surface but also on the side surface, so that the capacitance per unit area can be increased. Therefore, the deeper the opening 190, the larger the capacitance of the capacitive element 100 can be. Increasing the capacitance per unit area of ​​the capacitive element 100 in this way can stabilize the read operation of the memory device. In addition, miniaturization or high integration of the memory device can be promoted.

[0528] 17B and 17C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0529] A conductive layer 115 and an insulating layer 130 are laminated along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190. The capacitive element 100 having such a configuration may be called a trench type capacitor or a trench capacitor.

[0530] An insulating layer 280 is disposed on the capacitive element 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed below the insulating layer 280.

[0531] The transistor 200 includes a conductive layer 120 (corresponding to the conductive layer 220 in FIG. 7B etc.), a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 120 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode.

[0532] The transistor 200 can be described in the first embodiment (FIGS. 7, 9, etc.), and therefore detailed description thereof will be omitted. The transistor included in the memory cell 150 is not limited to the transistor 200 in the memory cell 150 shown in FIG. 7, FIG. 9, etc., and any of the transistors exemplified in the first embodiment can be used.

[0533] As shown in FIG. 17A to FIG. 17C, the transistor 200 is provided so as to overlap with the capacitor 100. An opening 290 in which part of the structure of the transistor 200 is provided has a region overlapping with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100, so that the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This can reduce the occupied area of ​​the memory cell 150, and therefore the memory cells 150 can be arranged at a high density, thereby increasing the memory capacity of the memory device. In other words, the memory device can be highly integrated.

[0534] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, and an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics can be suppressed.

[0535] A circuit diagram of the memory device described in this embodiment is shown in Figure 23(A). As shown in Figure 23(A), the configurations shown in Figures 17(A) to 17(C) function as memory cells. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0536] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitance element CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitance element CA is connected to a wiring CAL.

[0537] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in Figs. 17(A) to 17(C), it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 240 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided to cross each other. Also, in Fig. 17(A), the wiring CAL (conductive layer 110) is provided in a planar shape, but the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring WOL (conductive layer 260) or parallel to the wiring BIL (conductive layer 240).

[0538] The memory cells will be described in detail in a later embodiment.

[0539] [Capacitive element 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. In addition, a conductive layer 110 is provided under the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0540] The conductive layer 110 is provided on the insulating layer 140. The conductive layer 110 functions as a wiring CAL and can be provided in a planar shape, for example. The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the [Conductive Layer] section of Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0541] The conductive layer 115 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen, and is used in a single layer or a stacked layer. For example, titanium nitride or indium tin oxide to which silicon is added may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the conductive layer 110 can be prevented from being oxidized by the insulating layer 130. Furthermore, when an oxide is used for the insulating layer 180, the conductive layer 110 can be prevented from being oxidized by the insulating layer 180.

[0542] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to contact the upper surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 is preferably structured to cover the side end portions of the conductive layer 110. This can prevent the conductive layer 115 and the conductive layer 120 from shorting out.

[0543] Alternatively, a structure may be used in which the side ends of the insulating layer 130 coincide with the side ends of the conductive layer 115. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.

[0544] It is preferable to use a material having a high relative dielectric constant (high-k) for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0545] The insulating layer 130 is preferably made of a laminate of insulating layers made of a high-k material, and preferably has a laminate structure of a high dielectric constant (high-k) material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, the insulating film may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, the insulating film may be made of an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By using a laminate of insulating layers having a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 100 can be suppressed.

[0546] Moreover, a material that can have ferroelectricity may be used as the insulating layer 130. For details about the material that can have ferroelectricity, the description in the first embodiment can also be referred to.

[0547] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nm, and are therefore preferable for the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). In addition, for example, the film thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitive element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0548] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupancy area) of the ferroelectric layer in a plan view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Less than or equal to 0.1μm2 Even if the thickness is less than 10,000 nm, the material can have ferroelectric properties. 2 or less than 1000 nm 2 Even if the thickness is less than 100 nm, the material may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0549] A ferroelectric is an insulator, and has a property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. Therefore, a nonvolatile memory element can be formed by using a capacitance element (hereinafter, sometimes referred to as a ferroelectric capacitor) using this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device shown in this embodiment functions as a ferroelectric memory.

[0550] The conductive layer 120 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 120 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction. In a structure in which the insulating layer 130 covers the side end of the conductive layer 115, the side end of the conductive layer 120 may be located outside the side end of the conductive layer 115.

[0551] The conductive layer 120 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. It is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen as the conductive layer 120. For example, titanium nitride or tantalum nitride can be used. For example, a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, titanium nitride is in contact with the insulating layer 130, and tantalum nitride is in contact with the oxide semiconductor layer 230. With such a structure, excessive oxidation of the conductive layer 120 by the oxide semiconductor layer 230 can be suppressed. Furthermore, when an oxide is used for the insulating layer 130, excessive oxidation of the conductive layer 120 by the insulating layer 130 can be suppressed. Alternatively, for example, a structure in which tungsten is stacked on titanium nitride may be used as the conductive layer 120.

[0552] In addition, since the conductive layer 120 has a region in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material containing oxygen. By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 120 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen such as zirconium oxide is used for the insulating layer 130, the conductive layer 120 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used as the conductive layer 120 in a single layer or a stacked layer.

[0553] Since the insulating layer 180 functions as an interlayer film, it is preferable that the insulating layer 180 has a low relative dielectric constant. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low relative dielectric constant can be used in a single layer or a multilayer structure. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0554] 17(B) and 17(C), the insulating layer 180 is shown as a single layer, but the present invention is not limited to this. The insulating layer 180 may have a laminated structure of two layers, or a laminated structure of three or more layers.

[0555] <Storage device configuration example 2> 18A and 18B are cross-sectional views of a memory device including a transistor 200A and a transistor 200B.

[0556] 18A and 18B includes an insulating layer 140 over a substrate (not shown), a memory cell 150 over the insulating layer 140, and an insulating layer 180, an insulating layer 280, an insulating layer 283, and an insulating layer 285 over the insulating layer 140. The insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0557] Memory cell 150 includes transistor 200B on insulating layer 140 and transistor 200A on transistor 200B.

[0558] The transistor 200A will not be described in detail because the description of the transistor 200 in Embodiment 2, such as in FIGS. 9A to 9B, can be referred to. The conductive layer 220 of the transistor 200A (a two-layer stacked structure of a conductive layer 220a and a conductive layer 220b over the conductive layer 220a in FIGS. 18A and 18B) can function as a gate electrode of the transistor 200B. The insulating layer 180 and the conductive layer 145 have an opening 190. FIGS. 18A and 18B show an example in which the conductive layer 145 has a stacked structure of a conductive layer 145a and a conductive layer 145b over the conductive layer 145a. The conductive layer 120 has a recess overlapping with the opening 190. The transistor 200B includes a conductive layer 120, a conductive layer 145 over the insulating layer 180, a semiconductor layer 135 provided in contact with a bottom surface and a side surface of a recess of the conductive layer 120, a side surface of an opening 190, and an upper surface of the insulating layer 180, and an insulating layer 155 over the semiconductor layer 135. The conductive layer 220a is provided over the insulating layer 155 and has a region located in the opening 190. The conductive layer 120, the conductive layer 145a, the conductive layer 145b, the semiconductor layer 135, and the insulating layer 155 of the transistor 200B can refer to the conductive layer 220, the conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230, and the insulating layer 250 included in the transistor 200 in FIGS. 9A to 9B of Embodiment 2, respectively. Furthermore, the transistors included in the memory cell 150 are not limited to the combination of the transistor 200A and the transistor 200B, and one or more types of the transistors exemplified in the second embodiment may be used.

[0559] In the memory cell 150 shown in Figures 18(A) and 18(B), the capacitance generated between the conductive layer 220a and the conductive layer 145 can be used, so that data can be retained without forming a separate capacitor.

[0560] As shown in FIG. 18A and FIG. 18B, the transistor 200B is provided so as to overlap with the transistor 200A. The opening 290 has a region overlapping with the opening 190. The conductive layer 220a and the conductive layer 220b function as one of the source electrode and drain electrode of the transistor 200A and as the gate electrode of the transistor 200B, so that the transistors 200A and 200B share part of their structures. With this structure, the transistors 200A and 200B can be ...

Claims

1. An oxide semiconductor layer containing indium, the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are confirmed in each of the first region, the second region, and the third region.

2. In claim 1, the second region comprises zinc; the second region has crystals; The c-axis of the crystal is approximately parallel to a normal direction of a surface on which the oxide semiconductor layer is formed.

3. In claim 1, The second region has a higher c-axis orientation rate than the first region.

4. In claim 1, The third region has a higher c-axis orientation rate than the first region.

5. In claim 1, a content of indium in the first region is higher than a content of indium in the second region; an indium content in the third region being higher than an indium content in the second region;

6. forming a first metal oxide; forming a second metal oxide on the first metal oxide; A method for forming an oxide semiconductor layer by forming a third metal oxide over the second metal oxide, Each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent; the second metal oxide is formed by a sputtering method using a sputtering target containing indium.

7. In claim 6, The sputtering target comprises zinc, The sputtering method is performed in an atmosphere containing oxygen.

8. In claim 6, The method for forming an oxide semiconductor layer, wherein the substrate is heated to a temperature of 100° C. or higher and 350° C. or lower in the ALD method.

9. In claim 6, a first metal oxide layer formed on the first metal oxide layer, a second metal oxide layer formed on the second metal oxide layer, and a third metal oxide layer formed on the third metal oxide layer.

10. In claim 6, No clear boundary is observed between the first metal oxide and the second metal oxide; A method for forming an oxide semiconductor layer, wherein no clear boundary is observed between the second metal oxide and the third metal oxide.

11. In claim 6, After forming the third metal oxide on the second metal oxide, A method for forming an oxide semiconductor layer, comprising the steps of: performing heat treatment at a temperature higher than or equal to 350° C. and lower than or equal to 550° C.

12. a transistor on a first insulating layer and a second insulating layer; the transistor includes a first conductive layer on the first insulating layer, a second conductive layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode; the second insulating layer is located between the first conductive layer and the second conductive layer; the second conductive layer is located on the second insulating layer; the second insulating layer and the second conductive layer have a first opening reaching the first conductive layer; the oxide semiconductor layer is in contact with a side surface of the second insulating layer in the first opening and a side surface of the second conductive layer in the first opening; the gate insulating layer is located on the oxide semiconductor layer; the gate electrode has a region in the first opening that overlaps with the oxide semiconductor layer with the gate insulating layer interposed therebetween; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to the formation surface are confirmed in each of the first region, the second region, and the third region.

13. In claim 12, a side surface of the second insulating layer in the first opening has a fourth region that forms an angle of 75 degrees or more and 90 degrees or less with respect to an upper surface of the first conductive layer; The first region is in contact with the fourth region.

14. forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a first opening reaching the first conductive layer by removing a portion of the second conductive layer and a portion of the first insulating layer to expose an upper surface of the first conductive layer; forming a first metal oxide so as to be in contact with a top surface of the first conductive layer, a side surface of the first opening of the first insulating layer, a side surface of the first opening of the second conductive layer, and a top surface of the second conductive layer; forming a second metal oxide on the first metal oxide; forming a third metal oxide on the second metal oxide; forming a second insulating layer in contact with an upper surface of the third metal oxide; forming a third conductive layer on the second insulating layer; Each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent; The second metal oxide is formed by a sputtering method using a sputtering target containing indium.

15. In claim 14, The method for manufacturing a semiconductor device, wherein the third conductive layer is formed by a metal CVD method at a temperature of 250° C. or higher.

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