Solid-state imaging apparatus, method for driving solid-state imaging apparatus, and electronic apparatus

Abstract

To provide a solid-state imaging apparatus, a method for driving a solid-state imaging apparatus, and an electronic apparatus, capable of substantially achieving a wide dynamic range and a high frame rate by minimizing the reduction of an SNR at the coupling point of an HCG signal and an LCG signal, without being affected by optical specification and sufficiently exhibiting single exposure high dynamic range (SEHDR) performance.SOLUTION: In a solid-state imaging apparatus 10, pixels 200 arranged in matrix in a pixel part 20 include a photoelectric conversion read-out part 210 and the voltage level of a first low conversion gain signal for reading out with a first low conversion gain LCG1 is equivalent to the voltage level of a second low conversion gain signal for reading out with a second low conversion gain LCG2.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device, a driving method for a solid-state imaging device, and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Complementary Metal Oxide Semiconductor (CMOS) image sensors are in practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate electric charges. CMOS image sensors are widely used as part of various electronic devices, such as digital cameras, video cameras, surveillance cameras, medical endoscopes, personal computers (PCs), car-mounted cameras, and portable terminal devices (mobile devices) such as mobile phones.

[0003] CMOS image sensors have a photodiode (photoelectric conversion element) and a floating diffusion (FD) amplifier with a floating diffusion layer for each pixel, and the mainstream readout method is the column-parallel output type, which selects a row in the pixel array and reads out the pixels simultaneously in the column output direction.

[0004] Generally, each pixel of a CMOS image sensor is composed of four active elements: a transfer transistor as a transfer element, a reset transistor as a reset element, a source follower transistor as a source follower element (amplification element), and a selection transistor as a selection element, for example for one photodiode.

[0005] The transfer transistor is selected during a predetermined transfer period to become conductive, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode to the floating diffusion FD. The reset transistor is selected during a predetermined reset period and becomes conductive, resetting the floating diffusion FD to the potential of the power supply line. The selection transistor is selected and turned on during read scanning, which causes the source follower transistor to output the column output read signal converted into a voltage signal by the floating diffusion FD to the vertical signal line.

[0006] For example, in a read scan period, after the floating diffusion FD is reset to, for example, the potential (reference potential) of the power supply line during the reset period, the charge of the floating diffusion FD is converted into a voltage signal with a gain according to the FD capacitance and output to the vertical signal line as a reference level read reset signal (reference level signal) VRST. Then, during a predetermined transfer period, the charge (electrons) photoelectrically converted and accumulated in the photodiode is transferred to the floating diffusion FD. The charge in the floating diffusion FD is converted into a voltage signal with a gain according to the FD capacitance, and is output to the vertical signal line as a signal level readout signal (signal level signal) VSIG. The output signal of the pixel is subjected to CDS (correlated double sampling) processing as a differential signal (VSIG-VRST) in the column readout circuit.

[0007] In this way, a normal pixel read signal (hereinafter, sometimes referred to as a pixel signal) PS is formed by a read reset signal VRST of one reference level and a read signal VSIG of one signal level.

[0008] In a CMOS image sensor, photoelectric charges generated and accumulated in a photodiode are read out by sequentially scanning each pixel or each row. In this progressive scanning, that is, when a rolling shutter is used as an electronic shutter, the start and end times of exposure for accumulating photoelectric charges cannot be made consistent for all pixels, which causes a problem of distortion in the captured image when capturing a moving subject.

[0009] Therefore, for applications such as capturing images of fast-moving subjects where image distortion cannot be tolerated, or sensing applications that require synchronicity of captured images, a global shutter is used as the electronic shutter, which starts and ends exposure at the same timing for all pixels in the pixel array.

[0010] A CMOS image sensor that employs a global shutter as an electronic shutter has, for example, a signal holding section in a pixel that holds a signal read out from a readout section in a signal holding capacitor. In a CMOS image sensor that uses a global shutter, electric charges from the photodiodes are simultaneously stored as voltage signals in the signal holding capacitors of the signal holding section using an analog sample-and-hold operation, and then the signals are read out sequentially, ensuring simultaneity of the entire image (for example, see non-patent document 1).

[0011] As typical configurations of each pixel, a four-transistor (4Tr) APS pixel (see, for example, Patent Document 1) or a capacitive feedback transimpedance amplifier (CTIA) pixel (see, for example, Patent Documents 2 and 3) are known.

[0012] Known pixels having a global shutter function for a high-quality CMOS image sensor having a wide dynamic range include a VMGS (voltage mode global shutter) pixel and a CMGS (charge mode global shutter) pixel.

[0013] Among these, the VMGS pixel has the advantages of higher shutter efficiency and lower parasitic light sensitivity (PLS) compared to the CMGS pixel.

[0014] In recent years, the demand for global shutter (GS) CMOS image sensors (CIS) has been increasing, especially in the fields of machine vision and IoT (Internet of Things). In these fields, there is a strong demand for not only GS functionality but also single exposure high dynamic range (SEHDR) performance. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] FIG. 2 [Patent Document 2] Special Publication No. 2006-505975 [Patent Document 3] Special Publication No. 2002-501718 [Patent Document 4] JP 2005-328493 A [Non-patent literature]

[0016] [Non-Patent Document 1] J. Aoki, et al., “A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with -160dB Parasitic Light Sensitivity In-Pixel Storage Node”ISSCC 2013 / SESSION 27 / IMAGE SENSORS / 27.3. Summary of the Invention [Problem to be solved by the invention]

[0017] As mentioned above, CMOS image sensors (CIS) can be constructed employing a variety of unique structures that improve the dynamic range of the pixels.

[0018] One approach to achieving a high dynamic range is a Lateral Overflow Integration Capacitor (LOFIC) configuration (see, for example, Patent Document 4).

[0019] A pixel with a LOFIC configuration has a storage capacitor as a storage capacitance element and a storage transistor as a storage connection element added to the basic configuration described above, and the oversaturated charge that overflows from the photodiode during the same exposure time is stored in the storage capacitor rather than being discarded.

[0020] This LOFIC pixel can have two types of conversion gain: one due to the floating diffusion capacitance Cfd1 (high gain side: proportional to 1 / Cfd1) and one due to the floating diffusion capacitance Cfd1 + the LOFIC capacitance Clofic of the storage capacitor C2 (low gain side: proportional to 1 / (Cfd1+Clofic)). That is, in the LOFIC pixel, a low conversion gain (LCG) signal and a high conversion gain (HCG) signal are used to achieve large saturation and small dark noise, respectively.

[0021] However, LOFIC has a major problem of SNR degradation at the junction of the high conversion gain (HCG) and low conversion gain (LCG) signals. That is, the LOFIC configuration alone cannot remove the kTC noise of the LCG signal, resulting in a decrease in SNR at the junction of the HCG and LCG signals.

[0022] The signal directions of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal are opposite to each other, and in the readout process using the low conversion gain (LCC), the reset noise of the readout reset signal VRST is different from the reset noise of the readout luminance signal VSIG, so it is difficult to remove the reset noise using a subtraction process called differential double sampling (DDS).

[0023] One method to achieve the lowest SNR degradation is a triple conversion gain readout technique with dual conversion gain readout, LOFIC and split pixel.

[0024] However, this kind of pixel structure (split pixel type) has some challenges in optical specifications, such as the optical structure between the large photodiode PD and the small photodiode PD, the different angular response and different quantum efficiency (QE) or responsivity between the large photodiode PD and the small photodiode PD.

[0025] Therefore, with the above-mentioned CMOS image sensor, it is difficult to reduce the degradation of the SNR, and it is difficult to realize a high dynamic range.

[0026] The present invention provides a solid-state imaging device, a driving method for a solid-state imaging device, and electronic equipment that can minimize the decrease in SNR at the joining point of a high conversion gain (HCG) signal and a low conversion gain (LCG) signal without being affected by optical specifications, and thereby fully realize single exposure high dynamic range (SEHDR) performance. [Means for solving the problem]

[0027] A solid-state imaging device according to a first aspect of the present invention has a pixel section in which pixels including at least a photoelectric conversion readout section are arranged, and a readout section that reads out pixel signals from the pixel section, the photoelectric conversion readout section including a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period, a transfer element capable of transferring the charges accumulated in the photoelectric conversion element during a transfer period following the accumulation period, a floating diffusion to which the charges accumulated in the photoelectric conversion element are transferred via the transfer element, a reset element that discharges at least the accumulated charges in the floating diffusion to a reset potential, a storage capacitance element that is controlled to be connected or disconnected from the floating diffusion depending on a conversion gain, and a capacitance of the floating diffusion and a storage capacitance of the storage capacitance element, and a FWC (Full Well Control) of at least the floating diffusion of the floating diffusion and the photoelectric conversion element. and a conversion signal readout unit operable at least in a first conversion gain readout mode capable of reading out a signal corresponding to a first low conversion gain and a first high conversion gain associated with a capacitance of the floating diffusion and a storage capacitance of the storage capacitance element, the conversion signal readout unit amplifying and outputting a voltage signal converted with the conversion gain, wherein the pixel is capable of reading out a readout reset signal in a reset state and a readout signal corresponding to an accumulated charge of the photoelectric conversion element in accordance with the first low conversion gain and the first high conversion gain as a pixel signal in the first conversion gain readout mode, and is capable of reading out a readout reset signal in a reset state and a readout signal corresponding to an accumulated charge or an overflow charge of the photoelectric conversion element in accordance with at least the second low conversion gain as a pixel signal in the second conversion gain readout mode, and a voltage level of the first low conversion gain signal readout with the first low conversion gain and a voltage level of the second low conversion gain signal readout with the second low conversion gain are equivalent.

[0028] A solid-state imaging device according to a first aspect of the present invention includes a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading the accumulated charges at different conversion gains are arranged, and a readout section that reads out pixel signals from the pixels of the pixel section in accordance with the conversion gain, the pixels including a photoelectric conversion region having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by photoelectric conversion, at least two first photoelectric conversion elements and a second photoelectric conversion element that are arranged adjacent to each other, one microlens that directs light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element, at least two first transfer elements and a second transfer element that are capable of individually transferring the charges accumulated in each of the first photoelectric conversion element and the second photoelectric conversion element, and a floating diffusion layer to which the accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element are transferred through each of the first transfer element and the second transfer element. the first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements; a first charge storage capacity capable of storing charge of the floating diffusion via the first connection element, the first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements; a first charge storage capacity capable of storing charge of the first photoelectric conversion element is smaller than a second charge storage capacity capable of storing charge of the second photoelectric conversion element, an overflow path section capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion can be formed in a charge transfer path section from at least the first photoelectric conversion element to the floating diffusion via the first transfer element, and a charge discharge path section capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region can be formed in a charge transfer path section from at least the second photoelectric conversion element to the floating diffusion outer region.

[0029] A second aspect of the present invention is a method for driving a solid-state imaging device having a pixel section in which pixels including at least a photoelectric conversion readout section are arranged, and a readout section for reading out pixel signals from the pixel section, the photoelectric conversion readout section including a photoelectric conversion element for accumulating charge generated by photoelectric conversion during an accumulation period, a transfer element capable of transferring the charge accumulated in the photoelectric conversion element during a transfer period after the accumulation period, a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred via the transfer element, a reset element for discharging at least the accumulated charge in the floating diffusion to a reset potential, a storage capacitance element that is controlled to be connected or disconnected from the floating diffusion depending on a conversion gain, and a conversion signal readout section for amplifying and outputting a voltage signal converted with the conversion gain, the method including: determining a capacitance of the floating diffusion and a storage capacitance of the storage capacitance element, and a FWC (Full Well Clock) of at least the floating diffusion out of the floating diffusion and the photoelectric conversion element, and a second conversion gain readout mode in which a signal corresponding to at least a second low conversion gain associated with the capacitance of the floating diffusion and the storage capacitance of the storage capacitance element can be read out, and the pixel reads out, as a pixel signal, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge of the photoelectric conversion element in accordance with the first low conversion gain and the first high conversion gain in accordance with the first low conversion gain and the first high conversion gain, and reads out, as a pixel signal, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge or overflow charge of the photoelectric conversion element in accordance with at least the second low conversion gain in accordance with the second low conversion gain, and a voltage level of the first low conversion gain signal read out with the first low conversion gain and a voltage level of the second low conversion gain signal read out with the second low conversion gain are equivalent.

[0030] A second aspect of the present invention provides a semiconductor device comprising: a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading out the accumulated charges at different conversion gains are arranged; and a readout section that reads out pixel signals from the pixels of the pixel section in accordance with the conversion gain, the pixels including a photoelectric conversion region having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by the photoelectric conversion, the pixel including at least two first photoelectric conversion elements and a second photoelectric conversion element that are arranged adjacent to each other; one microlens that directs light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element; at least two first transfer elements and a second transfer element that are capable of individually transferring the charges accumulated in each of the first photoelectric conversion element and the second photoelectric conversion element; a floating diffusion through which the accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element are transferred through each of the first transfer element and the second transfer element; a first connection element connected to a floating diffusion and a first storage capacitance element capable of storing charge of the floating diffusion via the first connection element, the first floating diffusion being shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements, the first charge storage capacity capable of storing charge of the first photoelectric conversion element being formed to be smaller than a second charge storage capacity capable of storing charge of the second photoelectric conversion element, an overflow path section is formed in a charge transfer path section extending from at least the first photoelectric conversion element to the floating diffusion via the first transfer element, the overflow path section is formed in a charge transfer path section extending from at least the second photoelectric conversion element to a region outside the floating diffusion, and a charge discharge path section is formed in a charge transfer path section extending from the second photoelectric conversion element to a region outside the floating diffusion, the charge discharge path section is formed in a charge transfer path section extending from the second photoelectric conversion element to a region outside the floating diffusion, the charge discharge path section is formed to be capable of discharging a charge signal from the second photoelectric conversion element to the region outside the floating diffusion.

[0031] According to a third aspect of the present invention, there is provided an electronic device comprising: a solid-state imaging device; and an optical system for forming an image of a subject on the solid-state imaging device. The solid-state imaging device comprises a pixel section in which pixels including at least a photoelectric conversion readout section are arranged; and a readout section for reading out pixel signals from the pixel section. The photoelectric conversion readout section comprises a photoelectric conversion element for storing charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charges stored in the photoelectric conversion element during a transfer period after the accumulation period; a floating diffusion to which the charges stored in the photoelectric conversion element are transferred via the transfer element; a reset element for discharging at least the accumulated charges in the floating diffusion to a reset potential; a storage capacitance element controlled to a connected state or a disconnected state with respect to the floating diffusion depending on a conversion gain; and a conversion signal readout unit operable at least in a first conversion gain readout mode capable of reading out a signal corresponding to a first low conversion gain and a first high conversion gain associated with a capacitance of the floating diffusion and a storage capacitance of the storage capacitance element, the conversion signal readout unit amplifying and outputting a voltage signal converted with the conversion gain, wherein the pixel is capable of reading out a readout reset signal in a reset state and a readout signal corresponding to an accumulated charge of the photoelectric conversion element in accordance with the first low conversion gain and the first high conversion gain as a pixel signal in the first conversion gain readout mode, and is capable of reading out a readout reset signal in a reset state and a readout signal corresponding to an accumulated charge or an overflow charge of the photoelectric conversion element in accordance with at least the second low conversion gain as a pixel signal in the second conversion gain readout mode, and a voltage level of the first low conversion gain signal readout with the first low conversion gain and a voltage level of the second low conversion gain signal readout with the second low conversion gain are equivalent.

[0032] An electronic device according to a third aspect of the present invention comprises a solid-state imaging device and an optical system for forming an image of a subject on the solid-state imaging device, the solid-state imaging device comprising a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading out the accumulated charges at different conversion gains are arranged, and a readout section for reading out pixel signals from the pixels of the pixel section in accordance with the conversion gain, the pixels including photoelectric conversion regions having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by the photoelectric conversion, and at least one of the photoelectric conversion regions arranged adjacent to each other. a microlens for directing light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element; at least two first transfer elements and second transfer elements capable of individually transferring charges accumulated in the first photoelectric conversion element and the second photoelectric conversion element; and a transfer element for transferring the accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element through the first transfer element and the second transfer element. the first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements; a first charge storage capacity capable of storing the first photoelectric conversion element is smaller than a second charge storage capacity capable of storing the second photoelectric conversion element; an overflow path section capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion can be formed in a charge transfer path section extending from at least the first photoelectric conversion element to the floating diffusion via the first transfer element; and a charge discharge path section capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region can be formed in a charge transfer path section extending from at least the second photoelectric conversion element to the floating diffusion outer region. [Brief description of the drawings]

[0033] [Figure 1] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present invention. [Diagram 2] 2 is a circuit diagram showing an example of the configuration of a photoelectric conversion readout section of a pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. [Diagram 3] 2 is a circuit diagram showing an example of the configuration of a signal holding unit of a pixel of the solid-state imaging device according to the first embodiment of the present invention. [Figure 4] 4A to 4C are diagrams for explaining photoelectric conversion characteristics related to triple conversion gain readout processing in the solid-state imaging device according to the first embodiment of the present invention. [Diagram 5] 2 is a simplified cross-sectional view showing an example of the configuration of a main part of a photoelectric conversion readout section according to the first embodiment of the present invention. FIG. [Figure 6] 6A to 6C are diagrams illustrating an example of a read reset signal and a read signal for each conversion gain read process that a signal selection unit of the solid-state imaging device according to the first embodiment of the present invention causes a signal holding unit to hold the read signal in accordance with an illuminance scene. [Figure 7] FIG. 11 is a diagram for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to the first embodiment of the present invention, and is a diagram for explaining the readout operation sequence and potential transition for each conversion gain readout process, as well as the photoelectric conversion characteristics related to the conversion gain readout process. [Figure 8] FIG. 11 is a diagram for explaining an example of a conversion gain readout process according to an illuminance scene in a signal selection unit of a solid-state imaging device according to a first embodiment of the present invention, and is a diagram showing an example of a readout operation sequence and potential transition for each conversion gain readout process that the signal selection unit causes to be held in the signal holding unit according to the illuminance scene. [Figure 9] 2 is a circuit diagram showing an example of the configuration of a signal selection section of the solid-state imaging device according to the first embodiment of the present invention. [Figure 10] 4 is a diagram for explaining the timing of a comparison and determination operation in a comparison section of a signal selection section of the solid-state imaging device according to the first embodiment of the present invention. FIG. [Figure 11] 3 is a diagram for explaining a comparison and determination operation in a comparator of a signal selection unit of the solid-state imaging device according to the first embodiment of the present invention, mainly in relation to node voltage transitions. FIG. [Figure 12] A timing chart for explaining an example of a read sequence in a read process in a first conversion gain read mode (dual conversion gain read mode) and a second conversion gain read mode (low conversion gain read mode) for a pixel of a solid-state imaging device according to the first embodiment of the present invention. [Figure 13] 13 is a diagram showing an operation state of a signal selection unit corresponding to each conversion gain readout process in FIG. 12. [Figure 14] 10 is a diagram for explaining a first example of an evaluation of an SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the first embodiment of the present invention. FIG. [Figure 15] 13 is a diagram for explaining a second example of evaluation of an SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the first embodiment of the present invention. FIG. [Figure 16] 10 is a circuit diagram showing an example of the configuration of a main part of a digital pixel in a solid-state imaging device according to a second embodiment of the present invention. FIG. [Figure 17] 17 is a circuit diagram showing a configuration example of an AD conversion unit in FIG. 16. [Figure 18] FIG. 11 is a circuit diagram illustrating an example of a pixel of a solid-state imaging device according to a third embodiment of the present invention. [Figure 19] FIG. 11 is a diagram showing an example of photoelectric conversion characteristics related to a multiple conversion gain readout process in a solid-state imaging device according to a third embodiment of the present invention. [Figure 20] 13 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor, which is a main part of a shared pixel according to a third embodiment of the present invention, as viewed from the Y direction. FIG. [Figure 21] 13 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor, which is a main part of a shared pixel according to a third embodiment of the present invention, as viewed from the X direction. FIG. [Figure 22] FIG. 11 is a diagram for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to a third embodiment of the present invention, and is a diagram for explaining the readout operation sequence and potential transition for each conversion gain readout process, as well as the photoelectric conversion characteristics related to the conversion gain readout process. [Figure 23] FIG. 11 is a diagram for explaining a first example of an evaluation of an SNR when a readout process is performed using a combination of three conversion gains in a solid-state imaging device according to a third embodiment of the present invention. [Figure 24] FIG. 13 is a circuit diagram illustrating an example of a pixel of a solid-state imaging device according to a fourth embodiment of the present invention. [Diagram 25] FIG. 13 is a diagram for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to a fourth embodiment of the present invention, and is a diagram for explaining photoelectric conversion characteristics related to the conversion gain readout process. [Figure 26] FIG. 13 is a diagram for explaining a second example of evaluation of SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the fourth embodiment of the present invention. [Figure 27] FIG. 13 is a diagram showing an example of a pixel layout of a solid-state imaging device according to a fifth embodiment of the present invention. [Figure 28] FIG. 13 is a simplified diagram showing an example of a pixel layout of a solid-state imaging device according to a sixth embodiment of the present invention. [Figure 29] 13 is a simplified diagram showing an example of a pixel layout of a solid-state imaging device according to a seventh embodiment of the present invention, and photoelectric conversion characteristics related to a multiple conversion gain readout process. FIG. [Diagram 30] 13 is a simplified diagram showing an example of a pixel layout of a solid-state imaging device according to an eighth embodiment of the present invention, and photoelectric conversion characteristics related to multiple conversion gain readout processing. FIG. [Diagram 31] 1 is a diagram showing an example of a configuration of an electronic device to which a solid-state imaging device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0035] (First embodiment) FIG. 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the configuration of a photoelectric conversion and readout section of a pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of a signal holding unit of a pixel of the solid-state imaging device according to the first embodiment of the present invention. In this embodiment, the solid-state imaging device 10 is formed of, for example, a CMOS image sensor.

[0036] As shown in FIG. 1, the solid-state imaging device 10 has as its main components a pixel section 20 as an imaging section, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60. Of these components, for example, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60 constitute a pixel signal readout section 70.

[0037] In this first embodiment, the solid-state imaging device 10 is configured as a CMOS image sensor in which the pixels 200 arranged in a matrix in the pixel section 20 include, for example, a photoelectric conversion readout section 210 and a signal holding section 220, have a rolling shutter (RS) operating function and a global shutter (GS) operating function, and can arbitrarily select the pixel operation mode of the rolling shutter (RS) and the global shutter (GS). Moreover, the conversion gain readout mode in which signals with different conversion gains are read out can be switched, for example, depending on the scene. As a result, the SNR reduction at the junction point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal can be minimized without being affected by the optical specifications, and thus the single exposure high dynamic range (SEHDR) performance can be fully realized.

[0038] As shown in FIG. 2, the photoelectric conversion readout unit 210 has a photodiode PD11 as a photoelectric conversion element that accumulates electric charges generated by photoelectric conversion during an accumulation period, a transfer transistor TG11-Tr as a transfer element that can transfer the electric charges accumulated in the photodiode PD11 during a transfer period after the accumulation period, and a floating diffusion FD11 to which the electric charges accumulated in the photodiode PD11 are transferred via the transfer transistor TG11-Tr. Furthermore, the photoelectric conversion readout section 210 includes a storage capacitor SC11 as a capacitive element having a storage capacitance C11, and a storage transistor SG11-Tr as a storage connection element that selectively connects the floating diffusion FD11 and the storage capacitor SC11.

[0039] Furthermore, the photoelectric conversion readout unit 210 is configured to include a conversion signal readout unit 211 that is operable at least in a first conversion gain readout mode CGRM1 capable of reading out a signal corresponding to a first low conversion gain LCG1 and a first high conversion gain HCG1 associated with the capacitance CFD of the floating diffusion FD11 and the storage capacitance C11 of the storage capacitor SC11, as well as the FWC (Full Well Capacity) of at least the floating diffusion FD11 out of the floating diffusion FD11 and the photodiode PD11, and a second conversion gain readout mode CGRM2 capable of reading out a signal corresponding to at least a second low conversion gain LCG associated with the capacitance CFD of the floating diffusion FD11 and the storage capacitance C11 of the storage capacitor SC11, and that amplifies and outputs a voltage signal converted with the conversion gain.

[0040] The photoelectric conversion readout unit 210 is formed in a layer deeper than at least the channel formation region of the transfer transistor TG11-Tr, and includes an overflow path OVFP that allows the charge overflowing from the photodiode PD11 to overflow toward the formation region of the floating diffusion FD11. The photoelectric conversion readout section 210 can also include a shutter gate transistor AB11-Tr that is connected to the photodiode PD11 and is capable of discharging electric charges from the photodiode PD11 in a direction outside the region in which the floating diffusion FD11 is formed.

[0041] In this first embodiment, in the first conversion gain readout mode CGRM1, the pixel 200 can read out a read reset signal in the reset state and a readout signal corresponding to the accumulated charge of the photodiode PD11 as a pixel signal according to at least two conversion gains, for example, a first high conversion gain (HCG1) and a first low conversion gain (LCG1). It should be noted that the first conversion gain readout mode CGRM1 can also be called a dual conversion gain readout mode. In the second conversion gain readout mode CGRM2, the pixel 200 can read out a readout reset signal in the reset state according to at least one conversion gain, for example the second low conversion gain LCG2, and a readout signal according to the accumulated charge or overflow charge of the photodiode PD11 as a pixel signal.

[0042] In the first embodiment, the voltage level VL1 of the first low conversion gain signal read out using the first low conversion gain LCG1 is equal to the voltage level VL2 of the second low conversion gain signal read out using the second low conversion gain LCG2. In this case, the voltage levels are equal, but the reset levels when taking the difference are different.

[0043] In the first embodiment, the pixel 200 has a signal holding unit 220 capable of holding a read reset signal VRST and a read signal VSIG that are converted with a predetermined conversion gain and read out from the photoelectric conversion readout unit 210. The photoelectric conversion readout section 210 is configured to include a signal selection section 212 that causes the readout reset signal VRST and the readout signal VSIG read out from the conversion signal readout section 211 to be held in a predetermined holding section of the signal holding section 220 for each conversion gain processing.

[0044] Here, the relationship between the first high conversion gain HCG1, the first low conversion gain LCG1, and the second low conversion gain LCG2 in the first embodiment and the photoelectric conversion characteristics related to the multiple (triple) conversion gain readout process will be described. FIG. 4 is a diagram for explaining photoelectric conversion characteristics related to triple conversion gain readout processing in the solid-state imaging device according to the first embodiment of the present invention.

[0045] In the first embodiment, the first high conversion gain HCG1 is associated with the read charge of the photodiode PD11 and is set to be limited by the FWC of the floating diffusion FD11. The reason why the first high conversion gain HCG1 needs to be converted with a small FD capacitance is to increase the gain with a small FD capacitance at the time of low illuminance and reduce the input-referred noise. The first low conversion gain LCG1 is set to be related to the readout charge of the photodiode PD11 and limited by the FWC of the photodiode PD11. The second low conversion gain LCG2 is set in relation to the readout charge of the photodiode PD11, the floating diffusion FD11, and the storage capacitor SC11.

[0046] In this first embodiment, the readout unit 70 can automatically switch between operating in the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 for each pixel depending on the scene (e.g., the magnitude (intensity) of the illuminance). The readout unit 70 switches to be operable for low-illumination scenes in a first high conversion gain (HCG1) readout process, switches to be operable for medium-illumination scenes in a first low conversion gain (LCG1) readout process, and switches to be operable for high-illumination scenes in a second high conversion gain (LCG2) readout process.

[0047] In this first embodiment, by applying a first conversion gain readout mode (e.g., a dual conversion gain readout mode) CGRM1 at low to medium illuminance and a second conversion gain readout mode CGRM2 at high illuminance, it is possible to minimize the degradation of SNR at the coupling point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal without being affected by the optical specifications, and thus it is possible to fully realize the single exposure high dynamic range (SEHDR) performance.

[0048] In this embodiment, as described above, the readout section 70 is capable of switching between the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 when operating in the rolling shutter (RS) mode.

[0049] In the first conversion gain read mode CGRM1, the read section 70 sequentially performs a first low conversion gain reset read process LCG1-RST, a first high conversion gain reset read process HCG1-RST, a first high conversion gain signal read process HCG1-SIG, and a first low conversion gain signal read process LCG1-SIG. In the second conversion gain read mode CGRM2, the read section 70 sequentially performs a second low conversion gain signal read process LCG2-SIG and a second low conversion gain reset read process LCG2-RST.

[0050] Furthermore, the readout section 70 can perform triple conversion gain readout mode processing MTCG1 with the first low conversion gain LCG1 as the medium conversion gain MCG1 through the first conversion gain readout mode MLCG1 and the second conversion gain readout mode MLCG2. In the triple conversion gain read mode MTCG1, the readout section 70 performs a medium conversion gain reset readout process MCG1-RST, a first high conversion gain reset readout process HCG1-RST, a first high conversion gain signal readout process HCG1-SIG, and a medium conversion gain signal readout process MCG1-SIG. The readout section 70 further sequentially performs a second low conversion gain signal readout process LCG2-SIG and a second low conversion gain reset readout process LCG2-RST.

[0051] In this first embodiment, the readout unit 70 does not perform the second low conversion gain signal readout process LCG2-SIG, but instead uses the second low conversion gain signal LCG2-S in combination with the medium conversion gain signal MCG1-SIG acquired in the previous medium conversion gain signal readout process MCG1-SIG.

[0052] The configuration and functions of the characteristic readout process in the solid-state imaging device 10 according to the first embodiment have been outlined above. Next, we will provide a detailed description of the configuration and function of each part of the solid-state imaging device 10, in particular the specific configuration and function of the photoelectric conversion readout section 210 and the signal holding section 220 of the pixel 200 arranged in the pixel section 20, and the readout processing related thereto.

[0053] As described above, the photoelectric conversion readout unit 210 includes a storage capacitor SC11 as a capacitive element having a storage capacitance C11, and a storage transistor SG11-Tr as a storage connection element that selectively connects the floating diffusion FD11 and the storage capacitor SC11.

[0054] (Configuration of pixel 200) As described above, FIGS. 2 and 3 show examples of the circuit configuration of the pixel 200 of the solid-state imaging device 10. FIG. That is, FIG. 2 is a circuit diagram showing an example of the configuration of a photoelectric conversion readout section of a pixel of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of the configuration of a signal holding unit of a pixel of the solid-state imaging device according to the first embodiment of the present invention.

[0055] As described above, the pixel 200 disposed in the pixel section 20 includes a photoelectric conversion readout section 210 and a signal holding section 220. The pixel section 20 of the first embodiment is configured as a stacked CMOS image sensor of a first substrate 110 and a second substrate 120, as described in detail later. In this example, however, as shown in Figures 2 and 3, a photoelectric conversion readout section 210 is formed on the first substrate 110, and a signal holding section 220 is formed on the second substrate 120.

[0056] The photoelectric conversion readout unit 210 of the pixel 200 includes a photodiode (photoelectric conversion element) and an in-pixel amplifier.

[0057] The photodiode PD11 accumulates electric charges generated by photoelectric conversion during an accumulation period. A transfer transistor TG11-Tr serving as a transfer element is connected between the photodiode PD11 and the floating diffusion FD11.

[0058] In the photoelectric conversion readout section 210 of the first embodiment, a shutter gate transistor AB11-Tr capable of discharging charges from the diode PD11 is disposed. That is, the photoelectric conversion readout unit 210 according to the first embodiment has a shutter gate transistor AB11-Tr that is connected to a photodiode PD11 as a photoelectric conversion element and is capable of discharging electric charge from the photodiode PD11 in a direction outside the formation region of the floating diffusion FD11, for example, to a power supply potential VDD (Vdd, VAAPIX).

[0059] The shutter gate transistor AB11-Tr of the photoelectric conversion readout section 210 is controlled by a control signal AB1 applied to the gate through a control line. The shutter gate transistor AB11-Tr is selected and turned on while the control signal AB1 is at high (H) level, and discharges the charges (electrons) converted and accumulated in the photodiode PD11 to the power supply potential VDD.

[0060] The photoelectric conversion readout unit 210 has, for a floating diffusion FD11 as one output node ND1, a reset transistor RST11-Tr as a reset element, a source follower transistor SF11-Tr as a source follower element, a selection transistor SEL11-Tr as a selection element, a storage transistor SG11-Tr as a storage connection element, a storage capacitor SC11 as a storage capacitance element, a readout node ND2, and a signal selection unit 212.

[0061] In the first embodiment, the source follower transistor SF11-Tr, the selection transistor SEL11-Tr, and the read node ND2 (and further the signal selection unit 212) constitute a conversion signal read unit 211 as an output buffer unit. The photoelectric conversion readout section 210 includes a signal selection section (SSL) 212 that causes the readout reset signal VRST and the readout signal VSIG read out from the conversion signal readout section 211 to be held in a predetermined holding section of the signal holding section 220 for each conversion gain processing. The conversion signal readout unit 211 is connected to an internal signal line LSGN1 and a vertical signal line LSGN2.

[0062] Further, a gain switching section 213 is configured including a storage transistor SG11-Tr and a storage capacitor SC11 serving as a storage capacitance element.

[0063] In the photoelectric conversion readout section 210 according to the first embodiment, a readout node ND2 of the conversion signal readout section 211 is connected to an input section of the signal selection section 212, and is also connected to a vertical signal line LSGN2 via a selection transistor SEL11-Tr. In the photoelectric conversion readout section 210 according to the first embodiment, the output section of the signal selection section 212 is connected to the input section of the signal holding section 220 via an internal signal line LSGN1. In the global shutter (GS) mode, the conversion signal readout unit 211 converts the charge of the floating diffusion FD11 serving as an output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal VSL to the signal selection unit 212. The signal selection unit 212 outputs the read reset signal VRST and the read signal VSIG read from the conversion signal read unit 211 to the signal holding unit 220, and causes them to be held in a predetermined holding unit of the signal holding unit 220 for each conversion gain process.

[0064] On the other hand, in the rolling shutter (RS) mode, the conversion signal readout unit 211 converts the charge of the floating diffusion FD11 as an output node into a voltage signal corresponding to the amount of charge, and outputs the converted voltage signal VSL to the vertical signal line LSGN2 via the selection transistor SEL11-Tr.

[0065] The photodiode PD11 generates and accumulates a signal charge (here, electrons) in an amount corresponding to the amount of incident light. In the following, a case will be described in which the signal charges are electrons and each transistor is an n-type transistor, but the signal charges may be holes and each transistor may be a p-type transistor. This embodiment is also effective in the case where each transistor is shared between a plurality of photodiodes and transfer transistors.

[0066] In each pixel 200, a buried photodiode (PPD) is used as the photodiode (PD). The surface of the substrate on which the photodiode (PD) is formed has interface states due to defects such as dangling bonds, so a large amount of charge (dark current) is generated by thermal energy, making it impossible to read out the correct signal. In a buried photodiode (PPD), the charge storage section of the photodiode (PD) is embedded in a substrate, making it possible to reduce the inclusion of dark current in a signal.

[0067] The transfer transistor TG11-Tr of the photoelectric conversion readout unit 210 is connected between the photodiode PD11 and the floating diffusion FD11, and is controlled by a control signal TG1 applied to the gate via a control line. The transfer transistor TG11-Tr is selected and turned on during a transfer period PT when the control signal TG1 is at a high (H) level, and transfers the charges (electrons) photoelectrically converted and accumulated in the photodiode PD11 to the floating diffusion FD11.

[0068] After the photodiode PD11 and floating diffusion FD11 are reset to a predetermined reset potential, the transfer transistor TG11-Tr becomes non-conductive with the control signal TG1 at the low (L) level, and the photodiode PD11 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charge that exceeds the saturation charge amount overflows into the floating diffusion FD11 as overflow charge through the overflow path OVFP below the transfer transistor TG11-Tr. Furthermore, in the case of extremely high illuminance, for example, charges exceeding the saturation charge amount of the floating diffusion FD11 overflow into the storage capacitor SC11 as overflow charges through the overflow path below the storage transistor SG11-Tr.

[0069] The reset transistor RST11-Tr is connected between the power supply line Vdd of the power supply voltage VDD and the floating diffusion FD11, and is controlled by a control signal RST1 applied to the gate via a control line. The reset transistor RST11-Tr is selected and turned on during the reset period when the control signal RST1 is at H level, and resets the floating diffusion FD11 and the storage capacitor SC11 to the potential of the power line Vdd of the power supply voltage VDD.

[0070] The storage transistor SG11-Tr is connected between the floating diffusion FD11 and the reset transistor RST11-Tr, and the storage capacitor SC11 is connected between a connection node ND3 thereof and the reference potential VSS. The storage transistor SG11-Tr is controlled by a control signal SG1 applied to its gate through a control line. The storage transistor SG11-Tr is selected and turned on during the reset period when the control signal SG1 is at H level, and connects the floating diffusion FD11 and the storage capacitor SC11.

[0071] The source follower transistor SF11-Tr serving as a source follower element has a source connected to the read node ND2, a drain connected to the power supply line Vdd, and a gate connected to the floating diffusion FD11. An internal signal line LSGN1 between the read node ND2 and the input section of the signal holding section 220 is driven by a current transistor as a current source element.

[0072] The drain and source of a selection transistor SEL11-Tr as a selection element are connected between the read node ND2 and the vertical signal line LSGN2. The gate of the selection transistor SEL11-Tr is connected to a supply line of a control signal SEL1. The vertical signal line LSGN2, which is connected to the read node ND2 via the selection transistor SEL11-Tr, is driven by a current transistor serving as a current source element.

[0073] Next, a simplified cross-sectional structure of the photoelectric conversion readout section according to the first embodiment will be described.

[0074] (Specific Configuration Example of Main Part of Photoelectric Conversion Readout Unit (Readout Pixel) 210) FIG. 5 is a simplified cross-sectional view showing an example of the configuration of a main part of a photoelectric conversion readout unit according to the first embodiment of the present invention. In this case, the readout pixel including a buried photodiode (PPD) is denoted by reference numeral 2000.

[0075] The readout pixel 2000 in Figure 5 has a semiconductor substrate (hereinafter simply referred to as substrate) 2100 having a first substrate surface 2110 side (e.g., the back side) onto which light L is irradiated, and a second substrate surface 2120 side (front side) opposite the first substrate surface 2110 side. The readout pixel 2000 includes a first conductivity type (n type in this embodiment) semiconductor layer (n layer) 2210 formed so as to be embedded in the substrate 2100, and has a photoelectric conversion unit 2200 as a first photodiode PD11 having a photoelectric conversion function for received light and a charge storage function, and a second conductivity type (p type in this embodiment) semiconductor layer 2300 formed on at least a side portion of the n layer (first conductivity type semiconductor layer) 2210 of the photoelectric conversion unit 2200. Furthermore, the n-layer (first conductive type semiconductor layer) 2210 of the photoelectric conversion section 2200 is formed with a concentration gradient such that the impurity concentration of n-ions increases stepwise from the first substrate surface 2110 side toward the second substrate surface 2120 side.

[0076] Furthermore, the readout pixel 2000 has a transfer transistor TG11-Tr capable of transferring charges accumulated in the photoelectric conversion unit 2200, a floating diffusion FD11 to which charges are transferred through the transfer transistor TG11-Tr, a storage transistor SG11-Tr whose source is connected to the floating diffusion FD11, and a storage capacitor CS11 as a storage capacitance element that accumulates charges from the floating diffusion FD11 via the drain side of the storage transistor SG11-Tr. In the readout pixel 2000, the storage capacitor CS11, which is a storage capacitance element, is formed on the second substrate surface 2120 side so as to have a spatial overlap with the photoelectric conversion section 2200 in a direction perpendicular to the substrate surface (the Z direction of the Cartesian coordinate system in the figure).

[0077] Furthermore, in the photoelectric conversion section 2200, a second conductive type semiconductor region (p+ region) 2230 having a higher impurity concentration than the side p layer (second conductive type semiconductor layer) 2300 is formed on the surface of the n layer (first conductive type semiconductor layer) 2220 on the second substrate surface 2120 side. In addition, the storage capacitor CS11, which is a storage capacitance element, shares the n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the p-layer (second conductivity type semiconductor layer) 2300 on the second substrate surface 2120 side as a first electrode EL1.

[0078] That is, in this first embodiment, the storage capacitor CS11, which is a storage capacitance element, is configured to include a first electrode EL1 formed by an n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the second substrate surface 2120 of the substrate 2100, and a second electrode EL2 formed on the second substrate surface 2120 so as to face the first electrode EL1 at a predetermined interval in a direction perpendicular to the substrate surface.

[0079] In the first embodiment, a flat layer 2250 is formed on the surfaces of the n-layer (first conductive type semiconductor layer) 2210 and p-layer (second conductive type semiconductor layer) 2300 of the photoelectric conversion section 2200 on the first substrate surface 2110 side. A color filter section CF is formed on the light incident side of this flat layer 2250, and further, a microlens MCL is formed on the light incident side of the color filter section so as to correspond to the photoelectric conversion section 2200 as the photodiode PD11 and the p-layer (second conductivity type semiconductor layer) 2300.

[0080] In the first embodiment, a transfer transistor TG11-Tr, a floating diffusion FD11, and a storage transistor SG11-Tr are formed in a p-layer (first conductivity type semiconductor layer) 2320 in the right region of the second substrate surface 2120 of the substrate 2100 in the figure.

[0081] The floating diffusion FD11 is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive type semiconductor region) 2330 having a higher impurity concentration than the n layers (first conductive type semiconductor layers) 2210, 2220 of the photoelectric conversion section 2200.

[0082] The capacitive connection node ND11 (ND3 in FIG. 2) between the storage capacitor CS11 of the storage transistor SG11-Tr is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive type semiconductor region) 2340 having a higher impurity concentration than the n layers (first conductive type semiconductor layers) 2210, 2220 of the photoelectric conversion section 2200. The n+ region 2340 serving as the node ND11 is connected to the second electrode EL2 of the storage capacitor CS1 via a wiring layer WR1.

[0083] The transfer transistor TG11-Tr is formed to include a gate electrode 2510 arranged on the second substrate surface 2120 of the substrate 2100 between the p+ region (second conductive type semiconductor region) 2230 and the n+ region (first conductive type semiconductor region) 2330 as the floating diffusion FD11.

[0084] The storage transistor SG11-Tr is formed to include a gate electrode 2520 arranged on the second substrate surface 2120 of the substrate 2100 between an n+ region (first conductive type semiconductor region) 2330 as the floating diffusion FD11 and an n+ region (first conductive type semiconductor region) 2340 as the capacitance connection node ND11.

[0085] In this first embodiment, an embedded overflow path (OVFP) 2600 is formed, which is connected to the upper layer side (p+ layer 2230 side) of the n layer 2220 of the photoelectric conversion unit 2200 and can transfer the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion FD11 and further to the capacitive connection node ND11 with the storage capacitor CS11. The buried overflow path 2600 is formed so as to interconnect the lower layer of the channel formation under the gate electrode 2510 of the transfer transistor TG11-Tr, the lower layer of the n+ region (first conductivity type semiconductor region) 2330 as the floating diffusion FD11, the lower layer of the channel formation region under the gate electrode 2520 of the storage transistor SG11-Tr, and the lower portion of the n+ region (first conductivity type semiconductor region) 2340 as the capacitance connection node ND11. The buried overflow path 2600 is formed of an n− layer having a lower impurity concentration than the n layer 2220 of the photoelectric conversion section 2200 .

[0086] In this way, in the readout pixel 2000 of the first embodiment, an embedded overflow path 2600 is formed, which is connected to the upper layer side (p+ layer 2230 side) of the n layer 2220 of the photoelectric conversion unit 2200 and can transfer the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion FD11 and further to the capacitance connection node ND11 with the storage capacitor CS11. Therefore, during the exposure period, the transfer transistor TG11-Tr is always turned off (non-conductive state), so that the charge can overflow while suppressing the generation of dark current at the silicon interface below the transfer transistor TG11-Tr.

[0087] Furthermore, in the readout pixel 2000 of this first embodiment, the storage capacitor CS11, which is a storage capacitance element, is configured to include, on the second substrate surface 2120 side, a first electrode EL1 formed by an n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the second substrate surface 2120 of the substrate 2100 so as to have a spatial overlapping portion with the photoelectric conversion unit 2200 in a direction perpendicular to the substrate surface (the Z direction of the Cartesian coordinate system in the figure), and a second electrode EL2 formed on the second substrate surface 2120 so as to face the first electrode EL1 at a predetermined interval in a direction perpendicular to the substrate surface. Therefore, even if the capacitance of the storage capacitor CS11 is set large, it is possible to prevent the aperture of the photodiode PD11 from lowering and the sensitivity from decreasing. Moreover, even if the light receiving area of ​​the photodiode PD11 is set large, the area occupied by the storage capacitor CS11 becomes small, and as a result, it is possible to prevent a decrease in the dynamic range. That is, according to the first embodiment, it is possible to achieve both a wide dynamic range and high sensitivity.

[0088] (Specific Configuration Example of Signal Selection Unit 212) Next, a specific example of the configuration of the signal selection unit 212 in the photoelectric conversion readout unit 210 of the pixel 200 will be described.

[0089] The signal selection unit 212 compares the read reset signal VRST and read signal VSIG read out from the conversion signal read out unit 211 with a reference signal Vref, determines the read processing mode (conversion gain processing) and whether it is the read reset signal VRST or the read signal VSIG depending on the comparison result, and holds the read reset signal VRST and read signal VSIG read out from the conversion signal read out unit 211 in a predetermined holding unit of the signal holding unit 220, for example a sample and hold circuit, for each conversion gain processing depending on the determination result.

[0090] FIG. 6 is a diagram showing an example of a read reset signal and a read signal for each conversion gain read process that the signal selection unit of the solid-state imaging device according to the first embodiment of the present invention causes the signal holding unit to hold the signal in accordance with an illuminance scene.

[0091] In this first embodiment, as described above, the readout unit 70 is capable of switching between operating in the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 depending on the scene (e.g., the magnitude (intensity) of the illuminance). The readout unit 70, for example, switches to be operable for a low illum scene (Low illum.) in a first high conversion gain (HCG1) readout process HCG1-RDO, switches to be operable for a medium illum scene (Middle illum.) in a first low conversion gain (LCG1) readout process LCG1-RDO, and switches to be operable for a high illum scene (High illum.) in a second low conversion gain (LCG2) readout process LCG2-RDO.

[0092] Then, under the control of the readout section 70, in the first high conversion gain read process HCG1-RDO, the signal selection section 212 causes the signal holding section 220 to hold the read reset signal HCG1-RST and the readout signal HCG1-SIG by the first high conversion gain HCG1. In the first low conversion gain read process LCG1-RDO, the signal selection unit 212 causes the signal holding unit 220 to hold the read reset signal LCG1-RST and read signal LCG1-SIG by the first low conversion gain LCG1, or the read signal LCG2-SIG by the second low conversion gain LCG2. In the second low conversion gain read process LCG2-RDO, the signal selection unit 212 causes the signal holding unit 220 to hold the read reset signal LCG2-RST and read signal LCG2-SIG by the second low conversion gain LCG2, or the read signal LCG1-SIG by the first low conversion gain LCG1.

[0093] Figures 7(A) to (D) are diagrams for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to the first embodiment of the present invention, and are diagrams for explaining the readout operation sequence and potential transition for each conversion gain readout process, as well as the photoelectric conversion characteristics related to the conversion gain readout process. FIG. 7(A) shows an operation sequence for a high illum. scene, FIG. 7(B) shows an operation sequence for a medium illum. scene, and FIG. 7(C) shows an operation sequence for a low illum. scene. 7D shows the photoelectric conversion characteristics related to the conversion gain readout process. In this example, the dual conversion gain readout mode corresponds to the first low conversion gain LCG1 and the first high conversion gain HCG1, and the LOFIC mode corresponds to the first high conversion gain HCG1 and the second low conversion gain LCG2.

[0094] 8A to 8C are diagrams for explaining an example of a conversion gain readout process according to an illuminance scene in a signal selection unit of a solid-state imaging device according to the first embodiment of the present invention, and are diagrams showing an example of a readout operation sequence and potential transition for each conversion gain readout process that the signal selection unit causes to be held in the signal holding unit according to the illuminance scene. FIG. 8(A) shows an operation sequence for a high illum. scene, FIG. 8(B) shows an operation sequence for a medium illum. scene, and FIG. 8(C) shows an operation sequence for a low illum. scene.

[0095] In this first embodiment, by applying a first conversion gain readout mode (e.g., dual conversion gain readout mode) CGRM1 at low to medium illuminance and a second conversion gain readout mode (e.g., LOFIC mode) CGRM2 at high illuminance, it is possible to minimize the reduction in SNR at the coupling point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal without being affected by the optical specifications, and thus it is possible to fully realize the single exposure high dynamic range (SEHDR) performance, thereby making it possible to substantially achieve a wide dynamic range.

[0096] In the example of Figure 8, under the control of the readout unit 70, when a predetermined period of time has elapsed since the start of the exposure period PEXP, during the first low conversion gain readout period of the first low conversion gain readout process LCG1-RDO, the signal selection unit 212 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD (Vsfo) as the first low conversion gain readout reset signal LCG1-RST.

[0097] Next, during the first high conversion gain read period of the first high conversion gain read process HCG1-RDO, when the voltage signal VFD read out from the conversion signal read out unit 211 is higher than the reference signal Vref, the signal selection unit 212 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD as the first high conversion gain read out reset signal HCG1-RST.

[0098] Next, during a second high conversion gain read period of the first high conversion gain read process HCG1-RDO following the first transfer period, when the voltage signal VFD read out from the conversion signal read out unit 211 is higher than the reference signal Vref, the signal selection unit 212 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal Vref as the first high conversion gain read out signal HCG1-SIG.

[0099] Next, in the second high conversion gain read period of the first low conversion gain read period of the first low conversion gain read period of the second ... first low conversion gain read period of the first low conversion gain read period of the first low conversion gain read period of the second low conversion

[0100] In addition, during the second low conversion gain read period of the second low conversion gain read process LCG2-RDO after the reset period of the floating diffusion FD11 and the storage capacitor SC11 after the first low conversion gain read period of the second low conversion gain read process LCG2-RDO, the signal selection unit 212 causes the signal holding unit 220 to hold a signal corresponding to the voltage signal VFD read out from the conversion signal read out unit 211 as a second low conversion gain read reset signal LCG2-RST.

[0101] An example of the circuit configuration and functions of the signal selection unit 212 according to the first embodiment will be described below.

[0102] FIG. 9 is a circuit diagram showing an example of the configuration of a signal selection unit of the solid-state imaging device according to the first embodiment of the present invention.

[0103] The signal selection unit 212 in FIG. 9 includes a comparison unit COMP212, a read reset signal selection unit RSEL212, and a read signal selection unit SSEL212.

[0104] The comparison unit COMP212 compares the read voltage signal Vsfo (VFD) read out from the conversion signal readout unit 211 with the reference signal Vrefn (n = 1 to 6), sets the signal Vcomp according to the comparison result to a high level (H) or a low level (L), and outputs it to the read reset signal selection unit RSEL212 and the read signal selection unit SSEL212.

[0105] The comparison unit COMP212 includes a first input terminal TI1, a second input terminal TI2, an output terminal TO1, a first switch SW1, a second switch SW2, a third switch SW3, a capacitor C1, a first inverter INV1, and a second inverter INV2.

[0106] A reference voltage Vrefn is supplied to the first input terminal TI1, which is connected in the circuit to a first terminal a of the second switch SW2. A read voltage signal Vsfo is supplied to the second input terminal TI2, which is connected in the circuit to a first terminal a of a third switch SW3. The capacitor C1 has one electrode connected to the second terminal b of the second switch SW2 and the second terminal b of the third switch SW3, and the node voltage of the connection node therebetween is given as Vc1. The other electrode of the capacitor C1 is connected to the first terminal a of the first switch SW1 and the input terminal of the first inverter INV1, and the node voltage of the connection node therebetween is given as Vc2. The output terminal of the first inverter INV1 is connected to the second terminal b of the first switch and to the input terminal of the second inverter INV2, and the node voltage of the connection node therebetween is given as Vop. The output terminal of the second inverter INV2 is connected to the output terminal TO1 as the output terminal of the signal Vcomp.

[0107] 10A to 10G are diagrams for explaining the timing of the comparison and discrimination operation in the comparison section of the signal selection section of the solid-state imaging device according to the first embodiment of the present invention. Figure 10(A) shows the control signal φ1 of the first switch SW1 and the second switch SW2, Figure 10(B) shows the control signal φ2 of the third switch SW3, Figure 10(C) shows the reference voltage Vrefn, Figure 10(D) shows the read voltage signal Vsfo, Figure 10(E) shows the terminal voltage Vc1 on the first electrode side of capacitor C1, Figure 10(F) shows the terminal voltage Vc2 on the second electrode side of capacitor C1, and Figure 10(G) shows the output signal Vcomp of the comparison unit 212COMP.

[0108] Fig. 10 shows, in the form of a timing chart, the concept of comparison and discrimination in pixel-by-pixel signal selection (mode selection), and also shows, as an example, a case in which Vsfo>Vrefn is compared and discriminated.

[0109] FIG. 11 is a diagram for explaining the comparison and discrimination operation in the comparator of the signal selection section of the solid-state imaging device according to the first embodiment of the present invention, mainly in relation to node voltage transitions.

[0110] In the comparison unit 212COMP, the first switch SW1 and the second switch SW2 are held in a conductive (ON) state during the first period Pφ1 (first phase Φ1) when the first control signal φ1 is at a high level, and are held in a non-conductive (OFF) state during the period when the first control signal φ1 is at a low level. The third switch SW3 is held in a conductive (ON) state during a second period Pφ2 in which the second control signal φ2 is at a high level, and is held in a non-conductive (OFF) state during a period in which the second control signal φ2 is at a low level.

[0111] The comparison discrimination period PCMP of the comparison unit 212COMP is formed by a first period Pφ1 of the first control signal φ1, a second period Pφ2 (second phase Φ2) of the second control signal φ2 following the first control signal φ1, and an indefinite period PINF located between the first period Pφ1 and the second period Pφ2.

[0112] The readout section 70 switches the first control signal φ1 to a high level when the first phase Φ1 starts, which turns on the first switch SW1 and the second switch SW2 and keeps the third switch SW3 off. By this time, the setting of the reference voltage Vref must be completed.

[0113] Then, in order to end the first phase Φ1, the readout unit 70 switches the first control signal φ1 to a low level after the first period Pφ1 has elapsed, thereby turning off the first switch SW1 and the second switch SW2, and keeping the third switch SW3 off during the indefinite period PINF. As a result, the terminal voltage Vc1 on the first electrode side of the capacitor C1 becomes equal to the reference voltage Vref, and the terminal voltage Vc2 on the second electrode side of the capacitor C1 becomes equal to the operating point level Vop of the first inverter INV1. During the first phase Φ1, (Vref-Vop) is accumulated (stored) in the capacitor C1.

[0114] Next, the readout unit 70 switches the second control signal φ2 to a high level to start the second phase φ2, which turns on the third switch SW3 and keeps the first switch SW1 and the second switch SW2 off. By this time, the setting of the voltage signal Vsfo must be completed.

[0115] Then, in order to end the second phase Φ2, the readout section 70 switches the second control signal φ2 to a low level when the second period Pφ2 has elapsed. As a result, the terminal voltage Vc1 on the first electrode side of the capacitor C1 becomes the same level as the voltage signal Vsfo. The terminal voltage Vc2 on the second electrode side of the capacitor C1 becomes the level obtained by subtracting the voltage information (Vrefn-Vop) stored in the first phase Φ1 from the read voltage signal Vsfo, that is, Vc2 = {Vsfo - (Vrefn - Vop) =(Vsfo-Vrefn)+Vop It becomes. The second node voltage Vc2 increases by the amount that the first node voltage Vc1 increases.

[0116] Therefore, the comparison result signal Vcomp of the comparison unit 212COMP is output as the following comparison discrimination result. When the comparison discrimination result of Vsfo > Vrefn is obtained, the signal Vcomp is output to the read reset signal selection unit RSEL212 and the read signal selection unit SSEL212 at the "H" level. When the comparison discrimination result of Vsfo < Vrefn is obtained, the signal Vcomp is output to the read reset signal selection unit RSEL212 and the read signal selection unit SSEL212 at the "L" level.

[0117] (Configuration of the read reset signal selection unit RSEL212) As shown in FIG. 9, the read reset signal selection unit RSEL212 includes an AND gate AD1, a NOR gate NR1, NMOS switches NSW1 and NSW2, an output node TO2, and a capacitor C2.

[0118] The NMOS switches NSW1 and NSW2 are connected in series between the supply line of the voltage signal Vsfo and the output node TO2. The gate of the NMOS switch NSW1 is connected to the output terminal of the AND gate AD1, and the gate of the NMOS switch NSW2 is connected to the output terminal of the NOR gate NR1. One input terminal of the AND gate AD1 is connected to the supply line of the first read mode control signal X1, and the other input terminal is connected to the input line of the comparison result signal Vcomp. One input terminal of the NOR gate NR1 is connected to the supply line of the second read mode control signal X2, and the other input terminal is connected to the output node TO2. The capacitor C2 is connected between the output node TO2 and the reference potential VSS.

[0119] (Configuration of the read signal selection unit SEL212) As shown in FIG. 9, the read signal selection unit SSEL212 includes an AND gate AD2, a NOR gate NR2, NMOS switches NSW3 and NSW4, an output node TO3, and a capacitor C3.

[0120] The NMOS switches NSW3 and NSW4 are connected in parallel between the supply line of the voltage signal Vsfo and the output node TO3. The gate of the NMOS switch NSW3 is connected to the output terminal of the AND gate AD2, and the gate of the NMOS switch NSW4 is connected to the output terminal of the NOR gate NR2. One input terminal of the AND gate AD2 is connected to the supply line of the third read mode control signal X3, and the other input terminal is connected to the input line of the comparison result signal Vcomp; One input terminal of the NOR gate NR1 is connected to the supply line of the fourth read mode control signal X4, and the other input terminal is connected to the input line of the comparison result signal Vcomp. A capacitor C3 is connected between the output node TO3 and the reference potential VSS.

[0121] The first read mode control signal X1 is set to an active high level for a predetermined period of time during the read process of the first low conversion gain reset signal LCG1-RST, during the read process of the first high conversion gain reset signal HCG1-RST, and during the read process of the second low conversion gain reset signal LCG2-RST. The second read mode control signal X2 is set to an active high level for a predetermined period during the read process of the second low conversion gain reset signal LCG2-RST. The third read mode control signal X3 is set to an active high level for a predetermined period during the read process of the first high conversion gain signal HCG1-SIG. The fourth read mode control signal X4 is set to an active low level for a predetermined period during the read process of the first high conversion gain signal HCG1-SIG and during the read process of the second low conversion gain signal LCG2-SIG.

[0122] Here, we return to the explanation of the signal holding unit in FIG. The signal holding unit 220 is capable of taking in and holding a pixel signal, which is a voltage signal that is read out by the conversion signal reading unit 211 and further read out to the in-pixel signal line LSGN1 by the signal selection unit 212. In this first embodiment, the signal holding unit 220 is a voltage signal VFD (VRST, VSIG) corresponding to the accumulated charge of the photodiode PD11 transferred to the floating diffusion FD11 of the photoelectric conversion readout unit 210, and is configured to include a sample and hold circuit 230 that captures and holds the voltage signal as the pixel signal read out to the internal signal line LSGN1 by the signal selection unit 212 using a sampling signal.

[0123] That is, the signal holding unit 220 of the pixel 200 is configured with a sample-and-hold circuit 230 as a main component, as shown in FIG. The sample and hold circuit 230 basically includes an input section 231 including an input node ND22, a sample and hold section 232, an output section 233, and hold nodes ND23, ND24, ND25, ND26, and ND27.

[0124] The input section 231 is connected to the output section of the signal selection section 212, which is connected to the read node ND2 of the photoelectric conversion readout section 210, via an internal signal line LSGN1, and inputs the read reset signal (VRST) and readout signal (VSIG) output from the signal selection section 212 to the sample hold section 232.

[0125] The sample hold unit 222 is configured to include a first sampling transistor SH1-Tr as a first switch element, a second sampling transistor SH2-Tr as a second switch element, a third sampling transistor SH3-Tr as a third switch element, a fourth sampling transistor SH4-Tr as a fourth switch element, a fifth sampling transistor SH5-Tr as a fifth switch element, a first signal holding capacitor CH21, a second signal holding capacitor CH22, a third signal holding capacitor CH23, a fourth signal holding capacitor CH24, and a fifth signal holding capacitor CH25.

[0126] The first sampling transistor SH1-Tr is connected between an input node ND22 connected to the internal signal line LSGN1 and a hold node ND23. The first sampling transistor SH1-Tr selectively connects the first signal holding capacitor CH21 of the sample hold unit 232 to the internal signal line LSGN1 connected to the photoelectric conversion readout unit 210 via the holding node ND23 during the global shutter period or the signal holding capacitor clear period. The first sampling transistor SH1-Tr is in a conductive state, for example, while the control signal SH1 is at a high level. The first signal holding capacitor CH21 is connected between the holding node ND23 and the reference potential VSS.

[0127] The second sampling transistor SH2-Tr is connected between an input node ND22 connected to the internal signal line LSGN1 and a hold node ND24. The second sampling transistor SH2-Tr selectively connects the second signal holding capacitor CH22 of the sample and hold unit 232 to the internal signal line LSGN1 connected to the photoelectric conversion readout unit 210 via a holding node ND24 during the global shutter period or the signal holding capacitor clear period. The second sampling transistor SH2-Tr is in a conductive state, for example, while the control signal SH2 is at a high level. The second signal holding capacitor CS21 is connected between the holding node ND24 and the reference potential VSS.

[0128] The third sampling transistor SH3-Tr is connected between an input node ND22 connected to the internal signal line LSGN1 and a hold node ND25. The third sampling transistor SH3-Tr selectively connects the third signal holding capacitor CH23 of the sample hold unit 232 to the internal signal line LSGN1 connected to the photoelectric conversion readout unit 210 via the holding node ND25 during the global shutter period or the signal holding capacitor clear period. The third sampling transistor SH3-Tr is in a conductive state, for example, while the control signal SH3 is at a high level. The third signal holding capacitor CH23 is connected between the holding node ND25 and the reference potential VSS.

[0129] The fourth sampling transistor SH4-Tr is connected between an input node ND22 connected to the internal signal line LSGN1 and a hold node ND26. The fourth sampling transistor SH4-Tr selectively connects the fourth signal holding capacitor CH24 of the sample and hold unit 232 to the internal signal line LSGN1 connected to the photoelectric conversion readout unit 210 via the holding node ND26 during the global shutter period or the signal holding capacitor clear period. The fourth sampling transistor SH4-Tr is in a conductive state, for example, while the control signal SH4 is at a high level. The fourth signal holding capacitor CH24 is connected between the holding node ND26 and the reference potential VSS.

[0130] The fifth sampling transistor SH5-Tr is connected between an input node ND22 connected to the internal signal line LSGN1 and a hold node ND27. The fifth sampling transistor SH5-Tr selectively connects the fifth signal holding capacitor CH25 of the sample hold unit 232 to the internal signal line LSGN1 connected to the photoelectric conversion readout unit 210 via the holding node ND27 during the global shutter period or the signal holding capacitor clear period. The fifth sampling transistor SH5-Tr is in a conductive state, for example, while the control signal SH5 is at a high level. The fifth signal holding capacitor CH25 is connected between the holding node ND27 and the reference potential VSS.

[0131] The first sampling transistor SH1-Tr, the second sampling transistor SH2-Tr, the third sampling transistor SH3-Tr, the fourth sampling transistor SH4-Tr, and the fifth sampling transistor SH5-Tr are formed of MOS transistors, for example, p-channel MOS (PMOS) transistors.

[0132] The output section 233 includes a first output section 233-1, a second output section 233-2, a third output section 233-3, a fourth output section 233-4, and a fifth output section 233-5.

[0133] The first output section 233-1 includes a source follower transistor SF21-Tr as a second source follower element that basically outputs the signal held in the first signal holding capacitor CH21 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN11 via the selection transistor SEL21-Tr.

[0134] The source follower transistor SF21-Tr and the selection transistor SEL21-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN11.

[0135] A hold node ND23 is connected to the gate of the source follower transistor SF21-Tr, and the selection transistor SEL21-Tr is controlled by a control signal SEL21 applied to the gate through a control line. The selection transistor SEL21-Tr is selected and turned on during a selection period when the control signal SEL21 is at level H. As a result, the source follower transistor SF21-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the first signal holding capacitor CH21 to the vertical signal line LSGN11.

[0136] The second output section 233-2 includes a source follower transistor SF22-Tr as a third source follower element that basically outputs the signal held in the second signal holding capacitor CH22 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN12 via the selection transistor SEL22-Tr.

[0137] The source follower transistor SF22-Tr and the selection transistor SEL22-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN12.

[0138] A hold node ND24 is connected to the gate of the source follower transistor SF22-Tr, and the selection transistor SEL22-Tr is controlled by a control signal SEL22 applied to the gate through a control line. The selection transistor SEL22-Tr is selected and turned on during a selection period when the control signal SEL22 is at level H. As a result, the source follower transistor SF22-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the second signal holding capacitor CH22 to the vertical signal line LSGN12.

[0139] The third output section 233-3 includes a source follower transistor SF23-Tr as a fourth source follower element that basically outputs the signal held in the third signal holding capacitor CH23 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN13 via the selection transistor SEL23-Tr.

[0140] The source follower transistor SF23-Tr and the selection transistor SEL23-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN13.

[0141] A hold node ND25 is connected to the gate of the source follower transistor SF23-Tr, and the selection transistor SEL23-Tr is controlled by a control signal SEL23 applied to the gate through a control line. The selection transistor SEL23-Tr is selected and turned on during a selection period when the control signal SEL23 is at level H. As a result, the source follower transistor SF23-Tr outputs a column output read voltage (VRST) corresponding to the voltage held by the third signal holding capacitor CH23 to the vertical signal line LSGN13.

[0142] The fourth output section 233-4 includes a source follower transistor SF24-Tr as a fifth source follower element that basically outputs the signal held in the fourth signal holding capacitor CH24 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN14 via the selection transistor SEL24-Tr.

[0143] The source follower transistor SF24-Tr and the selection transistor SEL24-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN14.

[0144] A hold node ND26 is connected to the gate of the source follower transistor SF24-Tr, and the selection transistor SEL24-Tr is controlled by a control signal SEL24 applied to the gate through a control line. The selection transistor SEL24-Tr is selected and turned on during a selection period when the control signal SEL24 is at level H. As a result, the source follower transistor SF24-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the fourth signal holding capacitor CH24 to the vertical signal line LSGN14.

[0145] The fifth output section 233-5 includes a source follower transistor SF25-Tr as a sixth source follower element that basically outputs the signal held in the fifth signal holding capacitor CH25 in accordance with the holding voltage during the global shutter period, and selectively outputs the held signal to the vertical signal line LSGN15 via the selection transistor SEL25-Tr.

[0146] The source follower transistor SF25-Tr and the selection transistor SEL25-Tr are connected in series between the reference potential VSS and the vertical signal line LSGN15.

[0147] A hold node ND27 is connected to the gate of the source follower transistor SF25-Tr, and the selection transistor SEL25-Tr is controlled by a control signal SEL25 applied to the gate through a control line. The selection transistor SEL25-Tr is selected and turned on during a selection period when the control signal SEL25 is at level H. As a result, the source follower transistor SF25-Tr outputs a column output read voltage (VSIG) corresponding to the voltage held by the fifth signal holding capacitor CH25 to the vertical signal line LSGN15.

[0148] In this manner, in the solid-state imaging device 10 according to the first embodiment, the pixel signals are sampled simultaneously for all pixels in the signal holding section 220 as pixel signal storage in a voltage mode, and conversion signals corresponding to the readout signals held in the first signal holding capacitor CH21, the second signal holding capacitor CH22, the third signal holding capacitor CH23, the fourth signal holding capacitor CH24, and the fifth signal holding capacitor CH25 are read out to the vertical signal lines LSGN11-15 and supplied to the column readout circuit 40.

[0149] In the pixel section 20, the photodiodes of all pixels are reset simultaneously using the reset transistor RST11-Tr and the transfer transistor TG11-Tr, thereby starting exposure simultaneously and in parallel for all pixels. After a predetermined exposure period ends, the output signal from the photoelectric conversion readout section 210 is sampled by the signal holding section 220 using the transfer transistor TG11-Tr, thereby ending exposure simultaneously and in parallel for all pixels. This electronically achieves a complete shutter operation.

[0150] The configuration of the signal holding unit 220 described above is just an example, and any configuration is acceptable as long as the circuit has the function of holding the readout luminance signal (VSIG) and readout reset signal (VRST) output by the photoelectric conversion readout unit 210 described above during the global shutter period.

[0151] The vertical scanning circuit 30 drives the photoelectric conversion readout units 210 and signal holding units 220 of the pixels 200 through row scanning control lines in the shutter row and readout row under the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal, which is a row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photodiode PD, in accordance with the address signal.

[0152] The column readout circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured to enable column parallel processing by the plurality of column signal processing circuits. The column readout circuit 40 performs amplification and AD conversion on the pixel signals Pixout (VSL) read from the signal holding units 220 of the pixels 200 to the vertical signal lines LSGN11 to LSGN15 in the global shutter mode.

[0153] Here, the pixel signal Pixout (VSL) refers to a pixel read signal including a read signal VSIG and a read reset signal VRST that are sequentially read out from a pixel (in this example, the photoelectric conversion read unit 210 and further the signal holding unit 220 of the pixel 200) in global shutter mode.

[0154] In the solid-state imaging device 10 according to the first embodiment, the column readout circuit 40 is formed so as to be able to be shared in one circuit configuration regardless of the operating mode or the signal form of the readout signal (such as a single-ended or differential signal).

[0155] The column read circuit 40 includes, for example, an amplifier (AMP) and an ADC (analog-to-digital converter).

[0156] The horizontal scanning circuit 50 scans and horizontally transfers signals processed by a plurality of column signal processing circuits such as ADCs of the column readout circuit 40, and outputs them to a signal processing circuit (not shown).

[0157] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0158] In the first embodiment, the readout section 70 performs readout control according to the mode operation in the rolling shutter mode and in the global shutter mode. The readout section 70 is capable of switching between operating in the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 depending on the scene.

[0159] In a first conversion gain readout mode CGRM1 when operating in a rolling shutter (RS) mode, the readout unit 70 switches to be operable for at least one of low and medium illuminance scenes, and in a second conversion gain readout mode CGRM2 when operating in the rolling shutter (RS) mode, the readout unit 70 switches to be operable for high illuminance scenes.

[0160] In the first conversion gain read mode CGRM1, the read section 70 sequentially performs a read process of the first low conversion gain reset signal LCG1-RST, a read process of the first high conversion gain reset signal HCG1-RST, a read process of the first high conversion gain signal HCG1-SIG, and a read process of the first low conversion gain signal LCG1-SIG. In the second conversion gain read mode CGRM2, the read section 70 sequentially performs a read process of the second low conversion gain signal LCG2-SIG and a read process of the second low conversion gain reset signal LCG2-RST.

[0161] Furthermore, the readout section 70 can perform triple conversion gain readout mode processing MTCG1 with the first low conversion gain LCG1 as the medium conversion gain MCG1 through the first conversion gain readout mode MLCG1 and the second conversion gain readout mode MLCG2. In the triple conversion gain read mode MTCG1, the read section 70 performs read processing of the medium conversion gain reset signal MCG1-RST, read processing of the first high conversion gain reset signal HCG1-RST, read processing of the first high conversion gain signal HCG1-SIG, and read processing of the medium conversion gain signal MCG1-SIG. The readout section 70 further sequentially performs a readout process of the second low conversion gain signal LCG2-SIG and a readout process of the second low conversion gain reset signal LCG2-RST.

[0162] In this first embodiment, the readout section 70 can also use the second low conversion gain signal LCG2-SIG in combination with the medium conversion gain signal MCG1-S obtained in the readout process of the previous medium conversion gain signal MCG1-SIG without performing the second low conversion gain signal readout process LCG2-SIG.

[0163] (Readout Operation of Solid-State Imaging Device 10) Specific examples of the characteristic configurations and functions of each portion of the solid-state imaging device 10 have been described above. Next, an overview of the process of reading out pixel signals from the pixels of the solid-state imaging device 10 according to the first embodiment will be described in relation to a timing chart, an operation sequence, and a potential transition.

[0164] (Readout process in first conversion gain readout mode (dual conversion gain readout mode) and second conversion gain readout mode (low conversion gain readout mode)) Figures 12(A) to (I) are timing charts for explaining an example of a read sequence in a read process in a first conversion gain read mode (dual conversion gain read mode) and a second conversion gain read mode (low conversion gain read mode) for a pixel of a solid-state imaging device according to the first embodiment of the present invention.

[0165] 12(A) shows the control signal TG1 of the transfer transistor TG11-Tr, FIG. 12(B) shows the control signal SG1 of the storage transistor SG11-Tr, FIG. 12(C) shows the control signal RST1 of the reset transistor RST11-Tr, FIG. 12(D) shows the first read mode control signal X1 supplied to the signal selection unit, FIG. 12(E) shows the second read mode control signal X2 supplied to the signal selection unit, FIG. 12(F) shows the third read mode control signal X3 supplied to the signal selection unit, FIG. 12(G) shows the fourth read mode control signal X4 supplied to the signal selection unit, FIG. 12(H) shows the first phase signal φ1 supplied to the signal selection unit, and FIG. 12(I) shows the second phase signal φ1 supplied to the signal selection unit.

[0166] 12. Also, FIGS. 13(A) to 13(E) are diagrams showing the operation states of the signal selection section corresponding to each conversion gain readout process in FIG. Figure 13(A) shows the operating state of the signal selection unit during the read process of the first low conversion gain reset signal LCG1-RST, Figure 13(B) shows the operating state of the signal selection unit during the read process of the first high conversion gain reset signal HCG1-RST, Figure 13(C) shows the operating state of the signal selection unit during the read process of the first high conversion gain signal HCG1-SIG, Figure 13(D) shows the operating state of the signal selection unit during the read process of the first low conversion gain signal LCG1-SIG or the second low conversion gain signal LCG2-RST, and Figure 13(E) shows the operating state of the signal selection unit during the read process of the second low conversion gain reset signal LCG2-RST. In the following description, the signal symbols HCG1-RST, SIG, LCG1-RST, SIG, and LCG2-RST, SIG will be used as symbols for signal readout processing for ease of understanding.

[0167] (Readout process in first conversion gain readout mode (dual conversion gain readout mode)) In this case, the readout section 70 holds the transfer transistor TG11-Tr, the reset transistor RST11-Tr, and the storage transistor SG11-Tr in a conductive state for a predetermined period to reset the floating diffusion FD11, the storage capacitor SC11, and the photodiode PD11. Then, the readout section 70 turns off the transfer transistor TG11-Tr, the reset transistor RST11-Tr, and the storage transistor SG11-Tr to start the exposure period PEXP.

[0168] Next, the transfer transistor TG11-Tr and the reset transistor RST11-Tr are held in a non-conductive state, and the storage transistor SG11-Tr is switched to a conductive state, and the gain of the floating diffusion FD11 is set to a first low conversion gain LCG1 determined by the FD capacitance CFD and the capacitance C11 of the storage capacitor SC11. This causes the readout section 70 to perform the first low conversion gain reset readout process LCG1-RST.

[0169] In the first low conversion gain reset read process LCG1-RST, the first read mode control signal X1 is supplied to the signal selection unit 212 at a high level, the second read mode control signal X2 is supplied to the signal selection unit 212 at a low level, the third read mode control signal X3 is supplied to the signal selection unit 212 at a low level, and the fourth read mode control signal X4 is supplied to the signal selection unit 212 at a high level. In response to this, the signal selection section 212 selects the read reset signal VRST, and this read reset signal VRST is transferred to the signal holding section 220 and held in, for example, the holding capacitor CH21.

[0170] Next, the storage transistor SG11-Tr is switched to a non-conductive state, and the gain of the floating diffusion FD11 is set to a first high conversion gain HCG1 determined by the FD capacitance CFD. As a result, the readout section 70 performs the first high conversion gain reset readout process HCG1-RST.

[0171] In the first high conversion gain reset read process HCG1-RST, the first read mode control signal X1 is supplied to the signal selection unit 212 at a high level, the second read mode control signal X2 is supplied to the signal selection unit 212 at a low level, the third read mode control signal X3 is supplied to the signal selection unit 212 at a low level, and the fourth read mode control signal X4 is supplied to the signal selection unit 212 at a high level. In response to this, the signal selection section 212 selects the read reset signal VRST, and this read reset signal VRST is transferred to the signal holding section 220 and held in, for example, the holding capacitor CH22.

[0172] Next, the readout section 70 switches the transfer transistor TG11-Tr to a conductive state for a predetermined first transfer period to transfer the accumulated charge in the photodiode PD11 to the floating diffusion FD11. Then, the readout section 70 switches the transfer transistor TG11-Tr to a non-conductive state, and performs a first high conversion gain signal readout process HCG1-SIG in a first readout period following the first transfer period.

[0173] In the first high conversion gain signal read process HCG1-SIG, the first read mode control signal X1 is supplied to the signal selection unit 212 at a low level, the second read mode control signal X2 is supplied to the signal selection unit 212 at a low level, the third read mode control signal X3 is supplied to the signal selection unit 212 at a high level, and the fourth read mode control signal X4 is supplied to the signal selection unit 212 at a high level. In response to this, the signal selection unit 212 selects the read reset signal VRST, and this read reset signal VRST is transferred to the signal holding unit 220 and held in, for example, the holding capacitor CH23.

[0174] Next, the storage transistor SG11-Tr is switched to a conductive state, and the gain of the floating diffusion FD11 is set to a first low conversion gain LCG1 determined by the FD capacitance CFD and the capacitance C11 of the storage capacitor SC11. Alternatively, the storage transistor SG11-Tr is switched to a conductive state, and the gain of the floating diffusion FD11 is set to a second low conversion gain LCG2 determined by the FD capacitance CFD and the capacitance C11 of the storage capacitor SC11. The first low conversion gain LCG1 and the second low conversion gain LCG2 determined here have the same conversion gain, but only the number of read charges differs depending on the read mode. In response to this, the readout section 70 performs the first low conversion gain signal readout process LCG1-SIG or the second low conversion gain signal readout process LCG2-SIG.

[0175] In the first low conversion gain signal read process LCG1-SIG or the second low conversion gain signal read process LCG2-SIG, the first read mode control signal X1 is supplied at a low level, the second read mode control signal X2 is supplied at a low level, the third read mode control signal X3 is supplied at a low level, and the fourth read mode control signal X4 is supplied at a low level to the signal selection unit 212. In response to this, the signal selection unit 212 selects the read signal VSIG, which is then transferred to the signal holding unit 220 and held, for example, in the holding capacitor CH24.

[0176] Next, the readout section 70 switches the reset transistor RST11-Tr to a conductive state to reset the floating diffusion FD11. Next, the reset transistor RST11-Tr is switched to a non-conductive state, and a second low conversion gain reset signal read process LCG2-RST is performed in the subsequent read period.

[0177] In the second low conversion gain reset signal read process LCG2-RST, the first read mode control signal X1 is supplied to the signal selection unit 212 at a low level, the second read mode control signal X2 is supplied to the signal selection unit 212 at a high level, the third read mode control signal X3 is supplied to the signal selection unit 212 at a low level, and the fourth read mode control signal X4 is supplied to the signal selection unit 212 at a high level. In response to this, the signal selection unit 212 selects the read signal VSIG, which is then transferred to the signal holding unit 220 and held in, for example, the holding capacitor CH25.

[0178] As described above, according to the first embodiment, the solid-state imaging device 10 has pixels 200 arranged in a matrix in the pixel section 20, each of which includes, for example, a photoelectric conversion readout section 210 and a signal holding section 220, and has a rolling shutter (RS) operating function and a global shutter (GS) operating function, and is capable of arbitrarily selecting the pixel operation mode of the rolling shutter (RS) or the global shutter (GS), and is also capable of automatically switching within the chip the conversion gain readout mode for reading out signals with different conversion gains depending on the scene. The photoelectric conversion readout unit 210 has a photodiode PD11 as a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period, a transfer transistor TG11 as a transfer element that can transfer the charges accumulated in the photodiode PD11 during a transfer period after the accumulation period, and a floating diffusion FD11 to which the charges accumulated in the photodiode PD11 are transferred via the transfer transistor TG11. Furthermore, the photoelectric conversion readout section 210 includes a storage capacitor SC11 as a capacitive element having a storage capacitance C11, and a storage transistor SG11-Tr as a storage connection element that selectively connects the floating diffusion FD11 and the storage capacitor SC11.

[0179] Furthermore, the photoelectric conversion readout unit 210 is configured to include a conversion signal readout unit 211 that is operable at least in a first conversion gain readout mode CGRM1 capable of reading out a signal corresponding to a first low conversion gain LCG1 and a first high conversion gain HCG1 associated with the capacitance CFD of the floating diffusion FD11 and the storage capacitance C11 of the storage capacitor SC11, as well as the FWC (Full Well Capacity) of at least the floating diffusion FD11 out of the floating diffusion FD11 and the photodiode PD11, and a second conversion gain readout mode CGRM2 capable of reading out a signal corresponding to at least a second low conversion gain LCG associated with the capacitance CFD of the floating diffusion FD11 and the storage capacitance C11 of the storage capacitor SC11, and that amplifies and outputs a voltage signal converted with the conversion gain. The photoelectric conversion readout unit 210 is formed in a layer deeper than at least the channel formation region of the transfer transistor TG11-Tr, and includes an overflow path OVFP that allows the charge overflowing from the photodiode PD11 to overflow toward the formation region of the floating diffusion FD11. The photoelectric conversion readout section 210 includes a shutter gate AB11-Tr that is connected to the photodiode PD11 and is capable of discharging electric charges from the photodiode PD11 in a direction outside the region in which the floating diffusion FD11 is formed.

[0180] In this first embodiment, the readout unit 70 can automatically switch within the chip whether to operate in the first conversion gain readout mode CGRM1 or the second conversion gain readout mode CGRM2 depending on the scene (e.g., the magnitude (intensity) of the illuminance).

[0181] Therefore, according to the first embodiment, it is possible to prevent a decrease in SNR at a coupling point between signals having different conversion gains. Furthermore, according to the first embodiment, it is possible to expand the dynamic range with a small pixel size by using a predetermined readout mode. According to the first embodiment, it is possible to achieve a high dynamic range.

[0182] Furthermore, according to this first embodiment, it is possible to arbitrarily select a pixel operation mode between rolling shutter and global shutter, and it is also possible to automatically switch within the chip the conversion gain readout mode, which reads out signals with different conversion gains, depending on the scene. As a result, according to the first embodiment, it is possible to minimize the decrease in SNR at the joining point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, thereby making it possible to achieve large saturation and small dark noise.

[0183] Here, an evaluation of the SNR when a readout process is performed by combining a plurality of conversion gains according to the first embodiment will be described. 14A and 14B are diagrams for explaining a first example of an evaluation of an SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the first embodiment of the present invention. 15A and 15B are diagrams for explaining a second example of an evaluation of an SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the first embodiment of the present invention. Figures 14 and 15 (A) show the SNR characteristics when a readout process is performed by combining three conversion gains: the first high conversion gain HCG1 and the second low conversion gain LCG2, and Figures 14 and 15 (B) show the evaluation conditions. In Figures 14 and 15 (A), the curve indicated by A shows the SNR characteristics when the first high conversion gain HCG1 is used, the curve indicated by B shows the SNR characteristics when the first low conversion gain LCG1 is used, the curve indicated by C shows the SNR characteristics when the second low conversion gain LCG2 is used, and the curve indicated by D shows the SNR characteristics when the ideal conversion gain is used.

[0184] The examples of Figures 14 and 15 relate to evaluation of the SNR when a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first low conversion gain LCG1, and a second low conversion gain LCG2. Now consider the noise of the first high conversion gain HCG1, the first low conversion gain LCG1, and the second low conversion gain LCG2. The following formula 1 represents the noise of the first high conversion gain HCG1, formula 2 represents the noise of the first low conversion gain LCG1, and formula 3 represents the noise of the second low conversion gain LCG2. The noise of the first high conversion gain HCG1 and the noise of the first low conversion gain LCG1 mainly consist of “shot noise” and “readout circuit noise,” while the noise of the second low conversion gain LCG2 mainly consists of “shot noise,” “readout circuit noise,” and “kTC noise” at the time of pixel reset.

[0185]

number

[0186]

number

[0187]

number

[0188] In the above formulas 1, 2, and 3, Vread represents read circuit noise, AG represents analog gain*SF gain, CFD represents FD capacitance, CMCG represents MCG capacitance, CLCG represents LCG capacitance, and q represents elementary charge.

[0189] As can be seen from Equation 2, a small CLCG is desirable to reduce the LCG1 noise of LOFIC, and a large CLCG is desirable to increase the FWC, but there is a trade-off between the two.

[0190] The example in Figure 14 is a case where a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first low conversion gain LCG1, and a second low conversion gain LCG2, and relates to an evaluation of the SNR at 20 fF. When using only the combination of the first high conversion gain HCG1 and the second low conversion gain LCG2 (LOFIC), the SNR drop at the signal combining point is about 17 dB @ Qsig=800e-. When using only the combination of the first low conversion gain LCG1 and the second low conversion gain LCG2, the SNR drop at the signal combining point is about 20 dB. When using only the combination of the first high conversion gain HCG1 and the first low conversion gain LCG1, the SNR drop at the signal combining point is about 4 dB. Also, the connection point between the first high conversion gain HCG1 and the first low conversion gain LCG1 is (~800e- @FDsat), and the connection point between the first low conversion gain LCG1 and the second low conversion gain LCG2 is (~30000e- @PDsat). Note that all PD charges can be read in the first low conversion gain LCG1 mode.

[0191] The example in Figure 15 is a case where a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first low conversion gain LCG1, and a second low conversion gain LCG2, and relates to an evaluation of the SNR for 10 fF. When using only the combination of the first high conversion gain HCG1 and the second low conversion gain LCG2 (LOFIC), the SNR drop at the signal combining point is about 11 dB @ Qsig=800e-. When using only the combination of the first low conversion gain LCG1 and the second low conversion gain LCG2, the SNR drop at the signal combining point is about 1 dB. When using only the combination of the first high conversion gain HCG1 and the first low conversion gain LCG1, the SNR drop at the signal coupling point is about 3 dB. Also, the connection point between the first high conversion gain HCG1 and the first low conversion gain LCG1 is (~800e- @FDsat), and the connection point between the first low conversion gain LCG1 and the second low conversion gain LCG2 is (~30000e- @PD sat). Note that all PD charges can be read in the first low conversion gain LCG1 mode.

[0192] As described above, according to the first embodiment, the following effects can be obtained. It is possible to improve the SNR at the signal combining point in LOFIC operation, thereby enabling a high dynamic range (HDR) to be achieved with minimal SNR degradation. In addition, the single PD structure maintains optical symmetry, which is difficult to achieve in a solid-state imaging device with an asymmetric split PD structure.

[0193] Second embodiment FIG. 16 is a circuit diagram showing an example of the configuration of a main part of a digital pixel in a solid-state imaging device according to the second embodiment of the present invention. FIG. 17 is a circuit diagram showing a configuration example of the AD conversion unit in FIG.

[0194] The pixel 200A of the solid-state imaging device 10A according to the second embodiment differs from the pixel 200 of the solid-state imaging device 10 according to the first embodiment in the following respects.

[0195] In the second embodiment, a solid-state imaging device 10A has a photoelectric conversion readout section 210 and a signal holding section 220A as digital pixels in a pixel section 20A. The signal holding unit 220A includes an AD (analog-digital) conversion unit and a memory unit, and is configured as, for example, a stacked CMOS image sensor having a global shutter operation function. In the solid-state imaging device 10A according to the second embodiment, each digital pixel DP has an AD conversion function, and the AD conversion section 240 has a comparator 241 that performs a comparison process to compare a voltage signal read out by the photoelectric conversion readout section with a reference voltage and output a digitized comparison result signal. The comparator 241, for example, under the control of the readout unit 70, is capable of performing a first comparison process that outputs a first comparison result signal digitized for a voltage signal corresponding to the overflow charge that overflowed from the photoelectric conversion element to the output node (floating diffusion) during the accumulation period, and a second comparison process that outputs a second comparison result signal digitized for a voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period.

[0196] The AD conversion section 40 further includes a counter 242, to which a memory section 250 including memories 251-255 is connected.

[0197] The photoelectric conversion and readout section 210 of the digital pixel 200A has the same configuration as that in Fig. 2. Therefore, a detailed description thereof will be omitted.

[0198] The AD conversion unit 240 of the digital pixel 200A has the function of converting the analog voltage signal VSL output by the photoelectric conversion readout unit 210 into a digital signal by comparing it with a reference voltage VREF, which is a ramp waveform changed with a predetermined slope or a fixed voltage.

[0199] As shown in FIG. 17, the AD conversion section 240 includes a comparator (COMP) 241, an input-side coupling capacitor C241, an output-side load capacitor C242, and a reset switch SW-RST.

[0200] The comparator 241 receives a voltage signal VSL output from the conversion signal readout unit 211 of the photoelectric conversion readout unit 210 to the internal signal line LSGN1 at its inverting input terminal (-) as a first input terminal, and receives a reference voltage VREF at its non-inverting input terminal (+) as a second input terminal, and performs a comparison process in which the comparator 241 compares the voltage signal VST with the reference voltage VREF and outputs a digitized comparison result signal SCMP.

[0201] The comparator 241 has a coupling capacitor C251 connected to its inverting input terminal (-) serving as a first input terminal, and is configured to achieve low noise and a high SNR at low illuminance by AC-coupling the output buffer section 211 of the photoelectric conversion readout section 210 on the first substrate 110 side and the input section of the comparator 241 of the AD conversion section 240 on the second substrate 120 side.

[0202] In addition, in the comparator 241, a reset switch SW-RST is connected between the output terminal and an inverting input terminal (-) serving as a first input terminal, and a load capacitor C242 is connected between the output terminal and a reference potential VSS.

[0203] Basically, in the AD conversion unit 240, the analog signal (potential VSL) read out from the output buffer unit 211 of the photoelectric conversion readout unit 210 to the signal line LSGN1 is compared in a comparator 241 with a reference voltage VREF, for example a ramp signal RAMP which is a slope waveform that changes linearly with a certain gradient. At this time, counters 242 arranged for each column similarly to the comparators 241 are operating, and the ramp signal RAMP having a ramp waveform and the counter value change in one-to-one correspondence to convert the voltage signal VSL into a digital signal. Basically, the AD conversion section 240 converts a change in the reference voltage VREF (for example, the ramp signal RAMP) into a change in time, and converts the change into a digital value by counting the time in a certain period (clock). Then, when the analog signal VSL and the ramp signal RAMP (reference voltage VREF) intersect, the output of the comparator 241 is inverted, and the input clock to the counter 242 is stopped, or the clock that had been stopped is input to the counter 242, and the value (data) of the counter 242 at that time is stored in the memory unit 250, completing the AD conversion. After the above AD conversion period ends, the data (signals) stored in the memory section 250 of each digital pixel 200A are output from the output circuit to a signal processing circuit (not shown), and a two-dimensional image is generated by predetermined signal processing.

[0204] According to the second embodiment, it is possible to obtain the same effects as those of the first embodiment described above.

[0205] (Third embodiment) FIG. 18 is a block diagram showing an example of the configuration of a solid-state imaging device according to the third embodiment of the present invention. FIG. 19 is a circuit diagram showing an example of a pixel of a solid-state imaging device according to the third embodiment of the present invention. In the third embodiment, the solid-state imaging device 10B is configured by, for example, a CMOS image sensor.

[0206] In the present third embodiment, as described in detail later, in the solid-state imaging device 10B, pixels (or pixel section 20) arranged in a matrix in the pixel section 20 have one floating diffusion FD as an output node and a source follower element (source follower transistor) forming an output buffer, which are shared by two or four photoelectric conversion elements (photodiodes PD) and transfer elements (transfer transistors). A floating diffusion FD is arranged in the center of the element formation region of the shared pixel, and multiple photoelectric conversion elements are arranged radially (in this embodiment, in the left-right (X), up-down (Y) directions, and diagonally (XY directions)) around this floating diffusion FD.

[0207] The pixel of the solid-state imaging device 10B according to the third embodiment not only enables the pixel size to be reduced while maintaining the sensitivity and saturation charge number, but also has a characteristic configuration that suppresses an increase in junction capacitance and wiring capacitance, suppresses an increase in the capacitance of the floating diffusion as an output node, prevents a decrease in conversion gain, and ultimately improves noise characteristics. It also ensures maximum optical response, ensures reproducibility as well as low light SNR, and further reduces pixel size, thereby enabling efficient improvement of important performance such as dynamic range, responsiveness, and resolution. More specifically, the solid-state imaging device 10B is configured as a CMOS image sensor that can minimize the degradation of SNR at the junction point of a high conversion gain (HCG) signal and a low conversion gain (LCG) signal without being affected by optical specifications, thereby enabling the single exposure high dynamic range (SEHDR) performance to be fully realized.

[0208] The solid-state imaging device 10B according to the third embodiment minimizes the SNR decrease between connection points and achieves pixels with an SEHDR of 100 dB. Specifically, pixel 200 has a structure with 3Q-DPS and MCG1 (4TLCG1 or 4TMCG) readout processing without an asymmetric split PD.

[0209] In the solid-state imaging device 10B of the third embodiment, the first charge storage capacitance CA0 that can be stored by the first photoelectric conversion element (photodiode) PD0 is smaller than the second charge storage capacitance CA1 that can be stored by the second photodiode PD1, and an overflow path portion that can overflow the charge signal from PD0 to the FD can be formed in the charge transfer path portion from the first photodiode PD0 to the floating diffusion FD via the first transfer element (transfer transistor) TG0-Tr, and a charge discharge path portion that can discharge the charge signal from the second photodiode PD1 to the region outside the floating diffusion FD can be formed in the charge transfer from the second photodiode PD1 to the region outside the floating diffusion FD.

[0210] In the solid-state imaging device 10B according to the third embodiment, the shared FD structure of the pixel 200 includes a first photodiode PD0 and a second photodiode PD1, and a first saturation signal saturated in the first photodiode PD0 is completely transferred (overflowed) to the floating diffusion FD. In the pixel 200, the overflow signal from the second photodiode PD1, which is another shared PD, to the floating diffusion FD is discharged (discharged) to the drain via the other side of the shutter gate SG (AB). Therefore, there is no overflow signal to the floating diffusion FD. Therefore, even though this component has a common FD structure, the overflow signal does not get mixed in as signal crosstalk.

[0211] Two transfer gates are connected to each of the photodiodes PD0 and PD1, and the accumulation time can be individually controlled by discharging the accumulated charge. Also, as mentioned above, the overflow direction can be controlled so that it does not get mixed into the floating diffusion FD.

[0212] As described in detail later, pixel 200 includes a comparator that compares a voltage signal as a pixel signal read out to an internal signal line with a reference voltage, performs analog-to-digital (AD) conversion processing on the read voltage signal, and outputs a digitized comparison result signal, and two systems of memories MEM0 (for 3Q) and MEM1 (for 1Q) that hold the comparison result signal by the comparator for the voltage signal corresponding to the accumulated charges of at least the first photodiode PD0 and the second photodiode PD1 transferred to the floating diffusion FD.

[0213] The first photodiode PD0 of the pixel 200 has a small saturation charge number (maximum number of accumulated charges), and stores only one signal by selecting a readout mode according to overflow charge accumulation, conversion gain switching within the pixel, and the amount of light. In the pixel 200, an overflow path section OVF that can overflow the charge signal from the first photodiode PD0 to the floating diffusion FD via the first transfer element transistor TG0-Tr is formed in the charge transfer path section that leads to the floating diffusion FD.

[0214] The second photodiode PD1 of the pixel 200 has a saturation charge number (maximum number of accumulated charges) larger than that of the first photodiode PD0 conversion element. In the pixel 200, a charge discharge path section capable of discharging a charge signal from the second photodiode PD1 to the region outside the floating diffusion FD is formed in the charge transfer path section extending from the second photodiode PD1 to the region outside the floating diffusion FD.

[0215] In the solid-state imaging device 10 of the third embodiment, the charge accumulation operations of the first photodiode PD0 and the second photodiode PD1 are started simultaneously and in parallel under the control of the readout unit 70, and the readout operation is performed by first reading out the first photodiode PD0, followed by reading out the second photodiode PD1.

[0216] FIG. 19 is a diagram showing an example of photoelectric conversion characteristics related to multiple conversion gain readout processing in the solid-state imaging device according to the third embodiment of the present invention.

[0217] Under the control of the readout unit 70, the pixel 200 can operate in at least one of a first high conversion gain readout mode MHCG1, a first medium conversion gain readout mode MMCG1, a first low conversion gain readout mode MLCG1, a second low conversion gain readout mode MLCG2, and a time domain mode MTSS during readout depending on the conversion gain. In the pixel 200, in the first high conversion gain read mode MHCG1, readout is performed with a first high conversion gain HCG1 associated with the accumulated charge of the first photodiode PD0. In the first low conversion gain read mode MLCG1, readout is performed with a first low conversion gain LCG1 associated with the accumulated charge of the second photodiode PD1. In the second low conversion gain read mode MLCG2, readout is performed with a second low conversion gain LCG2 associated with the accumulated charges in the photodiode PD, the floating diffusion FD, and the first storage capacitance element (storage capacitor) CS. In the time domain mode MTSS, readout is performed with a third low conversion gain LCG3 associated with a charge equal to or greater than the accumulated charge of the photodiode PD, the floating diffusion FD, and the first storage capacitance element (storage capacitor) CS.

[0218] (Example of signal readout format) An example of a signal readout form of the solid-state imaging device 10B according to the third embodiment will be described.

[0219] In the third embodiment, the solid-state imaging device 10B includes, as pixels in the pixel section 20, a photoelectric conversion readout section 210, an AD (analog-to-digital) conversion section 220, and a memory section 230, and is configured as, for example, a stacked CMOS image sensor. The solid-state imaging device 10B may be configured to have a global shutter operation function. In the solid-state imaging device 10B according to the third embodiment, each pixel has an AD (analog-digital) conversion function, and the AD conversion section 220 has a comparator 221 that compares a voltage signal read out by the photoelectric conversion readout section 210 with a reference voltage, performs analog-digital (AD) conversion processing on the read out voltage signal VSL, and outputs a digitized comparison result signal.

[0220] Under the control of the readout unit 70, the comparator 221 performs a first comparison process to output a first comparison result signal digitized for a voltage signal corresponding to the overflow charge that overflowed from the photoelectric conversion element to the output node (floating diffusion) during the accumulation period (exposure period), and a second comparison process to output a second comparison result signal digitized for a voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the output node during the transfer period after the accumulation period.

[0221] In addition, in this third embodiment, even if irregular strong light is incident on the photoelectric conversion element during the second comparison process, a shutter gate (SG) is provided to release unnecessary charges from the photoelectric conversion element to outside the floating diffusion FD region, thereby preventing charges from overflowing from the photoelectric conversion element to the floating diffusion FD and causing the FD level to fluctuate. This makes it possible to prevent the FD level from fluctuating even if irregular strong light is incident on the photoelectric conversion element during the second comparison process, thereby enabling normal AD conversion processing to be realized.

[0222] In the solid-state imaging device 10B according to the third embodiment, in order to realize pixels with a small pixel size and an expanded dynamic range using a predetermined readout mode, the readout section 70 performs the process of reading pixel signals from digital pixels and storing the data after AD conversion processing as follows.

[0223] In the solid-state imaging device 10B, the comparator 221, under the control of the readout section , is capable of performing comparison processing on at least two types of mode readout signals read out in different readout sequences with respect to the accumulated charges of different photoelectric conversion elements. More specifically, the comparator 221 is connected to one photoelectric conversion readout section (pixel) 210 in which two different photodiodes (photoelectric conversion elements) PD share a floating diffusion FD as one output node ND0, and is configured to be capable of performing comparison processing on at least two systems of mode readout signals read out in different readout sequences for the accumulated charges of different photodiodes PD in the same photoelectric conversion readout section. Furthermore, the comparator 221 is selectively connected to a plurality of photoelectric conversion readout units 210, each of which includes one or more (two in this example) photodiodes PD, and one comparator is shared by the plurality of photoelectric conversion readout units, and is configured to be capable of performing comparison processing on at least two systems of mode readout signals read out in different readout sequences for the accumulated charges of different photodiodes PD0, PD1 in different photoelectric conversion readout units 210.

[0224] In this third embodiment, the readout unit 70 is capable of reading out pixel signals in at least two of four readout modes: a first readout mode RMD1 (MHCG1), a second readout mode RMD2 (MMCG1), a third readout mode RMD3 (MLCG2), and a fourth readout mode RMD4 (MTSS).

[0225] In the first read mode RMD1, the read section 70 is capable of reading out a read reset signal LCGVRST converted with a second conversion gain (for example, a low conversion gain: LCG) corresponding to the second charge amount of the output node (floating diffusion FD) ND0 from the output buffer section 211 during the reset read period PRRD after the reset period PR, and performing a second conversion gain reset read process LCGRRD in which the comparator 221 performs a comparison process on this read reset signal LCGVRST. Furthermore, during the first read mode RMD1, the read unit 70 is capable of reading out a read signal LCGVSIG converted with a second conversion gain corresponding to the second charge amount of the output node ND0 from the output buffer unit 211 during the read period PRD following the transfer period PT after the reset read period PRRD, and performing a second conversion gain read process LCGSRD in which the comparator 221 performs a comparison process on this read signal LCGVSIG.

[0226] Alternatively, in the first read mode RMD1, the read section 70 can read out a read reset signal HCGVRST converted with a first conversion gain (e.g., high conversion gain: HCG) corresponding to the first charge amount of the output node (floating diffusion FD) ND0 from the output buffer section 211 during the reset read period PRRD after the reset period PR, and perform a first conversion gain reset read process HCGRRD in which the comparator 221 performs a comparison process on this read reset signal HCGVRST. Furthermore, during the first read mode RMD1, the read unit 70 is capable of reading out a read signal HCGVSIG converted with a first conversion gain corresponding to the first charge amount of the output node ND0 from the output buffer unit 211 during the read period PRD following the transfer period PT after the reset read period PRRD, and performing a first conversion gain read process HCGSRD in which the comparator 221 performs a comparison process on this read signal HCGVSIG.

[0227] In the second read mode RMD2, during the reset read period PRRD after the reset period PR, the read section 70 is capable of reading from the output buffer section 211 a second read reset signal LCGVRST converted with a second conversion gain corresponding to the second amount of charge at the output node ND0, and performing a second conversion gain reset read process LCGRRD in which the comparator 221 performs a comparison process on the second read reset signal LCGVRST. Furthermore, in the second read mode RMD2, the read section 70 can perform a first conversion gain reset read process HCGRRD in which the gain is switched by the gain switching section 212, a first read reset signal HCGVRST converted with a first conversion gain corresponding to the first charge amount at the output node ND0 is read from the output buffer section 211, and a comparison process is performed on this first read reset signal HCGVRST by the comparator 221. Furthermore, during the second read mode RMD2, the read section 70 is capable of reading out a first read signal HCGVSIG converted with a first conversion gain corresponding to the first charge amount of the output node ND0 from the output buffer section 211 during the first read period PRD1 following the first transfer period PT1 after the reset read period PRRD, and performing a first conversion gain read process HCGSRD in which the comparator 221 performs a comparison process on this first read signal HCGVSIG. Furthermore, in the second read mode RMD2, the read unit 70 can switch the gain using the gain switching unit 212 after the first read period PRD1, and during the second read period PRD2 following the second transfer period PT2 after the first read period PRD1, read out from the output buffer unit 211 a second read signal LCGVSIG converted with a second conversion gain corresponding to the second amount of charge at the output node ND0, and perform a second conversion gain read process LCGSRD in which the comparator 221 performs a comparison process on this second read signal LCGVSIG.

[0228] In the third read mode RMD3, the read section 70 is capable of reading out the first read reset signal HCGVRST converted with a first conversion gain corresponding to the first amount of charge at the output node from the output buffer section 211 during the first reset read period PRRD1 after the first reset period PR1, and performing a first conversion gain reset read process HCGRRD in which the comparator 221 performs a comparison process on this first read reset signal HCGVRST. Furthermore, in the third read mode RMD3, the read unit 70 is capable of reading out a first read signal HCGVSIG converted with a first conversion gain corresponding to the first charge amount of the output node ND0 from the output buffer unit 211 during the first read period PRD1 following the first transfer period PT1 after the first reset read period PRRD1, and performing a first conversion gain read process HCGSRD in which the comparator 221 performs a comparison process on this first read signal HCGVSIG. Furthermore, in the third read mode RMD3, the read unit 70 can switch the gain using the gain switching unit 212 after the first read period PRD1, and during the second read period PRD2 following the second transfer period PT2 after the first read period PRD1, read out from the output buffer unit 211 a second read signal LCGVSIG converted with a second conversion gain corresponding to the second amount of charge at the output node ND0, and perform a second conversion gain read process LCGSRD in which the comparator 221 performs a comparison process on this second read signal LCGVSIG. Furthermore, in the third read mode RMD3, the read section 70 is capable of reading out a second read reset signal LCGVRST converted with a second conversion gain corresponding to the second amount of charge at the output node from the output buffer section 211 during the second reset read period PRRD2 following the second reset period PR2 after the second read period PRD2, and performing a second conversion gain reset read process LCGRSD in which the comparator 221 performs a comparison process on this second read reset signal LCGVRST.

[0229] In the fourth read mode RMD4, when irregular strong light is incident on the photoelectric conversion element, the readout unit 70 counts the time with a clock until the potential of the output node (floating diffusion FD) ND0 fluctuates due to overflow charge and the output of the comparator 221 is inverted, thereby predicting the signal amount, and during the first reset readout period PRRD1, it is possible to read out from the output buffer unit 211 a first readout reset signal HCGVRST converted with a first conversion gain corresponding to the first charge amount of the output node ND0, and perform a first conversion gain reset readout process HCGRRD in which the comparator 221 performs a comparison process on this first readout reset signal HCGVRST. Furthermore, in the fourth read mode RMD4, the read section 70 is capable of reading out a first read signal HCGVSIG converted with a first conversion gain corresponding to the first charge amount of the output node ND0 from the output buffer section 211 during the first read period PRD1 following the first transfer period PT1 after the first reset read period PRRD1, and performing a first conversion gain read process HCGSRD in which the comparator 221 performs a comparison process on this first read signal HCGVSIG. Furthermore, in the fourth read mode RMD4, the read unit 70 can switch the gain using the gain switching unit 212 after the first read period PRD1, and during the second read period PRD2 following the second transfer period PT2 after the first read period PRD1, read out from the output buffer unit 211 a second read signal LCGVSIG converted with a second conversion gain corresponding to the second amount of charge at the output node ND0, and perform a second conversion gain read process LCGSRD in which the comparator 221 performs a comparison process on this second read signal LCGVSIG. Furthermore, in the fourth read mode RMD4, the read section 70 is capable of reading out a second read reset signal LCGVRST converted with a second conversion gain corresponding to the second amount of charge at the output node ND0 from the output buffer section 211 during the second reset read period PRRD2 following the second reset period PR2 after the second read period PRD2, and performing a second conversion gain reset read process LCGRSD in which the comparator 221 performs a comparison process on this second read reset signal LCGVRST.

[0230] The configuration and function of each unit of the solid-state imaging device 10, in particular the configuration and function of the pixel section 20 and the pixel 200, and the associated readout process and the like will be described in detail below.

[0231] (Example of configuration of shared pixel 200) FIG. 18 shows an example of a circuit of a shared pixel 200 of a solid-state imaging device 10B according to the third embodiment of the present invention.

[0232] The pixel section 20 has a plurality of pixels 200 arranged in a matrix of N rows and M columns.

[0233] The shared pixel 200 according to the third embodiment includes a photoelectric conversion readout section 210, an AD conversion section 220, and a memory section 230. The pixel section 20 of the third embodiment is configured as a stacked CMOS image sensor of a first substrate 110 and a second substrate 120, but in this example, as shown in FIG. 18, a photoelectric conversion readout section 210 is formed on the first substrate 110, and an AD conversion section 220 and a memory section 230 are formed on the second substrate 120.

[0234] The photoelectric conversion readout unit 210 of the shared pixel 200 includes two photodiodes (photoelectric conversion elements) and one in-pixel amplifier. Specifically, the photoelectric conversion readout section 210 has, for example, a first photodiode PD0 which is a first photoelectric conversion element, and a photodiode PD1 which is a second photoelectric conversion element. In the shared pixel 200 of the third embodiment, the first photodiode PD0 and the second photodiode PD1 share a floating diffusion FD serving as an output node ND0.

[0235] The first photodiode PD0 and the second photodiode PD1 accumulate electric charges generated by photoelectric conversion during an accumulation period. A first transfer transistor TG0-Tr serving as a first transfer element is connected between the charge storage unit PND0 (CA0) of the first photodiode PD0 and the floating diffusion FD, and a first shutter gate transistor SG0-Tr serving as a first charge overflow gate element is connected between the charge storage unit PND0 (CA0) and a predetermined fixed potential VAAPIX. In addition, a second transfer transistor TG1-Tr serving as a second transfer element is connected between the charge storage unit PND1 (CA1) of the second photodiode PD1 and the floating diffusion FD, and a second shutter gate transistor SG1-Tr serving as a second charge overflow gate element is connected between the charge storage unit PND1 (CA1) and a predetermined fixed potential VAAPIX.

[0236] The photoelectric conversion readout unit 210 corresponds to a floating diffusion FD as one output node ND0 and has a reset transistor RST-Tr as a reset element, a source follower transistor SF-Tr as a source follower element, a storage transistor BIN-Tr as a storage element, a storage capacitor CS (CMCG) as a storage capacitance element, a clamp transistor CLP-Tr as a clamp element, a current transistor IC-Tr as a current source element, and a readout node ND1. The photoelectric conversion readout section 210 may further include a selection transistor SEL-Tr as a selection element.

[0237] In the third embodiment, the output buffer section 211 is configured to include the source follower transistor SF-Tr and the read node ND1. Further, the gain switching section 212 is configured to include the storage transistor BIN-Tr and the storage capacitor CS.

[0238] In the photoelectric conversion readout section 210 according to the third embodiment, a readout node ND1 of an output buffer section 211 is connected to an input section of an AD conversion section 220 via a signal selection section 213, for example. The photoelectric conversion readout section 210 converts the charge of the floating diffusion FD serving as an output node into a voltage signal according to the amount of charge, and outputs the converted voltage signal VSL to the AD conversion section 220.

[0239] The photoelectric conversion readout section 210 according to the third embodiment, under the control of the readout section 70, reads out the accumulated charge of the first photodiode PD0 serving as the first photoelectric conversion element in the fourth readout mode RMD4 or the third readout mode RMD3. The photoelectric conversion readout section 210 then reads out the accumulated charge of the second photodiode PD1 serving as the second photoelectric conversion element in the first readout mode RMD1 or the second readout mode RMD2. In this third embodiment, the accumulated charge of the first photodiode PD0 as the first photoelectric conversion element is read out using the fourth readout mode RMD4, and the accumulated charge of the second photodiode PD1 as the second photoelectric conversion element is read out using the second readout mode RMD2.

[0240] For example, during the first comparison processing period PCMP1 of the AD conversion section 220, the photoelectric conversion readout section 210 outputs a voltage signal VSL corresponding to the overflow charge that overflows from the photodiode PD0, which is a photoelectric conversion element, to the floating diffusion FD, which serves as an output node, during the accumulation period PI.

[0241] Furthermore, during the second comparison processing period PCMP2 of the AD conversion section 220, the photoelectric conversion readout section 210 outputs a voltage signal VSL according to the accumulated charge of the photodiode PD1 transferred to the floating diffusion FD as an output node during the transfer period PT after the accumulation period PI. The photoelectric conversion readout section 210 outputs a readout reset signal (signal voltage) (VRST) and a readout signal (signal voltage) (VSIG) as pixel signals to the AD conversion section 220 in the second comparison processing period PCMP2.

[0242] The first photodiode PD0 and the second photodiode PD1 generate and accumulate signal charges (electrons in this case) in an amount corresponding to the amount of incident light. In the following, a case will be described in which the signal charges are electrons and each transistor is an n-type transistor, but the signal charges may be holes and each transistor may be a p-type transistor.

[0243] In each shared pixel 200, as the photodiode (PD), a buried photodiode (PPD) is used, as described above. The surface of the substrate on which the photodiode (PD) is formed has interface states due to defects such as dangling bonds, so a large amount of charge (dark current) is generated by thermal energy, making it impossible to read out the correct signal. In a buried photodiode (PPD), the charge storage section of the photodiode (PD) is embedded in a substrate, making it possible to reduce the inclusion of dark current in a signal.

[0244] The first transfer transistor TG0-Tr of the photoelectric conversion readout unit 210 is connected between the charge storage unit PND0 of the first photodiode PD0 and the floating diffusion FD, and is controlled by a control signal TG0 applied to the gate via a control line. The first transfer transistor TG0-Tr is selected during the transfer period PT when the control signal TG0 is at a high (H) level, and becomes conductive, transferring the charges (electrons) photoelectrically converted and accumulated in the first photodiode PD0 to the floating diffusion FD. After the first photodiode PD0 and the floating diffusion FD are reset to a predetermined reset potential, the first transfer transistor TG0-Tr becomes non-conductive with the control signal TG0 at the low (L) level, and the first photodiode PD0 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charge that exceeds the PD saturation charge amount overflows into the floating diffusion FD as overflow charge through the overflow path below the first transfer transistor TG0-Tr.

[0245] The first shutter gate transistor SG0-Tr as a first charge overflow gate element is connected between the charge storage portion PND0 (CA0) of the first photodiode PD0 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG0 applied through a control line. The first shutter gate transistor SG0-Tr is selected and turned on during the period when the control signal SG0 is at H level, forming a charge discharge (ejection) path as an anti-blooming function between the charge storage section PND0 (CA0) of the first photodiode PD0 and a predetermined fixed potential VAAPIX, and discharging unnecessary charges to the fixed potential VAAPIX.

[0246] In this way, the first transfer transistor TG0-Tr and the first shutter gate transistor SG0-Tr are driven and controlled at individual timings.

[0247] The second transfer transistor TG1-Tr of the photoelectric conversion readout unit 210 is connected between the charge storage unit PND1 (CA1) of the second photodiode PD1 and the floating diffusion FD, and is controlled by a control signal TG1 applied to the gate via a control line. The second transfer transistor TG1-Tr is selected during the transfer period PT when the control signal TG1 is at a high (H) level, and becomes conductive, transferring the charges (electrons) photoelectrically converted and accumulated in the second photodiode PD1 to the floating diffusion FD. After the second photodiode PD1 and the floating diffusion FD are reset to a predetermined reset potential, the second transfer transistor TG1-Tr becomes non-conductive with the control signal TG1 at the low (L) level, and the second photodiode PD1 enters the accumulation period PI. At this time, if the intensity (amount) of the incident light is extremely high, charge that exceeds the saturation charge amount overflows into the fixed potential VAAPIX as overflow charge through the overflow path below the second shutter gate transistor SG1-Tr.

[0248] The second shutter gate transistor SG1-Tr as a second charge overflow gate element is connected between the charge storage portion PND1 of the second photodiode PD1 and a predetermined fixed potential VAAPIX, and is controlled by a control signal SG1 applied through a control line. The second shutter gate transistor SG1-Tr is selected and turned on during the period when the control signal SG1 is at H level, forming a charge discharge (ejection) path (route) as an anti-blooming function between the charge storage section PND1 (CA1) of the second photodiode PD1 and a predetermined fixed potential VAAPIX, and discharging unnecessary charges to the fixed potential VAAPIX.

[0249] In this manner, the second transfer transistor TG1-Tr and the second shutter gate transistor SG1-Tr are driven and controlled at separate timings.

[0250] The reset transistor RST-Tr is connected between a power supply line Vaapix of a power supply voltage VAAPIX and a floating diffusion FD, and is controlled by a control signal RST applied to the gate via a control line. The reset transistor RST-Tr is selected and turned on during a reset period when the control signal RST is at H level, and resets the floating diffusion FD to the potential (Vrst) of the power supply line Vaapix of the power supply voltage VAAPIX.

[0251] The storage transistor BIN-Tr is connected between the floating diffusion FD and the reset transistor RST-Tr, and a storage capacitor CS is connected between a connection node ND2 thereof and a reference potential VSS. The storage transistor BIN-Tr is controlled by a control signal BIN applied to its gate through a control line. The storage transistor BIN-Tr is selected and turned on during the reset period when the control signal BIN is at H level, and connects the floating diffusion FD and the storage capacitor CS.

[0252] In the first high conversion gain (luminance signal, reset) read mode MHCG1, the storage transistor BIN-Tr is held in a non-conductive state, and the charge of the floating diffusion FD, which is the output node ND0, is separated from the charge of the storage capacitor CS to perform the read process. In the first low conversion gain (luminance signal, reset) read mode MLCG1, the storage transistor BIN-Tr is held in a conductive state, and the read process is performed by sharing the charge of the floating diffusion FD, which is the output node ND0, and the charge of the storage capacitor CS. During the second low conversion gain (reset) read mode MLCG2, the reset transistor RST-Tr and the storage transistor BIN-Tr are held in a conductive state, and the charge of the floating diffusion FD, which is the output node ND0, and the charge of the storage capacitor CS are cleared to perform the read process. In the pixel 200, in the first high conversion gain read mode MHCG1, readout is performed with a first high conversion gain HCG1 associated with the accumulated charge of the first photodiode PD0. In the time domain mode MTSS, readout is performed with a third low conversion gain LCG3 associated with a charge equal to or greater than the accumulated charge in the photodiode PD, the floating diffusion FD and the storage capacitor CS.

[0253] A source follower transistor SF-Tr serving as a source follower element has a source connected to a read node ND1, a drain connected to a power supply line Vaapix, and a gate connected to a floating diffusion FD. A read node ND 1 forming the output buffer unit 211 is connected to a signal line LSGN 1 that is connected to the input unit of the AD conversion unit 220 . The drain and source of a current transistor IC-Tr as a current source element are connected between a signal line LSGN1 to which a read node ND1 is connected and a reference potential VSS (for example, GND). The gate of the current transistor IC-Tr is connected to a supply line of a control signal VBNPIX. A signal line LSGN1 between the read node ND1 and the input section of the AD conversion section 220 is driven by a current transistor IC-Tr as a current source element.

[0254] FIG. 20 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor, which is a main part of a shared pixel according to the third embodiment of the present invention, as viewed from the Y direction. FIG. 21 is a simplified cross-sectional view showing an example of the configuration of a charge accumulation and transfer system having a shutter gate transistor, which is a main part of a shared pixel according to the third embodiment of the present invention, as viewed from the X direction.

[0255] Each pixel cell PXLC is formed on a substrate (in this example, the first substrate 110) having a first substrate surface 2110 side (e.g., the back side) onto which light L is irradiated, and a second substrate surface 2120 side (e.g., the front side) opposite to the first substrate surface 2110, and the first photodiode PD0 and the second photodiode PD1 are separated by p-type isolation layers SPL1, SPL2, SPL3. The pixel cell PLXC according to the third embodiment of Figures 20 and 21 is configured to include, for example, a first photodiode PD0, a second photodiode PD1, a first transfer transistor TG0-Tr, a second transfer transistor TG1-Tr, a floating diffusion FD, a first shutter gate transistor SG0-Tr, a second shutter gate transistor -Tr, isolation layers SPL1, SPL2, SPL3, full DTI (FDTI) 2301, 2302 formed in the left and right isolation layers SPL1, SPL3 except for the central portion, and further a color filter section CF and a microlens ML, which form the photoelectric conversion readout section 210.

[0256] Although the pixels in FIG. 20 and FIG. 21 are shown as an example of a back-illuminated type, the present invention may also be of a front-illuminated type.

[0257] (Photodiode structure) The semiconductor substrate 2100 includes a first conductivity type (n type in this embodiment) semiconductor layer (n layer in this embodiment) 2102 formed so that a first photodiode PD0 and a second photodiode PD1 are embedded in and in parallel with a second conductivity type (p type in this embodiment) layer 2101 of the semiconductor substrate 2100 having a first substrate surface 2110 side and a second substrate surface 2120 side opposite the first substrate surface 2110 side, and is formed so as to have a photoelectric conversion function of received light and a charge storage function. Isolation layers SPL1, SPL2, SPL3 made of p-type layers 2101R, 2101C, 2101L are formed on both sides and the center of the first photodiode PD0 and the second photodiode PD1 in a direction (X direction) perpendicular to the normal to the substrate.

[0258] In this manner, in the third embodiment, as described above, a buried photodiode (PPD) is used as the photodiode (PD) in each pixel cell PXLC. The surface of the substrate on which the photodiode (PD) is formed has interface states due to defects such as dangling bonds, so a large amount of charge (dark current) is generated by thermal energy, making it impossible to read out the correct signal. In a buried photodiode (PPD), the charge storage section of the photodiode (PD) is embedded in a substrate, making it possible to reduce the inclusion of dark current in a signal.

[0259] In the first photodiode PD0 and the second photodiode PD1 in FIG. 20, ap+ layer 2103 is formed on the second substrate surface 2120 side of an n layer (first conductivity type semiconductor layer) 2102. A color filter section CF is formed on the light incident side of the p-type layer 2101, and further, a microlens ML is formed on the light incident side of the color filter section so as to correspond to the first photodiode PD0, the second photodiode PD1, and a part of the separation layer SPL.

[0260] (Configuration of separation layer in X direction (column direction)) An n+ layer 2104 that becomes a floating diffusion FD is formed on the second substrate surface 2120 side of the p-type isolation layer 2101C (SPL2) in the center in the X direction (column direction DPS) of FIG. An n+ layer 2105 that will become the drain of the shutter gate transistor SG0-Tr is formed on the second substrate surface 2120 side of the p-type isolation layer 2101L (SPL1) on the left side in the X direction (column direction) of FIG. An n+ layer 2106 that will become the drain of the shutter gate transistor SG1-Tr is formed on the second substrate surface 2120 side of the p-type isolation layer 2101R (SPL3) on the right side in the X direction (column direction) of FIG.

[0261] As shown in FIGS. 20 and 21, full DTIs 2301, 2302 are formed in the left and right separation layers SPL1, SPL3 except for the central separation layer PSL2 so as to penetrate between the second substrate surface 2120 and the first substrate surface 2110 in the Y direction. On the other hand, a floating diffusion FD is formed in the central separation layer SPL2, but a full DTI is not formed in this central separation layer SPL2 because this DTI structure is not effective under the floating diffusion FD for pixel sharing. That is, when it is placed under a pixel component such as an FD for a FD-sharing pixel, the formation area of ​​the full DTI is left partially empty.

[0262] A gate electrode 2108 of the first transfer transistor TG0-Tr and a gate electrode 2109 of the first shutter gate transistor SG0-Tr are formed on the p-type layer 2101L on the second substrate surface 2120 side, with a gate insulating film interposed therebetween. An overflow OVP is formed below the first transfer transistor TG0-Tr, extending from the first photodiode PD0 to the floating diffusion FD. The potential of the overflow path OVP can also be controlled by, for example, gate control.

[0263] On the other hand, on the p-type layer 2101R on the second substrate surface 2120 side, a gate electrode 2110 of the second transfer transistor TG1-Tr and a gate electrode 2111 of the second shutter gate transistor SG1-Tr are formed via a gate insulating film. A charge discharging path DMP extending from the photodiode PD0 to the n+ layer 2107 is formed under the second shutter gate transistor SG1-Tr.

[0264] In such a structure, when the intensity (amount) of incident light is very high, charges exceeding the saturation charge amount overflow into the floating diffusion FD as overflow charges through the overflow path OVP below the first transfer transistor TG0-Tr. In the first comparison process CMPR1 of the comparator 221, the overflow charge is used.

[0265] On the other hand, if irregular, strong light is incident on the first photodiode PD0 during the second comparison process of AD conversion, charge will overflow from the photodiode PD0 to the floating diffusion FD, causing the level of the floating diffusion FD, which is the output node, to fluctuate, which may make it impossible to achieve normal AD conversion processing. Therefore, in this embodiment, even if irregular strong light is incident on the first photodiode PD0 during the second comparison process, a first shutter gate transistor SG0-Tr is provided which discharges unnecessary charges from the first photodiode PD0 to outside the floating diffusion FD region, thereby preventing charges from overflowing from the first photodiode PD0 to the floating diffusion FD and causing the FD level to fluctuate. This prevents the FD level from fluctuating even if irregular strong light is incident on the first photodiode PD0 during the second comparison process, making it possible to realize normal AD conversion processing.

[0266] In the photoelectric conversion readout unit 210 of the pixel 200, in which two sets of a first photodiode PD0, a first transfer gate transistor TG0-Tr, and a first shutter gate transistor SG0-Tr, as well as a second photodiode PD1, a second transfer gate transistor TG1-Tr, and a second shutter gate transistor SG1-Tr share a floating diffusion FD as one output node ND0, the capacitance of the photodiode PD is made different depending on the corresponding readout mode in order to improve the dynamic range. In the third embodiment, the accumulated charge of the first photodiode PD0 is read out by the fourth readout mode RMD4, and the accumulated charge of the second photodiode PD1 is read out, for example, by the second readout mode RMD2, so that the capacitance of the first photodiode PD0 formed in the same photoelectric conversion readout section 210 is made smaller than the capacitance of the second photodiode PD1 formed adjacently in the same photoelectric conversion readout section 210.

[0267] The FWC of the first photodiode PD0 from which reading is performed in the fourth read mode RMD4 is limited by PD saturation, and is not limited by the FWC (Full Well Capacity) of the photodiode itself. On the other hand, the FWC of the first photodiode PD1 from which reading is performed in the first read mode RMD1 or the like is limited to the FWC of the photodiode. Therefore, the first photodiode PD0 from which readout is performed in the fourth readout mode RMD4 is formed to have a small FWC, and the second photodiode PD1 from which readout is performed in the first readout mode RMD1 etc. is formed to have a large FWC.

[0268] (Example of signal selection unit configuration) Next, a specific example of the configuration of the signal selection unit 213 in the photoelectric conversion readout unit 210 of the pixel 200 will be described.

[0269] The signal selection unit 213 compares the read reset signal VRST and read signal VSIG read out from the output buffer unit 211 with a reference signal Vref, determines the read processing mode (conversion gain processing) and whether it is the read reset signal VRST or the read signal VSIG depending on the comparison result, and holds the read reset signal VRST and read signal VSIG read out from the output buffer unit 211 in a predetermined holding unit of the signal holding unit 220 for each conversion gain processing depending on the determination result.

[0270] In the third embodiment, the readout section 70 can switch between operating in the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 depending on the scene (for example, the magnitude (intensity) of the illuminance). The readout unit 70, for example, switches to be operable for a low illum scene (Low illum.) in a first high conversion gain (HCG1) readout process HCG1-RDO, switches to be operable for a medium illum scene (Middle illum.) in a first low conversion gain (LCG1) readout process LCG1-RDO, and switches to be operable for a high illum scene (High illum.) in a second high conversion gain (LCG2) readout process LCG2-RDO.

[0271] Then, under the control of the readout section 70, in the first high conversion gain read process HCG1-RDO, the signal selection section 213 causes the signal holding section 220 to hold the read reset signal HCG1-RST and the readout signal HCG1-SIG by the first high conversion gain HCG1. In the first low conversion gain read process LCG1-RDO, the signal selection unit 213 causes the signal holding unit 220 to hold the read reset signal LCG1-RST and read signal LCG1-SIG by the first low conversion gain LCG1, or the read signal LCG2-SIG by the second low conversion gain LCG2. In the second low conversion gain read process LCG2-RDO, the signal selection unit 213 causes the signal holding unit 220 to hold the read reset signal LCG2-RST and read signal LCG2-SIG by the second low conversion gain LCG2, or the read signal LCG1-SIG by the first low conversion gain LCG1.

[0272] Figures 22(A) to (D) are figures for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to the third embodiment of the present invention, and are figures for explaining the readout operation sequence and potential transition for each conversion gain readout process, as well as the photoelectric conversion characteristics related to the conversion gain readout process. FIG. 22(A) shows an operation sequence for a high illum. scene, FIG. 22(B) shows an operation sequence for a medium illum. scene, and FIG. 22(C) shows an operation sequence for a low illum. scene. 22(D) shows the photoelectric conversion characteristics related to the conversion gain readout process. In this example, the dual conversion gain readout mode corresponds to the first low conversion gain LCG1 and the first high conversion gain HCG1, and the LOFIC mode corresponds to the first high conversion gain HCG1 and the second low conversion gain LCG2.

[0273] In this third embodiment, by applying a first conversion gain readout mode (e.g., dual conversion gain readout mode) CGRM1 at low to medium illuminance and a second conversion gain readout mode (e.g., LOFIC mode) CGRM2 at high illuminance, it is possible to minimize the reduction in SNR at the coupling point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal without being affected by the optical specifications, and thus it is possible to fully realize the single exposure high dynamic range (SEHDR) performance, thereby making it possible to substantially achieve a wide dynamic range.

[0274] In this example, under the control of the readout unit 70, when a predetermined period of time has elapsed since the start of the exposure period PEXP, during the first low conversion gain readout period of the first low conversion gain readout process LCG1-RDO, the signal selection unit 213 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD (Vsfo) as a first low conversion gain readout reset signal LCG1-RST.

[0275] Next, during the first high conversion gain read period of the first high conversion gain read process HCG1-RDO, when the voltage signal VFD read out from the output buffer unit 211 is higher than the reference signal Vref, the signal selection unit 213 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD as the first high conversion gain read reset signal HCG1-RST.

[0276] Next, during a second high conversion gain read period of the first high conversion gain read process HCG1-RDO following the first transfer period, when the voltage signal VFD read out from the output buffer unit 211 is higher than the reference signal Vref, the signal selection unit 213 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal Vref as the first high conversion gain read signal HCG1-SIG.

[0277] Next, in the second high conversion gain read period of the first low conversion gain read period of the first low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the second low conversion gain read period of the output buffer unit 211, when the voltage signal VFD is lower than the reference signal Vref, the signal selection unit 213 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD as the first low conversion gain read signal LCG1-SIG or the second low conversion gain read signal LCG2-SIG.

[0278] In addition, during a second low conversion gain read period of the second low conversion gain read process LCG2-RDO after the reset period of the floating diffusion FD11 and the storage capacitor SC11 after the first low conversion gain read period of the second low conversion gain read process LCG2-RDO, when the voltage signal VFD read out from the output buffer unit 211 is lower than the reference signal Vref, the signal selection unit 213 causes the signal holding unit 220 to hold a signal corresponding to this voltage signal VFD as a second low conversion gain read reset signal LCG2-RST.

[0279] Returning now to the description of FIGS.

[0280] The vertical scanning circuit 30 drives the photoelectric conversion readout units 210 and signal holding units 220 of the pixels 200 in the shutter row and readout row through row scanning control lines in accordance with the control of the timing control circuit 60 . Furthermore, the vertical scanning circuit 30 outputs a row selection signal, which is a row address of a read row for reading out a signal and a shutter row for resetting the charge accumulated in the photodiode PD, in accordance with the address signal.

[0281] The column readout circuit 40 may include a plurality of column signal processing circuits (not shown) arranged corresponding to each column output of the pixel section 20, and may be configured to enable column parallel processing by the plurality of column signal processing circuits. The column readout circuit 40 performs amplification and AD conversion on the pixel signals Pixout (VSL) read from the signal holding units 220 of the pixels 200 to the vertical signal lines LSGN11 to LSGN15 in the global shutter mode.

[0282] Here, the pixel signal Pixout (VSL) refers to a pixel read signal including a read signal VSIG and a read reset signal VRST that are sequentially read out from a pixel (in this example, the photoelectric conversion read unit 210 and further the signal holding unit 220 of the pixel 200) in global shutter mode.

[0283] In the solid-state imaging device 10B according to the third embodiment, the column readout circuit 40 is formed so as to be able to be shared by one circuit configuration regardless of the operation mode or the signal form of the readout signal (such as a single-ended or differential signal).

[0284] The column read circuit 40 includes, for example, an amplifier (AMP) and an ADC (analog-to-digital converter).

[0285] The horizontal scanning circuit 50 scans and horizontally transfers signals processed by a plurality of column signal processing circuits such as ADCs of the column readout circuit 40, and outputs them to a signal processing circuit (not shown).

[0286] The timing control circuit 60 generates timing signals necessary for signal processing in the pixel section 20, the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the like.

[0287] In the third embodiment, the readout section 70 performs readout control according to the mode operation in the rolling shutter mode and in the global shutter mode. The readout section 70 is capable of switching between operating in the first conversion gain readout mode CGRM1 and the second conversion gain readout mode CGRM2 depending on the scene.

[0288] In a first conversion gain readout mode CGRM1 when operating in a rolling shutter (RS) mode, the readout unit 70 switches to be operable for at least one of low and medium illuminance scenes, and in a second conversion gain readout mode CGRM2 when operating in the rolling shutter (RS) mode, the readout unit 70 switches to be operable for high illuminance scenes.

[0289] In the first conversion gain read mode CGRM1, the read section 70 sequentially performs a read process of the first low conversion gain reset signal LCG1-RST, a read process of the first high conversion gain reset signal HCG1-RST, a read process of the first high conversion gain signal HCG1-SIG, and a read process of the first low conversion gain signal LCG1-SIG. In the second conversion gain read mode CGRM2, the read section 70 sequentially performs a read process of the second low conversion gain signal LCG2-SIG and a read process of the second low conversion gain reset signal LCG2-RST.

[0290] Furthermore, the readout section 70 can perform triple conversion gain readout mode processing MTCG1 with the first low conversion gain LCG1 as the medium conversion gain MCG1 through the first conversion gain readout mode MLCG1 and the second conversion gain readout mode MLCG2. In the triple conversion gain read mode MTCG1, the read section 70 performs read processing of the medium conversion gain reset signal MCG1-RST, read processing of the first high conversion gain reset signal HCG1-RST, read processing of the first high conversion gain signal HCG1-SIG, and read processing of the medium conversion gain signal MCG1-SIG. The readout section 70 further sequentially performs a readout process of the second low conversion gain signal LCG2-SIG and a readout process of the second low conversion gain reset signal LCG2-RST.

[0291] In this third embodiment, the readout section 70 can also use the second low conversion gain signal LCG2-SIG in combination with the medium conversion gain signal MCG1-S obtained in the readout process of the previous medium conversion gain signal MCG1-SIG without performing the second low conversion gain signal readout process LCG2-SIG.

[0292] As described above, according to the third embodiment, in the solid-state imaging device 10B, the pixels 200 arranged in a matrix in the pixel section 20 include, for example, a photoelectric conversion readout section 210 and a signal holding section 220, have a rolling shutter (RS) operating function and a global shutter (GS) operating function, and are capable of arbitrarily selecting the pixel operation mode of the rolling shutter (RS) and the global shutter (GS), and further, are capable of automatically switching within the chip the conversion gain readout mode for reading out signals with different conversion gains depending on the scene. In the solid-state imaging device 10B according to the third embodiment, the pixels (or pixel section 20) arranged in a matrix in the pixel section 20 share one floating diffusion FD as an output node and a source follower element (source follower transistor) forming an output buffer with two or four photoelectric conversion elements (photodiodes PD) and transfer elements (transfer transistors).The floating diffusion FD is disposed in the center of the element formation region of the shared pixel, and a plurality of photoelectric conversion elements are disposed radially (in the left-right (X), up-down (Y) directions, and diagonally (XY) directions in this embodiment) around this floating diffusion FD.

[0293] In the solid-state imaging device 10B of the third embodiment, the first charge storage capacitance CP0 that can be stored by the first photoelectric conversion element (photodiode) PD0 is smaller than the second charge storage capacitance CP1 that can be stored by the second photodiode PD1, and an overflow path portion that can overflow the charge signal from the first photodiode PD0 to the floating diffusion FD via the first transfer element (transfer transistor) TG0-Tr can be formed in the charge transfer path portion from the first photodiode PD0 to the floating diffusion FD, and a charge discharge path portion that can discharge the charge signal from the second photodiode PD1 to the region outside the floating diffusion FD can be formed in the charge transfer from the second photodiode PD1 to the region outside the floating diffusion FD.

[0294] In the solid-state imaging device 10 according to the first embodiment, the shared FD structure of the pixel 200 includes a first photodiode PD0 and a second photodiode PD1, and a first saturation signal saturated in the first photodiode PD0 is completely transferred (overflowed) to the floating diffusion FD. In pixel 200, an overflow signal from the second photodiode PD1, which is another shared PD, to the floating diffusion FD is discharged (discharged) to the drain via the other side of the shutter gate SG(AB). Therefore, there is no overflow signal to the floating diffusion FD, and therefore, even though this component has a common FD structure, no overflow signal is mixed in as signal crosstalk.

[0295] Therefore, the pixel of the solid-state imaging device 10B according to the third embodiment not only makes it possible to reduce the pixel size while maintaining the sensitivity and saturation charge number, but also makes it possible to suppress an increase in junction capacitance and wiring capacitance, and to suppress an increase in the capacitance of the floating diffusion as an output node, thereby preventing a decrease in conversion gain, and ultimately making it possible to improve noise characteristics. It is therefore possible to ensure maximum light response, ensure reproducibility as well as low light SNR, and further reduce pixel size, thereby efficiently improving important performances such as dynamic range, responsiveness, and resolution. More specifically, the solid-state imaging device 10 can minimize the degradation of SNR at the joining point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal without being affected by the optical specifications, thereby enabling the single exposure high dynamic range (SEHDR) performance to be fully realized.

[0296] The pixel 200 according to the third embodiment has a structure with a 3Q-DPS and MLCG1 (4TLCG1 or 4TMCG) readout processing function without an asymmetric split PD, and realizes a 100 dB SEHDR pixel by minimizing the SNR degradation between connection points.

[0297] Therefore, according to the third embodiment, it is possible to prevent a decrease in SNR at a coupling point between signals having different conversion gains. Furthermore, according to the third embodiment, it is possible to expand the dynamic range with a small pixel size by using a predetermined readout mode. According to the third embodiment, it is possible to achieve a high dynamic range.

[0298] Furthermore, according to the third embodiment, it is possible to arbitrarily select a pixel operation mode between rolling shutter and global shutter, and it is also possible to automatically switch within the chip the conversion gain readout mode, which reads out signals with different conversion gains, depending on the scene. As a result, according to the third embodiment, it is possible to minimize the decrease in SNR at the joining point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, thereby making it possible to achieve large saturation and small dark noise.

[0299] Here, an evaluation of the SNR when a readout process is performed by combining a plurality of conversion gains according to the third embodiment will be described. 23A to 23D are diagrams for explaining a first example of an evaluation of an SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the first embodiment of the present invention. Figures 23(A) to (C) show the SNR characteristics when a readout process is performed by combining three conversion gains: the first high conversion gain HCG1, the first low conversion gain LCG1, and the second low conversion gain LCG2, and Figure 23(D) shows the evaluation conditions. In Figures 23(A) to (C), the curve shown by A shows the SNR characteristics when the first high conversion gain HCG1 is used, the curve shown by B shows the SNR characteristics when the first low conversion gain LCG1 is used, the curve shown by C shows the SNR characteristics when the second low conversion gain LCG2 is used, and the curve shown by D shows the SNR characteristics when the ideal conversion gain is used.

[0300] The example of FIG. 23 relates to evaluation of SNR when a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first low conversion gain LCG1, and a second low conversion gain LCG2.

[0301] The SNR estimate (4THCG-4TLCG-3TLCG-TTS) in the example of FIG. Since the SNR at the LCG-3T / LCG-3T junction point is >32dB, the SNR junction point must be >32dB. The LCG-4T SNR at the splice point is still <32 dB, as shown in FIG. 23(B). The LCG-4T SNR at the splice point is still <32 dB, as shown in FIG. 23(C). In addition, the connection point between the first high conversion gain HCG1 (4THCG) and the first low conversion gain LCG1 (4TLCG) is (~3000e- @FDsat), and the connection point between the first low conversion gain LCG1 (4TLCG) and the second low conversion gain LCG2 (4TLCG) is (~10000e- @1QPDsat).

[0302] Therefore, when the circuit noise is sufficiently small (up to 1e-), the method of performing readout processing in combination with the conversion gain described in relation to FIG. 23 is effective in improving the SNR.

[0303] Now consider the noise of the first high conversion gain HCG1, the first low conversion gain LCG1, and the second low conversion gain LCG2. The following formula 1 represents the noise of the first high conversion gain HCG1, formula 2 represents the noise of the first low conversion gain LCG1, and formula 3 represents the noise of the second low conversion gain LCG2. The noise of the first high conversion gain HCG1 and the noise of the first low conversion gain LCG1 mainly consist of “shot noise” and “readout circuit noise,” while the noise of the second low conversion gain LCG2 mainly consists of “shot noise,” “readout circuit noise,” and “kTC noise” at the time of pixel reset.

[0304]

number

[0305]

number

[0306]

number

[0307] In the above formulas 1, 2, and 3, Vread represents read circuit noise, AG represents analog gain*SF gain, CFD represents FD capacitance, CMCG represents MCG capacitance, CLCG represents LCG capacitance, and q represents elementary charge.

[0308] As can be seen from Equation 2, a small CLCG is desirable to reduce the LCG1 noise of LOFIC, and a large CLCG is desirable to increase the FWC, but there is a trade-off between the two. Furthermore, as can be seen from Equation 3, a small CLCG is desirable for reducing the LCG1 noise of LOFIC, and a large CLCG is desirable for increasing the FWC, but there is a trade-off between the two.

[0309] The example of Figure 23 is a case where a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first low conversion gain LCG1, and a second low conversion gain LCG2, and relates to an evaluation of the SNR for 20 fF. When using only the combination of the first high conversion gain HCG1 and the second low conversion gain LCG2 (LOFIC), the SNR drop at the signal combining point is about 32 dB<. When using only the combination of the first low conversion gain LCG1 and the second low conversion gain LCG2, the SNR drop at the signal combining point is about 20 dB. When using only the combination of the first high conversion gain HCG1 and the first low conversion gain LCG1, the SNR drop at the signal combining point is about 4 dB. Also, the connection point between the first high conversion gain HCG1 and the first low conversion gain LCG1 is (~800e- @FDsat), and the connection point between the first low conversion gain LCG1 and the second low conversion gain LCG2 is (~30000e- @PDsat). Note that all PD charges can be read in the first low conversion gain LCG1 mode.

[0310] As described above, according to the third embodiment, the following effects can be obtained. It is possible to improve the SNR at the signal combining point in LOFIC operation, thereby enabling a high dynamic range (HDR) to be achieved with minimal SNR degradation. In addition, the single PD structure maintains optical symmetry, which is difficult to achieve in a solid-state imaging device with an asymmetric split PD structure.

[0311] (Fourth embodiment) FIG. 24 is a circuit diagram showing an example of a pixel of a solid-state imaging device according to the fourth embodiment of the present invention. Figure 25 is a diagram for explaining an example of a conversion gain readout process according to an illuminance scene in a solid-state imaging device according to the fourth embodiment of the present invention, and is a diagram for explaining photoelectric conversion characteristics related to the conversion gain readout process.

[0312] The pixel 200C of the solid-state imaging device 10C according to the fourth embodiment differs from the pixel 200 of the solid-state imaging device 10B according to the third embodiment described above in the following respects.

[0313] In the pixel 200C of the solid-state imaging device 10C of the fourth embodiment, in addition to the components of the pixel 200 shown in FIG. 18, the pixel 200C further includes a second storage transistor BIN1-Tr as a second storage connection element connected to the floating diffusion FD, and a second storage capacitor CS1 capable of storing the charge of the floating diffusion FD via the second storage transistor BIN1-Tr. The pixel 200C has 3Q-DPS and 4TLCG (or 4TMCG) readout capabilities without an asymmetric split PD.

[0314] Under the control of the readout unit 70, the pixel 200C can operate in at least one of a first high conversion gain readout mode 4THCG1 (MHCG1), a first medium conversion gain readout mode 4TLCG1 (MMCG1), a second low conversion gain readout mode 4TLCG2 (MLCG2), and a time domain mode TTS during readout depending on the conversion gain.

[0315] In the first high conversion gain read mode 4THCG(MHCG1), the pixel 200C performs readout with a first high conversion gain HCG1 associated with the accumulated charge of the first photodiode PD0. In the first low / medium conversion gain readout mode 4TLCG1 (MLCG1) / 4TMCG1 (MMCG1), the pixel 200C reads out the accumulated charge in the second photodiode PD1 with a first low conversion gain 4TLCG1 or a medium conversion gain MMCG1 associated with the accumulated charge in the floating diffusion FD and the second storage capacitor CS1. In a second low conversion gain readout mode 4TLCG2 (MLCG2), the pixel 200C is read out with a second low conversion gain LCG2 associated with the photodiode PD, the floating diffusion FD and the stored charge in the first storage capacitor CS0. The pixel 200C is read out in the time domain mode TTS with a third low conversion gain LCG3 associated with the photodiode PD, the floating diffusion FD and a charge equal to or greater than the stored charge on the first storage capacitor.

[0316] To summarize: 4THCG High conversion gain mode (3QPD electronic readout only), 4TLCG / 4TMCG...Low / medium conversion gain mode (1QPD electronic readout only), 3TLCG: Low conversion gain mode (PD&FD&CS all-electronic readout), TTS: Time domain mode (can read out more than PD+CS+FD electrons).

[0317] As described above, in the fourth embodiment, an MCG capacitor (CMCG) and a switch (BIN1) are added to the circuit of FIG. 2, enabling an additional MCG readout. In the fourth embodiment, the method for reading out the 3QPD is the same as that described in the first embodiment. On the other hand, 1QPD is read out by capacitance (CFD+CMCG).

[0318] According to the fourth embodiment, like the above-described third embodiment, it is possible to prevent a decrease in SNR at a coupling point between signals having different conversion gains. Furthermore, according to the fourth embodiment, it is possible to expand the dynamic range with a small pixel size by using a predetermined readout mode. According to the fourth embodiment, it is possible to achieve a high dynamic range.

[0319] Furthermore, according to the fourth embodiment, it is possible to arbitrarily select a pixel operation mode between rolling shutter and global shutter, and it is also possible to automatically switch within the chip the conversion gain readout mode, which reads out signals with different conversion gains, depending on the scene. As a result, according to the fourth embodiment, it is possible to minimize the decrease in SNR at the joining point of the high conversion gain (HCG) signal and the low conversion gain (LCG) signal, thereby making it possible to achieve large saturation and small dark noise.

[0320] As described above, in the fourth embodiment, an MCG capacitor (CMCG) and a switch (BIN1) are added to the circuit of FIG. 2, enabling an additional MCG readout.

[0321] Here, an evaluation of the SNR when a readout process is performed by combining a plurality of conversion gains according to the fourth embodiment will be described. 26(A) to 26(D) are diagrams for explaining a second example of evaluation of the SNR when a readout process is performed using a combination of three conversion gains in the solid-state imaging device according to the second embodiment of the present invention. Figures 26(A) to (C) show the SNR characteristics when a readout process is performed by combining three conversion gains: the first high conversion gain HCG1, the first low conversion gain LCG1 or the first medium conversion gain MCG1, and the second low conversion gain LCG2, and Figure 26(D) shows the evaluation conditions. In Figures 26(A) to (C), the curve shown by A shows the SNR characteristics when the first high conversion gain HCG1 is used, the curve shown by B shows the SNR characteristics when the first medium conversion gain MCG1 is used, the curve shown by C shows the SNR characteristics when the second low conversion gain LCG2 is used, and the curve shown by D shows the SNR characteristics when the ideal conversion gain is used.

[0322] The example of FIG. 26 relates to evaluation of SNR when a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first medium conversion gain MCG1, and a second low conversion gain LCG2.

[0323] The SNR estimate (4THCG-4TMCG-3TLCG-TTS) in the example of FIG. Since the SNR at the MCG-4T / LCG-3T junction point is >32dB, the SNR junction point must be >32dB. The SNR at the MCG-4T / LCG-3T connection point is >32 dB, as shown in FIG. 26(B). The SNR at the MCG-4T / LCG-3T connection point is >32 dB, as shown in FIG. 26(C). In addition, the connection point between the first high conversion gain HCG1 (4THCG) and the first medium conversion gain MCG1 (4TMCG1) is (~3000e- @FDsat), and the connection point between the first medium conversion gain MCG1 (4TMCG) and the second low conversion gain LCG2 (3TLCG) is (~10000e- @1QPDsat).

[0324] Therefore, when the circuit noise is large (up to 10e-), the method of performing readout processing in combination with the conversion gain described in relation to FIG. 26 is effective in improving the SNR.

[0325] Now consider the noise of the first high conversion gain HCG1, the first medium conversion gain MCG1, the first low conversion gain LCG1, and the second low conversion gain LCG2.

[0326] The following equation 4 represents the noise of the first high conversion gain HCG1, equation 5 represents the noise of the first medium conversion gain MCG1, equation 6 represents the noise of the first low conversion gain LCG1, and equation 7 represents the noise of the second low conversion gain LCG2. The noise of the first high conversion gain HCG1, the first medium conversion gain MCG1, and the first low conversion gain LCG1 mainly contain "shot noise" and "readout circuit noise," while the noise of the second low conversion gain LCG2 mainly contains "shot noise," "readout circuit noise," and "kTC noise" at the time of pixel reset.

[0327]

number

[0328]

number

[0329]

number

[0330]

number

[0331] In the above equations 4, 5, 6, and 7, Vread represents read circuit noise, AG represents analog gain*SF gain, CFD represents FD capacitance, CMCG represents MCG capacitance, CLCG represents LCG capacitance, and q represents elementary charge.

[0332] As can be seen from Equations 5 and 6, a small CMCG / CLCG is desirable to reduce the MCG1 (4TMCG) / LCG1 (4TLCG) noise in 3Q-DPS, and a large CLCG is desirable to increase the FWC, but there is a trade-off between the two. Also, as can be seen from Equation 7, a small CLCG is desirable to reduce LCG2 (3TLCG) noise in 3Q-DPS, and a large CLCG is desirable to increase FWC, but there is a trade-off between the two.

[0333] The example in Figure 26 is a case where a readout process is performed by combining three conversion gains: a first high conversion gain HCG1, a first medium conversion gain MCG1 or a first low conversion gain LCG1, and a second low conversion gain LCG2, and relates to an evaluation of the SNR at 20 fF.

[0334] As described above, according to the fourth embodiment, the following effects can be obtained. It is possible to improve the SNR at the signal combining point in LOFIC operation, thereby enabling a high dynamic range (HDR) to be achieved with minimal SNR degradation. In addition, the pixel 200C has a single PD structure, and therefore maintains optical symmetry. For example, it is difficult to obtain such an effect in a solid-state imaging device having an asymmetric split PD structure.

[0335] As described above, in the third and fourth embodiments, a solid-state imaging device 10 has been described that employs a configuration that is linked to the characteristics of the pixel photodiodes 3QPD and 1QPD and the circuit system, and thereby makes it possible to improve the SNR at the signal coupling point between signals with different conversion gains while maintaining optical symmetry, thereby making it possible to realize a high dynamic range (HDR) with minimal SNR degradation. Below, as fifth to eighth embodiments, a solid-state imaging device 10 is described which employs a configuration related to the pixel layout, the size of the charge storage section in the photodiode (1QPD, 3QPD), etc., thereby making it possible to improve the SNR at the signal coupling point between signals with different conversion gains while maintaining optical symmetry, thereby making it possible to realize a high dynamic range (HDR) with minimal SNR degradation.

[0336] Fifth embodiment FIG. 27 is a simplified diagram showing an example of a pixel layout of a solid-state imaging device according to the fifth embodiment of the present invention.

[0337] The shared pixel 200D of the solid-state imaging device 10D according to the fifth embodiment of the present invention differs from the shared pixel 200B of the solid-state imaging device 10B according to the third embodiment described above in the following points.

[0338] In a shared pixel 200C of a solid-state imaging device 10C according to the third embodiment, two photodiodes PD0 and PD1 share one floating diffusion FD. The solid-state imaging device 10C of the third embodiment includes a first photodiode PD0 connected to a first transfer transistor TG0-Tr, a second photodiode PD1 connected to a second transfer transistor TG1-Tr, a floating diffusion FD connected to the first transfer transistor TG0-Tr and the second transfer transistor TG1-Tr, a first shutter gate transistor SG0-Tr serving as an anti-blooming gate connected to the first photodiode PD0, and a second shutter gate transistor SG1-Tr serving as an anti-blooming gate connected to the second photodiode PD1.

[0339] In contrast, in a shared pixel 200D of a solid-state imaging device 10D according to the fifth embodiment, four photodiodes PD0 to PD3, which are two photodiodes PD0 and PD1, and two more photodiodes PD2 and PD3, share one floating diffusion FD. Specifically, the solid-state imaging device 10D according to the fifth embodiment includes a first photodiode PD0 connected to the first transfer transistor TG0-Tr, a second photodiode PD1 connected to the second transfer transistor TG1-Tr, a third photodiode PD2 connected to the third transfer transistor TG2-Tr, a fourth photodiode PD3 connected to the fourth transfer transistor TG3-Tr, and a second photodiode PD4 connected to the first transfer transistor TG0-Tr, the second transfer transistor TG1-Tr, the third transfer transistor TG2-Tr, and the fourth transfer transistor TG3-Tr. The transistor includes a floating diffusion FD, a first shutter gate transistor SG0-Tr serving as an anti-blooming gate connected to a first photodiode PD0, a second shutter gate transistor SG1-Tr serving as an anti-blooming gate connected to a second photodiode PD1, a third shutter gate transistor SG2-Tr serving as an anti-blooming gate connected to a third photodiode PD2, and a fourth shutter gate transistor SG3-Tr serving as an anti-blooming gate connected to a fourth photodiode PD3.

[0340] Thus, the shared pixel 200D of the solid-state imaging device 10D according to the fifth embodiment further includes a third photodiode PD2 and a fourth photodiode PD3 coupled to the third transfer transistor TG2-Tr and the fourth transfer transistor TG3-Tr, respectively. The layout of the FD shared pixel 200D is formed to include a first photodiode PD0, a second photodiode PD1, a third photodiode PD2, and a fourth photodiode PD3, and all of the saturation signals SAT0 to SAT3 of PD0 to PD3 are completely transferred (overflowed) to the floating diffusion FD, and the opposite side of the transfer transistor TG (shutter gate transistor SG) can discharge its own overflow charge to the drain. In addition, at least one of the saturation signals SAT0 to SAT3 of PD0 to PD3 is configured to be completely transferred (overflowed) to the floating diffusion FD, but the opposite side of the transfer transistor TG (shutter gate transistor SG) can discharge its own overflow charge to the drain.

[0341] In the shared pixel 200D, two charge transfer transistors are connected to each of the photodiodes PD0 to PD3, and the accumulated charges can be discharged and the accumulation time can be individually controlled. In addition, the shared pixel 200D has a color filter formed on the corresponding FD shared PD. For example, a color filter configuration of RGB and G filters is applied to a 2x2 block of the FD shared PD. In addition, because of the shared FD structure, pixels can be formed on a BSI (Back Sided Isolations) structure using partial full DTI, which can prevent color signal crosstalk that occurs between the photodiodes PD0 to PD3.

[0342] In pixel 200D, one floating diffusion FD and one microlens ML are shared by four photodiodes PD0 to PD3, including the first photodiode PD and the second photodiode PD photoelectric conversion elements, and the third photodiode PD02 and the fourth photodiode PD3. Each of the first photoelectric conversion arrangement region LY0, the second photoelectric conversion arrangement region LY1, the third photoelectric conversion arrangement region LY2, and the fourth photoelectric conversion arrangement region LY3 in the four photodiodes PD0 to PD3 includes a DEEP-N doped region (DEEP-N) which is an impurity doped region of the same shape, and is arranged in a square shape in a predetermined rectangular portion RCT in the pixel array of the pixel section 20.

[0343] In the rectangular portion RCT, the charge accumulation portion CA0 of the first photodiode PD0 which is 3QPD is arranged in the first photoelectric conversion arrangement region LY0, leaving an empty space in approximately half of the region, the charge accumulation portion CA1 of the second photodiode PD1 which is 1QPD is arranged over approximately the entire region in the second photoelectric conversion arrangement region LY1, the charge accumulation portion CA2 of the third photodiode PD2 which is 1QPD is arranged over approximately the entire region in the third photoelectric conversion arrangement region LY2, and the charge accumulation portion CA3 of the fourth photodiode PD3 which is 3QPD is arranged in the fourth photoelectric conversion arrangement region LY3, leaving an empty space in approximately half of the region.

[0344] In the pixel 200D, the aperture ratio AP of the first photodiode PD0 (1QPD) and the second photodiode PD1 (3QPD) on the second surface side (rear surface side) is the same. Regarding the charge accumulation portions CA0, CA1 of the first photodiode PD0 and the second photodiode PD1 on the first surface side (front surface side), the first charge accumulation capacitance CAA0 of the first photodiode PD0 is smaller than the second charge accumulation capacitance CAA1 of the second photodiode PD1.

[0345] In pixel 200D, the structure of the charge storage capacitance CAA and charge storage unit CA of one of the third photodiode PD2 and the fourth photodiode PD3 is equivalent to the structure of the charge storage capacitance CAA and the first charge storage unit CA0 of the first photodiode PD0 described above, and the structure of the other charge storage capacitance CAA and charge storage unit CA is equivalent to the structure of the second charge storage capacitance CAA and the second charge storage unit CA of the second photodiode PD1. The photodiodes PD having the same structures of the charge storage capacitances CAA and the charge storage portions CA are arranged adjacent to each other in the diagonal direction in a square array.

[0346] In the third embodiment, photodiodes PD0 and PD3, which are 3QPD, are arranged adjacent to each other in the diagonal direction, and similarly, photodiodes PD1 and PD2, which are 1QPD, are arranged adjacent to each other in the diagonal direction.

[0347] Here, the pixel layout of the solid-state imaging device 10D according to the fifth embodiment will be considered.

[0348] To achieve optical symmetry between 1QPD and 3QPD, the microlens MCL needs to be shared by the four photodiodes PD0 to PD3, and 3QPD and 1QP are arranged so as to be diagonally adjacent in the arrangement regions LY0 to LY3 of the rectangular portion RCT. The 3QPD and 1QPD DEEP-N are formed in the same shape. The back side also has the same fill factor.

[0349] To achieve a larger 1QPDFWC and a smaller 3QPDFWC, the storage PD size is different for 1QPD and 3QPD. To realize overflow charge storage and 3Q of 3QPD and 4T readout of 1QPD, a buried overflow path is formed under the transfer transistor TG-Tr of 3QPD. It is formed in the lower layer of SG of 1QPD.

[0350] Sixth embodiment FIG. 28 is a simplified diagram showing an example of a pixel layout of a solid-state imaging device according to the sixth embodiment of the present invention.

[0351] The shared pixel 200E of the solid-state imaging device 10E according to the sixth embodiment of the present invention differs from the shared pixel 200D of the solid-state imaging device 10D according to the fifth embodiment described above in the following points.

[0352] In the shared pixel 200D of the solid-state imaging device 10D of the fifth embodiment, in the rectangular portion RCT, the charge accumulation portion CA0 of the first photodiode PD0 which is 3QPD is arranged in the first photoelectric conversion arrangement region LY0, leaving an empty space in approximately half of the region, the charge accumulation portion CA1 of the second photodiode PD1 which is 1QPD is arranged over approximately the entire region in the second photoelectric conversion arrangement region LY1, the charge accumulation portion CA2 of the third photodiode PD2 which is 1QPD is arranged over approximately the entire region in the third photoelectric conversion arrangement region LY2, and the charge accumulation portion CA3 of the fourth photodiode PD3 which is 3QPD is arranged in the fourth photoelectric conversion arrangement region LY3, leaving an empty space in approximately half of the region.

[0353] In contrast, in the shared pixel 200E of the solid-state imaging device 10E according to the sixth embodiment, a second storage capacitor CS1 is added, and accordingly, in the rectangular portion RCT, the charge storage section CA0 of the first photodiode PD0 having a size of 3QPD is arranged in approximately half of the region in the first photoelectric conversion arrangement region LY0, and an MCG capacitor is arranged in this vacant region, the charge storage section CA1 of the second photodiode PD1 having a size of 1QPD is arranged over approximately the entire region in the second photoelectric conversion arrangement region LY1, the charge storage section CA2 of the third photodiode PD2 having a size of 1QPD is arranged over approximately the entire region in the third photoelectric conversion arrangement region LY2, and the charge storage section CA3 of the charge storage section CA3 of the fourth photodiode PD3 having a size of 3QPD is arranged in the vacant region in approximately half of the region in the fourth photoelectric conversion arrangement region LY3, and an MCG capacitor is arranged in this vacant region.

[0354] According to the sixth embodiment, it is possible to obtain the same effects as those of the fourth and fifth embodiments described above.

[0355] Seventh embodiment FIG. 29 is a diagram showing an example of a pixel layout of a solid-state imaging device according to the seventh embodiment of the present invention, and a photoelectric conversion characteristic related to a multiple conversion gain readout process.

[0356] The shared pixel 200F of the solid-state imaging device 10F according to the seventh embodiment of the present invention differs from the shared pixel 200E of the solid-state imaging device 10E according to the sixth embodiment described above in the following points.

[0357] In the shared pixel 200F of the solid-state imaging device 10F according to the seventh embodiment, in the rectangular portion RCT, the capacitance of the fourth photodiode PD3 arranged in the fourth photoelectric conversion arrangement region LY3 is changed from a 3QPD photodiode to a 1QPD photodiode.

[0358] That is, in the solid-state imaging device 10F according to the seventh embodiment, the dynamic range (DR) can be further expanded by using large and small split PDs. In FIG. 29, R1QPD and R3QPD indicate the responsiveness of 1QPD and 3QPD.

[0359] In the seventh embodiment, 1QPD is used to reduce SNR drop and is not used to improve low light performance.

[0360] Eighth embodiment FIG. 30 is a diagram showing an example of a pixel layout of a solid-state imaging device according to the eighth embodiment of the present invention, and a photoelectric conversion characteristic related to a multiple conversion gain readout process.

[0361] The shared pixel 200G of the solid-state imaging device 10G according to the eighth embodiment of the present invention differs from the shared pixel 200D of the solid-state imaging device 10D according to the fifth embodiment described above in the following points.

[0362] In the shared pixel 200G of the solid-state imaging device 10G according to the eighth embodiment, in the rectangular portion RCT, the capacitance of the fourth photodiode PD3 arranged in the fourth photoelectric conversion arrangement area LY3 is changed from a 3QPD photodiode to a 1QPD photodiode.

[0363] That is, the solid-state imaging device 10G according to the eighth embodiment is configured to be able to further improve low illuminance sensitivity by using large and small split PDs. In FIG. 30, R1QPD and R3QPD indicate the responsiveness of 1QPD and 3QPD.

[0364] In this eighth embodiment, 1QPD is used to improve low light performance and is not used to reduce SNR drop.

[0365] Here, the pixel layouts of the solid-state imaging devices 10F and 10G according to the seventh and eighth embodiments will be considered.

[0366] In the seventh and eighth embodiments, in order to achieve a further expansion of the dynamic range (DR), the microlens MCL is shared by four photodiodes PD. In this example, a small 3QPD with a small fill factor and a large 1QPD with a large fill factor are arranged.

[0367] In the seventh embodiment, 1QPD is used to reduce SNR drop (4TMCG@1QPD is used in the medium light range), and is not used to improve low-illumination performance. 4THCG@3QPD is used in low light areas, but the fill factor of 3QPD is small, which may result in poor low light performance. Small 3QPD with a small fill factor and large 1QPD with a large fill factor are deployed.

[0368] In the eighth embodiment, 1QPD is used to improve low light performance. 4THCG@1QPD is used in low light areas and has a larger fill factor than 1QPD, which improves low light performance. However, it is not used to reduce SNR drop. 4THCG@3QPD is used for mid-light range, but the 3QPD / FD FWC is smaller. As a result, the SNR drop is the same as that of the conventional 3Q-DPS.

[0369] (Effects of the embodiment) According to this embodiment, it is possible to improve the SNR at the signal connection point during 3Q operation, thereby achieving HDR with little SNR degradation. In addition, the optical symmetry between the two PDs is maintained.

[0370] (The first configuration in which only the pixel content CLCG is arranged is effective in improving the SNR when the circuit noise is sufficiently small (= up to 1e-). According to the second configuration in which the pixel contents of CMCG and CLCG are arranged, it is effective in improving the SNR even if the circuit noise (= up to 10e-) is large.

[0371] The above-described solid-state imaging devices 10, 10A to 10G can be applied as imaging devices to electronic devices such as digital cameras, video cameras, mobile terminals, surveillance cameras, and medical endoscope cameras.

[0372] FIG. 31 shows a camera system to which a solid-state imaging device according to an embodiment of the present invention is applied. FIG. 13 is a diagram illustrating an example of a configuration of an electronic device.

[0373] As shown in FIG. 31, the electronic device 300 includes a CMOS image sensor 310 to which the solid-state imaging devices 10, 10A to 10G according to the present embodiment can be applied. Furthermore, the electronic device 300 has an optical system (lens or the like) 320 that guides incident light to the pixel region of the CMOS image sensor 310 (forms an image of a subject). The electronic device 300 includes a signal processing circuit (PRC) 330 that processes an output signal from the CMOS image sensor 310 .

[0374] The signal processing circuit 330 performs a predetermined signal processing on the output signal of the CMOS image sensor 310 . The image signal processed by the signal processing circuit 330 can be displayed as a moving image on a monitor such as an LCD display, or output to a printer. It can also be recorded directly on a recording medium such as a memory card, and various other forms are possible.

[0375] As described above, by mounting the above-mentioned solid-state imaging devices 10, 10A to 10G as the CMOS image sensor 310, it is possible to provide a high-performance, small-sized, low-cost camera system. This makes it possible to realize electronic devices such as surveillance cameras and medical endoscope cameras that are used in applications where the camera installation requirements include constraints such as mounting size, number of connectable cables, cable length, and installation height. [Explanation of symbols]

[0376] 10, 10A to 10G... solid-state imaging device, 20, 20A to 20G... pixel section, 200, 200A to 200G... pixel, PD11... photodiode, FD11... floating diffusion, TG11-Tr... transfer transistor, RST11-Tr... reset transistor, SF11-Tr... source follower transistor, SG11-Tr... storage transistor, SC11... storage capacitor, PD0... first photodiode, PD1... second photodiode, PD2... third photodiode, PD3... fourth photodiode, TG0-Tr... first transfer transistor, TG1-Tr... second transfer transistor, TG2-Tr... third transfer transistor, TG3-Tr... fourth transfer transistor, SG0-Tr···first shutter gate transistor, SG1-Tr···second shutter gate transistor, SG2-Tr···third shutter gate transistor, SG3-Tr···fourth shutter gate transistor, FD···floating diffusion, RST-Tr···reset transistor, SF-Tr···source follower transistor, BIN-Tr···storage transistor, CS···storage capacitor, 210···photoelectric conversion readout section, 220···AD conversion section, 30···vertical scanning circuit, 40···column readout circuit, 60···timing control circuit, 70···readout section, 300···electronic device, 310···CMOS image sensor, 320···optical system, 330···signal processing circuit (PRC).

Claims

1. a pixel section in which pixels including at least a photoelectric conversion readout section are arranged; A readout unit that reads out pixel signals from the pixel unit, The photoelectric conversion readout unit is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charge stored in the photoelectric conversion element during a transfer period following the storage period; a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a storage capacitance element that is controlled to be connected or disconnected from the floating diffusion in accordance with a conversion gain; a conversion signal readout unit operable at least in a first conversion gain readout mode capable of reading out a signal corresponding to a first low conversion gain and a first high conversion gain associated with the capacitance of the floating diffusion, the storage capacitance of the storage capacitance element, and a full well capacity (FWC) of at least the floating diffusion of the floating diffusion and the photoelectric conversion element, and a second conversion gain readout mode capable of reading out a signal corresponding to at least a second low conversion gain associated with the capacitance of the floating diffusion and the storage capacitance of the storage capacitance element, and amplifying and outputting a voltage signal converted with the conversion gain; The pixel is In the first conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to accumulated charges of the photoelectric conversion element can be read out as a pixel signal in accordance with the first low conversion gain and the first high conversion gain; In the second conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge of the photoelectric conversion element or the accumulated charge and overflow charge of the photoelectric conversion element can be read out as a pixel signal in accordance with at least the second low conversion gain, A voltage level of the first low conversion gain signal read out with the first low conversion gain is equal to a voltage level of the second low conversion gain signal read out with the second low conversion gain. Solid-state imaging device.

2. the first high conversion gain is associated with an accumulated charge of the photoelectric conversion element and is limited by a floating diffusion width coefficient (FWC); the first low conversion gain is related to the accumulated charge of the photoelectric conversion element and is limited by the FWC of the photoelectric conversion element; The second low conversion gain is associated with the floating diffusion and the stored charge of the storage capacitance element.

2. The solid-state imaging device according to claim 1.

3. The readout unit is whether to operate in the first conversion gain readout mode or the second conversion gain readout mode is switchable; in a first conversion gain read mode, a first low conversion gain reset read process, a first high conversion gain reset read process, a first high conversion gain signal read process, and a first low conversion gain signal read process are sequentially performed; In the second conversion gain read mode, a second low conversion gain signal read process and a second low conversion gain reset read process are performed in sequence.

3. The solid-state imaging device according to claim 2.

4. The readout unit is Through the first conversion gain readout mode and the second conversion gain readout mode, a triple conversion gain readout mode process can be performed with the first low conversion gain as a medium conversion gain; In the triple conversion gain read mode, a medium conversion gain reset read process, a first high conversion gain reset read process, a first high conversion gain signal read process, and a medium conversion gain signal read process are performed; A second low conversion gain signal read process and a second low conversion gain reset read process are sequentially performed.

3. The solid-state imaging device according to claim 2.

5. The readout unit is The second low conversion gain signal is used in combination with the medium conversion gain signal acquired in the previous medium conversion gain signal readout process without performing the second low conversion gain signal readout process.

5. The solid-state imaging device according to claim 4.

6. The photoelectric conversion readout unit is an overflow path that is formed in a layer deeper than at least a channel formation region of the transfer element and that is capable of causing charges overflowing from the photoelectric conversion element to overflow toward a region in which the floating diffusion is formed; 3. The solid-state imaging device according to claim 2.

7. The photoelectric conversion readout unit is a shutter gate connected to the photoelectric conversion element and capable of discharging electric charges from the photoelectric conversion element in a direction outside a region in which the floating diffusion is formed; 3. The solid-state imaging device according to claim 2.

8. a signal holding unit capable of holding a read reset signal and a read signal that are converted with a predetermined conversion gain and read out from the photoelectric conversion readout unit, The photoelectric conversion readout unit is a signal selection unit for causing a read reset signal and a read signal read from the conversion signal read unit to be held in a predetermined holding unit of the signal holding unit for each conversion gain processing 2. The solid-state imaging device according to claim 1.

9. The signal selection unit is A read reset signal and a read signal read from the conversion signal read unit are compared with a reference signal, and a conversion gain process of a read process and a read reset signal or a read signal are determined according to a comparison result, and the read reset signal and the read signal read from the conversion signal read unit are held in a predetermined holding unit of the signal holding unit for each conversion gain process according to the determination result.

9. The solid-state imaging device according to claim 8.

10. The readout unit is switching the first high conversion gain readout process to a low light scene as enabled; the first low conversion gain readout process switches to a medium illumination scene as enabled; switch to a high illumination scene as enabled in the second low conversion gain readout process; The signal selection unit is In the first high conversion gain read process, a read reset signal and a read signal due to a first high conversion gain are held in the signal holding unit; In the first low conversion gain read process, a read reset signal and a read signal due to a first low conversion gain are held in the signal holding unit; In the second low conversion gain read process, a read signal and a read reset signal based on the second low conversion gain are held in the signal holding unit.

10. The solid-state imaging device according to claim 9.

11. The signal selection unit is After a predetermined period of time has elapsed since the exposure period began, when the voltage signal read from the conversion signal read unit is higher than a reference signal during a first low conversion gain read period of the first low conversion gain read process, a signal corresponding to the voltage signal is held in the signal holding unit as the first low conversion gain read reset signal; Next, in a first high conversion gain readout period of the first high conversion gain readout process, when the voltage signal read out from the conversion signal readout unit is higher than a reference signal, a signal corresponding to the voltage signal is held in the signal holding unit as the first high conversion gain readout reset signal; Then, in a second high conversion gain readout period of the first high conversion gain readout process following the first transfer period, when the voltage signal read out from the conversion signal readout unit is higher than a reference signal, a signal corresponding to the voltage signal is held in the signal holding unit as the first high conversion gain readout signal; Then, in a second high conversion gain readout period of the first low conversion gain readout process or a first low conversion gain readout period of the second low conversion gain readout process following the second transfer period, when the voltage signal read out from the conversion signal readout unit is lower than a reference signal, a signal corresponding to the voltage signal is held in the signal holding unit as the first low conversion gain readout signal or as the second low conversion gain readout signal.

10. The solid-state imaging device according to claim 9.

12. The signal selection unit is In a second low conversion gain readout period of the second low conversion gain readout process after a reset period of the floating diffusion and the storage capacitance element after a first low conversion gain readout period of the second low conversion gain readout process, when the voltage signal read out from the conversion signal readout unit is lower than a reference signal, a signal corresponding to the voltage signal is held in the signal holding unit as the second low conversion gain readout reset signal. The solid-state imaging device according to claim 11.

13. The signal holding unit is The voltage signal corresponds to the accumulated charge of the photoelectric conversion element transferred to the floating diffusion, and a sample-and-hold circuit is included which captures and holds the voltage signal as a pixel signal read out to the internal signal line by a sampling signal.

10. The solid-state imaging device according to claim 9.

14. The signal holding unit is a comparator that compares the voltage signal as the pixel signal read out to the internal signal line with a reference voltage, performs an analog-to-digital (AD) conversion process on the read voltage signal, and outputs a digitized comparison result signal; a memory for storing the comparison result signal by the comparator for the voltage signal corresponding to the accumulated charge of the photoelectric conversion element transferred to the floating diffusion. The solid-state imaging device according to claim 13.

15. a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading the accumulated charges at different conversion gains are arranged; a readout unit that reads out pixel signals from the pixels of the pixel unit in accordance with a conversion gain, The pixel is At least two first and second photoelectric conversion elements, each of which includes a photoelectric conversion region having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by the photoelectric conversion, are arranged adjacent to each other; one microlens that directs light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element; at least two first transfer elements and second transfer elements capable of individually transferring charges stored in the first photoelectric conversion element and the second photoelectric conversion element, respectively; a floating diffusion to which accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element are transferred through the first transfer element and the second transfer element, respectively; a first connection element connected to the floating diffusion; a first storage capacitance element capable of storing charge of the floating diffusion via the first connection element; the first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements; a first charge storage capacity that can be stored in the first photoelectric conversion element is smaller than a second charge storage capacity that can be stored in the second photoelectric conversion element; an overflow path portion capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion via the first transfer element can be formed in a charge transfer path portion extending from the first photoelectric conversion element to the floating diffusion; At least in a charge transfer path portion extending from the second photoelectric conversion element to the floating diffusion outer region, a charge discharge path portion capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region can be formed. Solid-state imaging device.

16. The pixel is a comparator that compares the voltage signal as a pixel signal read out to an internal signal line with a reference voltage, performs analog-to-digital (AD) conversion processing on the read voltage signal, and outputs a digitized comparison result signal; and two systems of memories that hold the comparison result signal by the comparator for the voltage signal corresponding to the accumulated charge of at least the first photoelectric conversion element and the second photoelectric conversion element transferred to the floating diffusion.

16. The solid-state imaging device according to claim 15.

17. The first photoelectric conversion element is Overflow charge accumulation and conversion gain switching within the pixel, select the readout mode according to the amount of light, and hold only one signal. An overflow path portion capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion is formed in a charge transfer path portion that extends from the first photoelectric conversion element to the floating diffusion via the first transfer element.

17. The solid-state imaging device according to claim 16.

18. The second photoelectric conversion element is A charge transfer path portion extending from the second photoelectric conversion element to the floating diffusion outer region is formed with a charge discharge path portion capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region.

18. The solid-state imaging device according to claim 17.

19. The first photoelectric conversion element and the second photoelectric conversion element are controlled by the readout unit. Charge accumulation operations are started simultaneously and in parallel. In the read operation, the first photoelectric conversion element is read, and then the second photoelectric conversion element is read.

20. The solid-state imaging device according to claim 18.

20. The pixel is the aperture ratio of the first photoelectric conversion element and the aperture ratio of the second photoelectric conversion element on the back surface side are the same; The charge storage portions of the first photoelectric conversion element and the second photoelectric conversion element on the front surface side have a first charge storage capacity of the first photoelectric conversion element that is larger than a second charge storage capacity of the second photoelectric conversion element.

20. The solid-state imaging device according to claim 19.

21. The pixel is one of the floating diffusions and one of the microlenses, the first photoelectric conversion element, the second photoelectric conversion element, and the third photoelectric conversion element and the fourth photoelectric conversion element are shared by four photoelectric conversion elements; Each of the first photoelectric conversion arrangement region, the second photoelectric conversion arrangement region, the third photoelectric conversion arrangement region, and the fourth photoelectric conversion arrangement region in the four photoelectric conversion elements is The impurity doped regions have the same shape, and The pixels are arranged in a square grid.

21. The solid-state imaging device according to claim 20.

22. The pixel is Under the control of the readout unit, During readout, the laser diode can operate in at least one of a first high conversion gain readout mode, a first low conversion gain readout mode, a second low conversion gain readout mode, and a time domain mode according to the conversion gain; In the first high conversion gain read mode, reading is performed with a first high conversion gain associated with the accumulated charge of the first photoelectric conversion element; In the first low conversion gain read mode, reading is performed with a first low conversion gain associated with the accumulated charge of the second photoelectric conversion element; In the second low conversion gain read mode, reading is performed with a second low conversion gain associated with the accumulated charges of the photoelectric conversion element, the floating diffusion, and the first storage capacitance element; In the time domain mode, reading is performed with a third low conversion gain associated with a charge equal to or greater than the accumulated charge of the photoelectric conversion element, the floating diffusion, and the first storage capacitance element.

22. The solid-state imaging device according to claim 21.

23. The pixel is A second connection element connected to the floating diffusion; a second storage capacitance element capable of storing charge of the floating diffusion via the second connection element, The pixel is Under the control of the readout unit, During readout, the readout device is operable in at least one of a first high conversion gain readout mode, a first medium conversion gain readout mode, a second low conversion gain readout mode, and a time domain mode according to the conversion gain; In the first high conversion gain read mode, reading is performed with a first high conversion gain associated with the accumulated charge of the first photoelectric conversion element; In the first intermediate conversion gain readout mode, the accumulated charge of the second photoelectric conversion element is read out with a first intermediate conversion gain associated with the accumulated charge of the floating diffusion and the second storage capacitance element; In the second low conversion gain read mode, reading is performed with a second low conversion gain associated with the accumulated charges of the photoelectric conversion element, the floating diffusion, and the first storage capacitance element; In the time domain mode, reading is performed with a third low conversion gain associated with a charge equal to or greater than the accumulated charge of the photoelectric conversion element, the floating diffusion, and the first storage capacitance element.

22. The solid-state imaging device according to claim 21.

24. In the pixel, a structure of a charge storage capacitance and a charge storage portion of one of the third photoelectric conversion element and the fourth photoelectric conversion element is equivalent to a structure of the first charge storage capacitance and the first charge storage portion of the first photoelectric conversion element; the other charge storage capacitance and the charge storage portion have structures equivalent to the second charge storage capacitance and the second charge storage portion of the second photoelectric conversion element, Photoelectric conversion elements having the same charge storage capacitance and charge storage portion structure are arranged adjacent to each other in the diagonal direction in the square array.

22. The solid-state imaging device according to claim 21.

25. The pixel is A second connection element connected to the floating diffusion; a second storage capacitance element capable of storing charge of the floating diffusion via the second connection element, In the pixel, A structure of a charge storage capacitance and a charge storage portion of one of the third photoelectric conversion element and the fourth photoelectric conversion element is equivalent to a structure of the first charge storage capacitance and the first charge storage portion of the first photoelectric conversion element, or a structure of a charge storage capacitance and a charge storage portion of the third photoelectric conversion element and the fourth photoelectric conversion element is equivalent to a structure of the first charge storage capacitance and the first charge storage portion of the first photoelectric conversion element; the other charge storage capacitance and the charge storage portion have structures equivalent to the second charge storage capacitance and the second charge storage portion of the second photoelectric conversion element, The second charge storage element is disposed within the region in which the first charge storage portion is disposed so as to be adjacent to the first charge storage portion.

22. The solid-state imaging device according to claim 21.

26. a pixel section in which pixels including at least a photoelectric conversion readout section are arranged; A readout unit that reads out pixel signals from the pixel unit, The photoelectric conversion readout unit is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charge stored in the photoelectric conversion element during a transfer period following the storage period; a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a storage capacitance element that is controlled to be connected or disconnected from the floating diffusion in accordance with a conversion gain; A conversion signal readout unit that amplifies and outputs the converted voltage signal with a conversion gain. A method for driving a solid-state imaging device, comprising: a first conversion gain read mode capable of reading out a signal corresponding to a first low conversion gain and a first high conversion gain associated with a capacitance of the floating diffusion and a storage capacitance of the storage capacitance element, and a full well capacity (FWC) of at least the floating diffusion of the floating diffusion and the photoelectric conversion element; a second conversion gain read mode capable of reading out a signal corresponding to at least a second low conversion gain associated with the capacitance of the floating diffusion and the storage capacitance of the storage capacitance element; The pixel is In the first conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge of the photoelectric conversion element are read out as pixel signals in accordance with the first low conversion gain and the first high conversion gain; In the second conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge of the photoelectric conversion element or the accumulated charge and overflow charge of the photoelectric conversion element are read out as pixel signals in accordance with at least the second low conversion gain; A voltage level of the first low conversion gain signal read out with the first low conversion gain is equal to a voltage level of the second low conversion gain signal read out with the second low conversion gain. A method for driving a solid-state imaging device.

27. A solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: a pixel section in which pixels including at least a photoelectric conversion readout section are arranged; A readout unit that reads out pixel signals from the pixel unit, The photoelectric conversion readout unit is a photoelectric conversion element that accumulates charges generated by photoelectric conversion during an accumulation period; a transfer element capable of transferring the charge stored in the photoelectric conversion element during a transfer period following the storage period; a floating diffusion to which the charge accumulated in the photoelectric conversion element is transferred through the transfer element; a reset element that discharges the accumulated charge of at least the floating diffusion to a reset potential; a storage capacitance element that is controlled to be connected or disconnected from the floating diffusion in accordance with a conversion gain; a conversion signal readout unit operable at least in a first conversion gain readout mode capable of reading out a signal corresponding to a first low conversion gain and a first high conversion gain associated with the capacitance of the floating diffusion, the storage capacitance of the storage capacitance element, and a full well capacity (FWC) of at least the floating diffusion of the floating diffusion and the photoelectric conversion element, and a second conversion gain readout mode capable of reading out a signal corresponding to at least a second low conversion gain associated with the capacitance of the floating diffusion and the storage capacitance of the storage capacitance element, and amplifying and outputting a voltage signal converted with the conversion gain; The pixel is In the first conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to accumulated charges of the photoelectric conversion element can be read out as a pixel signal in accordance with the first low conversion gain and the first high conversion gain; In the second conversion gain readout mode, a readout reset signal in a reset state and a readout signal corresponding to the accumulated charge of the photoelectric conversion element or the accumulated charge and overflow charge of the photoelectric conversion element can be read out as a pixel signal in accordance with at least the second low conversion gain, A voltage level of the first low conversion gain signal read out with the first low conversion gain is equal to a voltage level of the second low conversion gain signal read out with the second low conversion gain. electronic equipment.

28. a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading the accumulated charges at different conversion gains are arranged; a readout unit that reads out pixel signals from the pixels of the pixel unit in accordance with a conversion gain, The pixel is At least two first and second photoelectric conversion elements, each of which includes a photoelectric conversion region having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by the photoelectric conversion, are arranged adjacent to each other; one microlens that directs light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element; at least two first transfer elements and second transfer elements capable of individually transferring charges stored in the first photoelectric conversion element and the second photoelectric conversion element, respectively; a floating diffusion to which accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element are transferred through the first transfer element and the second transfer element, respectively; a first connection element connected to the floating diffusion; a first storage capacitance element capable of storing charge of the floating diffusion via the first connection element; The first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements. A method for manufacturing a solid-state imaging device, comprising the steps of: forming a first charge storage capacitance capable of storing charge in the first photoelectric conversion element to be smaller than a second charge storage capacitance capable of storing charge in the second photoelectric conversion element; an overflow path portion capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion through the first transfer element is formed in a charge transfer path portion extending from the first photoelectric conversion element to the floating diffusion; At least in a charge transfer path portion extending from the second photoelectric conversion element to the floating diffusion outer region, a charge discharge path portion capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region is formed. A method for manufacturing a solid-state imaging device.

29. A solid-state imaging device; an optical system that forms a subject image on the solid-state imaging device; The solid-state imaging device includes: a pixel section in which pixels capable of accumulating charges generated by photoelectric conversion and reading the accumulated charges at different conversion gains are arranged; a readout unit that reads out pixel signals from the pixels of the pixel unit in accordance with a conversion gain, The pixel is At least two first and second photoelectric conversion elements, each of which includes a photoelectric conversion region having a photoelectric conversion function of receiving incident light and performing photoelectric conversion and a charge accumulation function of accumulating charges generated by the photoelectric conversion, are arranged adjacent to each other; one microlens that directs light to at least the first photoelectric conversion region of the first photoelectric conversion element and the second photoelectric conversion region of the second photoelectric conversion element; at least two first transfer elements and second transfer elements capable of individually transferring charges stored in the first photoelectric conversion element and the second photoelectric conversion element, respectively; a floating diffusion to which accumulated charges of the first photoelectric conversion element and the second photoelectric conversion element are transferred through the first transfer element and the second transfer element, respectively; a first connection element connected to the floating diffusion; a first storage capacitance element capable of storing charge of the floating diffusion via the first connection element; the first floating diffusion is shared by a plurality of the photoelectric conversion elements and a plurality of the transfer elements; a first charge storage capacity that can be stored in the first photoelectric conversion element is smaller than a second charge storage capacity that can be stored in the second photoelectric conversion element; an overflow path portion capable of overflowing a charge signal from the first photoelectric conversion element to the floating diffusion via the first transfer element can be formed in a charge transfer path portion extending from the first photoelectric conversion element to the floating diffusion; At least in a charge transfer path portion extending from the second photoelectric conversion element to the floating diffusion outer region, a charge discharge path portion capable of discharging a charge signal from the second photoelectric conversion element to the floating diffusion outer region can be formed. electronic equipment.

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