Light-emitting diode display panel and display unit using the same

Abstract

To provide reliable electrical connection between pads of a great number of LEDs and circuit boards for display.SOLUTION: A display panel includes a circuit board having a pad on a top face, and a plurality of pixel regions aligned on the circuit board. Each of the pixel regions includes: a first LED laminated layer disposed on the circuit board; a first bonding layer disposed between the first LED laminated layer and the circuit board; a second LED laminated layer disposed on the first LED laminated layer; a third LED laminated layer disposed on the second LED laminated layer; a first through via that penetrates the first LED laminated layer and the first bonding layer; a second through via that penetrates the second LED laminated layer; and a third through via that penetrates the third LED laminated layer. The first through via penetrates the first LED laminated layer and the first bonding layer, and is connected to a pad on circuit board.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present disclosure relates to an LED display panel and a display device having the same. [Background technology]

[0002] Light emitting diodes are inorganic light sources and are used in a variety of fields such as display devices, vehicle lamps, general lighting, etc. Light emitting diodes have advantages such as a long life, low power consumption, and fast response speed, and are rapidly replacing existing light sources.

[0003] Meanwhile, conventional light emitting diodes have been mainly used as backlight sources in display devices, but in recent years, LED displays that directly display images using light emitting diodes have been developed.

[0004] A display device generally realizes various colors using a mixture of blue, green, and red colors. The display device includes a plurality of pixels to realize various images, and each pixel includes blue, green, and red sub-pixels, and the color of a particular pixel is determined by the colors of these sub-pixels, and an image is realized by a combination of these pixels.

[0005] LEDs can emit light of various colors depending on the material they are made of, and individual LED chips emitting blue, green and red can be arranged on a two-dimensional plane to provide a display device.

[0006] Conventional LEDs used in large light-emitting displays are packaged and then aligned in pixel units, so the individual packages are mounted on a circuit board. However, displays of small electronic products such as smart watches, mobile phones, VR headsets, AR glasses, and TVs require micro LEDs, which are smaller than conventional LED packages, to achieve clear image quality.

[0007] Small LEDs are difficult to handle and therefore difficult to mount individually on a circuit board. For this reason, a method is being researched in which multiple LEDs are formed using a semiconductor layer grown on a substrate and then collectively transferred onto a display circuit board in accordance with pixel spacing. However, while transferring multiple LEDs collectively, some LEDs may become defective. In particular, due to the difference in thermal expansion coefficient between the display circuit board and the support substrate that supports the LEDs, some of the transferred LEDs may not be electrically connected to the pads on the display circuit board. In this case, it is necessary to replace the defective LEDs with good LEDs individually, but because the LEDs are small, it is extremely difficult to replace the defective LEDs. Therefore, a display device with a new structure that can electrically and stably connect LEDs to pads on a circuit board is required.

[0008] Meanwhile, since the subpixels are arranged on a two-dimensional plane, the area occupied by one pixel including the blue, green and red subpixels is relatively large. Therefore, in order to arrange the subpixels within the limited area, it is necessary to reduce the area of ​​each LED chip. However, reducing the size of the LED chip makes it difficult to mount the LED chip and also reduces the light-emitting area. Summary of the Invention [Problem to be solved by the invention]

[0009] The problem that this disclosure seeks to solve is providing reliable electrical connections between multiple LEDs for a display and pads on a circuit board.

[0010] Still another problem to be solved by the present disclosure is to provide an LED display panel that does not require transferring LEDs to a circuit board, and a display device having the same.

[0011] Another problem to be solved by the present disclosure is to provide an LED display panel capable of increasing the area of ​​each sub-pixel within a limited pixel area, and a method for manufacturing a display device having the same. [Means for solving the problem]

[0012] A display panel according to one embodiment of the present disclosure includes a circuit board having a pad on an upper surface thereof; and a plurality of pixel areas aligned on the circuit board, each of the pixel areas including a first LED stack disposed on the circuit board; a first bonding layer disposed between the first LED stack and the circuit board; a second LED stack disposed on the first LED stack; a third LED stack disposed on the second LED stack; a first through via extending through the first LED stack and first bonding layer; a second through via extending through the second LED stack; and a third through via extending through the third LED stack, the first through via extending through the first LED stack and first bonding layer and connected to a pad on the circuit board.

[0013] A display device according to an embodiment of the present disclosure includes the display panel. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic perspective view illustrating a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 1 is a schematic plan view illustrating a display panel according to an embodiment of the present disclosure. [Figure 3A] 1 is a schematic plan view showing an enlarged partial area of ​​a display panel according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic cross-sectional view taken along the cut line AA' of FIG. 3A. [Figure 3C] FIG. 3B is a schematic cross-sectional view taken along the cut line BB' of FIG. 3A. [Figure 3D]FIG. 3B is a schematic cross-sectional view taken along the cut line CC' of FIG. 3A. [Figure 4A] 1 is a schematic perspective view for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 4B] 11 is a schematic perspective view for explaining a method for manufacturing a display panel according to still another embodiment of the present disclosure. FIG. [Figure 5A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 5B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 6A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 6B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 6C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 7A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 7B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 8A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 8B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 9A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 9B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 10A]1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 10B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 11A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 11B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 12A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 12B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 12C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 13A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 13B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 13C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 14A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 14B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 15A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 15B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 16A]1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 16B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 17A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 17B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 18A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 18B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 18C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 19A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 19B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 20A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 20B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 21A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 21B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 22A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 22B]1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 22C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 22D] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 23A] 13 is a schematic plan view showing an enlarged view of a portion of a display panel according to still another embodiment of the present disclosure. FIG. [Figure 23B] FIG. 23B is a schematic cross-sectional view taken along the cut line DD' of FIG. 23A. [Figure 23C] FIG. 3B is a schematic cross-sectional view taken along the cut line EE' of FIG. 3A. [Figure 23D] FIG. 3B is a schematic cross-sectional view taken along the cut line FF' of FIG. 3A. [Figure 24A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 24B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 25A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 25B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 26A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 26B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 26C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 27A]1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 27B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 27C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 28A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 28B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 29A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 29B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 29C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 30A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 30B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 30C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 31A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 31B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 31C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 32A]1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 32B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 33A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 33B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 33C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 34A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 34B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 34C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 35A] 1A to 1C are schematic plan views for explaining a manufacturing method of a display panel according to an embodiment of the present disclosure. [Figure 35B] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 35C] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a display panel according to an embodiment of the present disclosure. [Figure 35D] 11A to 11C are schematic cross-sectional views illustrating a method for manufacturing a display panel according to still another embodiment of the present disclosure. [Figure 36A] 11 is a schematic enlarged cross-sectional view showing a partial area of ​​a display panel according to still another embodiment of the present disclosure. FIG. [Figure 36B] 11 is a schematic enlarged cross-sectional view showing a partial area of ​​a display panel according to still another embodiment of the present disclosure. FIG. [Figure 36C] 11 is a schematic enlarged cross-sectional view showing a partial area of ​​a display panel according to still another embodiment of the present disclosure. FIG. [Figure 37] 11 is a schematic enlarged cross-sectional view showing a partial area of ​​a display panel according to still another embodiment of the present disclosure. FIG. [Figure 38] 11 is a schematic enlarged cross-sectional view showing a partial area of ​​a display panel according to still another embodiment of the present disclosure. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to fully convey the concept of the present disclosure to those skilled in the art to which the present disclosure pertains. Therefore, the present disclosure is not limited to the embodiments described below, and may be embodied in other forms. In addition, in the drawings, the width, length, thickness, and the like of components may be exaggerated for convenience. In addition, when a component is described as being "on" or "above" another component, this includes not only the case where each part is "directly on" or "directly above" the other part, but also the case where another component is interposed between each component and the other component. The same reference numerals refer to the same components throughout the specification.

[0016] A display panel according to one embodiment of the present disclosure includes a circuit board having a pad on an upper surface thereof; and a plurality of pixel areas aligned on the circuit board, each of the pixel areas including a first LED stack disposed on the circuit board, a first bonding layer disposed between the first LED stack and the circuit board, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, a first through via extending through the first LED stack and the first bonding layer, a second through via extending through the second LED stack, and a third through via extending through the third LED stack, the first through via extending through the first LED stack and the first bonding layer and connected to a pad on the circuit board.

[0017] By stacking the first to third LED stacks on top of each other, the light emitting area of ​​each sub-pixel can be increased without increasing the pixel area.

[0018] In addition, since the first through via penetrates the first LED stack and is connected to the pad on the circuit board, the first through via can be formed on the circuit board, and therefore there is no need to transfer the light emitting element onto the circuit board using a bonding pad such as a bump pad, which solves the reliability problem that occurs in the light emitting element mounting process.

[0019] The display panel may further include a reflective layer disposed between the first LED stack and the circuit board, the reflective layer may be spaced apart from the pads and may be located within an area surrounded by the pads on the circuit board below the first LED stack.

[0020] Further, the display panel may further include a second bonding layer disposed between the first LED stack and the second LED stack; and a third bonding layer disposed between the second LED stack and the third LED stack, wherein the second through via may extend through the second bonding layer and the third through via may extend through the third bonding layer.

[0021] The display panel may further include first connection pads disposed between the first LED stack and the second LED stack, one of the first connection pads electrically connecting one of the first through vias to a first conductive type semiconductor layer of the first LED stack, and another of the first connection pads electrically connecting another of the first through vias to a second conductive type semiconductor layer of the first LED stack.

[0022] The display panel may also include a first ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the first LED stack, and one of the first connection pads may be electrically connected to the first conductive type semiconductor layer of the first LED stack through the first ohmic electrode.

[0023] In one embodiment, the display panel may further include a first transparent electrode in ohmic contact with the second conductive type semiconductor layer of the first LED stack between the first LED stack and the second LED stack, and another one of the first connection pads may be electrically connected to the second conductive type semiconductor layer of the first LED stack through the first transparent electrode.

[0024] In another embodiment, the display panel may further include a lower electrode in ohmic contact with the second conductive type semiconductor layer of the first LED stack between the first LED stack and the circuit board, and another one of the first connection pads may be electrically connected to the second conductive type semiconductor layer of the first LED stack through the lower electrode.

[0025] The bottom electrode may include a reflective layer.

[0026] Further, the first through via may include a first through via that penetrates the first LED stack and is electrically connected to the lower electrode, and another one of the first connection pads may be connected to the first through via that is electrically connected to the lower electrode.

[0027] Meanwhile, the display panel may further include second connection pads disposed between the second LED stack and the third LED stack, one of the second connection pads electrically connecting one of the second through vias to the first conductive type semiconductor layer of the second LED stack, and the other of the second connection pads electrically connecting another of the second through vias to the second conductive type semiconductor layer of the second LED stack.

[0028] The display panel may also include a second ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the second LED stack, and one of the second connection pads may be electrically connected to the first conductive type semiconductor layer of the second LED stack through the second ohmic electrode.

[0029] The display panel may further include a second transparent electrode in ohmic contact with the second conductive type semiconductor layer of the second LED stack, and another one of the second connection pads may be electrically connected to the second conductive type semiconductor layer of the second LED stack through the second transparent electrode.

[0030] In one embodiment, the second transparent electrode can be disposed between the second LED stack and a third LED stack.

[0031] In another embodiment, the second transparent electrode can be disposed between the first LED stack and the second LED stack, the second through via can include a second through via that penetrates the second LED stack and is electrically connected to the second transparent electrode, and another one of the second connection pads can be connected to the second through via that is electrically connected to the second transparent electrode.

[0032] The display panel may further include third connection pads arranged on the third LED stack, one of the third connection pads electrically connecting one of the third through vias to a first conductive type semiconductor layer of the third LED stack, and the other of the third connection pads electrically connecting the other of the third through vias to a second conductive type semiconductor layer of the third LED stack.

[0033] The display panel may further include a third ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the third LED stack, and one of the third connection pads may be electrically connected to the first conductive type semiconductor layer of the third LED stack through the third ohmic electrode.

[0034] The display panel may further include a third transparent electrode in ohmic contact with the second conductive type semiconductor layer of the third LED stack, and another one of the third connection pads may be electrically connected to the second conductive type semiconductor layer of the third LED stack through the third transparent electrode.

[0035] In one embodiment, the third transparent electrode may be disposed on the third LED stack.

[0036] In another embodiment, the third transparent electrode can be disposed between the second LED stack and a third LED stack, the third through via includes a third through via that penetrates the third LED stack and is electrically connected to the third transparent electrode, and another one of the third connection pads can be connected to a third through via that is electrically connected to the third transparent electrode.

[0037] The display panel may further include a lower insulating layer disposed between the first LED stack and the second LED stack; an intermediate insulating layer disposed between the second LED stack and the third LED stack; and an upper insulating layer disposed on the third LED stack, and the lower insulating layer, the intermediate insulating layer and the upper insulating layer may be disposed within upper regions of the first LED stack, the second LED stack and the third LED stack, respectively.

[0038] The first to third LED stacks can be driven independently, and light generated in the first LED stack can be emitted to the outside through the second LED stack and the third LED stack, and light generated in the second LED stack can be emitted to the outside through the third LED stack.

[0039] In one embodiment, the circuit board may include active circuits for active matrix driving.

[0040] A display device according to an embodiment of the present disclosure includes a display panel, which is the display panel described above.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0042] FIG. 1 is a schematic perspective view for explaining a display device according to an embodiment of the present disclosure.

[0043] The light-emitting element of the present disclosure is particularly, but not limited to, used in a VR display device such as a smart watch 1000a, a VR headset 1000b, or an AR display device such as an augmented reality glasses 1000c. In particular, the pixel pitch of an AR display device is very narrow, about 10 um or less, and the light-emitting element of the present disclosure is suitable for solving problems that occur in a display device having pixels with such a narrow pitch. However, the light-emitting element of the present disclosure is not limited to a display device having pixels with a narrow pitch, but can also be applied to a display device having pixels with a relatively wider pitch.

[0044] Meanwhile, a display panel for implementing an image is mounted in the display device. Fig. 2 is a schematic plan view for illustrating a display panel 1000 according to an embodiment of the present disclosure, Fig. 3A is a plan view showing an enlarged view of two pixel regions indicated by dotted lines in Fig. 2 for illustrating the display panel 1000 according to an embodiment of the present disclosure, and Figs. 3B, 3C, and 3D are cross-sectional views taken along the cut lines A-A', B-B', and C-C' in Fig. 3A, respectively.

[0045] 2, a display panel 1000 includes a circuit board 11 and a plurality of pixel areas PA. A light-emitting element 100 is disposed in each pixel area PA.

[0046] The circuit board 11 may include circuits for passive matrix driving or active matrix driving. In one embodiment, the circuit board 11 may include wiring and resistors therein. In another embodiment, the circuit board 11 may include wiring, transistors, and capacitors. In particular, in this embodiment, the circuit board 11 may include active circuits such as transistors for active matrix driving.

[0047] The circuit board 11 may also have pads 11a, 11b, 11c, and 11d on its top surface to allow electrical connection to circuitry disposed therein. Each light emitting element 100 is electrically connected to the circuit board 11 through the pads 11a, 11b, 11c, and 11d.

[0048] In this embodiment, the pixel area PA, i.e., the interval between the light emitting elements 100, may be smaller than the width of one light emitting element. In particular, the interval between the light emitting elements 100 may be smaller than 1 / 2 the width of the light emitting element. For example, the width of the light emitting element 100 may be 7 um or less, and the interval between the light emitting elements 100 may be 3 um or less.

[0049] 3A, 3B, 3C and 3D, a display panel 1000 includes a light-emitting element 100 disposed on a circuit board 11, a first LED stack 23, a second LED stack 33, a third LED stack 43, a first transparent electrode 25, a second transparent electrode 35, a third transparent electrode 45, a first ohmic electrode 123, a second ohmic electrode 133, a third ohmic electrode 143, a first bonding layer 20, a second bonding layer 2 ... second LED stack 33, a first LED stack 23, a second LED stack 33, a third LED stack 43, a first LED stack 23, a second LED stack 33, a first LED stack 24, a second LED stack 33, a first LED stack 25, a second LED stack 35, a third LED stack 45, a first LED stack 26, a second LED stack 27, a first LED stack 28, a second LED stack 36, a second LED stack 37, a first LED stack 29, a second LED stack 40, a first LED stack 29, a second LED stack 41, a first LED stack 29, a second LED stack 42, a first LED stack 29, a second LED stack 43, a first LED stack 29, a second LED stack 42, a first LED stack 29, a second LED stack 43, a first LED stack 29, a second LED stack 43, a first LED stack 29, a second LED stack 43, a first LED stack 29, a second LED stack 43, a first 30, third bonding layer 40, lower insulating layer 125, middle insulating layer 135, upper insulating layer 145, first sidewall insulating layer 127, second sidewall insulating layer 137, third sidewall insulating layer 147, first through via 129, second through via 139, third through via 149, first connection pads 131a, 131b, 131c, 131d, second connection pads 141a, 141b, 141c, and third connection pads 151a, 151b.

[0050] The circuit board 11 may include active or passive circuits as described above, and may include pads 11a, 11b, 11c, and 11d on the upper surface. At least four pads 11a, 11b, 11c, and 11d may be disposed in the lower region of each light-emitting element 100. Here, the first pad 11a is a common pad electrically connected to the first to third LED stacks 23, 33, and 43, the second pad 11b is an individual pad electrically connected to the third LED stack 43, the third pad 11c is an individual pad electrically connected to the second LED stack 33, and the fourth pad 11d is an individual pad electrically connected to the first LED stack 23. The first to third LED stacks 23, 33, and 43 can be driven independently using the common pad 11a and the individual pads 11b, 11c, and 11d. In one embodiment, the first pad 11a may be electrically connected in common to the first conductive type semiconductor layers of the first to third LED stacks 23, 33, 43 as a common pad, and the second to fourth pads 11b, 11c, 11d may be individually and electrically connected to the second conductive type semiconductor layers of the first to third LED stacks 23, 33, 43. In another embodiment, the first pad 11a may be electrically connected in common to the second conductive type semiconductor layers of the first to third LED stacks 23, 33, 43 as a common pad, and the second to fourth pads 11b, 11c, 11d may be individually and electrically connected to the first conductive type semiconductor layers of the first to third LED stacks 23, 33, 43. In the following, an example will be described in which the first pad 11a is commonly connected to the first conductive type semiconductor layers of the first to third LED stacks 23, 33, and 43, but a person skilled in the art should be able to understand that the first pad 11a can also be commonly connected to the second conductive type semiconductor layers of the first to third LED stacks 23, 33, and 43.

[0051] Furthermore, the circuit board 11 may further include a reflective layer 13 in the area between the light emitting element 100 and the circuit board 11. The reflective layer 13 may include a reflective metal layer such as, but not limited to, Al, Ag, or Au, and may include, for example, a distributed Bragg reflector. In one embodiment, the reflective layer 13 may be located in the area surrounded by the pads 11a, 11b, 11c, and 11d under the first LED stack 23.

[0052] The light emitting element 100 is disposed within the pixel region PA. Meanwhile, in the embodiment of the present disclosure, the first to third LED stacks 23, 33, 43 are stacked vertically. Although the LED stacks 23, 33, 43 are grown on different growth substrates, in the embodiment of the present disclosure, the growth substrates do not remain in the final light emitting element 100 but are all removed. Thus, the light emitting element 100 does not include a growth substrate. However, the present disclosure is not necessarily limited thereto, and at least one growth substrate may be included.

[0053] The first LED stack 23, the second LED stack 33 and the third LED stack 43 each include a first conductive type semiconductor layer 23a, 33a or 43a, a second conductive type semiconductor layer 23b, 33b or 43b and an active layer (not shown) interposed therebetween. The active layer may have a multiple quantum well structure.

[0054] The first LED stack 23 is disposed on the circuit board 11, the second LED stack 33 is disposed on the first LED stack 23, and the third LED stack 43 is disposed on the second LED stack 33. Light generated in the first to third LED stacks 23, 33, and 43 is finally emitted to the outside through the third LED stack 43.

[0055] In one embodiment, the first to third LED stacks 23, 33, and 43 may emit light with longer wavelengths as they are closer to the circuit board 11. For example, the first LED stack 23 may be an inorganic light emitting diode that emits red light, the second LED stack 33 may be an inorganic light emitting diode that emits green light, and the third LED stack 43 may be an inorganic light emitting diode that emits blue light. The first LED stack 23 may include an AlGaInP-based well layer, the second LED stack 33 may include an AlGaInP-based or AlGaInN-based well layer, and the third LED stack 43 may include an AlGaInN-based well layer.

[0056] In another embodiment, the second LED stack 33 may emit light at a shorter wavelength than the third LED stack 43. For example, the second LED stack 33 may be an inorganic light emitting diode that emits blue light, and the third LED stack 43 may be an inorganic light emitting diode that emits green light.

[0057] The first conductive type semiconductor layer 23a, 33a, 43a of each of the LED stacks 23, 33, and 43 may be an n-type semiconductor layer, and the second conductive type semiconductor layer 23b, 33b, 43b may be a p-type semiconductor layer. In this embodiment, the bottom surfaces of the first to third LED stacks 23, 33, and 43 are illustrated and described as being n-type semiconductor layers, but the present disclosure is not necessarily limited to this.

[0058] Meanwhile, the first LED stack 23, the second LED stack 33 and the third LED stack 43 may have through holes, and the first to third through vias 129, 139, 149 may be formed in the through holes. The first to third through vias 129, 139, 149 may be insulated from the LED stacks 23, 33, 43 by the first to third sidewall insulating layers 127, 137, 147, respectively, in the through holes.

[0059] In this embodiment, the surfaces of the first to third LED stacks 23, 33, 43 may be textured to improve light extraction efficiency. In particular, it is preferable that the surfaces of the first conductive type semiconductor layers 23a, 33a, 43a are textured. Furthermore, in order to improve light extraction from the first LED stack 23, the surface of the second conductive type semiconductor layer 23b may also be textured.

[0060] In this embodiment, the first LED stack 23, the second LED stack 33, and the third LED stack 43 may overlap and have light-emitting areas of approximately similar size. Furthermore, in each of the LED stacks 23, 33, and 43, the first conductive type semiconductor layers 23a, 33a, and 43a may have areas of approximately the same size as the second conductive type semiconductor layers 23b, 33b, and 43b, respectively. However, in the first to third LED stacks 23, 33, and 43, in order to form the ohmic electrodes 123, 133, and 143, a part of the second conductive type semiconductor layers 23b, 33b, and 43b is etched to expose the first conductive type semiconductor layers 23a, 33a, and 43a, so that the first conductive type semiconductor layers 23a, 33a, and 43a may have areas slightly larger than the second conductive type semiconductor layers 23b, 33b, and 43b.

[0061] The first transparent electrode 25 is disposed between the first LED stack 23 and the second LED stack 33. The first transparent electrode 25 is in ohmic contact with the second conductive type semiconductor layer 23b of the first LED stack 23 and transmits light generated in the first LED stack 23. The first transparent electrode 25 can be formed using a transparent oxide layer or a metal layer, such as tin oxide SnO2, indium oxide InO2, zinc oxide ZnO, indium tin oxide ITO, indium zinc oxide IZO, and indium tin zinc oxide ITZO.

[0062] Meanwhile, the second transparent electrode 35 is in ohmic contact with the second conductive type semiconductor layer 33b of the second LED stack 33. As shown, the second transparent electrode 35 may be in contact with the top surface of the second LED stack 33 between the second LED stack 33 and the third LED stack 43. For example, the second transparent electrode 35 may be formed of a metal layer or a conductive oxide layer that is transparent to red and green light.

[0063] Also, the third transparent electrode 45 is in ohmic contact with the second conductive type semiconductor layer 43b of the third LED stack 43. The third transparent electrode 45 may be located between the second LED stack 33 and the third LED stack 43, and contacts the top surface of the third LED stack 43. The third transparent electrode 45 may be formed of, for example, a metal layer or a conductive oxide layer transparent to red, green, and blue light. The first transparent electrode 25, the second transparent electrode 35, and the third transparent electrode 45 may be in ohmic contact with the p-type semiconductor layer of each LED stack 23, 33, and 43 to help residual dispersion. Examples of the conductive oxide layer used for the second and third transparent electrodes 35 and 45 include SnO2, InO2, ITO, ZnO, IZO, ITZO, and the like.

[0064] The first ohmic electrode 123 is in ohmic contact with the first conductive type semiconductor layer 23a. As shown in Fig. 3B, the first ohmic electrode 123 may be in ohmic contact with the first conductive type semiconductor layer 23a exposed through the first transparent electrode 25 and the second conductive type semiconductor layer 23b. The first ohmic electrode 123 may include an alloy containing Au, for example, AuGe or AuTe.

[0065] The second ohmic electrode 133 is in ohmic contact with the first conductive type semiconductor layer 33a. The second ohmic electrode 133 can be in ohmic contact with the first conductive type semiconductor layer 33a exposed through the second transparent electrode 35 and the second conductive type semiconductor layer 33b. The second ohmic electrode 133 can include an ohmic metal such as Ti, Cr, Ni, or Al.

[0066] The third ohmic electrode 143 is in ohmic contact with the first conductive type semiconductor layer 43a. The third ohmic electrode 143 may be in ohmic contact with the first conductive type semiconductor layer 43a exposed through the third transparent electrode 45 and the second conductive type semiconductor layer 43b. The third ohmic electrode 143 may include an ohmic metal such as Ti, Cr, Ni, or Al.

[0067] The first to third ohmic electrodes 123, 133, 143 may be arranged to overlap each other in the vertical direction. This can reduce loss of light generated in the first to third LED stacks 23, 33, 43 due to blocking by the first to third ohmic electrodes 123, 133, 143. However, the present disclosure is not limited to this, and the first to third ohmic electrodes 123, 133, 143 may be spaced apart from each other in the horizontal direction.

[0068] On the other hand, the first to third ohmic electrodes 123, 133, 143 are electrically connected to the common pad 11a, and therefore can be disposed closer to the common pad 11a than the individual pads 11b, 11c, 11d.

[0069] The lower insulating layer 125 may cover the first transparent electrode 25 and the first ohmic electrode 123. The lower insulating layer 125 may be located on the upper part of the first conductive type semiconductor layer 23a and may cover the side surface of the first conductive type semiconductor layer 23a and the side surface of the second conductive type semiconductor layer 23b. Meanwhile, the lower insulating layer 125 may have an opening for exposing the first ohmic electrode 123, and may also have an opening for exposing the first transparent electrode 25.

[0070] The intermediate insulating layer 135 can cover the second transparent electrode 35 and the second ohmic electrode 133. The intermediate insulating layer 135 is located on the upper part of the first conductive type semiconductor layer 33a and can cover the side surface of the first conductive type semiconductor layer 33a and the side surface of the second conductive type semiconductor layer 33b. Meanwhile, the intermediate insulating layer 135 can have an opening for exposing the second ohmic electrode 133, and can also have an opening for exposing the second transparent electrode 35.

[0071] The upper insulating layer 145 may cover the third transparent electrode 45 and the third ohmic electrode 143. The upper insulating layer 145 may be located on the upper portion of the first conductive type semiconductor layer 43a and may cover the side surface of the first conductive type semiconductor layer 43a and the side surface of the second conductive type semiconductor layer 43b. The upper insulating layer 145 may have an opening for exposing the third ohmic electrode 143, and may also have an opening for exposing the third transparent electrode 45.

[0072] The lower insulating layer 125, the intermediate insulating layer 135, and the upper insulating layer 145 are each made of, for example, SiO 2 In or Si 3 N 4 It can be formed by the following:

[0073] The first bonding layer 20 bonds the first LED stack 23 to the circuit board 11. In particular, the first bonding layer 20 can bond the first conductive type semiconductor layer 23a of the first LED stack 23 to the circuit board 11. The first bonding layer 20 may be located only in a lower region of the first LED stack 23, but is not limited thereto, and may also remain in a region between the light emitting elements 100.

[0074] The second bonding layer 30 bonds the second LED stack 33 to the first LED stack 23. The second bonding layer 30 may bond between the lower insulating layer 125 and the first conductivity type semiconductor layer 33a. The second bonding layer 30 may also be disposed in the areas between the light emitting elements 100.

[0075] The third bonding layer 40 bonds the third LED stack 43 to the first LED stack 23. The third bonding layer 40 may bond between the intermediate insulating layer 135 and the first conductivity type semiconductor layer 43a. The third bonding layer 40 may also be disposed in the areas between the light emitting elements 100.

[0076] The first bonding layer 20, the second bonding layer 30, or the third bonding layer 40 may be formed of a transparent organic layer or a transparent inorganic layer. Examples of the organic layer include SU8, poly(methylmethacrylate) (PMMA), polyimide, parylene, and benzocyclobutene (BCB), and examples of the inorganic layer include Al. 2 O 3 , SiO 2 , SiN x For example, the first bonding layer 20, the second bonding layer 30, or the third bonding layer 40 may be formed of spin-on-glass (SOG).

[0077] The first through via 129 penetrates the first LED stack 23. The first through via 129 can also penetrate the lower insulating layer 125, the first transparent electrode 25, and the first bonding layer 20, and can be electrically connected to the common pad 11a and the individual pads 11b, 11c, and 11d, respectively. The first through via 129 can include, for example, a Cu plating layer. The first through via 129 can also include a cap layer on the top to prevent oxidation of Cu, or the Cu layer can be treated with ENIG, ENEPIG, or the like.

[0078] The first sidewall insulating layer 127 insulates the first through via 129 from the first LED stack 23 within the through hole. The first sidewall insulating layer 127 covers the sidewall of the through hole and has an opening that exposes the floor of the through hole. The first sidewall insulating layer 127 can be formed using, for example, a chemical vapor deposition technique or an atomic layer deposition technique, and can be, for example, Al 2 O 3 , SiO 2 , SiN xIt can be formed by the following:

[0079] The first connection pads 131a, 131b, 131c, 131d may be located between the first LED stack 23 and the second LED stack 33. The first connection pads 131a, 131b, 131c, 131d may be disposed on the lower insulating layer 125 and may be covered with the second bonding layer 30.

[0080] 3B, the first connection pad 131a electrically connects the first through via 129 electrically connected to the common pad 11a to the first ohmic electrode 123. The first connection pad 131d electrically connects the first through via 129 electrically connected to the pad 11d to the first transparent electrode 25 exposed through the opening in the lower insulating layer 125 as shown in FIG.

[0081] On the other hand, the first connection pads 131b and 131c cover and are electrically connected to the first through vias 129 which are electrically connected to the pads 11c and 11d, respectively.

[0082] The second through via 139 penetrates the second LED stack 33. The second through via 139 can also penetrate the intermediate insulating layer 135, the second transparent electrode 35, and the second bonding layer 30, and can be electrically connected to the first connection pads 131a, 131b, and 131c, respectively. The second through via 139 can include, for example, a Cu plating layer. The second through via 139 can also include a cap layer on the upper stage to prevent oxidation of Cu, or the Cu layer can be treated with ENIG, ENEPIG, or the like.

[0083] The second sidewall insulating layer 137 insulates the second through via 139 from the second LED stack 33 within the through hole. The second sidewall insulating layer 137 covers the sidewall of the through hole and has an opening that exposes the floor of the through hole, e.g., the first connection pads 131a, 131b, 131c. The second sidewall insulating layer 137 can be formed, for example, using a chemical vapor deposition technique or an atomic layer deposition technique, and can be, for example, Al 2 O 3 , SiO 2 , SiNx It can be formed by the following:

[0084] The second connection pads 141a, 141b, 141c can be located between the second LED stack 33 and the third LED stack 43. The second connection pads 141a, 141b, 141c can be disposed on the intermediate insulating layer 135 and can be covered with the third bonding layer 40.

[0085] 3B, the second connection pad 141a electrically connects the second through via 139 electrically connected to the first connection pad 131a to the second ohmic electrode 133. The second connection pad 141c electrically connects the second through via 139 electrically connected to the first connection pad 131c to the second transparent electrode 35 exposed through the opening of the intermediate insulating layer 135 as shown in FIG.

[0086] On the other hand, the second connection pad 141b covers and is electrically connected to the second through via 139 which is electrically connected to the first connection pad 131b.

[0087] The third through via 149 penetrates the third LED stack 43. The third through via 149 can also penetrate the upper insulating layer 145, the third transparent electrode 45, and the third bonding layer 40, and can be electrically connected to the second connection pads 141a and 141b, respectively. The third through via 149 can include, for example, a Cu plating layer. The third through via 149 can also include a cap layer on the upper stage to prevent oxidation of Cu, or the Cu layer can be treated with ENIG, ENEPIG, or the like.

[0088] The third sidewall insulating layer 147 insulates the third through via 149 from the third LED stack 43 within the through hole. The third sidewall insulating layer 147 covers the sidewall of the through hole and has an opening that exposes the floor of the through hole, e.g., the second connection pads 141a, 141b. The third sidewall insulating layer 147 can be formed, for example, using a chemical vapor deposition technique or an atomic layer deposition technique, and can be, for example, Al 2 O 3 , SiO 2 , SiN x It can be formed by the following:

[0089] The third connection pads 151a, 151b can be located on the third LED stack 43. Further, the third connection pads 151a, 151b can be disposed on the top insulating layer 145.

[0090] 3B, the third connection pad 151a electrically connects the third through via 149 electrically connected to the second connection pad 141a to the third ohmic electrode 143. The third connection pad 151b electrically connects the third through via 149 electrically connected to the second connection pad 141b to the third transparent electrode 45 exposed through the opening in the upper insulating layer 145 as shown in FIG.

[0091] The first to third through vias 129, 139, and 149 can be formed by using a chemical mechanical polishing technique. For example, a seed layer is formed, the through holes are filled by using a plating technique, and then the metal layers on the insulating layers 125, 135, and 145 are removed by using a chemical mechanical polishing technique, thereby forming the through vias.

[0092] According to this embodiment, the first conductive type semiconductor layer 23a of the first LED stack 23, the first conductive type semiconductor layer 33a of the second LED stack 33, and the first conductive type semiconductor layer 43a of the third LED stack 43 are all electrically connected to the common pad 11a. Meanwhile, the second conductive type semiconductor layer 23b of the first LED stack 23 is electrically connected to the individual pad 11d, the second conductive type semiconductor layer 33b of the second LED stack 33 is electrically connected to the individual pad 11c, and the second conductive type semiconductor layer 43b of the third LED stack 43 is electrically connected to the individual pad 11b. Thus, the first LED stack 23 can be driven by supplying power to the pads 11a and 11d, the second LED stack 33 can be driven by supplying power to the pads 11a and 11c, and the third LED stack 43 can be driven by supplying power to the pads 11a and 11b.

[0093] Meanwhile, according to the present embodiment, the first through via 129 penetrating the first LED stack 23 can be directly connected to the pads 11a, 11b, 11c, and 11d on the circuit board 11. The first through via 129 can be formed using a CuCMP technique. Thus, the first through via 129 can be formed on the pads 11a, 11b, 11c, and 11d, rather than being bonded to the pads 11a, 11b, 11c, and 11d by a bonding process. As a result, the light emitting element 100 is formed on the circuit board 11, rather than being transferred to the circuit board 11, and thus the reliability problem caused by the transfer can be solved.

[0094] FIG. 4A is a schematic perspective view for explaining a method for manufacturing a display panel according to one embodiment of the present disclosure, and FIG. 4B is a schematic perspective view for explaining a method for manufacturing a display panel according to yet another embodiment of the present disclosure.

[0095] The display panel according to the present disclosure is manufactured through a process of individually bonding and processing a first LED stack 23, a second LED stack 33 and a third LED stack 43 which are individually manufactured on a circuit board 11.

[0096] At this time, as shown in FIG. 4A, the first LED stack 23, the second LED stack 33 and the third LED stack 43 may be provided in a size similar to that of the circuit board 11, and may be bonded to the circuit board 11 in sequence to perform the process.

[0097] Alternatively, as shown in FIG. 4B, first to third LED stacks 23, 33, and 43 that are relatively smaller than the circuit board 11 may be provided, and the LED stacks 23, 33, and 43 may be arranged in a tiled manner on the circuit board 11 in order.

[0098] If the first to third LED stacks 23, 33, 43 can be manufactured to a size similar to that of the circuit board 11, the process can be simplified since the LED stacks 23, 33, 43 can be bonded to one circuit board 11 without tiling as shown in Fig. 4A. However, generally, silicon wafers used as the circuit board 11 are provided to be relatively large, whereas the LED stacks 23, 33, 43 using compound semiconductors are manufactured to be relatively small. Therefore, by arranging a plurality of LED stacks in a tiled manner as shown in Fig. 4B, many light-emitting elements can be manufactured at one time.

[0099] After a plurality of light emitting devices are manufactured on the circuit board 11, the circuit board 11 can be divided again into an appropriate size.

[0100] A method for manufacturing the display panel 1000 will be described in detail below. The display manufacturing method described below can be implemented in the manner of Fig. 4A or Fig. 4B. Meanwhile, it is believed that the structure of the light emitting device 100 can be understood in detail through the manufacturing method described below.

[0101] Figures 5A, 5B, 6A, 6B, 6C, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 18C, 19A, 19B, 20A, 20B, 21A, 21B, 22A, 22B, 22C, and 22D are schematic plan views and cross-sectional views for explaining a manufacturing method of a display panel according to one embodiment of the present disclosure. Here, as explained in FIG. 3A, an area including two light emitting elements 100 is illustrated and explained as an example, but many more light emitting elements 100 are manufactured on one circuit board 11.

[0102] 5A and 5B, a circuit board 11 is provided. The circuit board 11 may include a circuit for active matrix driving or passive matrix driving therein. The circuit board 11 may be, for example, a silicon-based circuit board 11, and may include active circuits in particular.

[0103] The circuit board 11 also includes pads 11a, 11b, 11c, and 11d exposed on the top surface. The pads 11a, 11b, 11c, and 11d may be arranged for each region where the light emitting element 100 is formed, that is, for each pixel region PA. The pads 11a, 11b, 11c, and 11d are electrically connected to an active circuit inside the circuit board 11.

[0104] 6A, 6B and 6C, first to third LED stacks 23, 33, 43 are provided separately from a circuit board 11.

[0105] 6A, the first LED stack 23 may include a first conductive type semiconductor layer 23a and a second conductive type semiconductor layer 23b, and may be grown on a first substrate 21a. An active layer (not shown) may be interposed between the first conductive type semiconductor layer 23a and the second conductive type semiconductor layer 23b.

[0106] The first substrate 21a may be a substrate, such as a GaAs substrate, that can be used to grow the first LED stack 23. The first conductive type semiconductor layer 23a and the second conductive type semiconductor layer 23b may be formed of AlGaInAs-based or AlGaInP-based semiconductor layers, and the active layer may include, for example, an AlGaInP-based well layer. The first LED stack 23 may have an AlGaInP composition ratio that is such that it emits, for example, red light.

[0107] A first transparent electrode 25 is formed on the second conductive type semiconductor layer 23b. As described above, the first transparent electrode 25 may be formed of a metal layer or a conductive oxide layer that transmits light, such as red light, generated by the first LED stack 23. Before the first transparent electrode 25 is formed, the surface of the second conductive type semiconductor layer 23b may be textured to form a rough surface.

[0108] Meanwhile, the first temporary substrate 21b may be bonded to the first LED stack 23 via an adhesive 27, and the first substrate 21a may be removed from the first LED stack 23. After the first substrate 21a is removed, the exposed surface of the first conductive type semiconductor layer 23a may be textured to form a rough surface.

[0109] 6B, the second LED stack 33 may include a first conductive type semiconductor layer 33a and a second conductive type semiconductor layer 33b and may be grown on the second substrate 31a. An active layer (not shown) may be interposed between the first conductive type semiconductor layer 33a and the second conductive type semiconductor layer 33b.

[0110] The second substrate 31a may be a substrate that can be used to grow the second LED stack 33, such as a sapphire substrate, a GaN substrate, or a GaAs substrate. The first conductive type semiconductor layer 33a and the second conductive type semiconductor layer 33b may be formed of an AlGaInAs-series or AlGaInP-series semiconductor layer, or an AlGaInN-series semiconductor layer, and the active layer may include, for example, an AlGaInP-series well layer or an AlGaInN-series well layer. The composition ratio of AlGaInP or AlGaInN in the second LED stack 33 may be determined so as to emit, for example, green light.

[0111] The second transparent electrode 35 may be formed on the second conductive semiconductor layer 33b. As described above, the second transparent electrode 35 is formed of a metal layer or a conductive oxide layer that transmits light, such as red light and green light, generated by the first LED stack 23 and the second LED stack 33.

[0112] Meanwhile, the second temporary substrate 31b is bonded to the second LED stack 33 via an adhesive 37, and the second substrate 31a can be removed from the second LED stack 33. After the second substrate 31a is removed, the exposed surface of the first conductive type semiconductor layer 33a is textured to form a rough surface.

[0113] 6C, the third LED stack 43 includes a first conductive type semiconductor layer 43a and a second conductive type semiconductor layer 43b, and is grown on a third substrate 41a. An active layer (not shown) may be interposed between the first conductive type semiconductor layer 43a and the second conductive type semiconductor layer 43b.

[0114] The third substrate 41a may be a substrate that can be used to grow the third LED stack 43, such as a sapphire substrate, a SiC substrate, or a GaN substrate. In one embodiment, the third substrate 41a may be a flat sapphire substrate, but may also be a patterned sapphire substrate. The first conductive type semiconductor layer 43a and the second conductive type semiconductor layer 43b may be formed of AlGaInN-based semiconductor layers, and the active layer may include, for example, an AlGaInN-based well layer. The third LED stack 43 may have an AlGaInN composition ratio that emits, for example, blue light.

[0115] A third transparent electrode 45 may be formed on the second conductive type semiconductor layer 43b. The third transparent electrode 45 may be formed of a metal layer or a conductive oxide layer that transmits light generated in the first to third LED stacks 23, 33, and 43, such as red light, green light, and blue light, as described above.

[0116] Meanwhile, the third temporary substrate 41b may be bonded to the third LED stack 43 by an adhesive 47, and the third substrate 41a may be removed from the third LED stack 43. After the third substrate 41a is removed, the exposed surface of the first conductivity type semiconductor layer 43a may be textured to form a rough surface.

[0117] The first to third LED stacks 23, 33, 43 are grown on different growth substrates 21a, 31a, 41a, respectively, and therefore the manufacturing process sequence is not limited.

[0118] A method for manufacturing a display panel 1000 using the first to third LED stacks 23, 33, and 43 grown on the growth substrates 21a, 31a, and 41a will be described below.

[0119] 7A and 7B, a reflective layer 13 is formed on a circuit board 11 having pads 11a, 11b, 11c, and 11d. The reflective layer 13 can be formed of a reflective metal layer or a distributed Bragg reflector. When the reflective layer 13 is a metal reflective layer, the reflective layer 13 is spaced apart from the pads 11a, 11b, 11c, and 11d. When the reflective layer 13 is a distributed Bragg reflector, the reflective layer 13 may be in contact with the pads 11a, 11b, 11c, and 11d.

[0120] 8A and 8B, the first LED stack 23 is bonded to the circuit board 11 through the first bonding layer 20. The first LED stack 23 may be bonded to the circuit board 11 while attached to the first temporary substrate 21b, and then the first temporary substrate 21b and the adhesive 27 may be removed from the first LED stack 23.

[0121] As described with reference to Figure 4A, a first LED stack 23 having a size similar to that of the circuit board 11 is bonded onto the circuit board 11. Alternatively, as described with reference to Figure 4B, multiple first LED stacks 23 may be tiled onto the circuit board 11.

[0122] 9A and 9B, the first transparent electrode 25 and the second conductive type semiconductor layer 23b are patterned using a photo and etching technique to expose the first conductive type semiconductor layer 23a. This process corresponds to, for example, a mesa etching process, and can be performed using a photoresist pattern as an etching mask. For example, after forming an etching mask, the first transparent electrode 25 and the second conductive type semiconductor layer 23b can be etched. The first transparent electrode 25 and the second conductive type semiconductor layer 23b can be etched using the same dry etching process, or can be etched using different etching processes. For example, the first transparent electrode 25 can be first etched using a wet etching technique, and then the second conductive type semiconductor layer 23b can be etched using the same etching mask using a dry etching technique.

[0123] Thereafter, the first ohmic electrode 123 is formed on the exposed first conductive type semiconductor layer 23a.

[0124] 10A and 10B, a lower insulating layer 125 is formed, and a through hole H1 is formed in the lower insulating layer 125. An element isolation region ISO1 is formed together with the through hole H1.

[0125] The lower insulating layer 125 covers the first transparent electrode 25 and the first ohmic electrode 123. The lower insulating layer 125 may also function as a hard mask for forming the through-hole H1.

[0126] The through-hole H1 penetrates the lower insulating layer 125, the first transparent electrode 25, the first LED stack 23 and the first bonding layer 20 to expose the pads 11a, 11b, 11c and 11d. During the formation of the through-hole H1, an isolation region ISO1 may be formed at the same time. The isolation region ISO1 separates the regions in which the light-emitting elements 100 are formed from each other.

[0127] 11A and 11B, a first sidewall insulating layer 127 and a first through via 129 are formed. First, the first sidewall insulating layer 127 is formed on the lower insulating layer 125 in which the through hole H1 is formed. The first sidewall insulating layer 127 may be formed using, for example, an atomic layer deposition technique. The first sidewall insulating layer 127 may cover an upper surface of the lower insulating layer 125, and may further cover a sidewall and a bottom surface of the through hole H1. The first sidewall insulating layer 127 formed on the bottom surface of the through hole H1 may be removed through a blanket etching process, and thus the pads 11a, 11b, 11c, and 11d may be exposed. The first sidewall insulating layer 127 covering the upper surface of the lower insulating layer 125 may be removed during the blanket etching process. Meanwhile, the first sidewall insulating layer 127 is also formed on the sidewall of the element isolation region ISO1.

[0128] Next, a seed layer is formed on the entire surface, a metal layer is formed using a plating technique, and then the photoresist pattern is removed. The metal layer formed on the upper surface of the lower insulating layer 125 is removed using a chemical mechanical polishing technique, thereby completing a first through via 129 filling the through hole H1. The element isolation region ISO1 may be covered with a photoresist pattern to block the formation of the metal layer. The photoresist pattern is formed after the seed layer is formed and before the metal layer is plated, to define the region where the metal layer is to be formed. The photoresist pattern may be removed using a chemical mechanical polishing technique, or may be removed through a lift-off process before the chemical mechanical polishing process is performed. Also, the seed layer formed in the element isolation region ISO1 may be selectively removed through an etching process.

[0129] Meanwhile, in order to protect the first through via 129, a cap layer may be added on the metal layer formed in the through hole H1, or an oxidation prevention treatment such as ENIG or ENEPIG may be performed.

[0130] 12A, 12B, and 12C, the lower insulating layer 125 is patterned to form an opening 125a exposing the first ohmic electrode 123 and an opening 125b exposing the first transparent electrode 25. The lower insulating layer 125 may be patterned through a photolithography and etching process. The opening 125b may be disposed relatively close to the first through via 129 connected to the pad 11d.

[0131] 13A, 13B and 13C, first connection pads 131a, 131b, 131c, and 131d are formed on the lower insulating layer 125. The first connection pads 131a, 131b, 131c, and 131d can be formed using a photolithography process and an etching process or a lift-off technique.

[0132] The first connection pad 131a electrically connects the first through via 129 connected to the common pad 11a to the first ohmic electrode 123 exposed through the opening 125a, and the first connection pad 131d electrically connects the first through via 129 connected to the pad 11d to the first transparent electrode 25 exposed through the opening 125b.

[0133] On the other hand, the first connection pads 131b and 131c are electrically connected to the first through via 129 which is connected to the pads 11b and 11c.

[0134] 14A and 14B, the second LED stack 33 is bonded onto the first LED stack 23. The second LED stack 33 may be bonded onto the first LED stack 23 through the second bonding layer 30. The first conductive type semiconductor layer 33a may face downward and contact the second bonding layer 30, and the second transparent electrode 35 may be disposed on the upper side facing the second bonding layer 30. The second LED stack 33 may be bonded to the first LED stack 23 while attached to the second temporary substrate 31b, and then the second temporary substrate 31b and the adhesive 37 may be removed from the second LED stack 33.

[0135] The second bonding layer 30 can fill the element isolation region ISO1 and cover the first connection pads 131a, 131b, 131c, and 131d.

[0136] 15A and 15B, the second transparent electrode 35 and the second conductive type semiconductor layer 33b are patterned using photolithography and etching techniques to expose the first conductive type semiconductor layer 33a. This process corresponds to, for example, a mesa etching process, and can be performed using a photoresist pattern as an etching mask. For example, after forming an etching mask, the second transparent electrode 35 and the second conductive type semiconductor layer 33b can be etched. The second transparent electrode 35 and the second conductive type semiconductor layer 33b can be etched using the same dry etching process, or can be etched using different etching processes. For example, the second transparent electrode 35 can be first etched using a wet etching technique, and then the second conductive type semiconductor layer 33b can be etched using the same etching mask using a dry etching technique.

[0137] Thereafter, the second ohmic electrode 133 is formed on the exposed first conductive type semiconductor layer 33a.

[0138] 16A and 16B, an intermediate insulating layer 135 is formed, and a through hole H2 is formed. An element isolation region ISO2 can be formed together with the through hole H2.

[0139] The intermediate insulating layer 135 covers the second transparent electrode 35 and the second ohmic electrode 133. The intermediate insulating layer 135 also functions as a hard mask for forming the through-hole H2.

[0140] The through hole H2 penetrates the intermediate insulating layer 135, the second transparent electrode 35, the second LED stack 33 and the second bonding layer 30 to expose the first connection pads 131a, 131b, 131c connected to the first through via 129. During the formation of the through hole H2, an isolation region ISO2 may be formed at the same time. The isolation region ISO2 separates the regions in which the light emitting elements 100 are formed. The isolation region ISO2 may expose the second bonding layer 30. In another embodiment, the second bonding layer 30 in the isolation region ISO2 may be entirely removed to expose the top surface of the circuit board 11.

[0141] 17A and 17B, a second sidewall insulating layer 137 and a second through via 139 are formed. First, the second sidewall insulating layer 137 is formed on the intermediate insulating layer 135 in which the through hole H2 is formed. The second sidewall insulating layer 137 may be formed using, for example, an atomic layer deposition technique. The second sidewall insulating layer 137 may cover the upper surface of the intermediate insulating layer 135 and may further cover the sidewall and bottom surface of the through hole H2. The second sidewall insulating layer 137 formed on the bottom surface of the through hole H2 may be removed through a blanket etching process, thereby exposing the first connection pads 131a, 131b, and 131c. The second sidewall insulating layer 137 covering the upper surface of the intermediate insulating layer 135 may be removed during the blanket etching process. Meanwhile, the second sidewall insulating layer 137 may also be formed on the sidewall of the element isolation region ISO2.

[0142] Next, a seed layer is formed on the entire surface, a metal layer is formed using a plating technique, and then the photoresist pattern is removed, and the metal layer formed on the upper surface of the intermediate insulating layer 135 is removed using a chemical mechanical polishing technique, thereby completing the second through via 139 filling the through hole H2. The process of forming the second through via 139 is similar to the process of forming the first through via 129, and therefore a detailed description thereof will be omitted to avoid duplication.

[0143] Meanwhile, in order to protect the second through via 139, a cap layer may be added on the metal layer formed in the through hole H2, or an oxidation prevention treatment such as ENIG or ENEPIG may be performed.

[0144] 18A, 18B, and 18C, the intermediate insulating layer 135 is patterned to form an opening 135a exposing the second ohmic electrode 133 and an opening 135b exposing the second transparent electrode 35. The intermediate insulating layer 135 may be patterned through a photo and etching process. The opening 135b may be disposed relatively close to the second through via 139 electrically connected to the pad 11c.

[0145] Then, the second connection pads 141a, 141b, and 141c are formed on the intermediate insulating layer 135. The second connection pads 141a, 141b, and 141c can be formed using a photolithography and etching process or a lift-off technique.

[0146] The second connection pad 141a electrically connects the second through via 139 connected to the common pad 11a to the second ohmic electrode 133 exposed through the opening 135a, and the second connection pad 141c electrically connects the second through via 139 connected to the pad 11c to the second transparent electrode 35 exposed through the opening 135b.

[0147] On the other hand, the second connection pad 141b is electrically connected to the second through via 139 which is connected to the pad 11b.

[0148] 19A and 19B, the third LED stack 43 is bonded onto the second LED stack 33. The third LED stack 43 is bonded onto the second LED stack 33 through the third bonding layer 40. The first conductive type semiconductor layer 43a faces downward and contacts the third bonding layer 40, and the third transparent electrode 45 is disposed on the upper side facing the third bonding layer 40. The third LED stack 43 is bonded to the second LED stack 33 while being attached to the third temporary substrate 41b, and then the third temporary substrate 41b and the adhesive 47 are removed from the third LED stack 43.

[0149] The third bonding layer 40 can fill the element isolation region ISO2 and cover the second connection pads 141a, 141b, and 141c.

[0150] 20A and 20B, the third transparent electrode 45 and the second conductive type semiconductor layer 43b are patterned using photolithography and etching techniques to expose the first conductive type semiconductor layer 43a. This process corresponds to, for example, a mesa etching process, and can be performed using a photoresist pattern as an etching mask. For example, after forming an etching mask, the third transparent electrode 45 and the second conductive type semiconductor layer 43b can be etched. The third transparent electrode 45 and the second conductive type semiconductor layer 43b can be etched using the same dry etching process, or can be etched using different etching processes. For example, the third transparent electrode 45 can be first etched using a wet etching technique, and then the second conductive type semiconductor layer 43b can be etched using the same etching mask using a dry etching technique.

[0151] Thereafter, a third ohmic electrode 143 is formed on the exposed first conductive type semiconductor layer 43a.

[0152] Then, the upper insulating layer 145 is formed to cover the third transparent electrode 45 and the third ohmic electrode 143, and the through hole H3 is formed. The element isolation region ISO3 can be formed together with the through hole H3. The upper insulating layer 145 can also function as a hard mask for forming the through hole H3.

[0153] The through-hole H3 penetrates the upper insulating layer 145, the third transparent electrode 45, the third LED stack 43 and the third bonding layer 40 to expose the second connection pads 141a, 141b. During the formation of the through-hole H3, an isolation region ISO3 may be formed at the same time. The isolation region ISO3 separates the regions in which the light-emitting elements 100 are formed from each other. The isolation region ISO3 may expose the third bonding layer 40. In another embodiment, the third bonding layer 40 in the isolation region ISO3 may be entirely removed to expose the top surface of the circuit board 11.

[0154] 21A and 21B, a third sidewall insulating layer 147 and a third through via 149 are formed. First, a third sidewall insulating layer 147 is formed on the upper insulating layer 145 in which the through hole H3 is formed. The third sidewall insulating layer 147 may be formed using, for example, an atomic layer deposition technique. The third sidewall insulating layer 147 may cover an upper surface of the upper insulating layer 145, and may further cover a sidewall and a bottom surface of the through hole H3. The third sidewall insulating layer 147 formed on the bottom surface of the through hole H3 may be removed through a blanket etching process, and thus the second connection pads 141a and 141b may be exposed. The third sidewall insulating layer 147 covering the upper surface of the upper insulating layer 145 may be removed during the blanket etching process. Meanwhile, the third sidewall insulating layer 147 may also be formed on the sidewall of the element isolation region ISO3.

[0155] Next, a seed layer is formed on the entire surface, a metal layer is formed using a plating technique, and then the photoresist pattern is removed, and the metal layer formed on the upper surface of the upper insulating layer 145 is removed using a chemical mechanical polishing technique, thereby completing a third through via 149 filling the through hole H3. The process of forming the third through via 149 is similar to the process of forming the first through via 129, and therefore a detailed description thereof will be omitted to avoid duplication.

[0156] Meanwhile, in order to protect the third through via 149, a cap layer may be added on the metal layer formed in the through hole H3, or an oxidation prevention treatment such as ENIG or ENEPIG may be performed.

[0157] 22A, 22B, 22C, and 22D, the upper insulating layer 145 is patterned to form an opening exposing the third ohmic electrode 143 and an opening exposing the third transparent electrode 45. The upper insulating layer 145 may be patterned through a photolithography and etching process. The opening exposing the third transparent electrode 45 may be disposed relatively close to the third through via 149 electrically connected to the pad 11b.

[0158] Then, the third connection pads 151a, 151b are formed on the upper insulating layer 14. The third connection pads 151a, 151b can be formed using a photolithography and etching process, or a lift-off technique.

[0159] The third connection pad 151a electrically connects the third through via 149 connected to the common pad 11a to the third ohmic electrode 143 exposed through the opening, and the third connection pad 151b electrically connects the third through via 149 connected to the pad 11b to the third transparent electrode 45 exposed through the opening.

[0160] As a result, the light emitting element 100 and pixel area are completed on the circuit board 11. The circuit board 11 can then be divided into appropriate sizes, thereby completing a display panel of a desired size. Furthermore, the element isolation area ISO3 can be filled with a light blocking material or a light reflecting material.

[0161] FIG. 23A is a plan view illustrating a display panel 2000 according to another embodiment of the present disclosure, and FIG. 23B, FIG. 23C, and FIG. 23D are cross-sectional views taken along cut lines D-D', E-E', and F-F', respectively, of FIG. 23A.

[0162] 23A, 23B, 23C and 23D, a display panel 2000 includes a light-emitting element 200 disposed on a circuit board 11, a first LED stack 23, a second LED stack 33, a third LED stack 43, a bottom electrode 25', a second transparent electrode 35, a third transparent electrode 45, a first ohmic electrode 123a, a first bonding layer 20, a second bonding layer 30, a third bonding layer 40, a bottom insulating layer 123b, a bottom insulating layer 123c, a bottom insulating layer 123d, a bottom insulating layer 123e, a bottom insulating layer 123f, a bottom insulating layer 123g, a bottom insulating layer 123h, a bottom insulating layer 123h, a bottom insulating layer 123i, a bottom insulating layer 123j ... It may include an edge layer 125, an intermediate insulating layer 135, an upper insulating layer 145, a first sidewall insulating layer 127, a second sidewall insulating layer 137, a third sidewall insulating layer 147, a first through via 129, 129', a second through via 139, 139', a third through via 149, 149', a first connection pad 131a, 131b, 131c, 131d, a second connection pad 141a, 141b, 141c, and a third connection pad 151a, 151b.

[0163] The display panel 2000 according to this embodiment is generally similar to the display panel 1000 described with reference to Figures 3A, 3B, 3C and 3D, except that the first conductive type semiconductor layers 23a, 33a, 43a and the second conductive type semiconductor layers 23b, 33b, 43b are upside down. In order to avoid duplication, detailed descriptions of the same points will be omitted, and only the differences will be described in detail.

[0164] First, the first to third LED stacks 23, 33, 43 are stacked in the vertical direction. Here, the second conductive type semiconductor layers 23b, 33b, 43b of the LED stacks 23, 33, 43 are arranged facing the circuit board 11, and the first conductive type semiconductor layers 23a, 33a, 43a are arranged facing the emission surface from which light is emitted.

[0165] As described above, the first LED stack 23, the second LED stack 33, and the third LED stack 43 have through holes, and the first to third through vias 129, 139, and 149 are formed in the through holes. Furthermore, in this embodiment, through holes penetrating the first LED stack 23, the second LED stack 33, and the third LED stack 43 may be added, and the first to third through vias 129', 139', and 149' may be formed in the through holes. The first to third through vias 129, 139, and 149 penetrate the lower electrode 25', the second transparent electrode 35, and the third transparent electrode 45, respectively, but the first to third through vias 129', 139', and 149' stop at the lower electrode 25', the second transparent electrode 35, and the third transparent electrode 45.

[0166] The first to third through vias 129, 139, 149 and the first to third through vias 129', 139', 149' are insulated from the LED stacks 23, 33, 43 by first to third sidewall insulating layers 127, 137, 147, respectively, within the through holes.

[0167] In this embodiment, the first LED stack 23, the second LED stack 33, and the third LED stack 43 may overlap each other and have light-emitting areas of approximately similar size. Furthermore, in each LED stack 23, 33, and 43, the first conductive type semiconductor layer 23a, 33a, and 43a may have an area of ​​approximately the same size as the second conductive type semiconductor layer 23b, 33b, and 43b, respectively. In particular, there is no need to etch a portion of the second conductive type semiconductor layer to form the same ohmic electrodes 123, 133, and 143 as in the previous embodiment.

[0168] Meanwhile, the lower electrode 25' is in ohmic contact with the second conductive type semiconductor layer 23b of the first LED stack 23. The lower electrode 25' can cover substantially the entire surface of the second conductive type semiconductor layer 23b. In this embodiment, since the second conductive type semiconductor layer 23b of the first LED stack 23 is disposed to face the circuit board 11, the lower electrode 25' in ohmic contact with the second conductive type semiconductor layer 23b does not need to transmit light. In particular, the lower electrode 25' can be formed as a reflective layer that reflects light. For example, the lower electrode 25' can include AuBe or AuZn. Meanwhile, when the lower electrode 25' is formed as a reflective layer, the light toward the circuit board 11 can be reflected even if the reflective layer 13 formed on the circuit board 11 in the above embodiment is omitted. In another embodiment, the reflective layer 13 may be used together with the lower electrode 25'.

[0169] On the other hand, the second transparent electrode 35 is in ohmic contact with the second conductive type semiconductor layer 33b between the first LED stack 23 and the second LED stack 33, and the third transparent electrode 45 is in ohmic contact with the second conductive type semiconductor layer 43b between the second LED stack 33 and the third LED stack 43.

[0170] For example, the second transparent electrode 35 may be formed of a metal layer or a conductive oxide layer that is transparent to red light. Furthermore, the second transparent electrode 35 may be formed of a material that transmits green light, but is not limited thereto, and may be formed of a material that reflects green light.

[0171] The third transparent electrode 45 may be formed of, for example, a metal layer or a conductive oxide layer transparent to red and green light, and may be formed of a material transparent to blue light, but is not limited thereto, and may be formed of a material that reflects blue light.

[0172] The bottom electrode 25', the second transparent electrode 35 and the third transparent electrode 45 can make ohmic contact with the p-type semiconductor layer of each LED stack 23, 33, 43 to aid in current spreading. An example of a conductive oxide layer that can be used for the second and third transparent electrodes 35, 45 is SnO 2 ,InO 2 , ITO, ZnO, IZO, ITZO, etc.

[0173] The first ohmic electrode 123a is disposed on the first conductive type semiconductor layer 23a. The first ohmic electrode 123a may be formed of, for example, AuGe or AuTe. In order to reduce the ohmic resistance, the first conductive type semiconductor layer 23a may include an ohmic contact semiconductor layer (see 23c in FIG. 25B) such as AlGaAs. The ohmic contact semiconductor layer 23c may be located only under the first ohmic electrode 123a, thereby reducing light absorption by the ohmic contact semiconductor layer 23c.

[0174] The lower insulating layer 125 may cover the first ohmic electrode 123a and the first conductive type semiconductor layer 23a. The lower insulating layer 125 may be located only on the upper portion of the first conductive type semiconductor layer 23a, and may not cover the side surface of the first conductive type semiconductor layer 23a. Meanwhile, the lower insulating layer 125 may have an opening that exposes the first ohmic electrode 123a.

[0175] The intermediate insulating layer 135 covers the first conductive type semiconductor layer 33a. The intermediate insulating layer 135 may be located only on the first conductive type semiconductor layer 33a, and may not cover the side surfaces of the first conductive type semiconductor layer 33a. Meanwhile, the intermediate insulating layer 135 may have an opening that exposes the first conductive type semiconductor layer 33a.

[0176] The upper insulating layer 145 may cover the first conductive type semiconductor layer 43a. The upper insulating layer 145 may be located only on the upper portion of the first conductive type semiconductor layer 43a, and may not cover the side surface of the first conductive type semiconductor layer 43a. The upper insulating layer 145 may have an opening that exposes the first conductive type semiconductor layer 43a.

[0177] The first bonding layer 20 bonds the first LED stack 23 to the circuit board 11. In particular, the first bonding layer 20 may bond the bottom electrode 25′ of the first LED stack 23 to the circuit board 11. The second bonding layer 30 bonds the second LED stack 33 to the first LED stack 23. The second bonding layer 30 may bond between the second transparent electrode 35 and the bottom insulating layer 125. The third bonding layer 40 bonds the third LED stack 43 to the first LED stack 23. The third bonding layer 40 may bond between the middle insulating layer 135 and the third transparent electrode 45.

[0178] The first through vias 129, 129' penetrate the first LED stack 23. The first through vias 129 can also penetrate the lower insulating layer 125, the lower electrode 25', and the first bonding layer 20, and can be electrically connected to the common pad 11a and the individual pads 11b, 11c, and 11d, respectively. The first through vias 129' can be connected to the lower electrode 25'.

[0179] The first sidewall insulating layer 127 insulates the first through vias 129, 129' from the first LED stack 23 in the through holes.

[0180] The first connection pads 131a, 131b, 131c, 131d may be located between the first LED stack 23 and the second LED stack 33. The first connection pads 131a, 131b, 131c, 131d may be disposed on the lower insulating layer 125 and may be covered with the second bonding layer 30.

[0181] The first connection pad 131a electrically connects the first through via 129 electrically connected to the common pad 11a to the first ohmic electrode 123a as shown in Fig. 23B. The first connection pad 131d electrically connects the first through via 129 electrically connected to the pad 11d to the first through via 129' as shown in Fig. 23C.

[0182] Meanwhile, the first connection pads 131b and 131c cover and are electrically connected to the first through vias 129 electrically connected to the pads 11c and 11d, respectively.

[0183] The second through vias 139, 139' penetrate the second LED stack 33. The second through vias 139 can also penetrate the intermediate insulating layer 135, the second transparent electrode 35, and the second bonding layer 30, and can be electrically connected to the first connection pads 131a, 131b, and 131c, respectively. The second through vias 139' are electrically connected to the second transparent electrode 35.

[0184] The second sidewall insulating layer 137 insulates the second through vias 139, 139′ within the through holes from the second LED stack 33. The second sidewall insulating layer 137 covers the sidewalls of the through holes and has openings that expose the floors of the through holes, e.g., the first connection pads 131a, 131b, 131c and the second transparent electrode 35.

[0185] The second connection pads 141a, 141b, 141c may be located between the second LED stack 33 and the third LED stack 43. The second connection pads 141a, 141b, 141c may be disposed on the intermediate insulating layer 135 and may be covered with the third bonding layer 40.

[0186] 23B, the second connection pad 141a electrically connects the second through via 139 electrically connected to the first connection pad 131a to the first conductive type semiconductor layer 33a exposed through the opening of the intermediate insulating layer 135. A second ohmic electrode may be added on the first conductive type semiconductor layer 33a, and the intermediate insulating layer 135 may have an opening exposing the second ohmic electrode. In this case, the second connection pad 141a may electrically connect the second through via 139 to the second ohmic electrode.

[0187] The second connection pad 141c electrically connects the second through via 139 electrically connected to the first connection pad 131c to the second through via 139' electrically connected to the second transparent electrode 35, as shown in FIG. 23C.

[0188] Meanwhile, the second connection pad 141b covers and is electrically connected to the second through via 139 electrically connected to the first connection pad 131b.

[0189] The third through vias 149, 149′ penetrate the third LED stack 43. The third through via 149 can also penetrate the upper insulating layer 145, the third transparent electrode 45, and the third bonding layer 40, and can be electrically connected to the second connection pads 141a, 141b, respectively. The third through via 149′ is electrically connected to the third transparent electrode 45.

[0190] The third sidewall insulating layer 147 insulates the third through vias 149, 149′ within the through holes from the third LED stack 43. The third sidewall insulating layer 147 covers the sidewalls of the through holes and has openings that expose the floors of the through holes, e.g., the second connection pads 141a, 141b and the third transparent electrode 45.

[0191] 23B, the third connection pad 151a electrically connects the third through via 149 electrically connected to the second connection pad 141a to the first conductive type semiconductor layer 43a exposed through the opening of the upper insulating layer 145. A third ohmic electrode may be added on the first conductive type semiconductor layer 43a, and the upper insulating layer 145 may have an opening that exposes the third ohmic electrode. In this case, the third connection pad 151a may electrically connect the third through via 149 to the third ohmic electrode.

[0192] The third connection pad 151b electrically connects the third through via 149 electrically connected to the second connection pad 141b to the third through via 149' electrically connected to the third transparent electrode 45, as shown in FIG. 23D.

[0193] The first to third through vias 129, 139, 149, 129', 139', 149' can be formed using a chemical mechanical polishing technique as described in the above embodiments.

[0194] According to this embodiment, the first conductive type semiconductor layer 23a of the first LED stack 23, the first conductive type semiconductor layer 33a of the second LED stack 33, and the first conductive type semiconductor layer 43a of the third LED stack 43 are all electrically connected to the common pad 11a. Meanwhile, the second conductive type semiconductor layer 23b of the first LED stack 23 is electrically connected to the individual pad 11d, the second conductive type semiconductor layer 33b of the second LED stack 33 is electrically connected to the individual pad 11c, and the second conductive type semiconductor layer 43b of the third LED stack 43 is electrically connected to the individual pad 11b. Thus, the first LED stack 23 can be driven by supplying power to the pads 11a and 11d, the second LED stack 33 can be driven by supplying power to the pads 11a and 11c, and the third LED stack 43 can be driven by supplying power from the pads 11a and 11b.

[0195] Meanwhile, according to the present embodiment, the first through via 129 penetrating the first LED stack 23 can be directly connected to the pads 11a, 11b, 11c, and 11d on the circuit board 11. The first through via 129 can be formed using Cu CMP technology. Therefore, the first through via 129 can be formed on the pads 11a, 11b, 11c, and 11d, rather than being bonded to the pads 11a, 11b, 11c, and 11d by a bonding process. As a result, the light emitting element 100 is formed on the circuit board 11, rather than being transferred to the circuit board 11, and thus the reliability problem caused by the transfer can be solved.

[0196] A method for manufacturing the display panel 2000 will be described in detail below. The method for manufacturing the display panel described below is implemented in the manner of Fig. 4A or Fig. 4B. Meanwhile, it is believed that the structure of the light emitting device 200 can be understood in more detail through the manufacturing method described below.

[0197] 24A, 24B, 25A, 25B, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, 29A, 29B, 29C, 30A, 30B, 30C, 31A, 31B, 31C, 32A, 32B, 33A, 33B, 33C, 34A, 34B, 34C, 35A, 35B, 35C, and 35D are schematic plan views and cross-sectional views for explaining a manufacturing method of a display panel 2000 according to an embodiment of the present disclosure. Here, as explained in FIG. 3A, an area including two light-emitting elements 200 is illustrated and explained as an example, but more light-emitting elements 200 are manufactured on one circuit board 11.

[0198] First, referring to FIGS. 24A and 24B, a first LED stack 23 is bonded onto a circuit board 11 through a first bonding layer 20. As shown in FIG.

[0199] The circuit board 11 may include circuits for active matrix driving or passive matrix driving therein. The circuit board 11 may be, for example, a silicon substrate circuit board 11, and may include active circuits in particular.

[0200] The circuit board 11 also includes pads 11a, 11b, 11c, and 11d exposed on the top surface. The pads 11a, 11b, 11c, and 11d may be disposed in each area where the light emitting element 100 is formed. The pads 11a, 11b, 11c, and 11d are electrically connected to an active circuit inside the circuit board 11.

[0201] 6A, the first LED stack 23 may be formed on the first substrate 21a. In this embodiment, the step of bonding to the first temporary substrate 21b may be omitted, and the first substrate 21a may be removed from the first LED stack 23 after the first LED stack 23 is bonded to the circuit substrate 11. In addition, a bottom electrode 25′ may be formed on the second conductive type semiconductor layer 23b, and the first bonding layer 20 may bond the bottom electrode 25′ to the circuit substrate 11.

[0202] 25A and 25B, a first ohmic electrode 123a may be formed on a first conductive type semiconductor layer 23a. In order to improve ohmic contact characteristics, the first conductive type semiconductor layer 23a may include an ohmic contact semiconductor layer 23c such as AlGaAs on a surface, and the first ohmic electrode 123a may contact the ohmic contact semiconductor layer 23c. In addition, the ohmic contact semiconductor layer 23c may be etched away in the remaining region except for the ohmic contact semiconductor layer 23c under the first ohmic electrode 123a. In addition, after the ohmic contact semiconductor layer 23c is removed, the surface of the first conductive type semiconductor layer 23a may be textured to form a rough surface. In the following drawings, the ohmic contact semiconductor layer 23c is omitted to avoid complicating the drawings.

[0203] 26A, 26B, and 26C, a lower insulating layer 125 is formed, and through holes H1_1 and H1_2 are formed in the lower insulating layer 125. An element isolation region ISO1 is formed together with the through holes H1_1 and H1_2.

[0204] The lower insulating layer 125 covers the first conductive type semiconductor layer 23a and the first ohmic electrode 123a. The lower insulating layer 125 can also function as a hard mask for forming the through holes H1_1 and H1_2.

[0205] The through hole H1_1 penetrates the lower insulating layer 125, the first LED stack 23, the first transparent electrode 25, and the first bonding layer 20 to expose the pads 11a, 11b, 11c, and 11d. The through hole H1_1 exposes the lower electrode 25' around the pad 11d.

[0206] On the other hand, the size of the first LED stack 23 and the bottom electrode 25' are determined by the element isolation region ISO1, so that the bottom electrode 25' can be formed over the entire surface of the second conductivity type semiconductor layer 23b of the first LED stack 23.

[0207] 27A, 27B, and 27C, the first sidewall insulating layer 127, the first through vias 129, 129', and the first connection pads 131a, 131b, 131c, and 131d are formed. After forming the first through vias 129, 129', and before forming the first connection pads 131a, 131b, 131c, and 131d, an opening exposing the first ohmic electrode 123a is formed in the lower insulating layer 125.

[0208] The first sidewall insulating layer 127, the first through vias 129, 129' and the first connection pads 131a, 131b, 131c, 131d are formed in a manner similar to that of the previous embodiment, and therefore will not be described in detail.

[0209] 28A and 28B, the second LED stack 33 is bonded onto the first LED stack 23. The second LED stack 33 may be bonded onto the first LED stack 23 through the second bonding layer 30. The second transparent electrode 35 faces downward and contacts the second bonding layer 30, and the first conductive type semiconductor layer 33a is disposed on the upper side facing the second bonding layer 30. The second LED stack 33 is bonded to the first LED stack 23 while attached to a second substrate (31a in FIG. 6B), and then the second substrate 31a is removed from the second LED stack 33, for example, using a laser lift-off technique. The second temporary substrate 31b and the adhesive 37 are omitted.

[0210] 29A, 29B and 29C, an intermediate insulating layer 135 is formed, and through holes H2_1 and H2_2 are formed. An element isolation region ISO2 may be formed together with the through holes H2_1 and H2_2.

[0211] The first conductive type semiconductor layer 33a is covered with the intermediate insulating layer 135. The intermediate insulating layer 135 can also function as a hard mask for forming the through holes H2_1 and H2_2.

[0212] The through hole H2_1 penetrates the intermediate insulating layer 135, the second LED stack 33, the second transparent electrode 35, and the second bonding layer 30, and exposes the first connection pads 131a, 131b, and 131c connected to the first through via 129. The through hole H2_2 penetrates the intermediate insulating layer 135 and the second LED stack 33, and exposes the second transparent electrode 35. The through hole H2_2 can be disposed relatively close to the through hole H2_1 that exposes the first connection pad 131c.

[0213] 30A, 30B and 30C, the second sidewall insulating layer 137 and the second through vias 139, 139' are formed. The formation of the second sidewall insulating layer 137 and the through vias 139, 139' is similar to the embodiment described above, so a detailed description will be omitted. The second through vias 139 can be connected to the first connection pads 131a, 131b and 131c, respectively, and the second through vias 139' can be electrically connected to the second transparent electrode 35.

[0214] After the second through vias 139, 139' are formed, the intermediate insulating layer 135 is patterned to form an opening 135a' exposing the first conductive type semiconductor layer 33a. The intermediate insulating layer 135 may be patterned through a photolithography and etching process. The opening 135a' may be disposed relatively close to the second through via 139 electrically connected to the common pad 11a.

[0215] 31A, 31B and 31C, second connection pads 141a, 141b, 141c are formed on the intermediate insulating layer 135. The second connection pads 141a, 141b, 141c can be formed using a photolithography and etching process or using a lift-off technique.

[0216] The second connection pad 141a electrically connects the second through via 139 connected to the common pad 11a to the first conductive type semiconductor layer 33a exposed through the opening 135a', and the second connection pad 141c electrically connects the second through via 139 connected to the pad 11c to the second through via 139'. Meanwhile, the second connection pad 141b is electrically connected to the second through via 139 connected to the pad 11b.

[0217] In order to reduce the ohmic contact resistance of the first conductive type semiconductor layer 33a, an ohmic layer in ohmic contact with the first conductive type semiconductor layer 33a may be further formed before forming the intermediate insulating layer 135 or after forming the opening 135a' in the intermediate insulating layer 135. In this case, the second connection pad 141a may electrically connect the second through via 139 and the ohmic layer.

[0218] 32A and 32B, the third LED stack 43 is bonded onto the second LED stack 33. The third LED stack 43 can be bonded onto the second LED stack 33 through the third bonding layer 40. The third transparent electrode 45 can face downward and contact the third bonding layer 40, and the first conductive type semiconductor layer 43a can be disposed on the upper side facing the third bonding layer 40. The third LED stack 43 can be bonded to the second LED stack 33 while attached to the third substrate 41a, and then the third substrate 41a is removed from the third LED stack 43. Thus, the third temporary substrate 41b and the adhesive 47 can be omitted.

[0219] 33A, 33B, and 33C, an upper insulating layer 145 is formed to cover the first conductive type semiconductor layer 33a, and through holes H3_1 and H3_2 are formed. An element isolation region ISO3 can be formed together with the through holes H3_1 and H3_2. The upper insulating layer 145 can also function as a hard mask for forming the through holes H3_1 and H3_2.

[0220] The through hole H3_1 penetrates the upper insulating layer 145, the third LED stack 43, the third transparent electrode 45, and the third bonding layer 40 to expose the second connection pads 141a and 141b. The through hole H3_2 penetrates the upper insulating layer 145 and the third LED stack 43 to expose the third transparent electrode 45. The through hole H3_2 may be disposed relatively close to the third through via 149 electrically connected to the second connection pad 141b. The through hole H3_1 and the through hole H3_2 may be formed using different photoresist patterns.

[0221] 34A, 34B and 34C, a third sidewall insulating layer 147 and third through vias 149, 149' are formed, and an opening 145a' exposing the first conductive type semiconductor layer 43a is formed in the upper insulating layer 145. The process of forming the third sidewall insulating layer 147, the third through vias 149, 149' and the opening 145a' is similar to the process of forming the second sidewall insulating layer 137, the second through vias 139, 139' and the opening 135a', so a detailed description will be omitted. However, the opening 145a' may be disposed relatively close to the third through via 149 electrically connected to the second connection pad 141a.

[0222] 35A, 35B, 35C and 35D, third connection pads 151a and 151b are formed on the upper insulating layer 145. The third connection pads 151a and 151b can be formed using a photolithography and etching process or a lift-off technique.

[0223] The third connection pad 151a electrically connects the third through via 149 connected to the common pad 11a to the first conductive type semiconductor layer 43a exposed through the opening 145a', and the third connection pad 151b electrically connects the third through via 149 connected to the pad 11b to the third through via 149' connected to the third transparent electrode 45.

[0224] As a result, the light emitting element 200, i.e., the pixel region, is completed on the circuit board 11. Then, the circuit board 11 can be divided into an appropriate size, thereby completing the display panel 2000. Furthermore, the element isolation region ISO3 can be filled with a light blocking material or a light reflecting material.

[0225] 36A, 36B, and 36C are schematic cross-sectional views for illustrating a display panel 2000a according to another embodiment of the present disclosure, where FIG. 36A, FIG. 36B, and FIG. 36C correspond to cross-sectional views taken along cut lines D-D', E-E', and F-F' in FIG. 23A, respectively.

[0226] Referring to Figures 36A, 36B and 36C, the display panel 2000a of this embodiment is generally similar to the display panel 200 described with reference to Figures 23A, 23B, 23C and 23D above, except that it further includes a light absorbing layer 153.

[0227] The light absorbing layer 153 covers the third LED stack 43. The light absorbing layer 153 may also cover the top insulating layer 145, the third sidewall insulating layer 147, and the third bonding layer 40. In particular, as shown in Figures 36A, 36B, and 36C, the light absorbing layer 153 may cover the entire top surface of the display panel 2000a.

[0228] The light absorbing layer 153 can fill the element isolation region (ISO3 in FIG. 23B). The thickness of the light absorbing layer 153 disposed on the upper portion of the third LED stack 43 is smaller than the width of the element isolation region ISO3, and therefore, the absorption of light toward the upper portion of the third LED stack 43 can be relatively smaller than the absorption of light emitted to the side surface of the third LED stack 43.

[0229] The light absorbing layer 153 reduces light interference between adjacent sub-pixels to improve the contrast of the display panel.

[0230] The light absorbing layer 153 may be formed of a black material such as PDMA or black EMC (epoxy molding compound). For example, as described with reference to Figures 35A, 35B, 35C, and 35D, after the third connection pads 151a and 151b are formed, the light absorbing layer 153 may be formed by applying and curing a black material that covers the upper insulating layer 145, the third sidewall insulating layer 147, and the third connection pads 151a and 151b.

[0231] FIG. 37 is a schematic cross-sectional view illustrating a display panel 2000b according to still another embodiment of the present disclosure.

[0232] The display panel 2000b according to this embodiment is generally similar to the display panel 2000a described with reference to Figures 36A, 36B, and 36C, but differs in that the light absorbing layer 153a is patterned. Only the cross-sectional view corresponding to Figure 36A is shown here as a representative example.

[0233] 37, the light absorbing layer 153a may cover the third LED stack 43, as with the light absorbing layer 153 described above, and may further cover the upper insulating layer 145 and the third sidewall insulating layer 147, and may also fill the element isolation region ISO3. However, the light absorbing layer 153a may be patterned to have an opening that defines a light emission region. This may reduce optical interference between subpixels to improve contrast, and may reduce loss of light emitted to the upper part through the third LED stack 43 due to absorption by the light absorbing layer 153a.

[0234] FIG. 38 is a schematic cross-sectional view illustrating a display panel 2000c according to still another embodiment of the present disclosure.

[0235] The display panel 2000c according to this embodiment is generally similar to the display panel 2000a described with reference to Figures 36A, 36B, and 36C, but differs in that the light absorbing layer 153b is formed in the region between the subpixels. Here, only the cross-sectional view corresponding to Figure 36A is shown as a representative example.

[0236] 38, the light absorbing layer 153b covers the third LED stack 43 in the same manner as the light absorbing layer 153 described above, and further covers the upper insulating layer 145 and the third sidewall insulating layer 147, and can also fill the element isolation region ISO3. However, the light absorbing layer 153b can be formed to penetrate the second bonding layer 30 and the third bonding layer 40 in the region between the subpixels. This can reduce optical interference between the subpixels and improve contrast.

[0237] Furthermore, the light absorbing layer 153b may be patterned to have openings that define light emission areas, as described with reference to Fig. 37. This may reduce loss of light emitted upward through the third LED stack 43 due to absorption by the light absorbing layer 153b.

[0238] The light absorbing layer 153b may be formed by partially removing the second bonding layer 30 and the third bonding layer 40 in the regions between the sub-pixel regions, and then applying and curing a black material.

[0239] Although the embodiment display panels 2000a, 2000b, 2000c in which light absorbing layers 153, 153a, 153b are added to the display panel 2000 described with reference to Figures 23A, 23B, 23C, and 23D have been described with reference to Figures 36A, 36B, 36C, 37, and 38, the light absorbing layers 153, 153a, 153b can also be added to the display panel 1000 described with reference to Figures 3A, 3B, 3C, and 3D.

[0240] In this embodiment, the light absorbing layers 153, 153a, 153b are illustrated formed on two subpixels, but the light absorbing layers 153, 153a, 153b can also be formed on another subpixel adjacent to these two subpixels. The light absorbing layers 153, 153a, 153b can be in contact with the light absorbing layers covering the adjacent subpixels. Furthermore, the light absorbing layers 153, 153a, 153b can be formed continuously on the displays 2000, 2000a, 2000b, 2000c covering the areas between the subpixels.

[0241] Although various embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments. Furthermore, matters and components described in one embodiment can be applied to other embodiments without departing from the technical idea of ​​the present disclosure. [Explanation of symbols]

[0242] 11 Circuit Board 11a, 11b, 11c, 11d Pads 13 Reflective layer 14 Upper insulating layer 20 1st bonding layer 21a,31a,41a Growth substrate 21b First primary board 23 1st LED stack 23a First conductive type semiconductor layer 23b second conductive type semiconductor layer 23c Ohmic contact semiconductor layer 25 1st transparent electrode 25' Lower Electrode 27 Glue 30 Second bonding layer 31b 2nd temporary board 33 Second LED stack 33a first conductive type semiconductor layer 33b second conductive type semiconductor layer 35 Second transparent electrode 37 Glue 40 3rd bonding layer 41b Third primary board 43 3rd LED stack 43a First conductive type semiconductor layer 43b second conductive type semiconductor layer 45 Third transparent electrode 47 Adhesive 100 Light emitting element 123,133,143 Ohmic electrodes 123a First ohmic electrode 125,135,145 Insulating layer 125a opening 125b opening 127 First sidewall insulating layer 129,129' First through via 131a, 131b, 131c, 131d First connection pad 135a opening 135a' opening 135b opening 137 Second sidewall insulating layer 139,139' Second through via 139 Second Through Via 139' 2nd Through Via 141a, 141b, 141c Second connection pad 143 Third Ohmic Electrode 145a' opening 147 Third sidewall insulating layer 149,149' 3rd Through Via 151a, 151b 3rd connection pad 153, 153a, 153b Light absorbing layer 200 Light emitting element 1000 Display Panel 1000a Smart Watch 1000b VR headset 1000c Augmented Reality Glasses

Claims

1. a circuit board having pads on an upper surface thereof; a plurality of pixel areas aligned on the circuit board; Each of the pixel regions comprises: a first LED stack disposed on the circuit board; a first bonding layer disposed between the first LED stack and the circuit board; a second LED stack disposed on the first LED stack; a third LED stack disposed on the second LED stack; a first through via through the first LED stack and a first bonding layer; a second through via through the second LED stack; and a third through via extending through the third LED stack; The first through via passes through the first LED stack and a first bonding layer and is connected to a pad on the circuit board.

2. 10. The display panel of claim 1, further comprising a reflective layer disposed between the first LED stack and the circuit board.

3. The display panel of claim 2 , wherein the reflective layer is spaced apart from the pads and is located within an area surrounded by the pads on the circuit board below the first LED stack.

4. a second bonding layer disposed between the first LED stack and the second LED stack; a third bonding layer disposed between the second LED stack and the third LED stack; the second through via penetrates the second bonding layer; The display panel of claim 1 , wherein the third through via penetrates the third bonding layer.

5. a first connection pad disposed between the first LED stack and the second LED stack; one of the first connection pads electrically connects one of the first through vias to a first conductive type semiconductor layer of the first LED stack; The display panel of claim 1 , wherein another of the first connection pads electrically connects another of the first through vias to a second conductive type semiconductor layer of the first LED stack.

6. a first ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the first LED stack; The display panel of claim 5 , wherein one of the first connection pads is electrically connected to the first conductive type semiconductor layer of the first LED stack through the first ohmic electrode.

7. a first transparent electrode between the first LED stack and the second LED stack in ohmic contact with the second conductive type semiconductor layer of the first LED stack; The display panel of claim 6 , wherein another one of the first connection pads is electrically connected to the second conductive type semiconductor layer of the first LED stack through the first transparent electrode.

8. a bottom electrode between the first LED stack and the circuit board, the bottom electrode being in ohmic contact with the second conductive type semiconductor layer of the first LED stack; The display panel of claim 6 , wherein another one of the first connection pads is electrically connected to the second conductive type semiconductor layer of the first LED stack through the bottom electrode.

9. The display panel of claim 8 , wherein the lower electrode includes a reflective layer that substantially covers an entire surface of the second conductive type semiconductor layer of the first LED stack.

10. The first through via includes a first through via that penetrates the first LED stack and is electrically connected to the bottom electrode, The display panel of claim 8 , wherein another one of the first connection pads is connected to a first through via electrically connected to the lower electrode.

11. a second connection pad disposed between the second LED stack and the third LED stack, one of the second connection pads electrically connects one of the second through vias to the first conductive type semiconductor layer of the second LED stack; The display panel of claim 5 , wherein another of the second connection pads electrically connects another of the second through vias to the second conductive type semiconductor layer of the second LED stack.

12. a second ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the second LED stack; The display panel of claim 11 , wherein one of the second connection pads is electrically connected to the first conductive type semiconductor layer of the second LED stack through the second ohmic electrode.

13. a second transparent electrode in ohmic contact with the second conductive type semiconductor layer of the second LED stack; The display panel of claim 11 , wherein another of the second connection pads is electrically connected to the second conductive type semiconductor layer of the second LED stack through the second transparent electrode.

14. the second transparent electrode is disposed between the first LED stack and the second LED stack; The second through via includes a second through via that penetrates the second LED stack and is electrically connected to the second transparent electrode, The display panel according to claim 13 , wherein another one of the second connection pads is connected to a second through via electrically connected to the second transparent electrode.

15. a third connection pad disposed on the third LED stack; one of the third connection pads electrically connects one of the third through vias to the first conductive type semiconductor layer of the third LED stack; The display panel of claim 5 , wherein another of the third connection pads electrically connects another of the third through vias to the second conductive type semiconductor layer of the third LED stack.

16. a third ohmic electrode in ohmic contact with the first conductive type semiconductor layer of the third LED stack; The display panel of claim 15 , wherein one of the third connection pads is electrically connected to the first conductive type semiconductor layer of the third LED stack through the third ohmic electrode.

17. a third transparent electrode in ohmic contact with the second conductive type semiconductor layer of the third LED stack; The display panel of claim 15 , wherein another of the third connection pads is electrically connected to the second conductive type semiconductor layer of the third LED stack through the third transparent electrode.

18. the third transparent electrode is disposed between the second LED stack and the third LED stack; The third through via includes a third through via that penetrates the third LED stack and is electrically connected to the third transparent electrode, The display panel according to claim 17 , wherein another one of the third connection pads is connected to a third through via electrically connected to the third transparent electrode.

19. a lower insulating layer disposed between the first LED stack and the second LED stack; an intermediate insulating layer disposed between the second LED stack and the third LED stack; a top insulating layer disposed on the third LED stack, The display panel of claim 1 , wherein the lower insulating layer, the middle insulating layer and the upper insulating layer are disposed in upper regions of the first LED stack, the second LED stack and the third LED stack, respectively.

20. the first LED stack, the second LED stack, and the third LED stack are independently driven; Light generated in the first LED stack is transmitted through the second LED stack and the third LED stack and emitted to the outside, The display panel of claim 1 , wherein light generated in the second LED stack is transmitted through the third LED stack and emitted to the outside.

21. 21. The display panel of claim 20, wherein the circuit board includes active circuits for active matrix driving.

22. In a display device including a display panel, The display panel comprises: a circuit board having pads on an upper surface thereof; a plurality of pixel areas aligned on the circuit board; Each of the pixel regions comprises: a first LED stack disposed on the circuit board; a first bonding layer disposed between the first LED stack and the circuit board; a second LED stack disposed on the first LED stack; a third LED stack disposed on the second LED stack; a first through via through the first LED stack and a first bonding layer; a second through via through the second LED stack; a third through via extending through the third LED stack; The first through via passes through the first LED stack and the first bonding layer and is connected to a pad on the circuit board. Display panel.

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