Semiconductor device

Abstract

To provide a technique capable of securing high ESD resistance and protecting a semiconductor device by an ESD protection circuit of a small area.SOLUTION: A semiconductor device includes: an input / output cell connected between a first power wiring and a first ground wiring; a core logic circuit connected between a second power wiring and a second ground wiring; a first and a second power cell connected between the first power wiring and the first ground wiring; and a third and a fourth power cell connected between the second power wiring and the second ground wiring. Each of the first power cell, the second power cell, the third power cell, and the fourth power cell includes a protection circuit connected between the corresponding power wiring and the corresponding ground wiring, and a bidirectional diode connected between the first ground wiring and the second ground wiring.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and is a technique that is effective when applied to a semiconductor device having an electrostatic protection circuit. [Background technology]

[0002] As shown in JP 2020-161721 A, there is a semiconductor device in which a signal input to an input / output pad electrode from outside the semiconductor device is transferred to an internal circuit (core logic circuit) via an input / output cell including an ESD protection element (also called an ESD: Electro-Static-Discharge) protection circuit) and an input / output logic circuit, and a level shift circuit. Also, as shown in WO 2016 / 203648 A, there is a semiconductor device in which input / output cells and power cells are arranged in an IO region provided along the edge of the periphery of a semiconductor chip, and an internal circuit is provided in a central region surrounded by the IO region of the semiconductor chip.

[0003] One type of ESD test for semiconductor devices is the CDM test, which is a charged device model (CDM method) test that simulates a situation in which the semiconductor device being tested is itself charged and static electricity is discharged from the semiconductor device being tested. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-161721 A [Patent Document 2] International Publication No. 2016 / 203648 Summary of the Invention [Problem to be solved by the invention]

[0005] In a CDM test for a semiconductor device, the input logic circuit and internal circuit may be more likely to be destroyed due to potential differences than the ESD protection circuit.

[0006] An object of the present disclosure is to provide a technique capable of ensuring high ESD resistance and protecting a semiconductor device with an ESD protection circuit having a small area.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of representative aspects of this disclosure is as follows.

[0009] According to one embodiment, a semiconductor device includes an input / output cell connected between a first power supply wiring and a first ground wiring, a core logic circuit connected between a second power supply wiring and a second ground wiring, a first power supply cell and a second power supply cell connected between the first power supply wiring and the first ground wiring, and a third power supply cell and a fourth power supply cell connected between the second power supply wiring and the second ground wiring. Each of the first power supply cell, the second power supply cell, the third power supply cell and the fourth power supply cell includes a protection circuit connected between the corresponding power supply wiring and the corresponding ground wiring, and a bidirectional diode connected between the first ground wiring and the second ground wiring. Effect of the Invention

[0010] According to the semiconductor device of the above embodiment, high ESD resistance can be ensured, and the semiconductor device can be protected by a small-area ESD protection circuit. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an overall layout diagram of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic block diagram of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a schematic layout diagram of the semiconductor device of FIG. [Figure 4]FIG. 4 is a diagram illustrating the effect of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a schematic block diagram of a semiconductor device according to a second embodiment. [Figure 6] FIG. 6 is a schematic layout diagram of the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic block diagram of a semiconductor device according to a first comparative example. [Figure 8] FIG. 8 is a schematic layout diagram of the semiconductor device according to the first comparative example. [Figure 9] FIG. 9 is a schematic block diagram of a semiconductor device according to a second comparative example. [Figure 10] FIG. 10 is a schematic layout diagram of a semiconductor device according to a second comparative example. [Figure 11] FIG. 11 is a diagram for explaining a problem with the semiconductor device according to the first comparative example. [Figure 12] FIG. 12 is a diagram for explaining another problem of the semiconductor device according to the first comparative example. [Figure 13] FIG. 13 is a diagram illustrating a problem with the semiconductor device according to the second comparative example. [Figure 14] FIG. 14 is a diagram illustrating another problem of the semiconductor device according to the second comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the drawings. However, in the following description, the same components are given the same reference numerals and the repeated description may be omitted. Note that the drawings may be shown more diagrammatically than the actual embodiment in order to clarify the description, but they are merely examples and do not limit the interpretation of the present invention. EXAMPLES

[0013] A semiconductor device 10 according to a first embodiment will be described with reference to Figs. 1 to 3. Fig. 1 is an overall layout diagram of the semiconductor device according to the first embodiment. Fig. 2 is a schematic block diagram of the semiconductor device according to the first embodiment. Fig. 3 is a schematic layout diagram of the semiconductor device in Fig. 2. The layout diagram of the dotted line area indicated by V in Fig. 1 is shown in Fig. 3.

[0014] 1, a semiconductor device 10 includes an input / output cell (IOC) 11, a first power cell (IO power cell IOPC) 12 (IO power cell 12A, IO power cell 12B), and a second power cell (core power cell CPC) 13 (core power cell 13A, core power cell 13B) on the periphery of a rectangular semiconductor chip 101 such as made of single crystal silicon. In other words, the IO power cell 12A can be referred to as the first power cell, the IO power cell 12B as the second power cell, the core power cell 13A as the third power cell, and the core power cell 13B as the fourth power cell.

[0015] The region in which the input / output cells 11, the first power supply cells 12, and the second power supply cells 13 are arranged is called the IO region IOR. The IO region IOR is provided along four sides 21, 22, 23, and 24 of the chip end (edge) of the semiconductor chip 101 in a plan view. The four sides 21, 22, 23, and 24 include a first side 21, a third side 23 provided opposite the first side 21, a second side 22 provided between the first side 21 and the third side 23, and a fourth side 24 provided opposite the second side 22.

[0016] The semiconductor device 10 also includes an internal circuit 14 as a core logic circuit (CORE-LOG). A core logic region (also called a central region or a second region) CER in which the internal circuit 14 is arranged is provided in the central portion of the semiconductor chip 101 and is surrounded by an IO region.

[0017] The input / output cell 11 is a region for forming an input / output circuit connected to one input / output pad. The power supply cells 12 and 13 are regions for forming an ESD protection circuit (CESD, ESD) for protecting the semiconductor device 10 from ESD (Electro-Static-Discharge) and noise, and wiring for supplying a power supply potential (VDDIO, VDD) or a ground potential (VSSIO, VSS) to the inside of the chip.

[0018] Since it is necessary to uniformly reduce the power supply impedance, the power supply cells 12 and 13 are disposed in a distributed manner for each I / O cell 11 and are disposed adjacent to each other between the I / O cells 11 .

[0019] The power supply potentials (VDDIO, VDD) include a first power supply potential VDDIO of the input / output cells 11 and a second power supply potential VDD of the internal circuit 14. Similarly, the ground potentials (VSSIO, VSS) include a first ground potential VSSIO of the input / output cells 11 and a second ground potential VSS of the internal circuit 14. The first power supply potential VDDIO can be a potential greater than the second power supply potential VDD (VDDIO>VDD). The first power supply potential VDDIO, the first ground potential VSSIO, the second power supply potential VDD, and the second ground potential VSS are supplied to the input / output cells 11 via the power supply wiring. The second power supply potential VDD and the second ground potential VSS are supplied to the internal circuit 14 via the power supply wiring.

[0020] The IO power cell 12A includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first power supply potential VDDIO to a power supply wiring (first power supply wiring L1). The IO power cell 12B includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first ground potential VSSIO to a power supply wiring (L2: also called first ground wiring). The ESD protection circuit (ESD) can be configured with an N-channel MOS transistor NM.

[0021] The core power cell 13A includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second power supply potential VDD to the power supply wiring (second power supply wiring L3). The core power cell 13B includes an ESD protection circuit (CESD) and a bridge circuit 15, and supplies a second ground potential VSS to the power supply wiring (L4: also called the second ground wiring). The ESD protection circuit (CESD) can be configured with an N-channel MOS transistor NM.

[0022] The ESD protection circuit (ESD) (i.e., the source-drain path of the N-channel MOS transistor NM constituting the ESD protection circuit (ESD)) is connected between a power supply wiring supplied with a first power supply potential VDDIO and a power supply wiring supplied with a first ground potential VSSIO. The ESD protection circuit (CESD) (i.e., the source-drain path of the N-channel MOS transistor NM constituting the ESD protection circuit (CESD)) is connected between a power supply wiring supplied with a second power supply potential VDD and a power supply wiring supplied with a second ground potential VSS.

[0023] The bridge circuit 15 is connected between a power supply wiring supplied with a first ground potential VSSIO and a power supply wiring supplied with a second ground potential VSS, and includes a pair of bidirectional diodes connecting the power supply wiring supplied with the first ground potential VSSIO and the power supply wiring supplied with the second ground potential VSS. The anode of one diode is connected to the power supply wiring supplied with the first ground potential VSSIO, and the cathode is connected to the power supply wiring supplied with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring supplied with the second ground potential VSS, and the cathode is connected to the power supply wiring supplied with the first ground potential VSSIO. The bridge circuit 15 can also be called a bidirectional diode 15.

[0024] The input / output cell 11 incorporates an input / output circuit connected to an input / output terminal (TIO). The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are arranged on the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13, respectively, but may be arranged away from the input / output cell 11, the IO power supply cell 12, and the core power supply cell 13, respectively. The input / output terminal TIO, power supply terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are connected to bonding wires or the like, and are also called input / output pads, power supply pads, and ground pads, respectively.

[0025] The input / output circuit constituting the input / output cell 11 includes diodes D1 and D2 constituting an ESD protection circuit, and an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 as output transistors for transmitting an output signal to a signal wiring connected to the input / output terminal TIO. The input / output circuit further includes an input / output logic circuit IOL including a CMOS inverter that receives an input signal input from the input / output terminal TIO via the signal wiring, and a level shifter circuit LSC. The input signal input from the input / output terminal TIO via the signal wiring is input to the level shifter circuit LSC via the input / output logic circuit IOL, level-converted by the level shifter circuit LSC, and supplied to the internal circuit 14. Meanwhile, the signal output from the internal circuit 14 is input to the level shifter circuit LSC, level-converted, supplied to the input / output logic circuit IOL, and output as an output signal from an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 to the input / output terminal TIO. The P-channel transistor Q1 and the N-channel transistor Q2 can be configured as MOS transistors.

[0026] The source-drain path of the P-channel transistor Q1 is connected between the power supply wiring of the first power supply potential VDDIO and the signal wiring from the input / output terminal TIO, and the source-drain path of the N-channel transistor Q2 is connected between the signal wiring and the ground wiring of the first ground potential VSSIO. The anode of the diode D1 is connected to the signal wiring from the input / output terminal TIO, and the cathode is connected to the power supply wiring of the first power supply potential VDDIO. The anode of the diode D2 is connected to the ground wiring of the first ground potential VSSIO, and the cathode is connected to the signal wiring from the input / output terminal TIO. The diode D1 flows a surge current from the input / output terminal TIO through the signal wiring and the power supply wiring of the first power supply potential VDDIO toward the power supply terminal VDDIO, and the diode D2 flows a surge current from the ground terminal TVDDIO through the ground wiring of the first ground potential VSSIO and the signal wiring toward the input / output terminal TIO. The output circuit may be a so-called open drain type that does not have the P-channel transistor Q1. In addition, the input / output circuit may not have either the output circuit or the input circuit.

[0027] The input / output logic circuit IOL is connected between a power supply wiring of the first power supply potential VDDIO and a ground wiring of the first ground potential VSSIO. The level shifter circuit LSC is connected between the power supply wiring of the first power supply potential VDDIO and the power supply wiring to which the second power supply potential VDD is supplied, and the power supply wiring to which the second ground potential VSS is supplied.

[0028] The power supply cells 12A and 13A have ESD protection circuits (CESD, ESD) corresponding to the power supply terminals (TVDDIO, TVDD), and the power supply cells 12B and 13B have ESD protection circuits (CESD, ESD) corresponding to the ground terminals (TVSSIO, TVSS).

[0029] The first power supply potential VDDIO is, for example, 1.8 V (or 3.3 V), and the second power supply potential VDD is, for example, 0.8 V. The ground terminals (TVSSIO, TVSS) are, for example, 0.0 V.

[0030] For example, when the first power supply potential VDDIO is 1.8 V and the second power supply potential VDD is 0.8 V, 1) The output circuit transistors Q1 and Q2 and the input / output logic circuit IOL are composed only of MOSFETs with a withstand voltage of 1.8V (also called 1.8V-MOS). 2) The internal circuit 14 is composed only of MOSFETs (also called core MOS) having a withstand voltage of 0.8V. 3) The level shifter circuit LSC is composed of a mixture of 1.8V-MOS and core MOS. 4) The core power supply cells 13A and 13B protect the core MOS of the internal circuit 14 and the core MOS of the level shifter circuit LSC. 5) The IO power cells 12A and 12B protect the transistors Q1 and Q2 of the output circuit and the 1.8V-MOS of the input / output logic circuit IOL.

[0031] 3 shows the layout relationship between the IO power cells 12A, 12B, one input / output cell 11, and core power cells 13A, 13B arranged in the IO region IOR, and the internal circuit 14 arranged in the core logic region. As shown in Fig. 3, the IO power cells 12A, 12B, one input / output cell 11, and core power cells 13A, 13B are arranged in this order in the IO region IOR, and the internal circuit 14 is arranged adjacent to the IO region IOR in the core logic region CER above the IO region IOR.

[0032] 4 is a diagram for explaining the effect of the semiconductor device according to the first embodiment. In this case, in a CDM test, which is one of electrostatic tests, a case where a current flows into a capacitance component Cpkg that is parasitic on a power supply wiring to which a second ground potential VSS is supplied is considered. In FIG. 4, a first CDM test on an input / output terminal TIO and a second CDM test on a power supply terminal TVDD are assumed.

[0033] 1) In the first CDM test, there are a first charging path PT1 and a second charging path PT2 as shown below. First charging path PT1: TIO->D1->power supply wiring of first power supply potential VDDIO->ESD of 12B->power supply wiring supplied with first ground potential VSSIO->15 of 12B->power supply wiring supplied with second ground potential VSS->Cpkg. Second charging path PT2: TIO->D1->power supply wiring of first power supply potential VDDIO->ESD at 12A->power supply wiring supplied with first ground potential VSSIO->15 at 12A->power supply wiring supplied with second ground potential VSS->Cpkg.

[0034] 2) In the second CDM test, there are a third charging path PT3 and a fourth charging path PT4, as shown below. Third charging path PT3: TVDD->power supply wiring supplied with second power supply potential VDD->CESD at 13A->power supply wiring supplied with second ground potential VSS->Cpkg. Fourth charging path PT4: TVDD->power supply wiring supplied with second power supply potential VDD->CESD of 13B->power supply wiring supplied with second ground potential VSS->Cpkg.

[0035] That is, the semiconductor device 10 of the first embodiment has the following features.

[0036] 1) The bidirectional diode 15 between the power supply wiring to which the first ground potential VSSIO is supplied and the power supply wiring to which the second ground potential VSS is supplied is disposed in each of the IO power supply cells 12A and 12B and the core power supply cells 13A and 13B.

[0037] 2) In the first CDM test for the input / output terminal TIO, a discharge path (PT1, 2) can be easily formed from the input / output terminal TIO to the power supply wiring supplied with the second ground potential VSS to which the capacitive component Cpkg is parasitic, regardless of the layout arrangement of the input / output cell 11 and the core power supply cell 13B.

[0038] 3) As a result of 2 above, the CDM current flowing from the input / output terminal TIO to the power supply wiring supplied with the second ground potential VSS is less susceptible to the parasitic resistance Rvddio of the power supply wiring supplied with the first power supply potential VDDIO and the parasitic resistance Rvss of the power supply wiring supplied with the second ground potential VSS, thereby making it possible to avoid destruction of the input / output logic circuit IOL due to the potential difference.

[0039] 4) An ESD protection circuit (CESD) is arranged in each of the core power cells 13A and 13B, so that even in the second CDM test for the power terminal TVDD, a sufficient discharge path (PATH3, 4) can be secured from the power terminal TVDD to the power wiring supplied with the second ground potential VSS to which the capacitive component Cpkg is parasitic.

[0040] 5) As a result of 4 above, damage to the internal circuit 14 due to potential differences can also be avoided.

[0041] 3, the bidirectional diodes 15 of the IO power cells 12A, 12B are arranged on the side of the IO power cells 12A, 12B facing the internal circuit 14 (the upper end portion in FIG. 3). On the other hand, the bidirectional diodes 15 of the core power cells 13A, 13B are arranged not on the side of the core power cells 13A, 13B facing the internal circuit 14, but on the side of the core power cells 13A, 13B facing the chip edge side of the semiconductor chip 101 (the side of the four sides 21, 22, 23, 24 of the chip end in FIG. 1) (the lower end portion in FIG. 3). The locations of these bidirectional diodes 15 are the most efficient layout arrangement with the least effect of parasitic resistance in forming a discharge path between the power wiring supplied with the first ground potential VSSIO and the power wiring supplied with the second ground potential VSS. EXAMPLES

[0042] Next, a semiconductor device 10S according to a second embodiment will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a schematic block diagram of the semiconductor device according to the second embodiment. Fig. 6 is a schematic layout diagram of the semiconductor device in Fig. 5.

[0043] The semiconductor device 10S according to the second embodiment shown in FIG. 5 is different from the semiconductor device 10 according to the first embodiment shown in FIG. 2 in the following points. 1) The power supply wiring (L1) of the first power supply potential VDDIO is separated, and a power supply wiring (also called a fourth power supply wiring (L5). The power supply wiring of the first power supply potential VDDIO can be called a third power supply wiring (L1)) is provided to supply a power supply potential VDDIOL for the input / output logic circuit IOL. 2) The power supply terminal TVDDIOL is connected to the power supply potential VDDIOL. 3) An IO power cell (fifth power cell) 12C serving as an IO power cell IOPC is connected between the power supply potential VDDIOL and the power supply wiring to which the second ground potential VSS is supplied.

[0044] It should be noted that the basic configuration of the IO power supply cell 12C is the same as those of the IO power supply cells 12A and 12B.

[0045] 6, the IO power cell 12C is disposed in an area between the IO power cell 12B and the input / output cell 11 in the IO area IOR. A bidirectional diode 15 is also disposed in the added IO power cell 12C, which contributes to the formation of a discharge path leading to the power wiring to which the second ground potential VSS is supplied.

[0046] In the input / output cell 11, power supply wiring for supplying a power supply potential VDDIOL to the upper half region of the input / output cell 11 is laid out in accordance with the input / output logic circuit IOL.

[0047] In the IO power cell 12C, a power supply wiring to which a power supply potential VDDIOL is supplied and a power supply wiring to which a second ground potential VSS is supplied are laid out in the vertical direction.

[0048] For this reason, the bidirectional diode 15 in the IO power cell 12C is arranged on the side (the lower end portion in FIG. 3) facing the chip edge side (the side of the four sides 21, 22, 23, and 24 of the chip end in FIG. 1) of the semiconductor chip 101. For this reason, the arrangement of the bidirectional diode 15 in the IO power cell 12C, like the arrangement of the bidirectional diodes 15 in the core power cells 13A and 13B, is the most efficient layout arrangement in terms of forming a discharge path between the power wiring supplied with the first ground potential VSSIO and the power wiring supplied with the second ground potential VSS.

[0049] With this configuration, it is possible to obtain the same effects as in the embodiment 1. Furthermore, since it is possible to reduce the propagation of noise in the power supply wiring of the first power supply potential VDDIO to the input / output logic circuit IOL, it is possible to improve the performance (speed) of the input / output logic circuit IOL.

[0050] (Comparative Example) Fig. 7 is a schematic block diagram of a semiconductor device according to Comparative Example 1. Fig. 8 is a schematic layout diagram of the semiconductor device according to Comparative Example 1. Fig. 9 is a schematic block diagram of a semiconductor device according to Comparative Example 2. Fig. 10 is a schematic layout diagram of the semiconductor device according to Comparative Example 2.

[0051] 7 and 8, the semiconductor device 10r of Comparative Example 1 is configured such that the bidirectional diode 15 is not provided in the IO power cells 12A and 12B and the core power cell 13A, as compared to the semiconductor device 10 of FIG. 2. In addition, in the core power cell 13A of the semiconductor device 10r, the ESD protection circuit (CESD) is connected between the power wiring supplied with the second power supply potential VDD and the power wiring supplied with the first ground potential VSSIO. In the core power cell 13B of the semiconductor device 10r, the ESD protection circuit (CESD) is connected between the power wiring supplied with the first power supply potential VDDIO and the power wiring supplied with the second ground potential VSS.

[0052] 9 and 10, in the semiconductor device 10r1 of Comparative Example 2, the ESD protection circuit (CESD) of the core power cell 13A is connected between the power supply wiring to which the second power supply potential VDD is supplied and the power supply wiring to which the second ground potential VSS is supplied, in comparison with the semiconductor device 10r1 of Comparative Example 1. The core power cell 13B of the semiconductor device 10r1 is configured not to be provided with an ESD protection circuit (CESD).

[0053] 11 is a diagram for explaining a problem of the semiconductor device according to Comparative Example 1. FIG 12 is a diagram for explaining another problem of the semiconductor device according to Comparative Example 1.

[0054] As shown in Fig. 11, in the CDM test, which is one of the electrostatic tests, a current flows from the input / output terminal TIO to the discharge path (PT1r, PT2r) to the power supply wiring supplied with the second ground potential VSS, which has a parasitic capacitance component Cpkg. When the protected circuit becomes weaker with the miniaturization of the semiconductor device structure, a problem has been found in that the input / output logic circuit IOL is destroyed by the potential difference dV1 in the CDM test due to the influence of the parasitic resistance Rvddio of the power supply wiring supplied with the first ground potential VSSIO, the parasitic resistance Rvssio of the power supply wiring supplied with the first ground potential VSSIO, and the parasitic resistance Rvss of the power supply wiring supplied with the second ground potential VSS. To overcome this problem in Comparative Example 1, it is necessary to reduce the parasitic resistance Rvss of the power supply wiring to which the second ground potential VSS is supplied by increasing the cell width of the core power supply cell 13B, while also reducing the parasitic resistance Rvssio of the power supply wiring to which the first ground potential VSSIO is supplied by imposing strict layout constraints between the input / output cell 11 and the core power supply cell 13B. In this case, it was also found that there is a problem that the chip size of the semiconductor device 10r increases and design freedom is hindered.

[0055] 12, the ESD protection circuit (CESD) in the core power cell 13A is connected between the power wiring to which the second power potential VDD is supplied and the power wiring to which the first ground potential VSSIO is supplied. Therefore, in a CDM test on the power terminal TVDD, as shown by a discharge path PT3r, a current flows from the power terminal TVDD through the bidirectional diode 15 to the capacitance component Cpkg that is parasitic on the power wiring to which the second ground potential VSS is supplied. In addition, the potential difference dV2 generated by the bidirectional diode 15 also stresses the internal circuit 14, and a problem has arisen in that the internal circuit 14 is easily destroyed by the potential difference dV2. In particular, the internal circuit 14 uses multiple thin-film MOS transistors with relatively thin gate oxide films, and is therefore susceptible to potential difference stress.

[0056] 13 is a diagram for explaining a problem of the semiconductor device according to Comparative Example 2. FIG 14 is a diagram for explaining another problem of the semiconductor device according to Comparative Example 2.

[0057] As shown in FIG. 13, in the comparative example 2, similar to the description of the comparative example 1 in FIG. 11, a discharge path PT2r is formed, so that the input / output logic circuit IOL is destroyed by the potential difference dV1 in the CDM test, similar to the comparative example 1. Also, as shown in FIG. 14, in the comparative example 2, a discharge path PT4r is formed from the power supply terminal TVDD to the capacitance component Cpkg in the CDM test to the power supply terminal TVDD. In the semiconductor device 10r1 of the comparative example 2, the ESD protection circuit (CESD) is arranged only in the core power supply cell 13A, and the ESD protection circuit (CESD) does not exist in the core power supply cell 13B. Therefore, as shown in FIG. 13, in the CDM test to the power supply terminal TVDD, when the discharge performance of the ESD protection circuit (CESD) becomes insufficient and the protected circuit becomes weak with the miniaturization of the semiconductor device structure, there is also a problem that the internal circuit 14 is easily destroyed by the potential difference dV3. If the number of ESD protection circuits (CESD) in the core power cell 13A is small, the ESD protection circuit is also more susceptible to the influence of the parasitic resistance Rvss of the vertical wiring provided vertically between the ESD protection circuit (CESD) and the power wiring to which the second ground potential VSS is supplied.

[0058] According to the first and second embodiments, the issues and problems described in the first and second comparative examples can be avoided, so that high ESD resistance can be ensured and the semiconductor device can be protected by a small-area ESD protection circuit.

[0059] While the present disclosure has been specifically described above based on the embodiments, it goes without saying that the present disclosure is not limited to the above embodiments and can be modified in various ways. [Explanation of symbols]

[0060] 10: Semiconductor device 11: Input / Output Cell 12, 12A, 12B: Power cells for IO 13, 13A, 13B: Core power cells 14: Internal circuit 15: Bridge circuit (bidirectional diode) ESD,CESD:ESD protection circuit

Claims

1. a first power supply wiring to which a first power supply potential is supplied; a second power supply wiring to which a second power supply potential is supplied; a first ground wiring to which a first ground potential is supplied; a second ground wiring to which a second ground potential is supplied; an input / output cell connected between the first power supply wiring and the first ground wiring; a core logic circuit connected between the second power supply wiring and the second ground wiring; a first power supply cell and a second power supply cell connected between the first power supply wiring and the first ground wiring; a third power supply cell and a fourth power supply cell connected between the second power supply wiring and the second ground wiring; having Each of the first power cell, the second power cell, the third power cell, and the fourth power cell is a protection circuit connected between a corresponding power supply line and a corresponding ground line; a bidirectional diode connected between the first ground wiring and the second ground wiring, Semiconductor device.

2. 2. The semiconductor device according to claim 1, the bidirectional diodes of the first power supply cell and the second power supply cell are disposed between the core logic circuit and the protection circuit in a plan view; the bidirectional diodes of the third power cell and the fourth power cell are disposed on an end side of a semiconductor chip such that, in a plan view, the protection circuit is disposed between the core logic circuit and the bidirectional diodes.

3. 3. The semiconductor device according to claim 2, the input / output cell includes an output transistor and an input / output logic circuit; The first power supply wiring is a third power supply wiring connected to the output transistor; a fourth power supply wiring separated from the third power supply wiring and connected to the input / output logic circuit; the input / output logic circuit is connected between the fourth power supply wiring and the first ground wiring; a fifth power supply cell connected between the fourth power supply wiring and the first ground wiring; The fifth power cell is a protection circuit connected between the fourth power supply wiring and the first ground wiring; a bidirectional diode connected between the first ground wiring and the second ground wiring.

4. 4. The semiconductor device according to claim 3, the bidirectional diode of the fifth power supply cell is disposed on an end side of a semiconductor chip such that, in a plan view, the protection circuit of the fifth power supply cell is disposed between the core logic circuit and the bidirectional diode.

5. 3. The semiconductor device according to claim 2, a first power supply cell, a second power supply cell, an input / output cell, a third power supply cell, and a fourth power supply cell, which are arranged in this order between the core logic circuit and the end of the semiconductor chip in a planar view.

6. 5. The semiconductor device according to claim 4, a semiconductor device, wherein, in a planar view, the first power cell, the second power cell, the fifth power cell, the input / output cell, the third power cell, and the fourth power cell are arranged in this order between the core logic circuit and the end of the semiconductor chip.

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