Semiconductor device

Abstract

To stabilize voltage-withstanding of a semiconductor device.SOLUTION: A field plate electrode FP and a gate electrode GE are formed inside a plurality of trenches TR1. An outer peripheral trench TR2 surrounds the plurality of trenches TR1 in plan view. A field plate electrode FP (lead-out portion FPa) is formed inside the outer peripheral trench TR2. The outer peripheral trench TR2 has an extension portion TR2a extending in a Y direction, an extension portion TR2b extending in an X direction, and a corner portion TR2c that extends in a direction different from the Y direction and the X direction in the plan view and connects the extension portion TR2a and the extension portion TR2b to each other. In the Y direction, an interval L2 between an end portion 10 of a nearest trench TR1 which is nearest to the extension portion TR2a and the extension portion TR2b is longer than an interval L3 between the end portions 10 of the other trenches TR1 and the extension portion TR2b.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a gate electrode and a field plate electrode inside a trench. [Background technology]

[0002] In a semiconductor device having a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure in which a gate electrode is embedded inside a trench is applied. As a type of trench gate structure, a split gate structure has been developed in which a field plate electrode is formed in the lower part of the trench and a gate electrode is formed in the upper part of the trench. A source potential is supplied to the field plate electrode from a source electrode. By expanding a depletion layer in the drift region by this field plate electrode, it becomes possible to increase the concentration of the drift region and to reduce the resistance of the drift region.

[0003] In addition, a structure for improving the breakdown voltage is provided on the periphery of the semiconductor device. For example, in Patent Document 1, a peripheral trench is formed so as to surround a cell region in which multiple MOSFETs are formed. A field plate electrode is also formed inside the peripheral trench. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-82770 Summary of the Invention [Problem to be solved by the invention]

[0005] The peripheral trench extends in the X and Y directions in plan view so as to surround the cell region. However, compared to the planar portion of the peripheral trench which is independent in the X and Y directions, in the corner portion where the peripheral trench in the X direction intersects with the peripheral trench in the Y direction, the depletion layer extending from both the X and Y directions and the depletion layer extending from the end of the trench in the cell region are likely to overlap locally. Therefore, the charge balance is biased, and phenomena such as partial depletion or electric field concentration are likely to occur. In other words, there is a problem that the breakdown voltage is likely to decrease near the corner portion.

[0006] The main objective of the present application is to improve the breakdown voltage around the peripheral trench by reducing the overlap of depletion layers around the corners where the X-direction peripheral trench and the Y-direction peripheral trench intersect, thereby stabilizing the breakdown voltage of the semiconductor device.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief outline of a representative embodiment of the present invention will be described below.

[0009] a first field plate electrode formed in the first trench and electrically insulated from the semiconductor substrate; a first field plate electrode formed above the first field plate electrodes and electrically insulated from the semiconductor substrate and the first field plate electrodes; a second field plate electrode formed in the first trench and electrically insulated from the semiconductor substrate and the first field plate electrodes; a second field plate electrode formed in the second trench and electrically insulated from the semiconductor substrate and the first field plate electrodes; The peripheral trench has a first extension portion extending in the first direction, a second extension portion extending in the second direction, and a corner portion extending in a direction different from the first direction and the second direction in a plan view and connecting the first extension portion and the second extension portion to each other. The plurality of trenches have a first trench closest to the first extension portion in the second direction, and a second trench next closest to the first extension portion in the second direction after the first trench. The first trench has a first end portion located near the second extension portion in the first direction. The second trench has a second end portion located near the second extension portion in the first direction. In the first direction, the distance between the first end portion and the second extension portion is longer than the distance between the second end portion and the second extension portion.

[0010] a first field plate electrode formed in the first trench and electrically insulated from the semiconductor substrate; a first field plate electrode formed above the first field plate electrodes and electrically insulated from the semiconductor substrate and the first field plate electrodes; a second field plate electrode formed in the first trench and electrically insulated from the semiconductor substrate and the first field plate electrodes; a second field plate electrode formed in the second trench and electrically insulated from the semiconductor substrate and the first field plate electrodes; The peripheral trench has a first extension portion extending in the first direction, a second extension portion extending in the second direction, and a corner portion extending in a direction different from the first direction and the second direction in a plan view and connecting the first extension portion and the second extension portion to each other. The plurality of trenches have a first trench closest to the first extension portion in the second direction, and a second trench next closest to the first extension portion in the second direction after the first trench. The first trench has a first end portion located near the second extension portion in the first direction. The second trench has a second end portion located near the second extension portion in the first direction. The shape of the first end portion is different from the shape of the second end portion.

[0011] A semiconductor device according to one embodiment includes a semiconductor substrate having a first conductivity type and an upper surface and a lower surface, a plurality of trenches formed in the semiconductor substrate to extend from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate to a predetermined depth, the plurality of trenches extending in a first direction in a plan view and adjacent to each other in a second direction perpendicular to the first direction in a plan view, a plurality of first field plate electrodes formed within the plurality of trenches and electrically insulated from the semiconductor substrate, and a plurality of first field plate electrodes formed above the plurality of first field plate electrodes and electrically insulated from the semiconductor substrate and the plurality of first field plate electrodes. The semiconductor device includes a plurality of first gate electrodes each electrically insulated from a plate electrode, a peripheral trench formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate and extending in the first direction and the second direction so as to surround the plurality of trenches in a plan view, a second field plate electrode formed inside the peripheral trench and electrically insulated from the semiconductor substrate, and a first impurity region formed in the semiconductor substrate between the plurality of trenches and the peripheral trench and having a second conductivity type opposite to the first conductivity type. The peripheral trench has a first extension portion extending in the first direction, a second extension portion extending in the second direction, and a corner portion extending in a direction different from the first direction and the second direction in a plan view and connecting the first extension portion and the second extension portion to each other. The plurality of trenches includes a first trench closest to the first extension portion in the second direction. A second impurity region is formed in the semiconductor substrate between the corner portion and the first trench, and the impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region. Effect of the Invention

[0012] According to one embodiment, the breakdown voltage of the semiconductor device can be stabilized. [Brief description of the drawings]

[0013] [Figure 1]1 is a plan view showing a semiconductor device in a first embodiment. [Diagram 2] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Diagram 5] 4 is a plan view of a main portion showing the periphery of a corner portion of the peripheral trench in the first embodiment. FIG. [Figure 6] 4 is a plan view of a main portion showing a depletion layer spreading around a corner portion of the peripheral trench in the first embodiment. FIG. [Figure 7] 1 is a graph showing the results of measurements made by the inventors of the present application. [Figure 8] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] 11 is a plan view of a main portion showing the periphery of a corner portion of a peripheral trench in embodiment 2. FIG. [Figure 18] 11 is a plan view of a main portion showing a depletion layer spreading around a corner portion of a peripheral trench in the second embodiment. FIG. [Figure 19] 13 is a plan view of a main portion showing the periphery of a corner portion of a peripheral trench in embodiment 3. FIG. [Figure 20] 13 is a plan view of a main portion showing a depletion layer spreading around a corner portion of a peripheral trench in embodiment 3. FIG. [Figure 21] FIG. 11 is a cross-sectional view showing a semiconductor device in a third embodiment. [Figure 22] 13 is a plan view of a main portion showing the periphery of a corner portion of a peripheral trench in embodiment 4. FIG. [Figure 23] 13 is a plan view of a main portion showing a depletion layer spreading around a corner portion of a peripheral trench in embodiment 4. FIG. [Figure 24] FIG. 13 is a plan view of a main portion showing the periphery of a corner portion of a peripheral trench in the study example. [Diagram 25] FIG. 13 is a plan view of a main portion showing a depletion layer spreading around a corner portion of a peripheral trench in the study example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0015] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect with each other and are perpendicular to each other. In this application, the Z-direction is described as the up-down direction, height direction, or thickness direction of a structure. In addition, expressions such as "plan view" or "planar view" used in this application mean that a surface formed by the X-direction and the Y-direction is a "plane" and this "plane" is viewed from the Z-direction.

[0016] (Embodiment 1) <Structure of Semiconductor Device> A semiconductor device 100 according to a first embodiment will be described below with reference to Figures 1 to 7. The semiconductor device 100 includes a MOSFET having a trench gate structure as a semiconductor element. The MOSFET according to the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode FP inside a trench TR1.

[0017] FIG. 1 is a plan view of a semiconductor chip which is a semiconductor device 100. FIG. 2 and FIG. 3 are plan views of a main part in which a region 1A shown in FIG. 1 is enlarged. FIG. 3 shows the lower structure of FIG. 2, and mainly shows a trench gate structure formed in a semiconductor substrate SUB. The positions of holes CH1, CH2, and CH3 shown by dashed lines in FIG. 2 coincide with the positions of holes CH1, CH2, and CH3 shown in FIG. 3. FIG. 4 is a cross-sectional view taken along lines AA and BB shown in FIG. 2 and FIG. 3.

[0018] 5 and 6 are enlarged views of the periphery of the corner portion TR2c of the peripheral trench TR2 shown in Fig. 3. A main feature of the present application is the structure around the corner portion TR2c, which will be described in detail later.

[0019] 1 shows a wiring pattern formed mainly above a semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and an outer periphery region OR surrounding the cell region CR in a plan view. In the cell region CR, main semiconductor elements such as a plurality of MOSFETs are formed. The outer periphery region OR is used to connect a gate wiring GW to a gate electrode GE and to form an outer periphery trench TR2 that functions as a termination region.

[0020] As shown in FIG. 1 and FIG. 2, most of the cell region CR is covered with the source electrode SE. In plan view, the gate wiring GW surrounds the source electrode SE in plan view. Although not shown here, the source electrode SE and the gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and the gate wiring GW exposed in the opening become the source pad SP and the gate pad GP. By connecting an external connection member to the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring board, or the like. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clip made of a copper plate.

[0021] 3, a plurality of trenches TR1 are formed in the semiconductor substrate SUB in the cell region CR. The plurality of trenches TR1 are formed in stripes, each extending in the Y direction, and adjacent to each other in the X direction.

[0022] 4, inside the trench TR1, a field plate electrode FP is formed in the lower part of the trench TR1, and a gate electrode GE is formed in the upper part of the trench TR1. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR1.

[0023] A part of the field plate electrode FP forms an extension portion FPa. The field plate electrode FP forming the extension portion FPa is formed inside the trench TR1 not only in the lower portion of the trench TR1 but also in the upper portion of the trench TR1.

[0024] As shown in FIG. 3, a peripheral trench TR2 is formed in the semiconductor substrate SUB in the peripheral region OR. In the X direction, the trenches TR1 and the peripheral trench TR2 are arranged at the same pitch. The width of the peripheral trench TR2 is the same as that of the trench TR1. The peripheral trench TR2 extends in the Y direction and the X direction so as to surround the trenches TR1 in a plan view. The peripheral trench TR2 has a corner portion TR2c at a portion where a portion extending in the Y direction intersects with a portion extending in the X direction. A field plate electrode FP (lead portion FPa) is formed inside the peripheral trench TR2.

[0025] Although two outer periphery trenches TR2 are illustrated here, the number of outer periphery trenches TR2 may be one, or three or more.

[0026] A hole CH3 is formed on the lead-out portion FPa in each of the cell region CR and the outer peripheral region OR. The lead-out portion FPa is electrically connected to the source electrode SE through the hole CH3. In the outer peripheral region OR, a hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW through the hole CH2.

[0027] The cross-sectional structure of the semiconductor device 100 will be described below with reference to FIG.

[0028] 2 and 3 are substantially the same as the cross-sectional view taken along line BB, except that the trench reference symbol TR2 is different. Therefore, in the following, the explanation of the cross-sectional view taken along line BB also serves as the explanation of the cross-sectional view taken along line CC.

[0029] As shown in FIG. 4, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In that case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0030] An n-type drain region ND is formed in the lower part of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated. The drain region ND and the drain electrode DE are formed across the cell region CR and the peripheral region OR. A drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0031] A plurality of trenches TR1 are formed in the semiconductor substrate SUB, each of which extends from an upper surface TS of the semiconductor substrate SUB toward a lower surface BS of the semiconductor substrate SUB to a predetermined depth. The depth of each trench TR1 is, for example, 5 μm or more and 10 μm or less. Inside the trench TR1, a field plate electrode FP is formed on the lower part of the trench TR1 via an insulating film IF1. Also, inside the trench TR1, a gate electrode GE is formed above the field plate electrode FP via a gate insulating film GI. The field plate electrode FP and the gate electrode GE are each made of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced.

[0032] The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. The gate insulating film GI is formed inside the trench TR1 on the insulating film IF1. The insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the insulating film IF1. In addition, the gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB, with the gate insulating film GI and the insulating film IF2 interposed therebetween.

[0033] The insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These insulating films electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from one another.

[0034] The insulating films IF1, IF2, and gate insulating film GI are made of, for example, silicon oxide films. The thickness of the insulating film IF1 is thicker than the thicknesses of the insulating film IF2 and the gate insulating film GI. Inside the trench TR1, the thickness of the insulating film IF1 is, for example, not less than 400 nm and not more than 600 nm. Inside the trench TR1, the thickness of each of the insulating film IF2 and the gate insulating film GI is, for example, not less than 50 nm and not more than 100 nm. These thicknesses are measured in the X direction.

[0035] A p-type body region PB is formed in the semiconductor substrate SUB, extending from an upper surface TS of the semiconductor substrate SUB toward a lower surface BS of the semiconductor substrate SUB to a predetermined depth. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR1 from the upper surface TS of the semiconductor substrate SUB. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0036] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR1. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less.

[0037] A hole CH1 is formed in the interlayer insulating film IL. The hole CH1 penetrates the interlayer insulating film IL and the source region NS and reaches the body region PB. At the bottom of the hole CH1, a high-concentration diffusion region PR is formed in the body region PB. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The high-concentration diffusion region PR is provided mainly to reduce contact resistance with the source electrode SE and to prevent latch-up.

[0038] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR through a hole CH1, and supplies a source potential to these impurity regions.

[0039] As shown in the BB cross section of Fig. 4, a part of the field plate electrode FP forms the lead-out portion FPa of the field plate electrode FP. The position of the upper surface of the insulating film IF1 in contact with the lead-out portion FPa is higher than the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the lead-out portion FPa. An insulating film IF2 is formed on the side surface of the lead-out portion FPa. In addition, a body region PB is formed in the semiconductor substrate SUB in contact with the trench TR1 in which the lead-out portion FPa is formed, but a source region NS is not formed in this body region PB.

[0040] 4, a hole CH3 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and reaches the lead-out portion FPa. The source electrode SE is electrically connected to the lead-out portion FPa through the hole CH3, and supplies a source potential to the field plate electrode FP.

[0041] Although not shown here, a hole CH2 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and reaches the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE through the hole CH2 and supplies a gate potential to the gate electrode GE.

[0042] The source electrode SE is also embedded in the holes CH1 and CH3. The gate wiring GW is also embedded in the hole CH2. The source electrode SE and the gate wiring GW are made of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film, and the conductive film is, for example, an aluminum alloy film with added copper or silicon.

[0043] The source electrode SE and the gate wiring GW may be composed of a plug layer filling the inside of the holes CH1, CH2, and CH3, and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is composed of the barrier metal film and the conductive film. The plug layer is composed of a laminated film of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0044] <Main features of the first embodiment> Fig. 5 is a plan view of a main portion showing the periphery of a corner portion TR2c of the peripheral trench TR2, and Fig. 6 shows a depletion layer spreading around the corner portion TR2c.

[0045] 5, the peripheral trench TR2 has an extension portion TR2a extending in the Y direction, an extension portion TR2b extending in the X direction, and a corner portion TR2c connecting the extension portion TR2a and the extension portion TR2b to each other. The corner portion TR2c extends in a direction different from the Y direction and the X direction in a plan view, for example, extends in a direction inclined at an angle of 45 degrees from the Y direction and the X direction.

[0046] If such a corner portion TR2c is not provided, the extension portion TR2a and the extension portion TR2b are connected at a right angle. Then, at the right angle, the thickness of the insulating film IF1 is likely to vary, and the field plate electrode FP is likely to be embedded poorly. In addition, since the distance from the right angle to the trench TR1 is long, the depletion layer spreading from the right angle does not easily reach the depletion layer from the trench TR1 closest to the extension portion TR2a. The portion where the depletion layer does not spread in this way causes a partial decrease in the breakdown voltage. Therefore, in order to prevent such problems from occurring, it is preferable that the outer peripheral trench TR2 is provided with a corner portion TR2c.

[0047] In the following description, when describing the periphery of the corner portion TR2c as shown in Figures 5 and 6, the trench TR1 closest to the extension portion TR2a in the X direction will be referred to as the "closest trench TR1", and the trenches TR1 other than the closest trench TR1 will be referred to as the "other trenches TR1". Here, as the other trench TR1, a trench TR1 adjacent to the closest trench TR1 on the opposite side to the extension portion TR2a in the X direction will be exemplified. In other words, as the other trench TR1, a trench TR1 next closest to the extension portion TR2a in the X direction after the closest trench TR1 will be exemplified.

[0048] In addition, when explaining the depletion layer as shown in Figure 6, the depletion layer spreading from the field plate electrode FP inside trench TR1 to the drift region NV is sometimes referred to as the "depletion layer from trench TR1," and the depletion layer spreading from the field plate electrode FP inside peripheral trench TR2 to the drift region NV is sometimes referred to as the "depletion layer from peripheral trench TR2."

[0049] As shown in FIG. 5, each of the trenches TR1 has an end 10 located near the extension TR2b in the Y direction. However, in the Y direction, the position of the end 10 of the nearest trench TR1 is set back by a distance L1 from the position of the end 10 of the other trenches TR1. In other words, in the Y direction, the distance (spacing) L2 between the end 10 of the nearest trench TR1 and the extension TR2b is longer than the distance (spacing) L3 between the end 10 of the other trench TR1 and the extension TR2b. In further words, in the Y direction, the end 10 of the nearest trench TR1 is farther away from the extension TR2b than the end 10 of the other trenches TR1.

[0050] The reason for this will be described below in comparison with a study example. Figures 24 and 25 show a semiconductor device as a study example that was studied by the present inventors.

[0051] 24, in the examined example, the distance L3 between the end 10 of the nearest trench TR1 and the extension portion TR2b in the Y direction is the same as the distance L3 between the end 10 of another trench TR1 and the extension portion TR2b. In this case, as shown in FIG 25, the depletion layer spreads from the trench TR1 and the peripheral trench TR2, but there is an "excess region" where the depletion layer from the corner portion TR2c and its periphery overlaps with the depletion layer from the nearest trench TR1 over a wide range.

[0052] Here, in a MOSFET with a split-gate structure, it is known that impact ionization occurs near the bottom of each of the trench TR1 and the peripheral trench TR2 during avalanche breakdown, and hot holes generated at that time are injected into the insulating film IF1. If avalanche breakdown is repeated and such injected hot holes are accumulated in the insulating film IF1, the charge balance in the cell region changes, causing a problem of unstable breakdown voltage.

[0053] The areas where the depletion layer does not reach become a cause of a partial decrease in breakdown voltage. To prevent the occurrence of such areas, it is preferable that the depletion layer from the trench TR1 and the depletion layer from the peripheral trench TR2 overlap to some extent. However, in the "excess region" as shown in Figure 25, impact ionization is likely to occur from a low electric field due to electric field concentration, and a problem occurs in that many hot holes are injected into the insulating film IF1.

[0054] In the first embodiment, in order to suppress the occurrence of such an "excess region", the distance L2 is made longer than the distance L3 as shown in Fig. 5. As shown in Fig. 6, the overlap between the depletion layer from the corner portion TR2c and its periphery and the depletion layer from the nearest trench TR1 is reduced, so that the impact ionization is alleviated and the amount of hot holes injected into the insulating film IF1 can be suppressed. That is, according to the first embodiment, the breakdown voltage around the outer periphery trench TR2 can be improved and the breakdown voltage of the semiconductor device 100 can be stabilized.

[0055] FIG. 7 is a graph showing the relationship between drain current Id and drain voltage Vd, which is a result of measurements made by the inventor of the present application after performing breakdown operations several times for the study example and the first embodiment. As shown in FIG. 7, in the study example, it is found that the drain current Id starts to flow when the drain voltage Vd is low. That is, in the study example, it is found that a region with a locally low breakdown voltage exists in the cell. On the other hand, it is found that such a problem is suppressed in the first embodiment.

[0056] <Method of Manufacturing Semiconductor Device> Each manufacturing process included in the method for manufacturing the semiconductor device 100 will be described below with reference to FIGS.

[0057] First, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared as shown in Fig. 8. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0058] Next, a trench TR1 is formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. To form the trench TR1, first, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. Next, the silicon oxide film is patterned by photolithography technology and anisotropic etching to form a hard mask HM. Next, anisotropic etching is performed using the hard mask HM as a mask to form the trench TR1 in the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by, for example, a wet etching process using a solution containing hydrofluoric acid.

[0059] 9, an insulating film IF1 is formed inside the trench TR1 and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by a thermal oxidation process. Note that the insulating film IF1 may be a stacked film of a first silicon oxide film formed by a thermal oxidation process and a second silicon oxide film formed on the first silicon oxide film by a CVD method.

[0060] Next, a conductive film CF1 is formed on the insulating film IF1 by, for example, a CVD method so as to fill the inside of the trench TR1. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. In order to fill the inside of the trench TR1 with the conductive film CF1 satisfactorily, the conductive film CF1 may be formed in a plurality of times (for example, two times: the formation of a first polycrystalline silicon film and the formation of a second polycrystalline silicon film).

[0061] 10, the conductive film CF1 located outside the trench TR1 is removed by a polishing process using, for example, a CMP (Chemical Mechanical Polishing) method, whereby the conductive film CF1 remaining inside the trench TR1 is formed as a field plate electrode FP.

[0062] Next, as shown in FIG. 11, a portion of the field plate electrode FP is selectively removed so that the other portion of the field plate electrode FP is left as an extraction portion FPa.

[0063] Specifically, first, as shown in the BB cross section, a resist pattern RP1 is formed to selectively cover a portion of the field plate electrode FP that will become the lead portion FPa. Next, using the resist pattern RP1 as a mask, an etching process is performed using, for example, SF6 gas to remove the portion of the field plate electrode FP that will not become the lead portion FPa. That is, as shown in the AA cross section, the other portion of the field plate electrode FP that will not become the lead portion FPa is selectively set back toward the bottom of the trench TR1. The portion of the field plate electrode FP that is not set back becomes the lead portion FPa. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0064] 12, an isotropic etching process is performed on the insulating film IF1 using a solution containing hydrofluoric acid. As a result, the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB is removed, and the insulating film IF1 located inside the trench TR1 is recessed toward the bottom of the trench TR1 so that the position of the upper surface of the insulating film IF1 located inside the trench TR1 is lower than the position of the upper surface of the field plate electrode FP in a cross-sectional view.

[0065] At this point, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the drawn-out portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the drawn-out portion FPa. Also, as shown in the B-B cross section, by removing the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB, the position of the upper surface of the drawn-out portion FPa is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0066] Next, as shown in FIG. 13, a thermal oxidation process is performed to form a gate insulating film GI inside the trench TR1 located on the insulating film IF1, and an insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the insulating film IF1.

[0067] Next, a conductive film CF2 is formed on the gate insulating film GI and the insulating film IF2 by, for example, a CVD method so as to fill the inside of the trench TR1. The conductive film CF2 is, for example, an n-type polycrystalline silicon film.

[0068] Next, as shown in Fig. 14, the conductive film CF2 is polished using the CMP method. This reduces the thickness of the conductive film CF2, and the upper surface of the conductive film CF2 is flattened. Next, the conductive film CF2 is anisotropically etched to remove the conductive film CF2 located outside the trench TR1. As a result, the conductive film CF2 remaining inside the trench TR1 is formed as the gate electrode GE on the field plate electrode FP.

[0069] In order to completely remove the conductive film CF2 outside the trench TR1, the anisotropic etching process is performed by over-etching. Therefore, as shown in the AA cross section, the position of the upper surface of the gate electrode GE is slightly lower than the position of the upper surface TS of the semiconductor substrate SUB. In addition, the conductive film CF2 formed on the insulating film IF2 in contact with the lead-out portion FPa is removed by this anisotropic etching process.

[0070] Next, as shown in FIG. 15, for example, boron (B) is introduced by photolithography and ion implantation to selectively form a p-type body region PB in the semiconductor substrate SUB in the cell region CR.

[0071] Next, by introducing, for example, arsenic (As) using photolithography technology and ion implantation, an n-type source region NS is selectively formed in the body region PB of the cell region CR. Note that the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0072] Next, as shown in FIG. 16, first, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR1.

[0073] Next, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. First, a resist pattern having a pattern that opens the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, anisotropic etching is performed using the resist pattern as a mask to form a hole CH1 that penetrates the interlayer insulating film IL and the source region NS and reaches the inside of the body region PB. Next, boron (B), for example, is introduced by ion implantation into the body region PB at the bottom of the hole CH1 to form a p-type high concentration diffusion region PR. After that, the resist pattern is removed by ashing.

[0074] Next, a resist pattern having a pattern that opens above the lead-out portion FPa and the gate electrode GE is formed on the interlayer insulating film IL. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH3 that penetrates the interlayer insulating film IL and reaches the lead-out portion FPa. Although not shown here, in the process of forming the hole CH3, a hole CH2 that penetrates the interlayer insulating film IL and reaches the gate electrode GE is also formed. After that, the resist pattern is removed by an ashing process.

[0075] It does not matter which of the holes CH1 and the holes CH2 and CH3 is formed first.

[0076] Next, a source electrode SE is formed on the interlayer insulating film IL so as to fill the holes CH1 and CH3, and a gate line GW is formed on the interlayer insulating film IL so as to fill the hole CH2.

[0077] Specifically, first, a first barrier metal film is formed by sputtering inside the holes CH1, CH2, and CH3 and on the interlayer insulating film IL. The first barrier metal film is, for example, a titanium tungsten film. Next, a first conductive film is formed by sputtering on the first barrier metal film. The first conductive film is, for example, an aluminum alloy film with copper or silicon added. Next, the first barrier metal film and the first conductive film are patterned to form a source electrode SE and a gate wiring GW.

[0078] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Openings are formed in parts of the protective film to expose the areas of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0079] Thereafter, the structure shown in FIG. 4 is obtained through the following manufacturing steps. First, the lower surface BS of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface BS of the semiconductor substrate SUB by ion implantation. Note that if the semiconductor substrate SUB is composed of a laminate of an n-type silicon substrate and an n-type semiconductor layer, the high-concentration n-type silicon substrate forms the drain region ND, so that the formation of the drain region ND by the above-mentioned ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by sputtering.

[0080] (Embodiment 2) A semiconductor device 100 according to the second embodiment will be described below with reference to Figures 17 and 18. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0081] In the first embodiment, in order to suppress the occurrence of the "excess region" shown in FIG. 25, the end 10 of the nearest trench TR1 is located farther from the extension portion TR2b in the Y direction than the ends 10 of the other trenches TR1.

[0082] In the second embodiment, as shown in Fig. 17, the shape of the end 10 of the nearest trench TR1 is different from the shapes of the end 10 of the other trenches TR1. For example, the shape of the end 10 of the nearest trench TR1 recedes in a direction away from the corner portion TR2c. In other words, the width in the X direction of the end 10 of the nearest trench TR1 is narrower than the width in the X direction of the nearest trench TR1 other than the end 10, and is continuously narrower as it approaches the extension portion TR2b.

[0083] Such a change in the shape of the end 10 of the nearest trench TR1 can be achieved by changing the pattern of the hard mask HM in FIG.

[0084] In the second embodiment, similarly to the first embodiment, the occurrence of the "excess region" can be suppressed and the breakdown voltage around the peripheral trench TR2 can be improved. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0085] 18 of the second embodiment and FIG. 6 of the first embodiment, the depletion layers spreading from the trenches TR1 and TR2 have a higher degree of overlap uniformity in the second embodiment. Therefore, the second embodiment has an advantage that the breakdown voltage around the peripheral trench TR2 can be more easily stabilized than the first embodiment.

[0086] On the other hand, if the end 10 of the nearest trench TR1 is made too thin, it becomes difficult to satisfactorily embed the insulating film IF1 and the field plate electrode FP inside the end 10. Therefore, in terms of the embeddability of the insulating film IF1 and the field plate electrode FP, the first embodiment is superior to the second embodiment.

[0087] (Embodiment 3) A semiconductor device 100 according to the third embodiment will be described below with reference to Fig. 19 to Fig. 21. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted. Fig. 21 is a cross-sectional view taken along the line DD in Fig. 19.

[0088] In the third embodiment, as shown in Fig. 19, the distance between the end 10 of the nearest trench TR1 and the extension portion TR2b and the distance between the end 10 of another trench TR1 and the extension portion TR2b are the same distance L3. However, as shown in Fig. 19 and Fig. 21, a floating region PF which is a p-type impurity region is formed in the semiconductor substrate SUB located between the corner portion TR2c and the nearest trench TR1.

[0089] The impurity concentration of the floating region PF is higher than that of the p-type body region PB. The depth of the floating region PF from the upper surface TS of the semiconductor substrate SUB is deeper than the depth of the p-type body region PB from the upper surface TS of the semiconductor substrate SUB. The floating region PF is physically separated from the body region PB, is not electrically connected to the source electrode SE, and is in an electrically floating state.

[0090] In order to form such a floating region PF, an additional ion implantation process is performed. Before or after the manufacturing process of the body region PB in FIG. 15, impurities such as boron (B) are selectively implanted into the semiconductor substrate SUB located between the corner portion TR2c and the nearest trench TR1 using photolithography technology and ion implantation. This forms the floating region PF.

[0091] 20, by providing such a floating region PF, the spread of the depletion layer from the corner portion TR2c and its periphery and the spread of the depletion layer from the end 10 of the nearest trench TR1 are suppressed. Therefore, in the third embodiment, as in the first embodiment, the occurrence of an "excess region" can be suppressed and the breakdown voltage around the peripheral trench TR2 can be improved. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0092] (Embodiment 4) 22 and 23, a semiconductor device 100 according to the fourth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0093] 22, the end 10 of the nearest trench TR1 of the fourth embodiment is further away from the extension portion TR2b than the end 10 of the other trenches TR1. A trench TR3 is formed in the semiconductor substrate SUB located between the end 10 of the nearest trench TR1 and the extension portion TR2b, so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The trench TR3 is formed during the manufacturing process of the trench TR1 and the peripheral trench TR2, but is not connected to the trench TR1 and the peripheral trench TR2 and is formed as an independent trench.

[0094] A floating gate electrode FG is formed inside the trench TR3. The floating gate electrode FG is electrically insulated from the semiconductor substrate SUB and is in an electrically floating state. The floating gate electrode FG is formed for the purpose of reducing the electric field around the corner portion TR2c.

[0095] The internal structure of the trench TR3 may be composed of an insulating film IF1, a gate insulating film GI, an insulating film IF2, a field plate electrode FP, and a gate electrode GE, similar to the internal structure of the trench TR1 in the cell region CR. In this case, the field plate electrode FP and the gate electrode GE each become a floating gate electrode FG, and two floating gate electrodes FG are present inside the trench TR3.

[0096] The inner structure of the trench TR3 may be composed of an insulating film IF1 and a field plate electrode FP (pulled-out portion FPa) like the inner structure of the peripheral trench TR2 in the peripheral region OR. In this case, the field plate electrode FP (pulled-out portion FPa) becomes the floating gate electrode FG.

[0097] However, simply providing the trench TR3 and the floating gate electrode FG may result in the existence of a portion that is not reached by any of the depletion layers from the nearest trench TR1, the other trenches TR1, or the peripheral trench TR2.

[0098] 23, it is preferable that the shape of trench TR3 is adjusted so that all of the depletion layers from the nearest trench TR1, the other trench TR1, or the peripheral trench TR2 overlap with the floating gate electrode FG in a plan view. Therefore, the shape of trench TR3 is made close to the nearest trench TR1, the other trench TR1, or the peripheral trench TR2, as necessary.

[0099] 22, in the Y direction, the distance (spacing) L4 between the trench TR3 and the extension portion TR2b and the distance (spacing) L6 between the trench TR3 and the end 10 of the nearest trench TR1 are shorter than the distance (spacing) L5 between the end 10 of the other trench TR1 and the extension portion TR2b. In the X direction, the distance (spacing) L7 between the trench TR3 and the extension portion TR2a and the distance (spacing) L8 between the trench TR3 and the other trench TR1 are shorter than the distance (spacing) L9 between the nearest trench TR1 and the extension portion TR2a and the distance (spacing) L10 between the nearest trench TR1 and the other trench TR1.

[0100] In the fourth embodiment, similarly to the first embodiment, the occurrence of the "excess region" can be suppressed and the breakdown voltage around the outer periphery trench TR2 can be improved. Therefore, the breakdown voltage of the semiconductor device 100 can be stabilized.

[0101] Although the present invention has been specifically described above based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0102] 100 Semiconductor device 10 End 1A area BS Bottom surface of semiconductor substrate CF1, CF2 conductive film CH1, CH2, CH3 holes DE Drain electrode FG Floating gate electrode FP field plate electrode FPa Field plate electrode lead GE gate electrode GI Gate Insulator GP Gate Pad GW Gate wiring HM Hard Mask IF1, IF2 insulating film IL Interlayer insulating film ND drain region NS source region NV drift region PB Body Region PF p-type floating region PR high concentration diffusion region RP1 Resist pattern SE source electrode SP Source Pad SUB Semiconductor Substrate TR1 Trench TR2 Periphery Trench TR2a Y-direction extension TR2b X-direction extension TR2c corner section TR3 Trench TS Top surface of semiconductor substrate

Claims

1. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the trenches extending in a first direction in a plan view, and adjacent to each other in a second direction perpendicular to the first direction in a plan view; a plurality of first field plate electrodes formed within the plurality of trenches, respectively, and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of first field plate electrodes; a peripheral trench that is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate and that extends in the first direction and the second direction so as to surround the plurality of trenches in a plan view; a second field plate electrode formed within the peripheral trench and electrically insulated from the semiconductor substrate; Equipped with The peripheral trench is A first extension portion extending in the first direction; A second extension portion extending in the second direction; a corner portion that extends in a direction different from the first direction and the second direction in a plan view and connects the first extension portion and the second extension portion to each other; having The plurality of trenches include a first trench closest to the first extension portion in the second direction; a second trench that is next closest to the first extension portion in the second direction after the first trench; having the first trench has a first end located near the second extension in the first direction; the second trench has a second end located near the second extension in the first direction; a distance between the first end and the second extension portion in the first direction is longer than a distance between the second end and the second extension portion.

2. 2. The semiconductor device according to claim 1, A gate potential is supplied to the first gate electrodes; a source potential is supplied to the plurality of first field plate electrodes and the second field plate electrode.

3. 2. The semiconductor device according to claim 1, The corner portion extends in a direction inclined at an angle of 45 degrees from the first direction and the second direction in a plan view.

4. 2. The semiconductor device according to claim 1, a third trench is formed in the semiconductor substrate located between the first end and the second extension portion, the third trench extending from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate to a predetermined depth; a floating gate electrode electrically insulated from the semiconductor substrate is formed inside the third trench.

5. 5. The semiconductor device according to claim 4, In the first direction, a distance between the third trench and the second extension portion and a distance between the third trench and the first end portion are shorter than the distance between the second end portion and the second extension portion; a distance between the third trench and the first extension portion and a distance between the third trench and the second trench in the second direction are shorter than a distance between the first trench and the first extension portion and a distance between the first trench and the second trench.

6. 5. The semiconductor device according to claim 4, A gate potential is supplied to the first gate electrodes; a source potential is supplied to the plurality of first field plate electrodes and the second field plate electrode; The floating gate electrode is in an electrically floating state.

7. 5. The semiconductor device according to claim 4, The corner portion extends in a direction inclined at an angle of 45 degrees from the first direction and the second direction in a plan view.

8. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the trenches extending in a first direction in a plan view, and adjacent to each other in a second direction perpendicular to the first direction in a plan view; a plurality of first field plate electrodes formed within the plurality of trenches, respectively, and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of first field plate electrodes; a peripheral trench that is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate and that extends in the first direction and the second direction so as to surround the plurality of trenches in a plan view; a second field plate electrode formed within the peripheral trench and electrically insulated from the semiconductor substrate; Equipped with The peripheral trench is A first extension portion extending in the first direction; A second extension portion extending in the second direction; a corner portion that extends in a direction different from the first direction and the second direction in a plan view and connects the first extension portion and the second extension portion to each other; having The plurality of trenches include a first trench closest to the first extension portion in the second direction; a second trench that is next closest to the first extension portion in the second direction after the first trench; having the first trench has a first end located near the second extension in the first direction; the second trench has a second end located near the second extension in the first direction; The semiconductor device, wherein the first end has a different shape than the second end.

9. 9. The semiconductor device according to claim 8, The first end portion has a shape that is recessed in a direction away from the corner portion.

10. 9. The semiconductor device according to claim 8, A semiconductor device, wherein the width of the first end in the second direction is narrower than the width of the first trench other than the first end in the second direction, and becomes continuously narrower as the width approaches the second extension portion.

11. 9. The semiconductor device according to claim 8, A gate potential is supplied to the first gate electrodes; a source potential is supplied to the plurality of first field plate electrodes and the second field plate electrode.

12. 9. The semiconductor device according to claim 8, The corner portion extends in a direction inclined at an angle of 45 degrees from the first direction and the second direction in a plan view.

13. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a plurality of trenches formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, the trenches extending in a first direction in a plan view, and adjacent to each other in a second direction perpendicular to the first direction in a plan view; a plurality of first field plate electrodes formed within the plurality of trenches, respectively, and electrically insulated from the semiconductor substrate; a plurality of first gate electrodes respectively formed above the plurality of first field plate electrodes and respectively electrically insulated from the semiconductor substrate and the plurality of first field plate electrodes; a peripheral trench that is formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate and that extends in the first direction and the second direction so as to surround the plurality of trenches in a plan view; a second field plate electrode formed within the peripheral trench and electrically insulated from the semiconductor substrate; a first impurity region formed in the semiconductor substrate between the plurality of trenches and the peripheral trench, the first impurity region having a second conductivity type opposite to the first conductivity type; Equipped with The peripheral trench is A first extension portion extending in the first direction; A second extension portion extending in the second direction; a corner portion that extends in a direction different from the first direction and the second direction in a plan view and connects the first extension portion and the second extension portion to each other; having the plurality of trenches includes a first trench closest to the first extension portion in the second direction; a second impurity region is formed in the semiconductor substrate located between the corner portion and the first trench; The semiconductor device, wherein the second impurity region has a higher impurity concentration than the first impurity region.

14. 14. The semiconductor device according to claim 13, a depth of the second impurity region from the upper surface of the semiconductor substrate is greater than a depth of the first impurity region from the upper surface of the semiconductor substrate.

15. 14. The semiconductor device according to claim 13, the plurality of trenches further include a second trench that is next closest to the first extension portion in the second direction after the first trench, the first trench has a first end located near the second extension in the first direction; the second trench has a second end located near the second extension in the first direction; a distance between the first end and the second extension portion in the first direction is the same as a distance between the second end and the second extension portion.

16. 14. The semiconductor device according to claim 13, A gate potential is supplied to the first gate electrodes; a source potential is supplied to the plurality of first field plate electrodes and the second field plate electrode; the first impurity region and the second impurity region are in an electrically floating state.

17. 14. The semiconductor device according to claim 13, The corner portion extends in a direction inclined at an angle of 45 degrees from the first direction and the second direction in a plan view.

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