Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing crosstalk between channels.SOLUTION: A semiconductor device includes: a semiconductor substrate; a first coil, a second coil, a third coil, and a fourth coil; an insulating layer; and a first shield. The semiconductor substrate has a device region and a peripheral region. The peripheral region is present around the device region in a plan view. The first coil and the second coil are arranged on the device region and are arranged in a first direction in a plan view. The third coil and the fourth coil are respectively opposed to the first coil and the second coil via the insulating layer. The first shield is arranged between the semiconductor substrate and the first and second coils and overlaps with the first coil and the second coil in a plan view. A width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction and a width of the second coil in the second direction. The first shield is electrically connected to a reference potential.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] International Publication No. WO 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has multiple transformers. The transformers are composed of coils that face each other with an insulating layer interposed therebetween. Each of the multiple transformers forms a channel for transmitting and receiving signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097425 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, crosstalk may occur between channels. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield. The semiconductor substrate has an element region and a peripheral region. The peripheral region is located around the element region in a plan view. The first coil and the second coil are disposed on the element region and are aligned in a first direction in a plan view. The third coil and the fourth coil face the first coil and the second coil, respectively, via the insulating layer. The first shield is disposed between the semiconductor substrate and the first coil and the second coil, and overlaps the first coil and the second coil in a plan view. The width of the first shield in a second direction perpendicular to the first direction is larger than the width of the first coil in the second direction and the width of the second coil in the second direction. The first shield is electrically connected to a reference potential. Effect of the Invention

[0006] According to the semiconductor device of the present disclosure, crosstalk between channels can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a semiconductor device DEV1. [Diagram 2] 4 is an explanatory diagram showing an example of signal transmission from a control circuit CC to a drive circuit DR. FIG. [Diagram 3] FIG. 2 is a first plan view of the semiconductor chip CHP3. [Figure 4] FIG. 2 is a second plan view of the semiconductor chip CHP3. [Diagram 5] FIG. 13 is a third plan view of the semiconductor chip CHP3. [Figure 6A] 6 is a cross-sectional view taken along line VIA-VIA in FIG. 5. [Figure 6B] FIG. 6 is a cross-sectional view taken along line VIB-VIB in FIG. [Figure 7] 1 is a manufacturing process diagram of the semiconductor chip CHP3. [Figure 8] FIG. 11 is a cross-sectional view illustrating an ion implantation step S2. [Figure 9]FIG. 11 is a cross-sectional view illustrating a first insulating film forming step S3. [Figure 10] FIG. 11 is a cross-sectional view illustrating a first via plug forming step S4. [Figure 11] FIG. 11 is a cross-sectional view illustrating a shield forming step S5. [Figure 12] FIG. 11 is a cross-sectional view illustrating a second insulating film forming step S6. [Figure 13] FIG. 11 is a cross-sectional view illustrating a second via plug forming step S7. [Figure 14] FIG. 11 is a cross-sectional view illustrating a first coil forming step S8. [Figure 15] FIG. 11 is a cross-sectional view illustrating a third insulating film forming step S9. [Figure 16] 11 is a cross-sectional view illustrating a third via plug forming step S10. FIG. [Figure 17] 11 is a cross-sectional view illustrating a wiring forming step S11. [Figure 18] 11 is a cross-sectional view illustrating a second coil forming step S12. FIG. [Figure 19] FIG. 2 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV2. [Figure 20] FIG. 2 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV3. [Figure 21] FIG. 13 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV4. [Figure 22] FIG. 2 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV5. [Diagram 23] 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22. [Figure 24] FIG. 13 is a plan view of a semiconductor chip CHP3 in the semiconductor device DEV6. [Diagram 25] 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24. [Figure 26] 13 is a cross-sectional view of a semiconductor chip CHP3 according to a modified example of the semiconductor device DEV6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will now be described with reference to the accompanying drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0009] (First embodiment) A description will be given of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is referred to as a semiconductor device DEV1.

[0010] (Configuration of semiconductor device DEV1) The configuration of the semiconductor device DEV1 will be described below.

[0011] <Schematic configuration of semiconductor device DEV1> The schematic configuration of the semiconductor device DEV1 will be described below.

[0012] Fig. 1 is a block diagram of the semiconductor device DEV1. As shown in Fig. 1, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3.

[0013] The semiconductor chip CHP1 has a control circuit CC, a transmission circuit TX1, and a reception circuit RX2, and the semiconductor chip CHP2 has a drive circuit DR, a reception circuit RX1, and a transmission circuit TX2. The control circuit CC is electrically connected to the transmission circuit TX1 and the reception circuit RX2. The drive circuit DR is electrically connected to the reception circuit RX1 and the transmission circuit TX2.

[0014] The semiconductor chip CHP3 has a transformer TR1, a transformer TR2, and leads PL1 and PL2.

[0015] The transformer TR1 has a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 has a coil CL11 and a coil CL12, and the receiving coil CL2 has a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0016] More specifically, one end of the coil CL11 is electrically connected to the transmission circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmission circuit TX1. Also, one end of the coil CL21 is electrically connected to the reception circuit RX1, the other end of the coil CL21 is electrically connected to one end of the coil CL22 via the lead line PL1, and the other end of the coil CL22 is electrically connected to the reception circuit RX1. The lead line PL1 is connected to a reference potential. The reference potential is, for example, a ground potential.

[0017] The transformer TR2 has a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 has a coil CL31 and a coil CL32, and the receiving coil CL4 has a coil CL41 and a coil CL42. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0018] More specifically, one end of the coil CL31 is electrically connected to the transmission circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the transmission circuit TX2. Also, one end of the coil CL41 is electrically connected to the reception circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead line PL2, and the other end of the coil CL42 is electrically connected to the reception circuit RX2. The lead line PL2 is connected to a reference potential.

[0019] In the semiconductor device DEV1, a signal is transmitted from the control circuit CC to the driving circuit DR by the transmitting circuit TX1, the transformer TR1, and the receiving circuit RX1. Also, in the semiconductor device DEV1, a signal is transmitted from the driving circuit DR to the control circuit CC by the transmitting circuit TX2, the transformer TR2, and the receiving circuit RX2.

[0020] FIG. 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. As shown in FIG. 2, the control circuit CC inputs a signal SG1 to the transmission circuit TX1. The signal SG1 is a square wave. The transmission circuit TX1 modulates the signal SG1 to a signal SG2 and sends the signal SG2 to the transmission coil CL1. When the signal SG2 flows to the transmission coil CL1, a signal SG3 corresponding to the signal SG2 flows to the reception coil CL2 due to induced electromotive force. The reception circuit RX1 amplifies the signal SG3 and demodulates it to a signal SG4 (square wave), and outputs it to the drive circuit DR. In this way, a signal is transmitted from the control circuit CC to the drive circuit DR. Note that the signal is also transmitted from the drive circuit DR to the control circuit CC in the same manner. In this way, in the semiconductor device DEV1, the signal transmission between the transmission circuit TX1 and the reception circuit RX1 and the signal transmission between the transmission circuit TX2 and the reception circuit RX2 are performed by a pulse communication method.

[0021] <Detailed configuration of the CHP3 semiconductor chip> The detailed configuration of the semiconductor chip CHP3 will be described below.

[0022] FIG. 3 is a first plan view of the semiconductor chip CHP3. FIG. 4 is a second plan view of the semiconductor chip CHP3. FIG. 5 is a third plan view of the semiconductor chip CHP3. FIG. 6A is a cross-sectional view taken along VIA-VIA in FIG. 5. FIG. 6B is a cross-sectional view taken along VIB-VIB in FIG. 5. As shown in FIG. 3 to FIG. 6B, the semiconductor chip CHP3 has a semiconductor substrate SUB, an insulating film IF1, a shield SH1, wiring WL1, wiring WL2, wiring WL3, and wiring WL4, an insulating film IF2, via plugs VP1, VP2, VP3, via plugs VP4, VP5, via plugs VP6, VP7, and VP8, a transmitting coil CL1, a receiving coil CL4, wiring WL5, wiring WL6, wiring WL7, and wiring WL8, and a lead line PL2.

[0023] The semiconductor chip CHP3 further includes a plurality of insulating films IF3, a receiving coil CL2, an extraction line PL1, a transmitting coil CL3, pads PD1, PD2, PD3, PD4, and PD5, and a guard ring GR1. The semiconductor chip CHP3 further includes a guard ring GR2, a seal ring SR, a wiring WL9, and a passivation film PF.

[0024] The semiconductor substrate SUB has a first surface FS and a second surface SS. The first surface FS and the second surface SS are end surfaces in the thickness direction of the semiconductor substrate SUB. The second surface SS is the opposite surface to the first surface FS. The constituent material of the semiconductor substrate SUB is, for example, single crystal silicon. The semiconductor substrate SUB has an impurity-implanted region IR. The impurity-implanted region IR is formed in the first surface FS. The impurity-implanted region IR may be formed over the entire surface of the first surface FS, or may be formed partially in the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, p-type. The dopant concentration in the impurity-implanted region IR is higher than the dopant concentration in the regions other than the impurity-implanted region IR.

[0025] The semiconductor substrate SUB has an element region SUB1, a peripheral region SUB2, and an outer periphery region SUB3 in a plan view. The peripheral region SUB2 is located around the element region SUB1 and surrounds it. The outer periphery region SUB3 is located on the outer periphery of the semiconductor substrate SUB and surrounds the peripheral region SUB2.

[0026] The insulating film IF1 is disposed on the semiconductor substrate SUB. The insulating film IF1 is made of, for example, silicon oxide.

[0027] The shield SH1 is disposed on the insulating film IF1. The shield SH1 is disposed on the element region SUB1. The outer shape of the shield SH1 in a plan view is generally rectangular. The constituent material of the shield SH1 is, for example, aluminum, an aluminum alloy, copper, a copper alloy, or the like. That is, the constituent material of the shield SH1 is, for example, a conductive material mainly composed of aluminum or a conductive material mainly composed of copper. The term "main component" refers to a constituent element that occupies more than 50 mass percent of the constituent material.

[0028] The shield SH1 has an opening OP1, an opening OP2, and an opening OP3. The opening OP1, the opening OP2, and the opening OP3 penetrate the shield SH1 in the thickness direction.

[0029] The wiring WL1, wiring WL2, wiring WL3, and wiring WL4 are disposed on the insulating film IF1. The wiring WL1 is disposed inside the opening OP1 in a plan view. The wiring WL2 and wiring WL3 are disposed inside the opening OP2 in a plan view. The wiring WL4 is disposed inside the opening OP3. The wiring WL1, wiring WL2, wiring WL3, and wiring WL4 are made of a conductive material mainly composed of aluminum, for example. The wiring WL1, wiring WL2, wiring WL3, and wiring WL4 may be made of a conductive material mainly composed of copper.

[0030] The insulating film IF2 is disposed on the insulating film IF1 so as to cover the shield SH1, the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4. The insulating film IF2 is made of, for example, silicon oxide.

[0031] The via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in an insulating film IF2. The constituent material of the via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 is, for example, a conductive material mainly composed of tungsten.

[0032] The transmitting coil CL1 (coil CL11, coil CL12), the receiving coil CL4 (coil CL41, coil CL42) and the lead-out wire PL2 are disposed on the insulating film IF2. From another perspective, the coil CL11, coil CL12, coil CL41, coil CL42 and the lead-out wire PL2 are formed in the same layer on the semiconductor substrate SUB. The constituent material of the coil CL11, coil CL12, coil CL41, coil CL42 and the lead-out wire PL2 is, for example, a conductive material containing aluminum as a main component. The constituent material of the coil CL11, coil CL12, coil CL41, coil CL42 and the lead-out wire PL2 may be a conductive material containing copper as a main component.

[0033] Coil CL11, coil CL12, coil CL41, and coil CL42 are aligned in the first direction DR1 in a plan view. Coil CL12 and coil CL41 are adjacent to each other. Coil CL11 is adjacent to coil CL12 from the side opposite to coil CL41. Coil CL42 is adjacent to coil CL41 from the side opposite to coil CL12. Coil CL11, coil CL12, coil CL41, and coil CL42 are disposed on element region SUB1.

[0034] The coils CL11 and CL12 are spirally wound in a plan view. The coils CL11 and CL12 are electrically connected in series to each other. More specifically, the outermost end of the coil CL11 and the outermost end of the coil CL12 are electrically connected to each other.

[0035] The coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL12 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL11 may be opposite to the winding direction of the coil CL12. From another perspective, the coils CL11 and CL12 are configured in a serial aiding configuration.

[0036] The coil CL41 and the coil CL42 are wound in a spiral shape in a plan view. The coil CL41 and the coil CL42 are adjacent to each other in a plan view. The coil CL41 and the coil CL42 are electrically connected to each other in series. More specifically, the outermost end of the coil CL41 and the outermost end of the coil CL42 are electrically connected to each other. A lead line PL2 is formed between the coil CL41 and the coil CL42.

[0037] The coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL42 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL41 may be opposite to the winding direction of the coil CL42. From another perspective, the coil CL41 and the coil CL42 are configured in series to cooperate with each other.

[0038] The coils CL11, CL12, CL41, and CL42 overlap with the shield SH1 in plan view. That is, the shield SH1 is disposed between the coils CL11, CL12, CL41, and CL42 and the semiconductor substrate SUB. The shield SH1 is formed continuously across the coils CL12 and CL41 in plan view.

[0039] The second direction DR2 is a direction perpendicular to the first direction DR1. The width of the shield SH1 in the second direction DR2 is greater than the width of the coil CL11 in the second direction DR2, the width of the coil CL12 in the second direction DR2, the width of the coil CL41 in the second direction DR2, and the width of the coil CL42 in the second direction DR2.

[0040] The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 are disposed on the insulating film IF2. The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 are made of a conductive material mainly composed of aluminum, for example. The wiring WL5, wiring WL6, wiring WL7, and wiring WL8 may be made of a conductive material mainly composed of copper.

[0041] The wire WL5 is electrically connected to the wire WL1 by a via plug VP5, and the wire WL6 is electrically connected to the wire WL2 by a via plug VP6, the wire WL7 is electrically connected to the wire WL3 by a via plug VP7, and the wire WL8 is electrically connected to the wire WL4 by a via plug VP8.

[0042] A plurality of insulating films IF3 are stacked on the insulating film IF2. The insulating film IF3 in the lowermost layer covers the coil CL11, the coil CL12, the coil CL41, the coil CL42, the lead-out line PL2, the wiring WL5, the wiring WL6, the wiring WL7, and the wiring WL8. The insulating film IF3 is made of, for example, silicon oxide.

[0043] The coils CL21, CL22, CL31, and CL32 are disposed on the insulating film IF3, which is the top layer. The coils CL21, CL22, CL31, and CL32 are made of a conductive material mainly composed of aluminum, for example. The coils CL21, CL22, CL31, and CL32 may be made of a conductive material mainly composed of copper.

[0044] The coils CL21 and CL22 face the coils CL11 and CL12, respectively, via a plurality of insulating films IF3. From another perspective, the coils CL21 and CL22 overlap the coils CL11 and CL12 in a plan view. From yet another perspective, the coils CL21 and CL22 are magnetically coupled to the coils CL11 and CL12, respectively.

[0045] The coils CL21 and CL22 are spirally wound in a plan view. The coils CL21 and CL22 are adjacent to each other in a plan view. The coils CL21 and CL22 are electrically connected in series to each other. More specifically, the outermost end of the coil CL21 and the outermost end of the coil CL22 are electrically connected to each other. A lead wire PL1 is formed between the coils CL21 and CL22.

[0046] The coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL22 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL21 may be opposite to the winding direction of the coil CL22. From another point of view, the coil CL21 and the coil CL22 are configured in series to cooperate with each other.

[0047] The coils CL31 and CL32 face the coils CL41 and CL42, respectively, via a plurality of insulating films IF3. From another perspective, the coils CL31 and CL32 overlap the coils CL41 and CL42 in a plan view. From yet another perspective, the coils CL31 and CL32 are magnetically coupled to the coils CL41 and CL42, respectively.

[0048] The coil CL31 and the coil CL32 are spirally wound in a plan view. The coil CL31 and the coil CL32 are adjacent to each other in a plan view. The coil CL31 and the coil CL32 are electrically connected in series to each other. More specifically, the outermost end of the coil CL31 and the outermost end of the coil CL32 are electrically connected to each other.

[0049] The coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view. The coil CL32 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. That is, the winding direction of the coil CL31 may be opposite to the winding direction of the coil CL32. From another perspective, the coil CL31 and the coil CL32 are configured in series to cooperate with each other.

[0050] The distance between coil CL11 and coil CL21 or between coil CL12 and coil CL22 may be, for example, 6 μm or more and 14 μm or less. The distance between coil CL41 and coil CL31 or between coil CL42 and coil CL32 is, for example, 6 μm or more and 14 μm or less.

[0051] The pads PD1, PD2, PD3, PD4, and PD5 are disposed on the insulating film IF3 in the top layer. The pad PD1 is connected to the innermost end of the coil CL21, and the pad PD2 is connected to the innermost end of the coil CL22. The pad PD3 is connected to the innermost end of the coil CL31, and the pad PD4 is connected to the innermost end of the coil CL32. The pad PD5 is connected to the end of the lead wire PL1 on the opposite side to the coils CL21 and CL22. The pads PD1, PD2, PD3, PD4, and PD5 are made of a conductive material mainly made of aluminum, for example. The pads PD1, PD2, PD3, PD4, and PD5 may be made of a conductive material mainly made of copper.

[0052] The guard ring GR1 is disposed on the insulating film IF3, which is the uppermost layer. The guard ring GR1 has a first portion GR1a and a second portion GR1b. The first portion GR1a surrounds the receiving coil CL2 in a planar view, and the second portion GR1b surrounds the transmitting coil CL3 in a planar view. The pad PD5 is in contact with the guard ring GR1 (first portion GR1a). Therefore, the guard ring GR1 is connected to the reference potential in the same manner as the lead-out line PL1. The constituent material of the guard ring GR1 is, for example, a conductive material mainly composed of aluminum. The constituent material of the guard ring GR1 may be a conductive material mainly composed of copper.

[0053] The guard ring GR2 has a plurality of wirings WL10 and a plurality of via plugs VP9. The wirings WL10 are arranged on the insulating film IF1, on the insulating film IF2, or on each of the plurality of insulating films IF3. From another perspective, the shield SH1 is formed in the same layer as the wirings WL10 in the lowermost layer. The via plugs VP9 are embedded in the insulating film IF2 or in each of the plurality of insulating films IF3. The wirings WL10 and the via plugs VP9 are alternately stacked on the peripheral region SUB2. The guard ring GR2 (more specifically, the wirings WL10 in the uppermost layer) is connected to a reference potential.

[0054] The wiring WL10 is made of a conductive material mainly made of aluminum, for example. The wiring WL10 may be made of a conductive material mainly made of copper, for example. The via plug VP9 is made of a conductive material mainly made of tungsten, for example.

[0055] The wiring WL9 is disposed on the insulating film IF1. One end of the wiring WL9 is connected to the shield SH1, and the other end is connected to the wiring WL10 in the lowermost layer. This connects the shield SH1 to the reference potential. The wiring WL9 is made of a conductive material mainly composed of aluminum, for example. The wiring WL9 may also be made of a conductive material mainly composed of copper.

[0056] The seal ring SR has a plurality of wirings WL11 and a plurality of via plugs VP10. The wirings WL11 are disposed on the insulating film IF1, the insulating film IF2, or on each of the plurality of insulating films IF3. The via plugs VP10 are embedded in the insulating film IF1, the insulating film IF2, or each of the plurality of insulating films IF3. The wirings WL11 and the via plugs VP10 are alternately stacked and disposed on the outer peripheral region SUB3. Since the via plugs VP10 are also embedded in the insulating film IF1, the seal ring SR is electrically connected to the semiconductor substrate SUB (more specifically, the impurity-implanted region IR). A reference potential is connected to the seal ring SR (more specifically, the wirings WL11 in the uppermost layer). Therefore, the semiconductor substrate SUB is also connected to the reference potential.

[0057] The wiring WL11 is made of a conductive material mainly made of aluminum, for example. The wiring WL11 may be made of a conductive material mainly made of copper, for example. The via plug VP10 is made of a conductive material mainly made of tungsten, for example.

[0058] The passivation film PF is disposed on the insulating film IF3 in the uppermost layer so as to cover the receiving coil CL2 (coil CL21, coil CL22), the transmitting coil CL3 (coil CL31, coil CL32), the lead wire PL1, the pads PD1, PD2, PD3, PD4, PD5, the guard ring GR1, the wiring WL10 in the uppermost layer, and the wiring WL11 in the uppermost layer. The pads PD1, PD2, PD3, PD4, and PD5 are exposed from the openings in the passivation film PF. The constituent material of the passivation film PF is, for example, silicon nitride.

[0059] <Manufacturing method of semiconductor chip CHP3> A method for manufacturing the semiconductor chip CHP3 will be described below.

[0060] Fig. 7 is a manufacturing process diagram of the semiconductor chip CHP3. As shown in Fig. 7, the manufacturing method of the semiconductor chip CHP3 includes a preparation step S1, an ion implantation step S2, a first insulating film forming step S3, a first via plug forming step S4, a shield forming step S5, a second insulating film forming step S6, a second via plug forming step S7, a first coil forming step S8, a third insulating film forming step S9, a third via plug forming step S10, a wiring forming step S11, a second coil forming step S12, and a passivation film forming step S13.

[0061] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an ion implantation step S2 is performed. FIG. 8 is a cross-sectional view illustrating the ion implantation step S2. As shown in FIG. 8, in the ion implantation step S2, an impurity implanted region IR is formed by ion implantation. After the ion implantation step S2, a first insulating film formation step S3 is performed.

[0062] 9 is a cross-sectional view illustrating the first insulating film forming step S3. In the first insulating film forming step S3, an insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S3, a first via plug forming step S4 is performed.

[0063] 10 is a cross-sectional view for explaining the first via plug forming step S4. As shown in FIG. 10, in the first via plug forming step S4, a via plug VP10 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a via hole is formed in the insulating film IF1 by dry etching using a resist pattern formed by photolithography as a mask. Second, a constituent material of the via plug VP10 is embedded in the via hole by, for example, CVD. Third, a constituent material of the via plug VP10 protruding from the via hole is removed by, for example, CMP (Chemical Mechanical Polishing). After the first via plug forming step S4, a shield forming step S5 is performed.

[0064] FIG. 11 is a cross-sectional view for explaining the shield forming step S5. As shown in FIG. 11, in the shield forming step S5, a shield SH1 is formed on an insulating film IF1. In the shield forming step S5, first, a constituent material of the shield SH1 is formed by, for example, a sputtering method. Second, the formed constituent material of the shield SH1 is patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask. In the shield forming step S5, the wiring WL1, the wiring WL2, the wiring WL3, and the wiring WL4 are also formed in the same manner. Although not shown, in the shield forming step S5, the wiring WL9, the wiring WL10, and the wiring WL11 are also formed in the same manner. After the shield forming step S5, a second insulating film forming step S6 is performed.

[0065] Fig. 12 is a cross-sectional view for explaining the second insulating film forming step S6. As shown in Fig. 12, in the second insulating film forming step S6, the insulating film IF2 is formed on the insulating film IF1 so as to cover the shield SH1, the wiring WL1, the wiring WL2, the wiring WL3, the wiring WL4, the wiring WL9 (not shown in Fig. 12), the wiring WL10 (not shown in Fig. 12), and the wiring WL11 (not shown in Fig. 12). In the second insulating film forming step S6, first, the constituent material of the insulating film IF2 is formed into a film by, for example, the CVD method. Second, the constituent material of the formed insulating film IF2 is planarized by, for example, the CMP method. After the second insulating film forming step S6, the second via plug forming step S7 is performed.

[0066] Fig. 13 is a cross-sectional view for explaining the second via plug forming step S7. As shown in Fig. 13, in the second via plug forming step S7, via plugs VP1, VP2, VP3, VP4, VP5, VP6, VP7, and VP8 are embedded in the insulating film IF2 by the same method as in the first via plug forming step S4. Although not shown, in the second via plug forming step S7, via plugs VP9 and VP10 are also formed in the same manner. After the second via plug forming step S7, a first coil forming step S8 is performed.

[0067] FIG. 14 is a cross-sectional view for explaining the first coil forming step S8. As shown in FIG. 14, in the first coil forming step S8, the transmitting coil CL1 and the receiving coil CL4 are formed on the insulating film IF2. In the first coil forming step S8, first, the constituent material of the transmitting coil CL1 and the receiving coil CL4 is deposited by, for example, sputtering. Second, the deposited constituent material of the transmitting coil CL1 and the receiving coil CL4 is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. In the first coil forming step S8, the wiring WL5, the wiring WL6, the wiring WL7, the wiring WL8, and the drawing line PL2 are also formed in the same manner. Although not shown, in the first coil forming step S8, the wiring WL10 and the wiring WL11 are also formed in the same manner. After the first coil forming step S8, the third insulating film forming step S9 is performed.

[0068] Fig. 15 is a cross-sectional view for explaining the third insulating film forming step S9. As shown in Fig. 15, in the third insulating film forming step S9, an insulating film IF3 is formed on the insulating film IF2 so as to cover the transmitting coil CL1, the receiving coil CL4, the lead wire PL2, the wiring WL5, the wiring WL6, the wiring WL7, the wiring WL8 (all of which are not shown in Fig. 15), the wiring WL10, and the wiring WL11, in the same manner as in the second insulating film forming step S6. After the third insulating film forming step S9, a third via plug forming step S10 is performed.

[0069] FIG. 16 is a cross-sectional view for explaining the third via plug forming step S10. As shown in FIG. 16, in the third via plug forming step S10, via plugs VP9 and VP10 are embedded in the insulating film IF3 by the same method as in the second via plug forming step S7. After the third via plug forming step S10, the wiring forming step S11 is performed. FIG. 17 is a cross-sectional view for explaining the wiring forming step S11. As shown in FIG. 17, in the wiring forming step S11, the wiring WL10 and the wiring WL11 are formed by the same method as in the first coil forming step S8. The third insulating film forming step S9, the third via plug forming step S10, and the wiring forming step S11 are repeated until the insulating film IF3 in the uppermost layer is formed. After the insulating film IF3 in the uppermost layer is formed, the second coil forming step S12 is performed.

[0070] Fig. 18 is a cross-sectional view for explaining the second coil forming step S12. As shown in Fig. 18, in the second coil forming step S12, the receiving coil CL2, the transmitting coil CL3, the lead wire PL1, the pads PD1 to PD5, the guard ring GR1, the wiring WL10 (not shown in Fig. 18) and the wiring WL11 (not shown in Fig. 18) are formed on the insulating film IF3 in the uppermost layer by the same method as in the first coil forming step S8. After the second coil forming step S12, the passivation film forming step S13 is performed.

[0071] In the passivation film forming process S13, a passivation film PF is formed on the insulating film IF3 in the uppermost layer so as to cover the receiving coil CL2, the transmitting coil CL3, the lead wire PL1, the pads PD1 to PD5, the guard ring GR1, the wiring WL10, and the wiring WL11. In the passivation film forming process S13, first, a constituent material of the passivation film PF is formed by, for example, a CVD method. Second, the constituent material of the passivation film PF is patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask.

[0072] After the above steps are performed, the semiconductor chip CHP3 having the structure shown in FIG. 3 to FIG. 6B is formed by dividing the semiconductor chip into individual pieces by dicing or the like.

[0073] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0074] In the semiconductor device DEV1, the transformers TR1 and TR2 are integrated into a semiconductor chip CHP3. Since semiconductor elements such as transistors are not formed on the semiconductor chip CHP3, it is possible to optimize the manufacturing process of the semiconductor chip CHP3 in accordance with the transformers TR1 and TR2.

[0075] If the shield SH1 is not arranged, the insulating films IF1 and IF2 between the transmitting coil CL1 (coil CL11, coil CL12) and the semiconductor substrate SUB form a capacitance. Similarly, the insulating films IF1 and IF2 between the receiving coil CL4 (coil CL41, coil CL42) and the semiconductor substrate SUB form a capacitance. Since the impedance of the above capacitance is small for high-frequency signals, the current flowing through one of the transmitting coil CL1 and the receiving coil CL4 flows through the capacitance and the semiconductor substrate SUB to the other of the transmitting coil CL1 and the receiving coil CL4, causing crosstalk between the channels.

[0076] Incidentally, when the impurity implantation region is formed over the entire first face FS, it is not necessary to form a mask in the ion implantation step S2, and therefore the process for forming the semiconductor chip CHP3 is simplified. However, when the impurity implantation region is formed over the entire first face FS, the electrical resistance value of the semiconductor substrate SUB is reduced, and therefore the current flowing through one of the transmitter coil CL1 and the receiver coil CL4 is more likely to flow through the capacitance and the semiconductor substrate SUB to the other of the transmitter coil CL1 and the receiver coil CL4.

[0077] In the semiconductor device DEV1, the shield SH1 connected to the reference potential is disposed between the transmitting coil CL1 and the receiving coil CL4, so that the above-mentioned capacitive coupling is unlikely to occur. Therefore, the semiconductor device DEV1 can suppress crosstalk between the channels.

[0078] Second embodiment A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as a semiconductor device DEV2. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0079] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0080] The semiconductor device DEV2 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0081] Fig. 19 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV2. As shown in Fig. 19, in the semiconductor device DEV2, a plurality of openings OP4 are formed in the shield SH1. The openings OP4 penetrate the shield SH1 along the thickness direction. The plurality of openings OP4 are arranged, for example, in a lattice pattern in plan view. The plurality of openings OP4 may be arranged in a checkerboard pattern. In plan view, the length of the openings OP4 in the longitudinal direction is, for example, 50 μm or less. In these respects, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0082] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0083] Eddy currents may flow in the shield SH1 due to magnetic flux generated by currents flowing through the transmitting coil CL1 (coil CL11, coil CL12) and the receiving coil CL4 (coil CL41, coil CL42). However, in the semiconductor device DEV2, an opening OP4 is formed in the shield SH1, and the range in which the eddy currents tend to flow is limited by the opening OP4. In this way, the semiconductor device DEV2 is capable of suppressing the generation of eddy currents in the shield SH1. Note that if the longitudinal length of the opening OP4 is 50 μm or less in a plan view, the shield SH1 can sufficiently suppress crosstalk between channels even if the opening OP4 is formed.

[0084] Third embodiment A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as a semiconductor device DEV3. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0085] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0086] The semiconductor device DEV3 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV1.

[0087] Fig. 20 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV3. As shown in Fig. 20, in the semiconductor device DEV3, a plurality of slit openings OP5 are formed in the shield SH1. The slit openings OP5 penetrate the shield SH1 along the thickness direction. The plurality of slit openings OP5 are, for example, arranged radially in a plan view. In these respects, the configuration of the semiconductor device DEV3 differs from the configuration of the semiconductor device DEV1.

[0088] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0089] Eddy currents may flow in the shield SH1 due to magnetic flux generated by currents flowing through the transmitting coil CL1 (coil CL11, coil CL12) and the receiving coil CL4 (coil CL41, coil CL42). However, in the semiconductor device DEV3, a slit opening OP5 is formed in the shield SH1, and the range through which the eddy currents tend to flow is limited by the slit opening OP5. In this way, the semiconductor device DEV3 can suppress the generation of eddy currents in the shield SH1.

[0090] (Fourth embodiment) A semiconductor device according to a fourth embodiment will be described. The semiconductor device according to the fourth embodiment will be referred to as a semiconductor device DEV4. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0091] <Configuration of semiconductor device DEV4> The configuration of the semiconductor device DEV4 will be described below.

[0092] The semiconductor device DEV4 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV4 is common to the configuration of the semiconductor device DEV1.

[0093] Fig. 21 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV4. As shown in Fig. 21, in the semiconductor device DEV4, the shield SH1 is formed separately between the coil CL12 and the coil CL41 in a plan view. That is, in the semiconductor device DEV4, the shield SH1 has a first portion SH1a overlapping the transmitting coil CL1 in a plan view and a second portion SH1b overlapping the receiving coil CL4 in a plan view.

[0094] In the semiconductor device DEV4, the semiconductor chip CHP3 has wiring WL9a and wiring WL9b instead of the wiring WL9. The wiring WL9a is connected to the first portion SH1a at one end and to the wiring WL10 at the other end. As a result, the first portion SH1a is connected to the reference potential. The wiring WL9b is connected to the second portion SH1b at one end and to the wiring WL10 at the other end. As a result, the second portion SH1b is connected to the reference potential. In these respects, the configuration of the semiconductor device DEV4 differs from the configuration of the semiconductor device DEV1.

[0095] <Effects of semiconductor device DEV4> The effects of the semiconductor device DEV4 will be described below.

[0096] The insulating film IF2 between the transmitting coil CL1 (coil CL11, coil CL12) and the shield SH1 constitutes a capacitance. Similarly, the insulating film IF2 between the receiving coil CL4 (coil CL41, coil CL42) and the shield SH1 also constitutes a capacitance. Therefore, crosstalk may occur between the channels when a high-frequency current flowing through one of the transmitting coil CL1 and the receiving coil CL4 flows through the above-mentioned capacitance and the shield SH2 to the other of the transmitting coil CL1 and the receiving coil CL4.

[0097] In the semiconductor device DEV4, the shield SH1 is formed to be divided between the transmitter coil CL1 and the receiver coil CL4 (between the coil CL12 and the coil CL41) in a plan view, so that the above-mentioned current is unlikely to flow from one of the transmitter coil CL1 and the receiver coil CL4 to the other of the transmitter coil CL1 and the receiver coil CL4. Therefore, according to the semiconductor device DEV4, it is possible to further suppress crosstalk between the channels.

[0098] Fifth embodiment A semiconductor device according to a fifth embodiment will be described. The semiconductor device according to the fifth embodiment is designated as semiconductor device DEV5. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0099] <Configuration of semiconductor device DEV5> The configuration of the semiconductor device DEV5 will be described below.

[0100] The semiconductor device DEV5 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0101] Fig. 22 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV5. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 22. As shown in Fig. 22 and Fig. 23, the semiconductor device DEV5 has a shield SH2 and a plurality of via plugs VP11.

[0102] The shield SH2 is disposed between the transmitting coil CL1 and the receiving coil CL4 in a planar view. More specifically, the shield SH2 is disposed between the coil CL12 and the coil CL41 in a planar view. The shield SH2 is composed of, for example, a wiring WL12 and a via plug VP11.

[0103] The wiring WL12 is disposed on the insulating film IF2. That is, the wiring WL12 is formed in the same layer as the transmitting coil CL1 (coil CL11, coil CL12) and the receiving coil CL4 (coil CL41, coil CL42). The wiring WL12 extends in the second direction DR2 in a plan view. The wiring WL12 is made of a conductive material mainly composed of aluminum. The wiring WL12 may be made of a conductive material mainly composed of copper. The via plug VP11 is embedded in the insulating film IF2. The multiple via plugs VP11 are arranged at intervals in the second direction DR2 in a plan view. The via plugs VP11 are made of a conductive material mainly composed of tungsten.

[0104] The width of WL12 in the second direction DR2 is larger than the width of the coil CL12 in the second direction DR2 and the width of the coil CL41 in the second direction DR2. The wiring WL12 is connected to, for example, the wiring WL10 disposed on the insulating film IF2. The via plug VP11 electrically connects the wiring WL12 and the shield SH1. Therefore, the shield SH2 is electrically connected to the reference potential.

[0105] The shortest distance between the lower layer coils (transmitting coil CL1, receiving coil CL4) and the upper layer coils (receiving coil CL2, transmitting coil CL3) is the first distance. The shortest distance between the upper layer coils and the shield SH2 (wiring WL12) is the second distance. In order to ensure the withstand voltage between the lower layer coils and the upper layer coils, the second distance is greater than the first distance. In these respects, the configuration of the semiconductor device DEV5 is common to the configuration of the semiconductor device DEV1.

[0106] The via plug VP11 is formed in a second via plug forming step S7, and the wiring WL12 is formed in a first coil forming step S8.

[0107] <Effects of semiconductor device DEV5> The effects of the semiconductor device DEV5 will be described below.

[0108] Since the transmitter coil CL1 and the receiver coil CL4 are adjacent to each other, electromagnetic waves generated by a current flowing through one of the transmitter coil CL1 and the receiver coil CL4 may interfere with the other of the transmitter coil CL1 and the receiver coil CL4, causing crosstalk between the channels. In the semiconductor device DEV5, a shield SH2 electrically connected to a reference potential is disposed between the transmitter coil CL1 and the receiver coil CL4 in a plan view. Therefore, according to the semiconductor device DEV5, the shield SH2 functions as a Faraday shield, and it is possible to suppress the occurrence of the above-mentioned crosstalk between the channels.

[0109] In the semiconductor device DEV5, the constituent material of the shield SH2 (the constituent material of the wiring WL12 and the constituent material of the via plug VP11) is a metal material with low electrical resistance, and electrons induced by electromagnetic waves are quickly discharged from the shield SH2, so that the shield SH2 effectively functions as a Faraday shield.

[0110] Sixth embodiment A semiconductor device according to a sixth embodiment will be described. The semiconductor device according to the sixth embodiment will be referred to as a semiconductor device DEV6. Here, differences from the semiconductor device DEV5 will be mainly described, and overlapping descriptions will not be repeated.

[0111] <Configuration of semiconductor device DEV6> The configuration of the semiconductor device DEV6 will be described below.

[0112] The semiconductor device DEV6 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In this respect, the configuration of the semiconductor device DEV6 is common to the configuration of the semiconductor device DEV5.

[0113] Fig. 24 is a plan view of the semiconductor chip CHP3 in the semiconductor device DEV6. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 24. As shown in Fig. 24 and Fig. 25, the semiconductor device DEV6 does not have a shield SH1.

[0114] In the semiconductor device DEV6, the shield SH2 is composed of a wiring WL12, a wiring WL13, and a via plug VP11. That is, the shield SH2 is composed of a wiring formed in the same layer as the wiring WL10 on the insulating film IF1, a wiring formed in the same layer as the wiring WL10 on the insulating film IF2, and a via plug between these wirings. The wiring WL13 extends in the second direction DR2 in a plan view. The wiring WL13 is disposed on the insulating film IF1. The wiring WL13 overlaps with the wiring WL12 in a plan view. The wiring WL13 is made of a conductive material mainly composed of aluminum, for example. The wiring WL13 is made of a conductive material mainly composed of copper. In the semiconductor device DEV6, the wiring WL13 is formed in the shield formation process S5 instead of the shield SH1.

[0115] The wiring WL12 and the wiring WL13 are electrically connected by a plurality of via plugs VP11. Moreover, the wiring WL13 is connected to the wiring WL10 on the insulating film IF1. That is, the wiring WL12 and the wiring WL13 are stacked via a plurality of via plugs VP11. Therefore, the shield SH2 is connected to the reference potential. Since the plurality of via plugs VP11 are arranged at intervals, the wiring WL12 and the wiring WL13 are connected in a dot via structure. The interval between two adjacent via plugs VP11 is set as the interval SP. The interval SP is, for example, 0.3 μm or more and 2 μm or less. In these respects, the configuration of the semiconductor device DEV6 differs from the configuration of the semiconductor device DEV5.

[0116] <Modification> Fig. 26 is a cross-sectional view of a semiconductor chip CHP3 according to a modified example of the semiconductor device DEV6. Fig. 26 shows a cross section at a position corresponding to IIV-IIV in Fig. 24. As shown in Fig. 26, the number of via plugs VP11 may be one. In this case, the via plugs VP11 are continuously formed in the direction in which the wirings WL12 and WL13 extend in a plan view. From another perspective, the wirings WL12 and WL13 may be connected by a slit via structure.

[0117] <Effects of semiconductor device DEV6> The effects of the semiconductor device DEV6 will be described below.

[0118] In the semiconductor device DEV6, the shield SH2 electrically connected to the reference potential is disposed between the transmitter coil CL1 and the receiver coil CL4 in a plan view, so that the shield SH2 functions as a Faraday shield and can suppress the occurrence of crosstalk between the channels. If the interval SP is 2 μm or less, the interval SP becomes smaller than the wavelength of the electromagnetic waves generated by the transmitter coil CL1 and the receiver coil CL4, so that the occurrence of crosstalk between the channels can be sufficiently suppressed. If the via plugs VP11 are formed continuously in the direction in which the wiring WL12 and the wiring WL13 extend, there is no gap between the adjacent via plugs VP11, so that the occurrence of crosstalk between the channels can be further suppressed.

[0119] (Additional Note) The above embodiment includes the following configurations.

[0120] <Appendix 1> A first semiconductor chip; A second semiconductor chip; a third semiconductor chip; the first semiconductor chip has a first transmitting circuit and a first receiving circuit; the second semiconductor chip has a second transmitting circuit and a second receiving circuit; the third semiconductor chip includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield; the semiconductor substrate has an element region and a peripheral region; the peripheral region is located around the element region in a plan view, the first coil and the second coil are disposed on the element region and are aligned in a first direction in a plan view; the third coil and the fourth coil face the first coil and the second coil, respectively, via the insulating layer; the first shield is disposed between the semiconductor substrate and the first coil and the second coil, and overlaps the first coil and the second coil in a plan view; a width of the first shield in a second direction perpendicular to the first direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction; the first shield is electrically connected to a reference potential; a signal transmitted from the first transmission circuit is transmitted to the second reception circuit via the first coil and the third coil; A semiconductor device, wherein a signal transmitted from the second transmitting circuit is transmitted to the first receiving circuit via the fourth coil and the second coil.

[0121] <Appendix 2> 2. The semiconductor device according to claim 1, wherein a signal transmission method from the first transmission circuit to the second reception circuit and a signal transmission method from the second transmission circuit to the first reception circuit are a pulse communication method.

[0122] <Appendix 3> 2. The semiconductor device according to claim 1, wherein the first shield is formed continuously so as to straddle the first coil and the second coil in a plan view.

[0123] <Appendix 4> the first shield has a plurality of openings; 2. The semiconductor device according to claim 1, wherein the openings are arranged in a lattice or checkerboard pattern in a plan view.

[0124] <Appendix 5> 5. The semiconductor device according to claim 4, wherein, in a plan view, the length of the opening in the longitudinal direction is 50 μm or less.

[0125] <Appendix 6> the first shield has a plurality of slit openings; 2. The semiconductor device according to claim 1, wherein the plurality of slit openings are arranged radially in a plan view.

[0126] <Appendix 7> 2. The semiconductor device according to claim 1, wherein the first shield is formed separately between the first coil and the second coil in a plan view.

[0127] <Appendix 8> a second shield disposed between the first coil and the second coil in a plan view; a width of the second shield in the second direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction; 2. The semiconductor device according to claim 1, wherein the second shield is electrically connected to the reference potential.

[0128] <Appendix 9> 9. The semiconductor device according to claim 8, wherein the first shield is electrically connected to the second shield and is electrically connected to the reference potential via the second shield.

[0129] <Appendix 10> the second shield is spaced apart from the first coil and the second coil in a plan view, 9. The semiconductor device according to claim 8, wherein, in a plan view, a distance between the first coil and the second shield and a distance between the second coil and the second shield are 12 μm or more and 100 μm or less.

[0130] <Appendix 11> the second shield has a plurality of first via plugs, and a first wiring and a second wiring that are stacked with the plurality of first via plugs interposed therebetween; 9. The semiconductor device according to claim 8, wherein a distance between two adjacent ones of the plurality of first via plugs is not less than 0.3 μm and not more than 2 μm.

[0131] <Appendix 12> the second shield has a first via plug, and a first wiring and a second wiring stacked with the first via plug interposed therebetween; 9. The semiconductor device according to claim 8, wherein the first via plug is formed continuously along a direction in which the first wiring and the second wiring extend.

[0132] <Appendix 13> the second shield has at least one first via plug, and a first wiring and a second wiring stacked with the at least one first via plug interposed therebetween; a constituent material of the first via plug is a conductive material containing tungsten as a main component; 9. The semiconductor device according to claim 8, wherein a constituent material of the first wiring and a constituent material of the second wiring are conductive materials mainly composed of aluminum or copper.

[0133] <Appendix 14> 2. The semiconductor device according to claim 1, wherein the first shield is made of a conductive material mainly composed of aluminum or copper.

[0134] <Appendix 15> 2. The semiconductor device according to claim 1, further comprising a lead-out wiring formed in the same layer as the first shield and connected to the first shield.

[0135] <Appendix 16> a guard ring disposed on the peripheral region; the guard ring has a plurality of wirings and a plurality of second via plugs; the wiring and the second via plug are alternately stacked, the plurality of wirings include a third wiring in a lowermost layer and a fourth wiring in a layer above the third wiring; the first shield is formed in the same layer as the third wiring, The semiconductor device according to claim 8, wherein the second shield is formed in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring.

[0136] <Appendix 17> 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the distance between the first coil and the third coil or the distance between the second coil and the fourth coil is 6 μm or more and 14 μm or less.

[0137] <Appendix 18> the first coil and the third coil are magnetically coupled to each other, 2. The semiconductor device according to claim 1, wherein the second coil and the fourth coil are magnetically coupled to each other.

[0138] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0139] CHP1, CHP2, CHP3 semiconductor chips, CL1, CL3 transmitting coils, CL2, CL4 receiving coils, CL11, CL12, CL21, CL22, CL31, CL32, CL41, CL42 coils, D1, D2 distance, DEV1, DEV2, DEV3, DEV4, DEV5, DEV6 semiconductor device, DR driving circuit, DR1 first direction, DR2 second direction, FS first surface, GR1a, SH1a first portion, GR1b, SH1b second portion, GR1, GR2 guard rings, IF1, IF2, IF3 insulating film, IR impurity implanted region, OP1, OP2, OP3, OP4 opening, OP5 slit opening, PD1, PD2, PD3, PD4, PD5 pads, PF passivation film, PL1, PL2 lead wires, RX1, RX2 receiving circuit, S1 preparation process, S2 Ion implantation process, S3 First insulating film formation process, S4 First via plug formation process, S5 Shield formation process, S6 Second insulating film formation process, S7 Second via plug formation process, S8 First coil formation process, S9 Third insulating film formation process, S10 Third via plug formation process, S11 Wiring formation process, S12 Second coil formation process, S13 Passivation film formation process, SG1, SG2, SG3, SG4 Signal, SH1, SH2 Shield, SP Spacing, SR Seal ring, SS Second surface, SUB Semiconductor substrate, SUB1 Element region, SUB2 Peripheral region, SUB3 Outer periphery region, TR1, TR2 Transformer, TX1, TX2 Transmitting circuit, VP1, VP2, VP3, VP4, VP5, VP6, VP7, VP8, VP9, ​​VP10, VP11 Via plugs, WL1,WL2,WL3,WL4,WL5,WL6,WL7,WL8,WL9a,WL9,WL9b,WL10,WL11,WL12,WL13 wiring.

Claims

1. A semiconductor substrate; A first coil, a second coil, a third coil and a fourth coil; An insulating layer; a first shield; the semiconductor substrate has an element region and a peripheral region; the peripheral region is located around the element region in a plan view, the first coil and the second coil are disposed on the element region and are aligned in a first direction in a plan view, the third coil and the fourth coil face the first coil and the second coil, respectively, via the insulating layer; the first shield is disposed between the semiconductor substrate and the first coil and the second coil, and overlaps the first coil and the second coil in a plan view; a width of the first shield in a second direction perpendicular to the first direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction; The first shield is electrically connected to a reference potential.

2. The semiconductor device according to claim 1 , wherein the first shield is formed continuously across the first coil and the second coil in a plan view.

3. the first shield has a plurality of openings; The semiconductor device according to claim 1 , wherein the openings are arranged in a lattice or checkerboard pattern in a plan view.

4. The semiconductor device according to claim 3 , wherein the length of the opening in a longitudinal direction is 50 μm or less in a plan view.

5. the first shield has a plurality of slit openings; The semiconductor device according to claim 1 , wherein the plurality of slit openings are arranged radially in a plan view.

6. The semiconductor device according to claim 1 , wherein the first shield is formed separately between the first coil and the second coil in a plan view.

7. a second shield disposed between the first coil and the second coil in a plan view; a width of the second shield in the second direction is greater than a width of the first coil in the second direction and a width of the second coil in the second direction; The semiconductor device according to claim 1 , wherein the second shield is electrically connected to the reference potential.

8. 8. The semiconductor device according to claim 7, wherein said first shield is electrically connected to said second shield and is electrically connected to said reference potential via said second shield.

9. the second shield is spaced apart from the first coil and the second coil in a plan view, The semiconductor device according to claim 7 , wherein in a plan view, a distance between the first coil and the second shield and a distance between the second coil and the second shield are not less than 12 μm and not more than 100 μm.

10. the second shield has a plurality of first via plugs, and a first wiring and a second wiring that are stacked with the plurality of first via plugs interposed therebetween; 8. The semiconductor device according to claim 7, wherein a distance between two adjacent ones of the plurality of first via plugs is not less than 0.3 [mu]m and not more than 2 [mu]m.

11. the second shield has a first via plug, and a first wiring and a second wiring stacked with the first via plug interposed therebetween; 8. The semiconductor device according to claim 7, wherein said first via plug is formed continuously along a direction in which said first wiring and said second wiring extend.

12. the second shield has at least one first via plug, and a first wiring and a second wiring stacked with the at least one first via plug interposed therebetween; a constituent material of the first via plug is a conductive material containing tungsten as a main component; 8. The semiconductor device according to claim 7, wherein a constituent material of said first wiring and a constituent material of said second wiring are conductive materials mainly composed of aluminum or copper.

13. 2. The semiconductor device according to claim 1, wherein the first shield is made of a conductive material containing aluminum or copper as a main component.

14. The semiconductor device according to claim 1 , further comprising: a lead-out wiring formed in the same layer as said first shield and connected to said first shield.

15. a guard ring disposed on the peripheral region; the guard ring includes a plurality of wirings and a plurality of second via plugs; the wiring and the second via plug are alternately stacked, the plurality of wirings include a third wiring in a lowermost layer and a fourth wiring in a layer above the third wiring, the first shield is formed in the same layer as the third wiring, 8. The semiconductor device according to claim 7, wherein the second shield is formed in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring.

16. 2 . The semiconductor device according to claim 1 , wherein in a cross-sectional view, a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is not less than 6 μm and not more than 14 μm.

17. the first coil and the third coil are magnetically coupled to each other, The semiconductor device according to claim 1 , wherein the second coil and the fourth coil are magnetically coupled to each other.

18. A semiconductor substrate; a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; An insulating layer; a first shield; the semiconductor substrate has an element region and a peripheral region; the peripheral region is located around the element region in a plan view, the first coil, the second coil, the fifth coil, and the sixth coil are disposed on the element region and are aligned in a first direction in a plan view, The first coil and the second coil are adjacent to each other, the fifth coil is adjacent to the first coil from a side opposite to the second coil and is electrically connected in series to the first coil; the sixth coil is adjacent to the second coil from a side opposite to the first coil and is electrically connected in series to the second coil; the third coil, the fourth coil, the seventh coil, and the eighth coil face the first coil, the second coil, the fifth coil, and the sixth coil, respectively, via the insulating layer; the seventh coil is electrically connected in series with the third coil; the eighth coil is electrically connected in series with the fourth coil, the first shield is disposed between the semiconductor substrate and the first coil, the second coil, the fifth coil, and the sixth coil, and overlaps the first coil, the second coil, the fifth coil, and the sixth coil in a plan view; a width of the first shield in a second direction perpendicular to the first direction is greater than a width of the first coil in the second direction, a width of the second coil in the second direction, a width of the fifth coil in the second direction, and a width of the sixth coil in the second direction; The first shield is electrically connected to a reference potential.

19. a second shield disposed between the first coil and the second coil in a plan view; a width of the second shield in the second direction is greater than a width of the first coil in the second direction, a width of the second coil in the second direction, a width of the fifth coil in the second direction, and a width of the sixth coil in the second direction; The semiconductor device according to claim 18 , wherein the second shield is electrically connected to the reference potential.

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