Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the electric field concentration at a bottom part of a trench structure can be suppressed.SOLUTION: A semiconductor device includes a first layer formed of silicon carbide of a first conductivity type, a second layer formed of silicon carbide of a second conductivity type on the first layer, a third layer formed of silicon carbide of the first conductivity type on the second layer, and a plurality of trench structures formed in a stripe shape ranging from the third layer side to the first layer. The trench structure includes a first curved part formed at a bottom part and a second curved part formed between the bottom part and a side part in a cross-sectional view in a short-side direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a trench MOSFET. The trench MOSFET can increase the density of unit cells (component units of an element) per unit area and can increase the current density per unit area, which enables cost reduction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2023-013100 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a trench MOSFET, the electric field is concentrated at the bottom corners of the trench structure, which can cause dielectric breakdown at the bottom corners of the trench structure.

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress electric field concentration in a trench structure. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a first layer formed of silicon carbide of a first conductivity type, a second layer formed of silicon carbide of a second conductivity type on the first layer, a third layer formed of silicon carbide of the first conductivity type on the second layer, and a plurality of trench structures formed in a stripe pattern extending from the side of the third layer to the first layer, wherein the trench structure, in a cross-sectional view in the short direction, comprises a first curved portion formed at a bottom and a second curved portion formed between the bottom and a side.

[0007] In one embodiment of the present disclosure, the first curved portion has a radius of curvature larger than a radius of curvature of the second curved portion.

[0008] In one embodiment of the present disclosure, the first curved portion has a radius of curvature that is 1.5 to 3 times the radius of curvature of the second curved portion.

[0009] One embodiment of the present disclosure is that the trench structure includes a third curved portion that is formed between the first curved portion and the second curved portion in a cross-sectional view in the short side direction, and has a radius of curvature that gradually decreases from that of the first curved portion to that of the second curved portion as it moves from the first curved portion to the second curved portion.

[0010] In one aspect of the present disclosure, in the trench structure, the sides are inclined so that the upper portion of the trench is wider.

[0011] According to one embodiment of the present disclosure, the trench structure has a longitudinal side curved portion formed at an end portion in a longitudinal cross-sectional view and having a radius of curvature larger than the radius of curvature of the second curved portion.

[0012] According to one embodiment of the present disclosure, the first layer, the second layer, and the third layer are formed primarily from 4H silicon carbide, and the longitudinal direction of the trench structure is parallel to a hexagonal (11-20) plane, a (1-210) plane, or a (-2110) plane of 4H silicon carbide, which is a plane perpendicular to a main surface of a substrate formed by the first layer, the second layer, and the third layer.

[0013] According to one embodiment of the present disclosure, the first layer, the second layer, and the third layer are formed primarily from 4H silicon carbide, and the longitudinal direction of the trench structure is parallel to a hexagonal (1-100) plane, a (10-10) plane, or a (0-110) plane of 4H silicon carbide, which is a plane perpendicular to a main surface of a substrate formed by the first layer, the second layer, and the third layer.

[0014] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming a first oxide film on a substrate formed of a first layer made of silicon carbide of a first conductivity type, a second layer formed of silicon carbide of a second conductivity type on the first layer, and a third layer formed of silicon carbide of the first conductivity type on the second layer, thereby forming a first etching mask by forming a plurality of striped first grooves having inclined sides in the first oxide film; forming a second etching mask after the first etching mask forming step, forming a second oxide film on the first etching mask, thereby forming a plurality of striped second grooves having inclined sides and a bottom having multiple steps of curvature at positions of the plurality of striped first grooves; and forming a trench structure after the second etching mask forming step, by performing anisotropic etching on the substrate to form a plurality of striped trench structures having inclined sides and a bottom having multiple steps of curvature from the third layer side to the first layer. Effect of the Invention

[0015] According to the present disclosure, electric field concentration in a trench structure can be suppressed. [Brief description of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device in a first embodiment. [Diagram 2] 2 is a diagram showing crystal planes of a 4H silicon carbide crystal used in the semiconductor device in the first embodiment. FIG. [Diagram 3]1 is a diagram showing a crystal face of a 4H silicon carbide crystal used in the semiconductor device in the first embodiment, viewed from the (0001) plane side. [Figure 4] 2 is a cross-sectional view in the short side direction of a trench structure of the semiconductor device in the first embodiment. [Diagram 5] 1 is a cross-sectional view in a longitudinal direction of a trench structure of a semiconductor device in a first embodiment. [Figure 6] 2A to 2C are diagrams for explaining the manufacturing method of the semiconductor device in the first embodiment. [Figure 7] 2A to 2C are diagrams for explaining the manufacturing method of the semiconductor device in the first embodiment. [Figure 8] 2A to 2C are views for explaining a method of forming a trench structure of the semiconductor device in the first embodiment. [Figure 9] 2A to 2C are views for explaining a method of forming a trench structure of the semiconductor device in the first embodiment. [Figure 10] 4 is a diagram showing an optical image intensity distribution of a line and space pattern used in manufacturing the semiconductor device in the first embodiment. FIG. [Figure 11] 4 is a diagram showing a sensitivity curve of a positive resist used in manufacturing the semiconductor device in the first embodiment. [Figure 12] 4 is a cross-sectional view of trench structures of the semiconductor device in the first embodiment and a first and second comparative examples. FIG. [Figure 13] 4 is a diagram showing an electric field distribution in the vicinity of the trench structure of the semiconductor device in the first embodiment. FIG. [Figure 14] FIG. 4 is a diagram showing an electric field distribution in the vicinity of the trench structure of the first comparative example. [Figure 15] FIG. 11 is a diagram showing an electric field distribution in the vicinity of the trench structure of the second comparative example. [Figure 16] 11 is a diagram showing a comparison result of electric field intensity in the vicinity of a trench structure between the semiconductor device in the first embodiment and the first and second comparative examples. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiments will be described with reference to the accompanying drawings. In each drawing, the same or corresponding parts are denoted by the same reference numerals. Duplicate descriptions of the parts will be appropriately simplified or omitted.

[0018] Embodiment 1 FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment.

[0019] In Fig. 1, the semiconductor device 1 is a trench-type silicon carbide MOSFET. The semiconductor device 1 includes a drain layer 2, a drift layer 3, a plurality of body layers 4, a plurality of source layers 5, a plurality of body contact layers 6, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, and a drain electrode layer 12. The plurality of trench structures T are formed in a stripe shape in the depth direction of Fig. 1. Note that Fig. 1 illustrates only one of each of the plurality of gate insulating layers 7, the plurality of gate electrode layers 8, the plurality of interlayer insulating layers 9, and the plurality of trench structures T.

[0020] The drain layer 2 is made of silicon carbide of a first conductivity type. For example, the drain layer 2 is made of n + The drift layer 3 is formed of first conductivity type 4H silicon carbide having a lower impurity concentration than the drain layer 2. For example, the drift layer 3 is formed with nitrogen as an impurity. The drift layer 3 is formed as a first layer on a first surface (upper surface in FIG. 1 ) of the drain layer 2. The drift layer 3 is formed of first conductivity type silicon carbide having a lower impurity concentration than the drain layer 2. For example, the drift layer 3 is formed of n - This is the mold layer.

[0021] The body layers 4 are formed as second layers on the upper side of the drift layer 3. The body layers 4 are made of silicon carbide of a second conductivity type. For example, the body layers 4 are p-type layers. The source layers 5 are formed as third layers on the upper side of each of the body layers 4. The source layers 5 are made of silicon carbide of a first conductivity type having a higher impurity concentration than the drift layer 3. For example, the source layers 5 are n-type layers. +The body contact layers 6 are formed on the upper side of each of the body layers 4. In each of the body layers 4, the body contact layer 6 is surrounded by the source layer 5. The body contact layers 6 are formed of silicon carbide of the second conductivity type having a higher impurity concentration than the body layers 4. For example, the body contact layers 6 are formed of p + This is the mold layer.

[0022] The multiple gate insulating layers 7 are formed in the multiple stripe-shaped trench structures T extending from the source layer 5 side to the drift layer 3 in the adjacent body layers 4. For example, the multiple gate insulating layers 7 are made of silicon dioxide. For example, the multiple gate insulating layers 7 are made of aluminum oxide. The multiple gate electrode layers 8 are formed on the multiple gate insulating layers 7 in each of the multiple trench structures T.

[0023] The interlayer insulating layers 9 are formed so as to cover the gate electrode layers 8, respectively. The source electrode layers 10 are formed corresponding to the body layers 4, respectively. The source electrode layers 10 are formed so as to contact the source layers 5. The source electrode layers 10 may be formed so as to straddle the body contact layers 6. The wiring electrode layer 11 is formed so as to cover the source electrode layers 10. The drain electrode layer 12 is formed on a second surface (the lower surface in FIG. 1 ) of the drain layer 2.

[0024] Next, the direction in which the trench structure T is formed will be described with reference to FIGS. Fig. 2 is a diagram showing a crystal plane of a 4H silicon carbide crystal used in the semiconductor device in accordance with embodiment 1. Fig. 3 is a diagram showing the crystal plane of a 4H silicon carbide crystal used in the semiconductor device in accordance with embodiment 1, as viewed from the (0001) plane side.

[0025] The drain layer 2 and the drift layer 3 form a substrate mainly made of 4H silicon carbide. 4H silicon carbide is a hexagonal crystal. As shown in FIG. 2(a), the main surface of the hexagonal crystal is the (0001) Si surface. The trench structure T is formed so that its longitudinal direction is parallel to a surface perpendicular to the main surface. For example, as shown in FIG. 2(b), the trench structure T is formed so that its longitudinal direction is parallel to the (11-20) or (1-100) crystal orientation surface.

[0026] FIG. 3(a) shows the (11-20) plane, the (1-100) plane, the (1-210) plane, and the (-2110) plane. FIG. 3(b) shows the (1-100) plane, the (10-10) plane, and the (0-110) plane. FIG. 3(c) shows an orientation flat for checking the direction of the substrate. A hexagonal crystal has six-fold symmetry. For this reason, in FIG. 3(a), the (1-210) plane or the (-2110) plane may be taken as the longitudinal direction of the trench structure T. In FIG. 3(b), the (10-10) plane or the (0-110) plane may be taken as the longitudinal direction of the trench structure T.

[0027] Regarding 4H silicon carbide, epitaxial growth may be performed with the hexagonal crystal tilted at 4 degrees or 8 degrees. Therefore, the (10-10) plane, (0-110) plane, (1-210) plane, and (-2110) plane of the cubic crystal of 4H silicon carbide slightly change in angle from the top view. For example, the angle between the (1-210) plane and the (-2110) plane is 30 degrees when viewed from the top of the cubic crystal. In contrast, in the case of epitaxial growth with a 4 degree tilt, the angle between the (1-210) plane and the (-2110) plane is 29.94 degrees when viewed from the top of the substrate. The longitudinal direction of the trench structure T may be approximately parallel to any of the faces, including the above error and other manufacturing errors. It is preferable that the longitudinal direction of the trench structure T is within ±0.2 degrees of deviation from any of the faces.

[0028] As shown in FIG. 3C, the orientation flat generally coincides with the (1-100) plane. The angle between the orientation flat and the (1-100) plane may vary by ±5 degrees due to manufacturing errors. The longitudinal direction of the trench structure T is set in consideration of the variation. Specifically, the longitudinal direction of the trench structure T is set to be at any one of an angle between -5 degrees and 5 degrees, an angle between 25 degrees and 35 degrees, an angle between 55 degrees and 65 degrees, an angle between 85 degrees and 95 degrees, an angle between 115 degrees and 125 degrees, and an angle between 145 degrees and 155 degrees with respect to the orientation flat.

[0029] Next, the trench structure T will be described in detail with reference to FIGS. Fig. 4 is a sectional view in the short direction of the trench structure of the semiconductor device in accordance with the first embodiment. Fig. 5 is a sectional view in the long direction of the trench structure of the semiconductor device in accordance with the first embodiment.

[0030] As shown in FIG. 4, in a cross-sectional view of the trench structure T in the short direction, the side is inclined so that the upper part of the trench is wider. In a cross-sectional view of the trench structure T in the short direction, the bottom has a multi-step curvature. For example, a first curved portion 13, a second curved portion 14, and a third curved portion 15 are formed. The first curved portion 13 is formed in the center of the bottom of the trench structure T. The second curved portion 14 is formed between the bottom and the side of the trench structure T. The third curved portion 15 is formed between the first curved portion 13 and the second curved portion 14. The third curved portion 15 is continuously connected to the first curved portion 13 and the second curved portion 14. The radius of curvature of the first curved portion 13 is larger than the radius of curvature of the second curved portion 14. For example, the value of the radius of curvature of the first curved portion 13 is 1.5 to 3 times the value of the radius of curvature of the second curved portion 14. The radius of curvature of the third curved portion 15 gradually decreases from the radius of curvature of the first curved portion 13 to the radius of curvature of the second curved portion 14 as it moves from the first curved portion 13 to the second curved portion 14.

[0031] 5, in a cross-sectional view in the longitudinal direction of the trench structure T, a pair of longitudinal side curved portions 16 are formed. The pair of longitudinal side curved portions 16 are formed at the ends of the bottom in the longitudinal direction of the trench structure T. The radius of curvature of the longitudinal side curved portions 16 is larger than the radius of curvature of the second curved portion 14.

[0032] Next, a manufacturing method of the semiconductor device 1 will be described with reference to FIGS. 6 and 7 are diagrams for explaining a method for manufacturing a semiconductor device in embodiment 1. In addition, in Fig. 6 and Fig. 7, an upper surface of semiconductor device 1 in the manufacturing process is set as a first surface. A lower surface of semiconductor device 1 in the manufacturing process is set as a second surface.

[0033] First, as shown in (a) of Fig. 6, a drain layer formation process is performed. In the drain layer formation process, a drain layer 2 is formed. Then, as shown in (b) of Fig. 6, a drift layer formation process is performed. In the drift layer formation process, a drift layer 3 is formed by epitaxial growth.

[0034] Thereafter, as shown in (c) of FIG. 6, a body layer forming step, a source layer forming step, and a body contact layer forming step are performed. In the body layer forming step, a plurality of body layers 4 are formed. For example, the plurality of body layers 4 are formed by an ion implantation method using aluminum as an impurity. In the source layer forming step, a plurality of source layers 5 are formed. For example, the plurality of source layers 5 are formed by an ion implantation method using nitrogen as an impurity. In the body contact layer forming step, a plurality of body contact layers 6 are formed. For example, the plurality of body contact layers 6 are formed by an ion implantation method using aluminum as an impurity.

[0035] Thereafter, as shown in (d) of FIG. 6, a trench structure forming step, a carbon film forming step, a high-temperature annealing step, and a carbon film removing step are performed. In the trench structure forming step, a plurality of trench structures T are formed. In the carbon film forming step, a carbon film is formed so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. In the high-temperature annealing step, an annealing process is performed in a high-temperature atmosphere. In the carbon film removing step, the carbon film is removed.

[0036] Thereafter, as shown in (e) of Fig. 6, a gate insulating layer forming process is performed. In the gate insulating layer forming process, first, an oxide film is formed by a thermal oxidation method so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Then, a nitriding process is performed on the oxide film. Then, a resist pattern is formed. Then, the oxide film is etched. Then, the resist pattern is removed. As a result, a plurality of gate insulating layers 7 remain.

[0037] Thereafter, as shown in FIG. 7(a), a gate electrode layer forming step is performed. In the gate electrode layer forming step, first, a polysilicon film is formed by CVD so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Then, a resist pattern is formed. Then, the polysilicon film is etched. Then, the resist pattern is removed. As a result, a plurality of gate electrode layers 8 remain. Thereafter, as shown in FIG. 7(b), an interlayer insulating layer forming step is performed. In the interlayer insulating layer forming step, first, a silicon dioxide film is formed by CVD so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Then, a resist pattern is formed. Then, the silicon dioxide film is etched. Then, the resist pattern is removed. As a result, a plurality of interlayer insulating layers 9 remain.

[0038] Thereafter, as shown in FIG. 7(c), a source electrode layer forming process is performed. In the source electrode layer forming process, first, a metal film such as Ni, Ti, or the like is formed by sputtering so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. Then, an ohmic reaction layer is formed by RTA (Rapid Thermal Anneal). As a result, a plurality of source electrode layers 10 remain. Then, as shown in FIG. 7(d), a wiring electrode layer forming process is performed. In the wiring electrode layer forming process, first, a metal film such as Al, AlSi, or the like is formed by sputtering so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. As a result, the wiring electrode layer 11 remains.

[0039] Thereafter, as shown in (e) of Fig. 7, a drain electrode layer forming process is performed. In the drain electrode layer forming process, a metal film such as Ni, Ti, etc. is first formed by a sputtering method or the like so as to entirely cover the second surface side of the semiconductor device 1 in the manufacturing process. Then, an ohmic reaction layer is formed by laser annealing or RTA (Rapid Thermal Anneal). As a result, the drain electrode layer 12 remains.

[0040] Next, a method for forming the trench structure T will be described with reference to FIGS. 8 and 9 are diagrams for explaining a method of forming a trench structure of a semiconductor device in embodiment 1. An upper surface of the in-process structure is set to a first surface. A lower surface of the in-process structure is set to a second surface.

[0041] First, as shown in FIG. 8(a), a first silicon dioxide film forming step and a first resist film applying step are performed as part of a first etching mask forming step. In the first silicon dioxide film forming step, a first silicon dioxide film (first oxide film) 17 is formed so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. In the first resist film applying step, a first resist 18 is applied so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Thereafter, as shown in FIG. 8(b), a first resist pattern forming step is performed as part of a first etching mask forming step. In the first resist pattern forming step, a first resist pattern is formed by exposure and development. As a result, a plurality of stripe-shaped openings are formed in the first resist pattern.

[0042] Thereafter, as shown in FIG. 8(c), a first resist pattern inclination forming step is performed as a part of a first etching mask forming step. In the first resist pattern inclination forming step, inclinations are formed on the sides of a plurality of openings of the first resist pattern by thermal shrinkage or reflow. Thereafter, as shown in FIG. 8(d), a first anisotropic etching step is performed as a part of a first etching mask forming step. In the first anisotropic etching step, reactive ion etching is performed on the first silicon dioxide film 17 using the first resist 18 as a mask. At this time, the selectivity ratio between the first silicon dioxide film 17 and the first resist 18 is about 1:1. As a result, a plurality of stripe-shaped first grooves with inclined sides are formed in the first silicon dioxide film 17. Thereafter, as shown in FIG. 8(e), a first resist removal step is performed as a part of a first etching mask forming step. In the first resist removal step, the first resist 18 is removed. As a result, the first silicon dioxide film 17 is exposed as a first etching mask.

[0043] Thereafter, as shown in FIG. 8(f), a second silicon dioxide film forming step is performed as a part of a second etching mask forming step. In the second silicon dioxide film forming step, a second silicon dioxide film (second oxide film) 19 is formed so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. As a result, a plurality of stripe-shaped second grooves with inclined sides are formed in the second silicon dioxide film 19 at the positions of the plurality of stripe-shaped first grooves of the first etching mask. Thereafter, as shown in FIG. 9(a), a second resist film applying step is performed as a part of a second etching mask forming step. In the second resist film applying step, a second resist 20 is applied so as to entirely cover the first surface side of the semiconductor device 1 in the manufacturing process. Thereafter, as shown in FIG. 9(b), a second resist pattern forming step is performed as a part of a second etching mask forming step.

[0044] Here, the formation of the second resist pattern will be described with reference to FIG. 10 and FIG. 11. The second resist pattern is formed by photolithography using an optical stepper. FIG. 10 shows the optical image intensity distribution of a line and space pattern. At the correct focus position, the optical image intensity is high in the part irradiated with light, and the optical image intensity is almost zero at the bottom of the pattern having the pattern width W. However, when exposed in a defocused state, the optical image intensity is lower than the optical image intensity obtained at the correct focus position. FIG. 11 shows the sensitivity curve of a positive resist. This pattern shows the remaining film of the resist when an area assumed to be optically infinite is exposed and developed for a certain development time. As the exposure amount increases, the film thickness of the resist film decreases, and the resist film thickness becomes 0 at the exposure amount F. In other words, if the exposure amount is less than F, the resist film remains. This state is called underexposure. Also, even if the development time is shortened, the resist film remains in the same way. This state is called underdevelopment. If the exposure intensity of E shown in FIG. 10 is adjusted to the position of F in FIG. 11, it can be seen that in the case of defocusing, the exposure amount is insufficient and the resist film remains even in the position where light is irradiated. Also, as shown in FIG. 11, there are resists G and H which have different sensitivity characteristics. By appropriately selecting these resists, the shape of the resist remaining film can be changed. As explained above, by combining one or more of underexposure, underdevelopment, defocus, and the selection of resist type, multiple grooves with sloped sides and multi-step curvature at the bottom are formed in the second resist pattern so that the upper part of the trench is wider.

[0045] Thereafter, as shown in FIG. 9(c), a second anisotropic etching process is performed as a part of a second etching mask forming process. In the second anisotropic etching process, the second silicon dioxide film 19 is subjected to reactive ion etching using the second resist 20 as a mask. At this time, the selectivity ratio between the second silicon dioxide film 19 and the second resist 20 is about 1:1. As a result, a plurality of stripe-shaped second grooves having inclined sides and multi-step curvatures at the bottom are formed in the second silicon dioxide film 19. Thereafter, as shown in FIG. 9(d), a second resist removal process is performed as a part of a second etching mask forming process. In the second resist removal process, the second resist 20 is removed. As a result, the second silicon dioxide film 19 is exposed as a second etching mask.

[0046] Thereafter, as shown in FIG. 9(e), a third anisotropic etching process is performed as a part of the trench structure forming process. In the third anisotropic etching process, the first silicon dioxide film 17 and the second silicon dioxide film 19 are used as masks to perform reactive ion etching on the drift layer 3, the body layer 4, and the source layer 5. At this time, the selection ratio of silicon carbide constituting the drift layer 3, the body layer 4, and the source layer 5 and silicon dioxide constituting the first silicon dioxide film 17 and the second silicon dioxide film 19 is about 1:1. As a result, a plurality of stripe-shaped trench structures T having inclined sides and multi-step curvatures at the bottom are formed. Thereafter, as shown in FIG. 9(f), a silicon dioxide film removing process is performed as a part of the trench structure forming process. In the silicon dioxide film removing process, the first silicon dioxide film 17 and the second silicon dioxide film 19 are simultaneously removed. As a result, a plurality of stripe-shaped trench structures T are exposed.

[0047] Next, the electric field distribution on the surface of the trench portion will be described with reference to FIGS. Fig. 12 is a cross-sectional view of the trench structures of the semiconductor device according to the first embodiment, the first comparative example, and the second comparative example. Fig. 13 is a diagram showing an electric field distribution near the trench structure of the semiconductor device according to the first embodiment. Fig. 14 is a diagram showing an electric field distribution near the trench structure of the first comparative example. Fig. 15 is a diagram showing an electric field distribution near the trench structure of the second comparative example. Fig. 16 is a diagram showing a comparison of the electric field strength near the trench structure of the semiconductor device according to the first embodiment, and the first and second comparative examples.

[0048] Fig. 12(a) shows the trench structure T of the semiconductor device 1 in the first embodiment. Fig. 12(b) shows the trench structure of a first comparative example. Fig. 12(c) shows the trench structure of a second comparative example.

[0049] As shown in (a) of Fig. 12, the trench structure T of the semiconductor device 1 in the first embodiment includes a first curved portion 13, a second curved portion 14, and a third curved portion 15 similar to those in Fig. 4. For example, the radius of curvature of the first curved portion 13 is 2.55 µm. For example, the radius of curvature of the second curved portion 14 is 1.41 µm. The radius of curvature of the central portion of the third curved portion 15 is 2.02 µm.

[0050] As shown in Fig. 12(b), in the first comparative example, the trench structure includes a curved portion 21 similar to the second curved portion 14 in Fig. 12(a). The trench structure does not include curved portions similar to the first curved portion 13 and the third curved portion 15 in Fig. 12(a). For example, the radius of curvature of the curved portion 21 is 1.41 μm.

[0051] As shown in (c) of Fig. 12, in the second comparative example, the trench structure has a curved portion 22 at a position similar to the first curved portion 13 in (a) of Fig. 12. The trench structure does not have curved portions similar to the second curved portion 14 and the third curved portion 15 in (a) of Fig. 12. The radius of curvature of the curved portion 22 is larger than the radius of curvature of the first curved portion 13. For example, the radius of curvature of the curved portion 22 is 2.83 µm.

[0052] 13, in the trench structure T of the semiconductor device 1 according to the first embodiment, the electric field strength is almost uniform in the entire region including the bottom and side portions. For example, when a voltage of 1650 V is applied, the electric field strength is about 2.6 MV / cm to 2.7 MV / cm.

[0053] 14, in the trench structure of the first comparative example, the electric field is maximum near the curved portion 21. For example, when a voltage of 1650 V is applied, the electric field strength is about 2.8 MV / cm to 2.9 MV / cm.

[0054] 15, in the trench structure of the second comparative example, the electric field is maximum near the curved portion 22. For example, when a voltage of 1650 V is applied, the electric field strength is about 2.9 MV / cm to 3.0 MV / cm.

[0055] In FIG. 16, the horizontal axis is the position (μm) at the center of the short side of the surface of the trench structure. The vertical axis is the electric field strength (MV / cm). A shows the electric field strength distribution of the trench structure T of the semiconductor device 1 in embodiment 1. B shows the electric field strength distribution of the trench structure of the first comparative example. C shows the electric field strength distribution of the trench structure of the second comparative example. D is the dielectric breakdown field strength of 4H silicon carbide (2.8MV / cm). As shown in FIG. 16, only the electric field strength distribution A of the trench structure T of the semiconductor device 1 in embodiment 1 is lower than the dielectric breakdown field strength D of 4H silicon carbide over the entire region.

[0056] According to the first embodiment described above, the bottom of the trench structure T has multiple steps of curvature in a cross-sectional view in the short side direction. The trench structure T has at least a first curved portion 13 and a second curved portion 14. This makes it possible to suppress electric field concentration in the trench structure T.

[0057] Moreover, the radius of curvature of the first curved portion 13 is larger than the radius of curvature of the second curved portion 14. Therefore, the electric field concentration in the trench structure T can be suppressed more reliably.

[0058] Moreover, the value of the radius of curvature of the first curved portion 13 is 1.5 to 3 times the value of the radius of curvature of the second curved portion 14. Therefore, the electric field concentration in the trench structure T can be suppressed more reliably.

[0059] In addition, in a cross-sectional view of the trench structure T in the short side direction, the radius of curvature of the third curved portion 15 gradually decreases from the first curved portion 13 to the second curved portion 14. This makes it possible to more reliably suppress electric field concentration in the trench structure T.

[0060] Moreover, the side portions are inclined in a cross-sectional view in the short-side direction of the trench structure T. Therefore, it is possible to easily form the trench structure T in which electric field concentration is suppressed.

[0061] Furthermore, in a cross-sectional view in the longitudinal direction of the trench structure T, a longitudinal curved portion 16 is formed. Therefore, even at the end of the bottom of the trench structure T in the longitudinal direction, electric field concentration can be suppressed.

[0062] In addition, the longitudinal direction of the trench structure T is parallel to the (11-20) plane, (1-210) plane, or (-2110) plane of the hexagonal crystal of 4H silicon carbide, thereby suppressing electric field concentration and increasing channel mobility.

[0063] In addition, the longitudinal direction of the trench structure T is parallel to the (1-100), (10-10) or (0-110) plane of the hexagonal crystal of 4H silicon carbide, which suppresses electric field concentration and increases channel mobility.

[0064] In addition, when the substrate is a notch type, a line perpendicular to a line from the notch toward the center of the substrate is regarded as an orientation flat. In this case, the longitudinal direction of the trench structure T may be set to be at any one of angles between -5 degrees and 5 degrees, between 25 degrees and 35 degrees, between 55 degrees and 65 degrees, between 85 degrees and 95 degrees, between 115 degrees and 125 degrees, and between 145 degrees and 155 degrees with respect to the deemed orientation flat. In this case as well, the channel mobility can be increased.

[0065] Furthermore, in a cross-sectional view in the short side direction of the trench structure T, a third curved portion 15 may be locally provided between the first curved portion 13 and the second curved portion 14. In this case, the radius of curvature of the third curved portion 15 may be smaller than the radius of curvature of the first curved portion 13 and larger than the radius of curvature of the second curved portion 14. In this case as well, electric field concentration in the trench structure T can be suppressed.

[0066] Also, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case as well, electric field concentration in the trench structure T can be suppressed.

[0067] The semiconductor device 1 may be an IGBT. In this case, the drain layer 2 is + The source layer 5 may be an emitter layer. The source electrode layer 10 may be an emitter electrode layer. The drain electrode layer 12 may be a collector electrode layer.

[0068] Having described several aspects of at least one embodiment, it should be understood that various alterations, modifications, and improvements will readily occur to those skilled in the art and are intended to be part of this disclosure, and are intended to be within the scope of this disclosure.

[0069] It is to be understood that the embodiments of the method and apparatus described herein are not limited in their application to the details of construction and the arrangement of components set forth in the above description or illustrated in the accompanying drawings, and the method and apparatus can be implemented in other embodiments and practiced or carried out in various ways.

[0070] The specific implementations are provided herein for illustrative purposes only and are not intended to be limiting.

[0071] The phraseology and terminology used in this disclosure are for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "including" and variations thereof herein means the inclusion of the items listed thereafter and equivalents thereof as well as additional items.

[0072] References to "or" may be construed as meaning that any term described using "or" refers to one, more than one, and all of those described terms.

[0073] All references to front, back, left, right, top, bottom, up, down, horizontal, vertical, front and back are intended for convenience of description. Such references are not intended to limit the components of this disclosure to any one positional or spatial orientation. Accordingly, the foregoing description and drawings are by way of example only. [Explanation of symbols]

[0074] REFERENCE SIGNS LIST 1 semiconductor device, 2 drain layer, 3 drift layer, 4 body layer, 5 source layer, 6 body contact layer, 7 gate insulating layer, 8 gate electrode layer, 9 interlayer insulating layer, 10 source electrode layer, 11 wiring electrode layer, 12 drain electrode layer, 13 first curved portion, 14 second curved portion, 15 third curved portion, 16 longitudinal curved portion, 17 first silicon dioxide film (first oxide film), 18 first resist, 19 second silicon dioxide film (second oxide film), 20 second resist, 21 curved portion, 22 curved portion

Claims

1. a first layer formed of silicon carbide of a first conductivity type; a second layer formed of silicon carbide of a second conductivity type on the first layer; a third layer formed of silicon carbide of the first conductivity type on the second layer; a plurality of trench structures formed in stripes from the third layer side to the first layer; Equipped with The trench structure has, in a cross-sectional view in a short direction, A first curved portion formed on the bottom portion; a second curved portion formed between the bottom and side portions; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first curved portion has a radius of curvature larger than a radius of curvature of the second curved portion.

3. The semiconductor device according to claim 2 , wherein the first curved portion has a radius of curvature that is 1.5 to 3 times the radius of curvature of the second curved portion.

4. The trench structure has, in a cross-sectional view in a short direction, a third curved portion formed between the first curved portion and the second curved portion, the radius of curvature of which gradually decreases from the radius of curvature of the first curved portion to the radius of curvature of the second curved portion as the radius of curvature of the third curved portion increases from the radius of curvature of the first curved portion to the radius of curvature of the second curved portion; The semiconductor device according to claim 1 or 2, comprising:

5. 3. The semiconductor device according to claim 1, wherein the side portions of the trench structure are inclined so that an upper portion of the trench is wider.

6. The trench structure, in a longitudinal cross-sectional view, a longitudinal curved portion formed at the end portion and having a radius of curvature larger than the radius of curvature of the second curved portion; The semiconductor device according to claim 1 or 2, comprising:

7. the first layer, the second layer, and the third layer are formed primarily of 4H silicon carbide, 3. The semiconductor device according to claim 1, wherein a longitudinal direction of the trench structure is parallel to a (11-20) plane, a (1-210) plane or a (-2110) plane of a hexagonal crystal of 4H silicon carbide, the hexagonal plane being a plane perpendicular to a main surface of a substrate formed by the first layer, the second layer and the third layer.

8. the first layer, the second layer, and the third layer are formed primarily of 4H silicon carbide, 3. The semiconductor device according to claim 1, wherein a longitudinal direction of the trench structure is parallel to a (1-100) plane, a (10-10) plane or a (0-110) plane of a hexagonal crystal of 4H silicon carbide, the hexagonal plane being a plane perpendicular to a main surface of a substrate formed by the first layer, the second layer and the third layer.

9. a first etching mask forming step of forming a first oxide film on a substrate formed of a first layer made of silicon carbide of a first conductivity type, a second layer made of silicon carbide of a second conductivity type on the first layer, and a third layer made of silicon carbide of the first conductivity type on the second layer, and forming a first etching mask by forming a plurality of stripe-shaped first grooves having inclined sides in the first oxide film; a second etching mask forming step of forming a second oxide film on the first etching mask after the first etching mask forming step, and forming a second etching mask by forming a plurality of stripe-shaped second grooves having inclined sides and a bottom having multiple steps of curvature at the positions of the plurality of stripe-shaped first grooves; a trench structure forming step of forming a plurality of stripe-shaped trench structures having inclined sides and a multi-step curvature at the bottom from the third layer side to the first layer by performing anisotropic etching on the substrate after the second etching mask forming step; A method for manufacturing a semiconductor device comprising the steps of:

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