Semiconductor device

Abstract

To provide a semiconductor device which allows characteristic improvement.SOLUTION: A trench structure part has: a field plate electrode; a first insulation film provided between the field plate electrode and a semiconductor layer; a second insulation film, provided above the field plate electrode, which extends to a side closer to a first surface of the semiconductor layer than the first insulation film; and a gate electrode having a first portion provided above the second insulation film, and a second portion, provided above the first insulation film, which is thicker than the first portion. A gate contact part extends from a gate wiring layer toward the second portion so as to make contact with the second portion, but it is not located between the first portion and the gate wiring layer. In a second direction, the first portion is located adjacent to a lower end part where the gate contact part makes contact with the second portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] In a semiconductor device having a trench gate structure, a structure in which a field plate electrode is provided under a gate electrode is known, and in such a structure, a structure in which an insulating film having an upward convex shape is provided between the gate electrode and the field plate electrode is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-180645 A [Patent Document 2] JP 2019-9258 A Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device that can improve characteristics. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a semiconductor layer having a first surface and a second surface located on an opposite side of the first surface in a first direction, a trench structure extending in the first direction from the first surface, a gate wiring layer provided on the first surface and on the trench structure, and a gate contact extending from the gate wiring layer toward the trench structure, the trench structure including a field plate electrode, a first insulating film provided between the field plate electrode and the semiconductor layer, and a gate contact provided on the field plate electrode and closer to the first insulating film than the first insulating film. a gate electrode having a second insulating film extending toward a surface of the gate electrode, a first portion provided on the second insulating film, and a second portion provided on the first insulating film and thicker than the first portion; and a third insulating film provided between the second portion of the gate electrode and the semiconductor layer, wherein the gate contact portion extends from the gate wiring layer toward the second portion and contacts the second portion, is not located between the first portion and the gate wiring layer, and in a second direction perpendicular to the first direction, the first portion is located adjacent to a lower end where the gate contact portion contacts the second portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic plan view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 2 is a schematic cross-sectional view taken along line BB in FIG. [Figure 4] 2 is a schematic cross-sectional view taken along line CC in FIG. 1. [Diagram 5] FIG. 2 is a schematic cross-sectional view taken along line DD in FIG. [Figure 6] 1A to 1C are schematic plan views showing examples of the arrangement of gate contact parts. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals. In the following embodiments, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0008] The semiconductor device of the embodiment will be described with reference to Figures 1 to 5. The semiconductor device of the embodiment includes a semiconductor layer 10, a trench structure t, a gate wiring layer 50, and a gate contact portion 55.

[0009] 2 to 5, the semiconductor layer 10 has a first surface 10a and a second surface 10b. A direction connecting the first surface 10a and the second surface 10b at the shortest distance is defined as a first direction Z. The second surface 10b is located on the opposite side of the first surface 10a in the first direction Z. Two directions perpendicular to the first direction Z are defined as a second direction Y and a third direction X. The second direction Y and the third direction X are perpendicular to each other.

[0010] In this specification, the "thickness" refers to the maximum thickness in a particular direction (first direction Z, second direction Y, or third direction X).

[0011] The semiconductor layer 10 may be made of, for example, silicon. Alternatively, the semiconductor layer 10 may be made of, for example, silicon carbide, gallium nitride, or the like.

[0012] 2, in a cross-sectional view, the trench structure t extends from the first surface 10a along the first direction Z and is located in the semiconductor layer 10. Also, as shown in Fig. 1, the trench structure t extends in the third direction X in a plan view. For example, a plurality of trench structures t extend in the third direction X.

[0013] The trench structure portion t has a field plate electrode 20, a first insulating film 41, a second insulating film 42, a third insulating film 43, and a gate electrode 30. These are provided in a trench formed in the semiconductor layer 10. The field plate electrode 20, the first insulating film 41, the second insulating film 42, and the third insulating film 43 extend in the third direction X in the trench.

[0014] The field plate electrode 20 relieves electric field concentration in the vicinity of the gate electrode 30 in the semiconductor layer 10. The field plate electrode 20 may be made of, for example, polycrystalline silicon.

[0015] The first insulating film 41 is provided between the field plate electrode 20 and the semiconductor layer 10. The first insulating film 41 is provided between the side surface of the field plate electrode 20 and the semiconductor layer 10, and between the lower end of the field plate electrode 20 and the semiconductor layer 10. As the first insulating film 41, for example, a silicon oxide film can be used.

[0016] The second insulating film 42 is provided on the field plate electrode 20, and extends closer to the first surface 10a of the semiconductor layer 10 than the first insulating film 41. The upper end of the second insulating film 42 is located closer to the first surface 10a than the upper end of the first insulating film 41. As the second insulating film 42, for example, a BPSG (boro-phospho silicate glass) film can be used.

[0017] The gate electrode 30 has a first portion 31 provided on the second insulating film 42, and a second portion 32 provided on the first insulating film 41. The second insulating film 42 is located between the field plate electrode 20 and the first portion 31 in the first direction Z. The first portion 31 and the second portion 32 are integrally provided using the same material. The material of the gate electrode 30 can be, for example, polycrystalline silicon.

[0018] The thickness of the second portion 32 in the first direction Z is greater than the thickness of the first portion 31 in the first direction Z. Conversely, the thickness of the first portion 31 in the first direction Z is smaller than the thickness of the second portion 32 in the first direction Z. Since the second insulating film 42 extends to the gate electrode 30, the first portion 31 located on the second insulating film 42 of the gate electrode 30 is thinner than the second portion 32 to which the second insulating film 42 does not extend.

[0019] The second insulating film 42 extends into the gate electrode 30 so as to recess a part of the gate electrode 30 toward the upper surface side of the gate electrode 30 from the lower surface of the second portion 32. This makes it possible to increase the distance in the first direction Z between the field plate electrode 20 and the gate electrode 30, compared to a case in which the second insulating film 42 does not extend into the gate electrode 30. This makes it possible to increase the dielectric breakdown resistance between the gate electrode 30 and the field plate electrode 20. In addition, it is possible to reduce the capacitance between the gate electrode 30 and the field plate electrode 20, and increase the switching speed. It is preferable that the second insulating film 42 extends from the lower surface of the second portion 32 into the gate electrode 30 by 25% or more of the thickness of the second portion 32 in the first direction Z.

[0020] The third insulating film 43 is provided between the side surface of the second portion 32 of the gate electrode 30 and the semiconductor layer 10. As the third insulating film 43, for example, a silicon oxide film can be used.

[0021] The gate wiring layer 50 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t via an interlayer insulating layer 80. The gate wiring layer 50 may have, for example, a first metal film 51 provided on the interlayer insulating layer 80, a second metal film 52 provided on the first metal film 51, and a third metal film 53 provided on the second metal film 52. For example, a titanium film may be used as the first metal film 51, a tungsten film may be used as the second metal film 52, and an aluminum film may be used as the third metal film 53. The thicknesses of the second metal film 52 and the third metal film 53 in the first direction Z are each thicker than the thickness of the first metal film 51 in the first direction Z. The first metal film 51 functions as a barrier film that prevents diffusion of metals in the second metal film 52 and the third metal film 53.

[0022] As shown in FIG. 1, the gate wiring layer 50 may have a gate pad 50A, a first extension portion 50B, and a second extension portion 50C. A first connection member such as a wire is bonded to the gate pad 50A. The gate wiring layer 50 is electrically connected to a gate drive circuit via the first connection member. The first extension portion 50B extends from the gate pad 50A in a third direction X. The second extension portion 50C extends from the gate pad 50A or the first extension portion 50B in a second direction Y. A plurality of second extension portions 50C extend in the second direction Y.

[0023] 2, the interlayer insulating layer 80 may have, for example, a first layer 81 provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t, and a second layer 82 provided on the first layer 81. For example, silicon oxide may be used as the material of the first layer 81, and BPSG may be used as the material of the second layer 82.

[0024] The gate contact portion 55 extends from the gate wiring layer 50 toward the trench structure portion t. For example, the gate contact portion 55 extends from the second metal film 52 toward the trench structure portion t. For example, the gate contact portion 55 can be composed of a portion made of the same material as the second metal film 52 and a first metal film 51 covering the surface of that portion.

[0025] The gate contact portion 55 extends from the gate wiring layer 50 toward the second portion 32 of the gate electrode 30 and is in contact with the second portion 32. The gate contact portion 55 in contact with the second portion 32 may be referred to as a first gate contact portion 55A, to be distinguished from a gate contact portion 55 (second gate contact portion 55B) in contact with a third portion 33 described later. The gate electrode 30 is electrically connected to the gate wiring layer 50 via the gate contact portion 55. In the example shown in FIG. 1, the gate contact portion 55 is located at a portion where the second extension portion 50C of the gate wiring layer 50 and the gate electrode 30 intersect.

[0026] The gate contact portion 55 is formed by forming a contact trench that penetrates the interlayer insulating layer 80 and reaches the gate electrode 30, and then filling the contact trench with a metal material. The contact trench can be formed by, for example, a reactive ion etching (RIE) method. According to this embodiment, the gate contact portion 55 is not located between the first portion 31 of the gate electrode 30 and the gate wiring layer 50. Therefore, it is possible to prevent the contact trench from penetrating the first portion 31, which is a thin portion of the gate electrode 30, and reaching the field plate electrode 20 below the first portion 31. This makes it possible to prevent a short circuit between the gate electrode 30 and the field plate electrode 20 via the gate contact portion 55, and to increase the reliability of the semiconductor device. The thickness of the first portion 31 in the first direction Z is, for example, 500 nm or less.

[0027] In the second direction Y, the first portion 31 is located next to a lower end 55a where the first gate contact portion 55A contacts the second portion 32. This makes it possible to reduce the thickness of a portion of the gate electrode 30 to increase the distance between the gate electrode 30 and the field plate electrode 20, while suppressing a reduction in the cross-sectional area of ​​the gate electrode 30 on the upper surface side of the gate electrode 30 to which the gate contact portion 55 is connected, thereby suppressing an increase in the gate resistance.

[0028] The gate electrode 30 further has a third portion 33 located adjacent to the first portion 31 in the second direction Y and provided on the first insulating film 41. The thickness of the third portion 33 in the first direction Z is greater than the thickness of the first portion 31 in the first direction Z. In the second direction Y, the first portion 31 is located between the second portion 32 and the third portion 33. The first portion 31, the second portion 32, and the third portion 33 are integrally provided using the same material.

[0029] At least two gate contact portions 55A, 55B are disposed for one trench structure portion t, spaced apart from each other in the second direction Y. As described above, the first gate contact portion 55A of the two gate contact portions 55A, 55B extends from the gate wiring layer 50 toward the second portion 32 of the gate electrode 30 and contacts the second portion 32. The second gate contact portion 55B of the two gate contact portions 55A, 55B extends from the gate wiring layer 50 toward the third portion 33 and contacts the third portion 33. The two gate contact portions 55A, 55B contact the gate electrode 30 in one trench structure portion t, thereby increasing the contact area between the gate wiring layer 50 and the gate electrode 30, and reducing the gate resistance.

[0030] The first portion 31 is located in the second direction Y between a lower end 55a where the first gate contact portion 55A contacts the second portion 32 and a lower end 55b where the second gate contact portion 55B contacts the third portion 33. This makes it possible to suppress a reduction in the cross-sectional area of ​​the gate electrode 30 on the upper surface side of the gate electrode 30 to which the gate contact portion 55 is connected, thereby suppressing an increase in gate resistance.

[0031] 3 and 4, the semiconductor device of the embodiment further includes a first electrode layer 60 provided on the first surface 10a and the trench structure portion t of the semiconductor layer 10. The first electrode layer 60 is provided on the first surface 10a and the trench structure portion t with an interlayer insulating layer 80 interposed therebetween.

[0032] 4 and 5, the field plate electrode 20 is electrically connected to the first electrode layer 60. Therefore, the same potential is applied to the first electrode layer 60 and the field plate electrode 20.

[0033] For example, the first electrode layer 60 and the gate wiring layer 50 can be formed simultaneously using the same material. In this case, the first electrode layer 60 can have a first metal film 51, a second metal film 52, and a third metal film 53, similar to the gate wiring layer 50 described above.

[0034] As shown in FIG. 1, the first electrode layer 60 is separated from the gate wiring layer 50 on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t. The first electrode layer 60 can have a first pad 60A, a third extension portion 60B, and a fourth extension portion 60C. A second connection member such as a wire is bonded to the first pad 60A. The first electrode layer 60 is electrically connected to an external circuit via the second connection member. The third extension portion 60B extends from the first pad 60A in a third direction X. A plurality of fourth extension portions 60C extend from the third extension portion 60B in a second direction Y. In the third direction X, the second extension portion 50C of the gate wiring layer 50 is located between the fourth extension portions 60C of the first electrode layer 60 and between the fourth extension portion 60C and the first pad 60A.

[0035] 1, the semiconductor device of the embodiment includes a first region R1, a second region R2, and a third region R3. The first region R1, the second region R2, and the third region R3 are aligned in a third direction X.

[0036] The first region R1 includes an intersection portion between the second extension portion 50C of the gate wiring layer 50 and the trench structure portion t. In the first region R1, the gate electrode 30 has a first portion 31, a second portion 32, and a third portion 33, as shown in FIG. 2. In the first region R1, a second insulating film 42 is provided between the field plate electrode 20 and the first portion 31 of the gate electrode 30. In the first region R1, a gate contact portion 55 is in contact with the second portion 32 and the third portion 33 of the gate electrode 30.

[0037] As shown in FIG. 2 to FIG. 4, the semiconductor layer 10 has an n-type first semiconductor portion 11 and a p-type second semiconductor portion 12 provided on the first semiconductor portion 11. The semiconductor layer 10 also has an n-type fourth semiconductor portion 14. The first semiconductor portion 11 is provided on the fourth semiconductor portion 14. The n-type impurity concentration of the fourth semiconductor portion 14 is higher than the n-type impurity concentration of the first semiconductor portion 11. The surface of the fourth semiconductor portion 14 opposite to the first semiconductor portion 11 becomes the second surface 10b of the semiconductor layer 10. In the first region R1, the upper surface of the second semiconductor portion 12 becomes the first surface 10a of the semiconductor layer 10. The semiconductor device of the embodiment has a second electrode layer 70 provided on the second surface 10b and electrically connected to the fourth semiconductor portion 14. The first semiconductor portion 11, the fourth semiconductor portion 14, and the second electrode layer 70 are provided in the first region R1, the second region R2, and the third region R3.

[0038] 3, in the second region R2, the semiconductor layer 10 further has an n-type third semiconductor portion 13 provided on the second semiconductor portion 12. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11. In the second region R2, the upper surface of the third semiconductor portion 13 becomes the first surface 10a of the semiconductor layer 10.

[0039] In the second region R2, a first electrode layer 60 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t via an interlayer insulating layer 80. The third semiconductor portion 13 is electrically connected to the first electrode layer 60.

[0040] In the second region R2, the second contact portion 62 extends from the first electrode layer 60 toward the second semiconductor portion 12. The second contact portion 62 penetrates the interlayer insulating layer 80 and the third semiconductor portion 13 and contacts the p-type fifth semiconductor portion 15 provided in the second semiconductor portion 12. The p-type impurity concentration of the fifth semiconductor portion 15 is higher than the p-type impurity concentration of the second semiconductor portion 12. In the second region R2, the second semiconductor portion 12 and the third semiconductor portion 13 are electrically connected to the first electrode layer 60 via the second contact portion 62. In the example shown in FIG. 3, the side surface of the second contact portion 62 contacts the third semiconductor portion 13. In the second region R2, a plurality of second contact portions 62 are arranged in the second direction Y. In the second direction Y, the second contact portion 62 is located between adjacent trench structure portions t.

[0041] In the second region R2, the gate electrodes 30 in one trench structure portion t are separated in the second direction Y. In the second region R2, a part 80A of the interlayer insulating layer 80 extends toward the field plate electrode 20, separating the gate electrodes 30 in the second direction Y. The side surfaces of each of the gate electrodes 30 separated in the second direction Y face the second semiconductor portion 12 via the third insulating film 43.

[0042] The semiconductor device according to the embodiment has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. For example, the first electrode layer 60 functions as a source electrode, the second electrode layer 70 functions as a drain electrode, the first semiconductor portion 11 functions as a drift layer, the second semiconductor portion 12 functions as a base layer, the third semiconductor portion 13 functions as a source layer, and the fourth semiconductor portion 14 functions as a drain layer.

[0043] When a first potential (e.g., ground potential) is applied to the first electrode layer 60, a second potential (e.g., positive potential) higher than the first potential is applied to the second electrode layer 70, and a gate voltage equal to or higher than a threshold value is applied to the gate electrode 30, an n-type inversion layer (channel) is formed in a portion of the second semiconductor portion 12 in the second region R2 that faces the gate electrode 30. Then, in the second region R2, a current flows between the second electrode layer 70 (drain electrode) and the first electrode layer 60 (source electrode) via the fourth semiconductor portion 14 (drain layer), the channel, and the third semiconductor portion 13 (source layer).

[0044] The semiconductor device according to the embodiment may have an IGBT (Insulated Gate Bipolar Transistor) structure.

[0045] In the first region R1, as shown in FIG. 2, a fourth insulating film 44 is provided between the second portion 32 of the gate electrode 30 and the second semiconductor portion 12, and between the third portion 33 of the gate electrode 30 and the second semiconductor portion 12, in addition to the third insulating film 43. As the fourth insulating film 44, for example, a silicon oxide film can be used. The thickness of the insulating film (third insulating film 43 and fourth insulating film 44) between the side surface of the gate electrode 30 and the semiconductor layer 10 in the first region R1 is thicker than the thickness of the insulating film (third insulating film 43) between the side surface of the gate electrode 30 and the semiconductor layer 10 in the second region R2 shown in FIG. 3. This makes it possible to increase the dielectric breakdown resistance between the gate electrode 30 and the first semiconductor portion 11 to which the drain potential is applied in the first region R1. In particular, an electric field is applied directly from the first semiconductor portion 11 to a portion of the gate electrode 30 where the second semiconductor portion 12 is not located adjacent to the second direction Y, so that increasing the thickness of the insulating film between the side surface of the gate electrode 30 and the semiconductor layer 10 is effective for increasing the dielectric breakdown resistance.

[0046] As shown in Fig. 1, the third region R3 includes both ends of the trench structure portion t in the third direction X. As shown in Fig. 4, in the third region R3, a first electrode layer 60 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t, with an interlayer insulating layer 80 interposed therebetween. The third region R3 does not include the second semiconductor portion 12 and the third semiconductor portion 13. In the third region R3, the upper surface of the first semiconductor portion 11 becomes the first surface 10a of the semiconductor layer 10.

[0047] In the third region R3, no gate electrode is provided on the field plate electrode 20, and a first contact portion 61 is provided on the field plate electrode 20. The first contact portion 61 extends from the first electrode layer 60 through the interlayer insulating layer 80 toward the field plate electrode 20 and contacts the field plate electrode 20. The field plate electrode 20 is electrically connected to the first electrode layer 60 via the first contact portion 61.

[0048] 5, the field plate electrode 20 has an extension portion 20a extending toward the first surface 10a at the end portion of the trench structure portion t in the third direction X. A first contact portion 61 of the first electrode layer 60 is connected to the extension portion 20a.

[0049] 6(a) to 6(c) are schematic plan views showing examples of the arrangement of a plurality of gate contact portions 55 in the first region R1.

[0050] In the example shown in Figures 6(a) and 6(b), a plurality of first gate contact portions 55A connected to the second portion 32 of the gate electrode 30 are arranged spaced apart from each other in the third direction X, and a plurality of second gate contact portions 55B connected to the third portion 33 of the gate electrode 30 are arranged spaced apart from each other in the third direction X.

[0051] In the example shown in FIG. 6(a), the first gate contact portion 55A and the second gate contact portion 55B are aligned with each other in the second direction Y.

[0052] In the example shown in FIG. 6(b), the first gate contact portions 55A and the second gate contact portions 55B are arranged in a staggered manner and are not aligned with each other in the second direction Y.

[0053] In the example shown in FIG. 6(c), the first gate contact portion 55A extends continuously in the third direction X, and the second gate contact portion 55B extends continuously in the third direction X.

[0054] 2, the trench structure t in the first region R1 may include a fifth insulating film 45 provided between the field plate electrode 20 and the second insulating film 42. The fifth insulating film 45 is, for example, a silicon oxide film formed by thermal oxidation. Also, as shown in FIG. 3, in the second region R2, the fifth insulating film 45 may be provided between the field plate electrode 20 and a portion 80A of the interlayer insulating layer 80.

[0055] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0056] 10...semiconductor layer, 10a...first surface, 10b...second surface, 11...first semiconductor portion, 12...second semiconductor portion, 13...third semiconductor portion, 14...fourth semiconductor portion, 15...fifth semiconductor portion, 20...field plate electrode, 30...gate electrode, 31...first portion, 32...second portion, 33...third portion, 41...first insulating film, 42...second insulating film, 43...third insulating film, 44...fourth insulating film, 45...fifth insulating film, 50...gate wiring layer, 55...gate contact portion, 55A...first gate contact portion, 55B...second gate contact portion, 60...first electrode layer, 61...first contact portion, 62...second contact portion, 70...second electrode layer, 80...interlayer insulating layer, t...trench structure portion, R1...first region, R2...second region, R3...third region

Claims

1. a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in a first direction; a trench structure extending in the first direction from the first surface; a gate wiring layer provided on the first surface and on the trench structure; a gate contact portion extending from the gate wiring layer toward the trench structure; Equipped with The trench structure is A field plate electrode; a first insulating film provided between the field plate electrode and the semiconductor layer; a second insulating film provided on the field plate electrode and extending closer to the first surface than the first insulating film; a gate electrode having a first portion provided on the second insulating film and a second portion provided on the first insulating film and thicker than the first portion; a third insulating film provided between the second portion of the gate electrode and the semiconductor layer; having the gate contact portion extends from the gate wiring layer toward the second portion and contacts the second portion, and is not located between the first portion and the gate wiring layer; A semiconductor device, wherein in a second direction perpendicular to the first direction, the first portion is located adjacent to a lower end where the gate contact portion contacts the second portion.

2. the gate electrode further has a third portion located adjacent to the first portion in the second direction, the gate contact portion extends from the gate wiring layer toward the third portion and contacts the third portion; 2. The semiconductor device according to claim 1, wherein the first portion is located in the second direction between a lower end where the gate contact portion contacts the second portion and a lower end where the gate contact portion contacts the third portion.

3. 3. The semiconductor device according to claim 1, wherein said second insulating film extends into said gate electrode by 25% or more of a thickness of said second portion in said first direction.

4. a first electrode layer provided on the first surface and on the trench structure portion and separated from the gate wiring layer; The semiconductor device according to claim 1 , wherein the field plate electrode is electrically connected to the first electrode layer.

5. The semiconductor layer is A first semiconductor portion of a first conductivity type; a second semiconductor portion of a second conductivity type provided on the first semiconductor portion and facing the gate electrode via the third insulating film; a third semiconductor portion of a first conductivity type provided on the second semiconductor portion and electrically connected to the first electrode layer; The semiconductor device according to claim 4 , further comprising:

6. a first region in which the first portion and the second portion of the gate electrode are provided; a second region in which the third semiconductor portion is provided; Equipped with The semiconductor device according to claim 5 , wherein in said second region, said gate electrodes are separated in said second direction.

7. Further comprising a third region; 7. The semiconductor device according to claim 6, wherein in the third region, the gate electrode is not located on the field plate electrode, and a first contact portion is provided that extends from the first electrode layer toward the field plate electrode and contacts the field plate electrode.

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