Semiconductor device

Abstract

To provide a semiconductor device which is reduced in inductance.SOLUTION: A semiconductor device includes: an insulating substrate; a frame body; a first semiconductor chip which includes a first upper electrode, a first lower electrode, and a first semiconductor layer, and is provided on the insulating substrate; a first electrode terminal which includes a first flat plate part, and is electrically connected to one of the first upper electrode and the first lower electrode; a second electrode terminal which includes a second flat plate part opposite to the first flat plate part, and is electrically connected to the other of the first upper electrode and the first lower electrode; a first resin member that is fixed to at least one of the first electrode terminal and the second electrode terminal, and includes a fit part fit into the frame body, in which the fit part contains a first resin having first volume resistivity and first Young's modulus; and a second resin member which is provided between the first flat plate part and the second flat plate part, and has a second resin that has second volume resistivity larger than the first volume resistivity and second Young's modulus larger than the first Young's modulus.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In a power semiconductor module, for example, a power semiconductor chip is mounted on an insulating substrate. The power semiconductor chip is, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

[0003] If the internal inductance of a power semiconductor module is large, for example, a surge voltage during switching will be large, which may cause problems such as the destruction of semiconductor chips. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6921794 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device with reduced inductance. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment includes an insulating substrate, a frame surrounding the insulating substrate, a first upper electrode, a first lower electrode, and a first semiconductor layer between the first upper electrode and the first lower electrode, and includes a first semiconductor chip provided on the insulating substrate, a first flat plate portion, a first electrode terminal electrically connected to one of the first upper electrode or the first lower electrode, and a second flat plate portion opposed to the first flat plate portion, and a first electrode terminal electrically connected to the other of the first upper electrode or the first lower electrode. a first resin member including a first resin having a first volume resistivity and a first Young's modulus; and a second resin member provided between the first flat plate portion and the second flat plate portion, the second resin member including a second resin having a second volume resistivity greater than the first volume resistivity and a second Young's modulus greater than the first Young's modulus. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 3] 1 is a schematic top view of the semiconductor device according to the first embodiment with some members removed; [Figure 4] 1 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. [Diagram 5] 1 is a schematic top view of the semiconductor device according to the first embodiment with some members removed; [Figure 6] 1 is a schematic top view of the semiconductor device according to the first embodiment with some members removed; [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 8] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 9] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 10] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 11] 3A to 3C are schematic cross-sectional views of the semiconductor device according to the first embodiment during its manufacture. [Figure 12] 3A to 3C are schematic cross-sectional views of the semiconductor device according to the first embodiment during its manufacture. [Figure 13] FIG. 5 is a schematic top view of a semiconductor device according to a second embodiment. [Figure 14] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 11 is a schematic top view of the semiconductor device according to the second embodiment with some members removed. [Figure 16] FIG. 11 is a schematic top view of the semiconductor device according to the second embodiment with some members removed. [Figure 17] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 18] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 19] FIG. 5 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In this specification, the same or similar components are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0009] In this specification, the upward direction of the drawing may be described as "upper" and the downward direction of the drawing may be described as "lower" in order to indicate the positional relationship of parts, etc. In this specification, the concepts of "upper" and "lower" do not necessarily refer to the direction of gravity.

[0010] (First embodiment) The semiconductor device of the first embodiment includes an insulating substrate, a frame surrounding the insulating substrate, a first upper electrode, a first lower electrode, and a first semiconductor layer between the first upper electrode and the first lower electrode, and includes a first semiconductor chip provided on the insulating substrate, a first flat plate portion, a first electrode terminal electrically connected to one of the first upper electrode or the first lower electrode, and a second flat plate portion facing the first flat plate portion, and a first electrode terminal electrically connected to the other of the first upper electrode or the first lower electrode. the first resin member including a first resin having a first volume resistivity and a first Young's modulus; and a second resin member provided between the first flat plate portion and the second flat plate portion, the second resin member including a second resin having a second volume resistivity greater than the first volume resistivity and a second Young's modulus greater than the first Young's modulus.

[0011] Fig. 1 is a schematic top view of the semiconductor device of the first embodiment, Fig. 2, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 are schematic cross-sectional views of the semiconductor device of the first embodiment.

[0012] Fig. 3, Fig. 5 and Fig. 6 are schematic top views of the semiconductor device of the first embodiment with some members removed Fig. 4 is an equivalent circuit diagram of the semiconductor device of the first embodiment.

[0013] FIG 2 is a cross-section taken along line AA' in FIG 1, FIG 3, FIG 5 and FIG 6. FIG 7 is a cross-section taken along line BB' in FIG 1, FIG 3, FIG 5 and FIG 6. FIG 8 is a cross-section taken along line CC' in FIG 1, FIG 3, FIG 5 and FIG 6. FIG 9 is a cross-section taken along line DD' in FIG 1, FIG 3, FIG 5 and FIG 6. FIG 10 is a cross-section taken along line EE' in FIG 1, FIG 3, FIG 5 and FIG 6.

[0014] The semiconductor device of the first embodiment is a power semiconductor module 100. As shown in Fig. 4, the power semiconductor module 100 of the first embodiment is a so-called "2-in-1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 100 has three half-bridge units connected in parallel. For example, a three-phase inverter circuit can be configured by using three power semiconductor modules 100 of the first embodiment.

[0015] As shown in FIG. 4, the power semiconductor module 100 includes a negative terminal N (first electrode terminal), a positive terminal P (second electrode terminal), an AC output terminal AC, a plurality of high-side MOSFETs 11 (first semiconductor chips), and a plurality of low-side MOSFETs 21 (second semiconductor chips).

[0016] The multiple high-side MOSFETs 11 are connected in parallel. The multiple low-side MOSFETs 21 are connected in parallel. The multiple high-side MOSFETs 11 and the multiple low-side MOSFETs 21 are connected in series.

[0017] 1 to 10, a case in which there are three high-side MOSFETs 11 and three low-side MOSFETs 21 is illustrated.

[0018] As shown in FIGS. 1 to 10 , the power semiconductor module 100 of the first embodiment includes a negative terminal N (first electrode terminal), a positive terminal P (second electrode terminal), an AC output terminal AC, a plurality of high-side MOSFETs 11 (first semiconductor chips), a plurality of low-side MOSFETs 21 (second semiconductor chips), a resin case 24 (frame), a lid 26, a metal base 28, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36, a second gate metal layer 37, a back surface metal layer 40, a first gate terminal 41, a second gate terminal 42, bonding wires 44, an electrode support member 51 (first resin member), a spacer member 52 (second resin member), and a sealing member 53 (third resin member).

[0019] Each of the multiple high-side MOSFETs 11 (first semiconductor chips) includes a first source electrode 11a (first upper electrode), a first drain electrode 11b (first lower electrode), a first gate electrode 11c, and a first silicon carbide layer 11x (first semiconductor layer).

[0020] Each of the multiple low-side MOSFETs 21 (second semiconductor chips) includes a second source electrode 21a (second upper electrode), a second drain electrode 21b (second lower electrode), a second gate electrode 21c, and a second silicon carbide layer 21x (second semiconductor layer).

[0021] Fig. 3 is a top view of the power semiconductor module 100 in a state where the negative terminal N (first electrode terminal), the positive terminal P (second electrode terminal), the AC output terminal AC, the lid 26, the electrode support member 51 (first resin member), the spacer member 52 (second resin member), and the sealing member 53 are removed from the power semiconductor module 100. Fig. 5 is a top view of the power semiconductor module 100 in a state where the lid 26, the electrode support member 51 (first resin member), the spacer member 52 (second resin member), and the sealing member 53 are removed from the power semiconductor module 100. Fig. 6 is a top view of the power semiconductor module 100 in a state where the negative terminal N (first electrode terminal), the lid 26, the electrode support member 51 (first resin member), the spacer member 52 (second resin member), and the sealing member 53 are removed from the power semiconductor module 100.

[0022] The metal base 28 is made of, for example, copper. For example, when the power semiconductor module 100 is mounted on a product, a heat sink (not shown) is connected to the rear surface of the metal base 28.

[0023] The insulating substrate 30 is provided on the metal base 28. The insulating substrate 30 is provided between the metal base 28 and the high-side MOSFET 11. The insulating substrate 30 is provided between the metal base 28 and the low-side MOSFET 21.

[0024] The insulating substrate 30 serves to electrically isolate the metal base 28 from the high-side MOSFET 11 and the metal base 28 from the low-side MOSFET 21 .

[0025] The insulating substrate 30 is, for example, a ceramic, aluminum oxide, aluminum nitride, or silicon nitride.

[0026] A first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36, and a second gate metal layer 37 are provided on the surface of the insulating substrate 30. The first metal layer 31, the second metal layer 32, the third metal layer 33, the first gate metal layer 36, and the second gate metal layer 37 are made of, for example, copper.

[0027] A back metal layer 40 is provided on the back surface of the insulating substrate 30. The back metal layer 40 is, for example, copper. The back metal layer 40 is bonded to the metal base 28 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0028] The resin case 24 is provided around the metal base 28 and the insulating substrate 30. The resin case 24 is an example of a frame. A portion of the resin case 24 is provided on the metal base 28.

[0029] The resin case 24 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0030] As shown in FIGS. 10 and 11, the resin case 24 has an inner side surface provided with a notch 24a into which the fitting portion 51a of the electrode support member 51 is fitted.

[0031] The resin case 24 includes a fourth resin and is formed of, for example, the fourth resin.

[0032] The fourth resin has a fourth volume resistivity and a fourth Young's modulus. The fourth resin is, for example, polyphenylene sulfide resin (PPS resin). The resin case 24 is, for example, made of polyphenylene sulfide resin (PPS resin).

[0033] A lid 26 is provided on the upper part of the resin case 24. The lid 26 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0034] The multiple high-side MOSFETs 11 are provided on the second metal layer 32. Each of the multiple high-side MOSFETs 11 includes a first source electrode 11a, a first drain electrode 11b, a first gate electrode 11c, and a first silicon carbide layer 11x. The first source electrode 11a is an example of a first upper electrode. The first drain electrode 11b is an example of a first lower electrode. The first silicon carbide layer 11x is an example of a first semiconductor layer.

[0035] The first silicon carbide layer 11x is provided between the first source electrode 11a and the first drain electrode 11b. The high-side MOSFET 11 is a vertical MOSFET.

[0036] The first source electrode 11a is electrically connected to the third metal layer 33. The first source electrode 11a and the third metal layer 33 are electrically connected using a bonding wire 44, for example.

[0037] The first source electrode 11 a is electrically connected to the negative terminal N via the third metal layer 33, the low-side MOSFET 21, and the first metal layer 31.

[0038] The first drain electrode 11b is electrically connected to the second metal layer 32. The first drain electrode 11b is electrically connected to the second metal layer 32 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0039] The first drain electrode 11b is electrically connected to the positive terminal P via the second metal layer 32.

[0040] The multiple high-side MOSFETs 11 are arranged in a direction parallel to the insulating substrate 30 .

[0041] The plurality of low-side MOSFETs 21 are provided on the third metal layer 33. Each of the plurality of low-side MOSFETs 21 includes a second source electrode 21a, a second drain electrode 21b, a second gate electrode 21c, and a second silicon carbide layer 21x. The second source electrode 21a is an example of a second upper electrode. The second drain electrode 21b is an example of a second lower electrode. The second silicon carbide layer 21x is an example of a second semiconductor layer.

[0042] The second silicon carbide layer 21x is provided between the second source electrode 21a and the second drain electrode 21b. The low-side MOSFET 21 is a vertical MOSFET.

[0043] The second source electrode 21a is electrically connected to the first metal layer 31. The second source electrode 21a and the first metal layer 31 are electrically connected to each other using, for example, a bonding wire 44. The second drain electrode 21b is electrically connected to the third metal layer 33. The second drain electrode 21b is electrically connected to the third metal layer 33 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0044] The low-side MOSFETs 21 are arranged in a direction parallel to the insulating substrate 30 .

[0045] The sealing member 53 is filled in the resin case 24. The sealing member 53 is surrounded by the resin case 24. The sealing member 53 covers the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0046] The sealing member 53 has a function of protecting the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30. In addition, the sealing member 53 has a function of insulating the high-side MOSFET 11, the low-side MOSFET 21, and the insulating substrate 30.

[0047] The sealing member 53 includes a third resin. The sealing member 53 is formed of, for example, the third resin.

[0048] The third resin has a third volume resistivity and a third Young's modulus. The third resin is, for example, a silicone gel. The third resin may be, for example, a polyimide resin or another resin.

[0049] The negative terminal N is provided on the upper side of the insulating substrate 30. The negative terminal N is an example of a first electrode terminal.

[0050] The negative terminal N has a first flat plate portion Np and a first connection portion Nc. The negative terminal N has a wiring connection hole.

[0051] The negative terminal N is electrically connected to the first metal layer 31 using a first connection portion Nc. The first metal layer 31 and the first connection portion Nc are connected to each other using, for example, ultrasonic metal bonding. The first metal layer 31 and the first connection portion Nc are also connected to each other using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0052] For example, a negative voltage is applied from the outside to the negative terminal N. The negative terminal N is made of a metal. For example, the negative terminal N is made of copper.

[0053] The positive terminal P is provided on the upper side of the insulating substrate 30. The positive terminal P is an example of a second electrode terminal.

[0054] The positive terminal P has a second flat plate portion Pp and a second connection portion Pc. The positive terminal P has a wiring connection hole.

[0055] The positive terminal P is electrically connected to the second metal layer 32 using the second connection portion Pc. The second metal layer 32 and the second connection portion Pc are connected using, for example, ultrasonic metal bonding. The second metal layer 32 and the second connection portion Pc are also connected using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0056] The second plate portion Pp faces the first plate portion Np. The second plate portion Pp and the first plate portion Np are parallel to each other.

[0057] The distance between the first flat plate portion Np and the insulating substrate 30 is, for example, greater than the distance between the second flat plate portion Pp and the insulating substrate 30. The second flat plate portion Pp is provided between the first flat plate portion Np and the insulating substrate 30, for example.

[0058] The distance (d in FIG. 2) between the first flat plate portion Np and the second flat plate portion Pp is, for example, not less than 0.2 mm and not more than 2 mm.

[0059] For example, a positive voltage is applied from the outside to the positive terminal P. The positive terminal P is made of a metal. For example, the positive terminal P is made of copper.

[0060] The AC output terminal AC is provided on the upper side of the insulating substrate 30. The AC output terminal AC and the positive terminal P and the negative terminal N are provided on the same side of the insulating substrate 30.

[0061] The AC output terminal AC has a third connection portion ACc and a wiring connection hole.

[0062] The AC output terminal AC is electrically connected to the third metal layer 33 by using the third connection part ACC. The third metal layer 33 and the third connection part ACC are connected by using, for example, ultrasonic metal bonding. The third metal layer 33 and the third connection part ACC are connected by using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0063] The AC output terminal AC outputs an output current of the half-bridge circuit. The AC output terminal AC is made of a metal. For example, the AC output terminal AC is made of copper.

[0064] The first gate terminal 41 is electrically connected to the first gate electrode 11c of the high-side MOSFET 11. The first gate terminal 41 is electrically connected to the first gate electrode 11c by using, for example, the first gate metal layer 36 and a bonding wire 44.

[0065] The second gate terminal 42 is electrically connected to the second gate electrode 21c of the low-side MOSFET 21. The second gate terminal 42 is electrically connected to the second gate electrode 21c by using, for example, the second gate metal layer 37 and a bonding wire 44.

[0066] The first metal layer 31 is provided on the insulating substrate 30. The first metal layer 31 is electrically connected to the negative terminal N. The first metal layer 31 is electrically connected to the second source electrode 21a of the low-side MOSFET 21.

[0067] A second metal layer 32 is provided on the insulating substrate 30. The second metal layer 32 is electrically connected to the positive terminal P.

[0068] The second metal layer 32 is provided between the high-side MOSFET 11 and the insulating substrate 30. The second metal layer 32 is electrically connected to the first drain electrode 11b of the high-side MOSFET 11.

[0069] The third metal layer 33 is provided on the insulating substrate 30. The third metal layer 33 is electrically connected to the AC output terminal AC.

[0070] The third metal layer 33 is provided between the low-side MOSFET 21 and the insulating substrate 30. The third metal layer 33 is electrically connected to the second drain electrode 21b of the low-side MOSFET 21.

[0071] The electrode support member 51 supports, for example, the negative terminal N. The electrode support member 51 is fixed, for example, to the negative terminal N. The negative terminal N and the electrode support member 51 are integrated, for example, by insert molding. Note that the electrode support member 51 may be fixed, for example, to the positive terminal P.

[0072] The electrode support member 51 includes a fitting portion 51a. The fitting portion 51a has a protrusion shape.

[0073] 11 and 12 are schematic cross-sectional views during the manufacture of the semiconductor device of the first embodiment.

[0074] Fig. 11 shows a cross section corresponding to Fig. 10. Fig. 12 shows a cross section corresponding to Fig. 7.

[0075] As shown in FIGS. 10, 11 and 12, the fitting portion 51a is fitted into a notch 24a provided in the inner side surface of the resin case 24, whereby the electrode support member 51 is fixed to the resin case 24.

[0076] The fitting portion 51a includes a first resin having a first volume resistivity and a first Young's modulus. The fitting portion 51a is formed of, for example, the first resin. The entire electrode support member 51 may be formed of the first resin.

[0077] The first resin is, for example, a polyamide resin (PA resin) or a polybutylene terephthalate resin (PBT resin). The fitting portion 51a is, for example, formed of a polyamide resin (PA) or a polybutylene terephthalate resin (PBT).

[0078] The spacer member 52 is provided between the first flat plate portion Np of the negative terminal N and the second flat plate portion Pp of the positive terminal P. The spacer member 52 is fixed to the negative terminal N, for example. The negative terminal N, the spacer member 52, and the electrode support member 51 are integrated by, for example, insert molding. The spacer member 52 may be fixed to the positive terminal P, for example.

[0079] The spacer member 52 is in contact with, for example, the first flat plate portion Np. The spacer member 52 is in contact with, for example, the second flat plate portion Pp. The spacer member 52 may be separated from, for example, the first flat plate portion Np or the second flat plate portion Pp.

[0080] The spacer member 52 has a function of electrically insulating the negative terminal N and the positive terminal P. The spacer member 52 has a function of electrically insulating the first flat plate portion Np and the second flat plate portion Pp.

[0081] The thickness of the spacer member 52 is, for example, not less than 0.2 mm and not more than 2 mm.

[0082] The spacer member 52 includes a second resin having a second volume resistivity and a second Young's modulus, and is formed of, for example, the second resin.

[0083] The second volume resistivity is greater than the first volume resistivity, and the second Young's modulus is greater than the first Young's modulus.

[0084] The second resin is, for example, polyphenylene sulfide resin (PPS resin). The spacer member 52 is formed of, for example, polyphenylene sulfide resin (PPS resin).

[0085] The first resin is, for example, a polyamide resin, and the second resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polyamide resin. The first resin is, for example, a polybutylene terephthalate resin, and the second resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polybutylene terephthalate resin.

[0086] The third resin contained in the sealing member 53 has a third volume resistivity and a third Young's modulus. The third volume resistivity is, for example, larger than the second volume resistivity. The third Young's modulus is, for example, smaller than the first Young's modulus.

[0087] When the first resin is, for example, a polyamide resin and the second resin is, for example, a polyphenylene sulfide resin, the third resin is, for example, a silicone gel having a volume resistivity higher than that of the polyphenylene sulfide resin and a Young's modulus lower than that of the polyamide resin.

[0088] Furthermore, when the first resin is, for example, a polybutylene terephthalate resin and the second resin is, for example, a polyphenylene sulfide resin, the third resin is, for example, a silicone gel having a volume resistivity higher than that of the polyphenylene sulfide resin and a Young's modulus lower than that of the polybutylene terephthalate resin.

[0089] The fourth resin contained in the resin case 24 has a fourth volume resistivity and a fourth Young's modulus. The fourth volume resistivity is, for example, greater than the first volume resistivity. Also, the fourth Young's modulus is, for example, greater than the first Young's modulus.

[0090] The fourth resin contained in the resin case 24 is the same as the second resin contained in the spacer member 52, for example.

[0091] When the first resin is, for example, a polyamide resin, the fourth resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polyamide resin. When the first resin is, for example, a polybutylene terephthalate resin, the fourth resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polybutylene terephthalate resin.

[0092] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0093] If the inductance inside the power semiconductor module is large, for example, a surge voltage during switching will be large. If the surge voltage during switching is large, for example, a problem will occur in that the semiconductor chip will be destroyed. Therefore, it is desirable to reduce the inductance inside the power semiconductor module.

[0094] The inductance of a wiring consists of self-inductance due to self-induction and mutual inductance due to mutual induction. The inductance of a wiring is the sum of the self-inductance and the mutual inductance.

[0095] For example, in the power semiconductor module 100 of the first embodiment, the inductance of the negative terminal N and the positive terminal P is the sum of the self-inductance of each of the negative terminal N and the positive terminal P and the mutual inductance due to mutual induction between the negative terminal N and the positive terminal P.

[0096] In the power semiconductor module 100 of the first embodiment, a first flat plate portion Np is provided on the negative terminal N, and a second flat plate portion Pp is provided on the positive terminal P. The first flat plate portion Np and the second flat plate portion Pp face each other in parallel.

[0097] The current flows in the first flat plate portion Np and the second flat plate portion Pp in the opposite directions. Therefore, the mutual inductance acts in a direction that cancels out the self-inductance. This reduces the inductance of the negative terminal N and the positive terminal P. This reduces the internal inductance of the power semiconductor module 100.

[0098] The smaller the distance between the first flat plate portion Np and the second flat plate portion Pp, the more the inductance between the negative terminal N and the positive terminal P can be reduced, and the more the inductance inside the power semiconductor module 100 can be reduced. However, if the distance between the first flat plate portion Np and the second flat plate portion Pp becomes small, electrical insulation between the negative terminal N and the positive terminal P cannot be ensured, and the negative terminal N and the positive terminal P may be short-circuited, which may destroy the power semiconductor module 100.

[0099] In the power semiconductor module 100 of the first embodiment, the spacer member 52 is provided between the first flat plate portion Np and the second flat plate portion Pp, thereby ensuring electrical insulation between the negative terminal N and the positive terminal P. It is desirable that the resin constituting the spacer member 52 has a large volume resistivity.

[0100] In the power semiconductor module 100 of the first embodiment, the negative terminal N is attached by fitting the electrode support member 51 to which the negative terminal N is fixed into the resin case 24. By using the electrode support member 51 for attachment, it becomes possible to easily attach the negative terminal N. Furthermore, by using the electrode support member 51 for attachment, high mechanical strength of the power semiconductor module 100 and high electrical insulation of the power semiconductor module 100 are ensured.

[0101] The electrode support member 51 is fixed to the resin case 24 by fitting the fitting portion 51a provided on the electrode support member 51 into the notch portion 24a provided on the inner side surface of the resin case 24. At this time, if the amount of elastic deformation of the protruding fitting portion 51a is not large, the fitting portion 51a may be damaged. Therefore, it is desirable that the resin constituting the fitting portion 51a has a small Young's modulus.

[0102] In the power semiconductor module 100 of the first embodiment, the fitting portion 51a includes a first resin having a first volume resistivity and a first Young's modulus, and the spacer member 52 includes a second resin having a second volume resistivity and a second Young's modulus.

[0103] The second volume resistivity is greater than the first volume resistivity. Also, the second Young's modulus is greater than the first Young's modulus. That is, the spacer member 52 has a greater volume resistivity and a higher electrical insulation than the fitting portion 51a. Also, the fitting portion 51a has a smaller Young's modulus and a larger amount of elastic deformation than the spacer member 52.

[0104] Since the spacer member 52 has high electrical insulation, it is possible to reduce the distance between the first flat plate portion Np and the second flat plate portion Pp. Therefore, the internal inductance of the power semiconductor module 100 can be reduced.

[0105] Moreover, the increased elastic deformation of the fitting portion 51a of the electrode support member 51 facilitates attachment of the negative terminal N to the resin case 24. Furthermore, damage to the fitting portion 51a is suppressed, and the manufacturing yield of the power semiconductor module 100 is improved.

[0106] According to the power semiconductor module 100 of the first embodiment, it is possible to achieve both a reduction in the internal inductance of the power semiconductor module 100 and a high manufacturing yield of the power semiconductor module 100.

[0107] From the viewpoint of achieving both a reduction in inductance and a high manufacturing yield, it is preferable that the first resin contained in the fitting portion 51a is a polyamide resin, and the second resin contained in the spacer member 52 is a polyphenylene sulfide resin.

[0108] From the viewpoint of achieving both a reduction in inductance and a high manufacturing yield, it is preferable that the first resin contained in the fitting portion 51a is a polybutylene terephthalate resin, and the second resin contained in the spacer member 52 is a polyphenylene sulfide resin.

[0109] From the viewpoint of easily ensuring electrical insulation within the power semiconductor module 100, it is preferable that the sealing member 53 contains a third resin having a third volume resistivity greater than the second volume resistivity and a third Young's modulus smaller than the first Young's modulus.

[0110] From the viewpoint of easily ensuring the mechanical strength and electrical insulation of the power semiconductor module 100, it is preferable that the resin case 24 contains a fourth resin having a fourth volume resistivity greater than the first volume resistivity and a fourth Young's modulus greater than the first Young's modulus.

[0111] From the viewpoint of reducing the internal inductance of the power semiconductor module 100, the distance (d in FIG. 2) between the first flat plate portion Np and the second flat plate portion Pp is preferably 2 mm or less, more preferably 1.5 mm or less, and even more preferably 1 mm or less.

[0112] As described above, according to the first embodiment, it is possible to provide a semiconductor device with reduced inductance.

[0113] Second embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the semiconductor device of the second embodiment does not include a second semiconductor chip. In the following, some of the contents that overlap with the first embodiment may be omitted.

[0114] Fig. 13 is a schematic top view of the semiconductor device of the second embodiment, Fig. 14, Fig. 17, Fig. 18, and Fig. 19 are schematic cross-sectional views of the semiconductor device of the second embodiment.

[0115] 15 and 16 are schematic top views of the semiconductor device according to the second embodiment with some members removed.

[0116] Fig. 14 is a cross-section taken along line AA' in Figs. 13, 15 and 16. Fig. 17 is a cross-section taken along line BB' in Figs. 13, 15 and 16. Fig. 18 is a cross-section taken along line CC' in Figs. 13, 15 and 16. Fig. 19 is a cross-section taken along line EE' in Figs. 13, 15 and 16.

[0117] The semiconductor device of the second embodiment is a power semiconductor module 200. The power semiconductor module 200 of the second embodiment is a so-called "1-in-1" type module. The power semiconductor module 200 has three MOSFETs connected in parallel.

[0118] A plurality of MOSFETs 10 (first semiconductor chips) are connected in parallel.

[0119] 13 to 19 show an example in which three MOSFETs 10 are provided.

[0120] As shown in Figures 13 to 19, the power semiconductor module 200 of the second embodiment includes a negative terminal N (first electrode terminal), a positive terminal P (second electrode terminal), a plurality of MOSFETs 10 (first semiconductor chips), a resin case 24 (frame), a lid 26, a metal base 28, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a gate metal layer 35, a back surface metal layer 40, a gate terminal 43, a bonding wire 44, an electrode support member 51 (first resin member), a spacer member 52 (second resin member), and a sealing member 53 (third resin member).

[0121] Each of the multiple MOSFETs 10 (first semiconductor chips) includes a source electrode 10a (first upper electrode), a drain electrode 10b (first lower electrode), a gate electrode 10c, and a silicon carbide layer 10x (first semiconductor layer).

[0122] Fig. 15 is a top view of the power semiconductor module 200 with the negative terminal N (first electrode terminal), the positive terminal P (second electrode terminal), the lid 26, the electrode support member 51 (first resin member), the spacer member 52 (second resin member), and the sealing member 53 removed. Fig. 16 is a top view of the power semiconductor module 100 with the lid 26, the electrode support member 51 (first resin member), the spacer member 52 (second resin member), and the sealing member 53 removed.

[0123] On the surface of an insulating substrate 30, a first metal layer 31, a second metal layer 32, and a gate metal layer 35 are provided.

[0124] As shown in FIG. 19, the resin case 24 has an inner side surface provided with a notch 24a into which the fitting portion 51a of the electrode support member 51 is fitted.

[0125] The resin case 24 includes a fourth resin and is formed of, for example, the fourth resin.

[0126] The fourth resin has a fourth volume resistivity and a fourth Young's modulus. The fourth resin is, for example, a polyphenylene sulfide resin. The resin case 24 is, for example, made of a polyphenylene sulfide resin.

[0127] The multiple MOSFETs 10 are provided on the second metal layer 32. Each of the multiple MOSFETs 10 includes a source electrode 10a, a drain electrode 10b, a gate electrode 10c, and a silicon carbide layer 10x. The source electrode 10a is an example of a first upper electrode. The drain electrode 10b is an example of a first lower electrode. The silicon carbide layer 10x is an example of a first semiconductor layer.

[0128] The silicon carbide layer 10x is provided between the source electrode 10a and the drain electrode 10b. The MOSFET 10 is a vertical MOSFET.

[0129] The source electrode 10a is electrically connected to the first metal layer 31. The source electrode 10a and the first metal layer 31 are electrically connected using a bonding wire 44, for example.

[0130] The source electrode 10a is connected to the negative terminal N via a first metal layer 31.

[0131] The drain electrode 10b is electrically connected to the second metal layer 32. The drain electrode 10b is connected to the positive terminal P via the second metal layer 32.

[0132] The multiple MOSFETs 10 are arranged in a direction parallel to the insulating substrate 30 .

[0133] The sealing member 53 is filled in the resin case 24. The sealing member 53 is surrounded by the resin case 24. The sealing member 53 covers the MOSFET 10 and the insulating substrate 30.

[0134] The sealing member 53 includes a third resin. The sealing member 53 is formed of, for example, the third resin.

[0135] The third resin has a third volume resistivity and a third Young's modulus. The third resin is, for example, a silicone gel. The third resin may be, for example, a polyimide resin or another resin.

[0136] The negative terminal N is provided on the upper side of the insulating substrate 30. The negative terminal N is an example of a first electrode terminal.

[0137] The negative terminal N has a first flat plate portion Np and a first connection portion Nc. The negative terminal N has a wiring connection hole.

[0138] The negative terminal N is electrically connected to the first metal layer 31 by means of a first connection Nc.

[0139] To the negative terminal N, for example, a negative voltage is applied from the outside.

[0140] The positive terminal P is provided on the upper side of the insulating substrate 30. The positive terminal P is an example of a second electrode terminal.

[0141] The positive terminal P has a second flat plate portion Pp and a second connection portion Pc. The positive terminal P has a wiring connection hole.

[0142] The positive terminal P is electrically connected to the second metal layer 32 by means of a second connection Pc.

[0143] The second plate portion Pp faces the first plate portion Np. The second plate portion Pp and the first plate portion Np are parallel to each other.

[0144] The distance between the first flat plate portion Np and the insulating substrate 30 is, for example, greater than the distance between the second flat plate portion Pp and the insulating substrate 30. The second flat plate portion Pp is provided between the first flat plate portion Np and the insulating substrate 30, for example.

[0145] The distance (d in FIG. 14) between the first flat plate portion Np and the second flat plate portion Pp is, for example, not less than 0.2 mm and not more than 2 mm.

[0146] To the positive terminal P, for example, a positive voltage is applied from the outside.

[0147] The gate terminal 43 is electrically connected to the gate electrode 10c of the MOSFET 10. The gate terminal 43 is electrically connected to the gate electrode 10c using, for example, the gate metal layer 35 and a bonding wire 44.

[0148] The first metal layer 31 is provided on the insulating substrate 30. The first metal layer 31 is electrically connected to the negative terminal N. The first metal layer 31 is electrically connected to the source electrode 10a of the MOSFET 10.

[0149] A second metal layer 32 is provided on the insulating substrate 30. The second metal layer 32 is electrically connected to the positive terminal P.

[0150] The second metal layer 32 is provided between the MOSFET 10 and the insulating substrate 30. The second metal layer 32 is electrically connected to the drain electrode 10b of the MOSFET 10.

[0151] The electrode support member 51 supports, for example, the negative terminal N. The electrode support member 51 is fixed, for example, to the negative terminal N. The negative terminal N and the electrode support member 51 are integrated, for example, by insert molding. Note that the electrode support member 51 may be fixed, for example, to the positive terminal P.

[0152] The electrode support member 51 includes a fitting portion 51a. The fitting portion 51a has a protrusion shape.

[0153] As shown in FIG. 19, the fitting portion 51a is fitted into a notch 24a provided in the inner side surface of the resin case 24, whereby the electrode support member 51 is fixed to the resin case 24.

[0154] The fitting portion 51a includes a first resin having a first volume resistivity and a first Young's modulus. The fitting portion 51a is formed of, for example, the first resin. The entire electrode support member 51 may be formed of the first resin.

[0155] The first resin is, for example, a polyamide resin or a polybutylene terephthalate resin. The fitting portion 51a is made of a polyamide resin or a polybutylene terephthalate resin.

[0156] The spacer member 52 is provided between the first flat plate portion Np of the negative terminal N and the second flat plate portion Pp of the positive terminal P. The spacer member 52 is fixed to the negative terminal N, for example. The negative terminal N, the spacer member 52, and the electrode support member 51 are integrated by, for example, insert molding. The spacer member 52 may be fixed to the positive terminal P, for example.

[0157] The spacer member 52 is in contact with, for example, the first flat plate portion Np. The spacer member 52 is in contact with, for example, the second flat plate portion Pp. The spacer member 52 may be separated from, for example, the first flat plate portion Np or the second flat plate portion Pp.

[0158] The spacer member 52 has a function of electrically insulating the negative terminal N and the positive terminal P. The spacer member 52 has a function of electrically insulating the first flat plate portion Np and the second flat plate portion Pp.

[0159] The thickness of the spacer member 52 is, for example, not less than 0.2 mm and not more than 2 mm.

[0160] The spacer member 52 includes a second resin having a second volume resistivity and a second Young's modulus, and is formed of, for example, the second resin.

[0161] The second volume resistivity is greater than the first volume resistivity, and the second Young's modulus is greater than the first Young's modulus.

[0162] The second resin is, for example, a polyphenylene sulfide resin. The spacer member 52 is formed of, for example, a polyphenylene sulfide resin.

[0163] The first resin is, for example, a polyamide resin, and the second resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polyamide resin. The first resin is, for example, a polybutylene terephthalate resin, and the second resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polybutylene terephthalate resin.

[0164] The third resin contained in the sealing member 53 has a third volume resistivity and a third Young's modulus. The third volume resistivity is, for example, larger than the second volume resistivity. The third Young's modulus is, for example, smaller than the first Young's modulus.

[0165] When the first resin is, for example, a polyamide resin and the second resin is, for example, a polyphenylene sulfide resin, the third resin is, for example, a silicone gel having a volume resistivity higher than that of the polyphenylene sulfide resin and a Young's modulus lower than that of the polyamide resin.

[0166] Furthermore, when the first resin is, for example, a polybutylene terephthalate resin and the second resin is, for example, a polyphenylene sulfide resin, the third resin is, for example, a silicone gel having a volume resistivity higher than that of the polyphenylene sulfide resin and a Young's modulus lower than that of the polybutylene terephthalate resin.

[0167] The fourth resin contained in the resin case 24 has a fourth volume resistivity and a fourth Young's modulus. The fourth volume resistivity is, for example, greater than the first volume resistivity. Also, the fourth Young's modulus is, for example, greater than the first Young's modulus.

[0168] The fourth resin contained in the resin case 24 is the same as the second resin contained in the spacer member 52, for example.

[0169] When the first resin is, for example, a polyamide resin, the fourth resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polyamide resin. When the first resin is, for example, a polybutylene terephthalate resin, the fourth resin is, for example, a polyphenylene sulfide resin having a higher volume resistivity and a higher Young's modulus than the polybutylene terephthalate resin.

[0170] According to the power semiconductor module 200 of the second embodiment, similarly to the power semiconductor module 100 of the first embodiment, it is possible to achieve both a reduction in the internal inductance of the power semiconductor module 200 and a high manufacturing yield of the power semiconductor module 200.

[0171] As described above, according to the second embodiment, a semiconductor device with reduced inductance can be provided.

[0172] In the first and second embodiments, the case where the number of power semiconductor chips arranged in parallel is three has been described as an example, but the number of power semiconductor chips may be two or four or more.

[0173] In the first and second embodiments, the power semiconductor modules are described as being of the "2-in-1" type and the "1-in-1" type, but the power semiconductor module may have other circuit configurations, such as a "4-in-1" type, a "6-in-1" type, a chopper circuit, etc. Also, the number of power semiconductor chips may be one.

[0174] In the first and second embodiments, the semiconductor chip is a MOSFET. However, the semiconductor chip may be another type of semiconductor chip, such as an Insulated Gate Bipolar Transistor (IGBT) or a diode.

[0175] In the first and second embodiments, the semiconductor layer of the semiconductor chip is described as a silicon carbide layer, but the semiconductor layer of the semiconductor chip may be other semiconductor layers, such as a nitride semiconductor layer or a silicon layer.

[0176] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0177] 10 MOSFET (first semiconductor chip) 10a Source electrode (first upper electrode) 10b Drain electrode (first lower electrode) 10x silicon carbide layer (first semiconductor layer) 11 High-side MOSFET (first semiconductor chip) 11a: first source electrode (first upper electrode) 11b first drain electrode (first lower electrode) 11x first silicon carbide layer (first semiconductor layer) 21 Low-side MOSFET (second semiconductor chip) 21a: second source electrode (second upper electrode) 21b Second drain electrode (second lower electrode) 21x second silicon carbide layer (second semiconductor layer) 24 Resin case (frame) 30 Insulating substrate 31 First metal layer 32 Second Metal Layer 33 Third Metal Layer 51 Electrode support member (first resin member) 51a Mating part 52 Spacer member (second resin member) 53 Sealing member (third resin member) 100 Power semiconductor module (semiconductor device) 200 Power semiconductor module (semiconductor device) N Negative terminal (first electrode terminal) Np 1st plate part P positive terminal (second electrode terminal) Pp Second flat section

Claims

1. An insulating substrate; A frame surrounding the insulating substrate; a first semiconductor chip provided on the insulating substrate, the first semiconductor chip including a first upper electrode, a first lower electrode, and a first semiconductor layer between the first upper electrode and the first lower electrode; a first electrode terminal including a first flat plate portion and electrically connected to one of the first upper electrode or the first lower electrode; a second electrode terminal including a second flat plate portion facing the first flat plate portion and electrically connected to the other of the first upper electrode or the first lower electrode; a first resin member fixed to at least one of the first electrode terminal and the second electrode terminal and including a fitting portion fitted into the frame, the fitting portion including a first resin having a first volume resistivity and a first Young's modulus; a second resin member provided between the first flat plate portion and the second flat plate portion, the second resin member including a second resin having a second volume resistivity larger than the first volume resistivity and a second Young's modulus larger than the first Young's modulus; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising a third resin member covering the first semiconductor chip and including a third resin having a third volume resistivity greater than the second volume resistivity and a third Young's modulus smaller than the first Young's modulus.

3. 3. The semiconductor device according to claim 2, wherein said third resin is a silicone gel.

4. 2. The semiconductor device according to claim 1, wherein said frame includes a fourth resin having a fourth volume resistivity greater than said first volume resistivity and a fourth Young's modulus greater than said first Young's modulus.

5. 5. The semiconductor device according to claim 4, wherein said fourth resin is the same as said second resin.

6. 2. The semiconductor device according to claim 1, wherein said first resin is a polyamide resin, and said second resin is a polyphenylene sulfide resin.

7. 2. The semiconductor device according to claim 1, wherein said first resin is a polybutylene terephthalate resin, and said second resin is a polyphenylene sulfide resin.

8. 2. The semiconductor device according to claim 1, wherein a distance between said first flat plate portion and said insulating substrate is greater than a distance between said second flat plate portion and said insulating substrate, and said first resin member is fixed to said first electrode terminal.

9. a first metal layer provided on the insulating substrate and electrically connected to the first electrode terminal; a second metal layer provided on the insulating substrate and electrically connected to the second electrode terminal; 2. The semiconductor device according to claim 1, wherein the second metal layer is provided between the first semiconductor chip and the insulating substrate, the first upper electrode is electrically connected to the first metal layer, and the first lower electrode is electrically connected to the second metal layer.

10. a second semiconductor chip provided on the insulating substrate, the second semiconductor chip including a second upper electrode, a second lower electrode, and a second semiconductor layer between the second upper electrode and the second lower electrode; a third metal layer provided on the insulating substrate; 10. The semiconductor device of claim 9, wherein the third metal layer is provided between the second semiconductor chip and the insulating substrate, the second upper electrode is electrically connected to the first metal layer, and the second lower electrode is electrically connected to the third metal layer.

11. 2. The semiconductor device according to claim 1, wherein the distance between said first flat plate portion and said second flat plate portion is 2 mm or less.

12. The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises a silicon carbide layer.

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