Semiconductor device

Abstract

To provide a semiconductor device whose variations in rising voltage and forward voltage can be suppressed.SOLUTION: A semiconductor device according to an embodiment includes a SiC layer having a first surface formed of a silicon surface and a second surface formed of a carbon surface, a plurality of projection parts whose top surface is a part of the first surface and side surfaces in contact with the top surface, a first electrode forming Schottky junction with the projection parts, a second electrode on the second surface, a first semiconductor region of a first conductivity type provided in the SiC layer, a second semiconductor region of a second conductivity type provided in the SiC layer between the projection parts and positioned between the first semiconductor region and the first electrode, and a third semiconductor region of the first conductivity type provided on the side surface of the projection part, positioned between the first electrode and the first semiconductor region in the projection part, and having higher impurity concentration of the first conductivity type than the first semiconductor region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Schottky barrier diodes (SBDs), which are semiconductor devices that are bonded to metal, are known as a type of semiconductor device. F ) and short reverse recovery time. SBDs have the advantage of low leakage current (I R ), but to suppress leakage current, a JBS (Junction Barrier Schottky Diode) structure in which a p-type region is embedded on the surface of the n-type semiconductor layer is used. Furthermore, it is known that a trench structure is used on the metal interface side of the n-type semiconductor layer to reduce both the forward voltage and leakage current.

[0003] In order to achieve high breakdown voltage, silicon carbide (SiC) is used as the semiconductor material. However, in a trench-structure SBD using SiC, the Schottky junction characteristics are different between the surface and side of the trench, so the rise voltage (V th ) and forward voltage variations. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2017-55009 A [Patent Document 2] Patent No. 7067698 [Patent Document 3] Patent No. 5557581 [Patent Document 4] JP 2023-046669 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of suppressing variations in the rise voltage and the forward voltage. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface opposite to the first surface, a plurality of protrusions provided in the SiC layer, the protrusions having a top surface that is a portion of the first surface and a side surface connected to the top surface, a first electrode forming a Schottky junction between the plurality of protrusions, a second electrode provided on the second surface, a first semiconductor region of a first conductivity type provided in the SiC layer, a second semiconductor region of a second conductivity type provided in the SiC layer between the plurality of protrusions and positioned between the first semiconductor region and the first electrode, and a third semiconductor region of the first conductivity type provided on the side surface of the protrusions, positioned between the first electrode and the first semiconductor region in the protrusions, and having a higher impurity concentration of the first conductivity type than the first semiconductor region. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is an enlarged view of region A in FIG. [Diagram 3] 11 is a graph showing IF-VF characteristics of a Schottky barrier diode when a Schottky characteristic adjusting unit is not provided. [Figure 4] 4 is a graph showing IF-VF characteristics of a Schottky barrier diode of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 4 is a partial cross-sectional view of a semiconductor device according to a second embodiment. [Figure 6] 10 is a graph showing IF-VF characteristics of a Schottky barrier diode of the semiconductor device according to the second embodiment. [Figure 7]FIG. 11 is a partial cross-sectional view of a semiconductor device according to a third embodiment. [Figure 8] FIG. 4 is a diagram showing a partial cross section of another semiconductor device to which the Schottky characteristic adjustment parts according to the first to third embodiments can be applied. [Figure 9] 9 is a partial plan view of the semiconductor device shown in FIG. 8. [Figure 10] 1 is a partial plan view of a semiconductor device including a high-concentration anode region having an octagonal planar shape. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] In the following description, n + , n, n - , p + , p, p - The notation n may be used. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + Shape and n - The p-type is an example of the first conductivity type in the claims. + Shape and p - The n-type is an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be the p-type and the second conductivity type may be the n-type.

[0010] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy).

[0011] (First embodiment) A semiconductor device according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a cross-sectional view of a semiconductor device 1 according to this embodiment. Fig. 2 is an enlarged view of a region A in Fig. 1. Fig. 1 is also a drawing for the second and third embodiments described later.

[0012] 1, the semiconductor device 1 includes a SiC layer 10, a silicide layer 16, an anode electrode 20, a cathode electrode 30, and a field oxide film 40. The semiconductor device 1 is a trench-type SBD in which the metal interface side of the n-type semiconductor layer has a trench structure, and more specifically, is a trench-type JBS in which a p-type semiconductor region is provided at the bottom of the trench.

[0013] The SiC layer 10 is single crystal SiC (silicon carbide), and is made of, for example, 4H-SiC. The SiC layer 10 may be an epitaxial layer, a semiconductor substrate, or may be composed of a semiconductor substrate and an epitaxial layer provided thereon. The SiC layer 10 may be of other crystal forms, such as 3C-SiC or 6H-SiC.

[0014] 1, the SiC layer 10 has an upper surface 10a and a lower surface 10b, which is the main surface opposite to the upper surface 10a. The upper surface 10a is a (0001) surface, and the lower surface 10b is a (000-1) surface. The (0001) surface is sometimes called a silicon surface, and the (000-1) surface is sometimes called a carbon surface.

[0015] Note that the upper surface 10a and the lower surface 10b of the SiC layer 10 do not necessarily have to strictly coincide with the (0001) and (000-1) planes, respectively. For example, the upper surface 10a is a surface inclined at an angle of 0 to 8 degrees with respect to the (0001) plane, and the lower surface 10b is a surface inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0016] In the present application, when a surface is expressed as "composed of a silicon surface", the above range is included. In other words, when referring to an upper surface 10a composed of a silicon surface, the upper surface 10a is a surface inclined at an angle of 0 to 8 degrees with respect to the (0001) surface. Similarly, when referring to a lower surface 10b composed of a carbon surface, the lower surface 10b is a surface inclined at an angle of 0 to 8 degrees with respect to the (000-1) surface.

[0017] A plurality of protrusions 10p are provided in the SiC layer 10. These protrusions 10p appear by forming a plurality of trenches in the upper surface 10a of the SiC layer 10. Each protrusion 10p has a top surface 10pt and a side surface 10ps connected to the top surface 10pt. The top surface 10pt is a part of the upper surface 10a of the SiC layer 10, and is a surface composed of a silicon surface. A silicide layer 16 is provided on a surface connecting adjacent protrusions 10p (i.e., the bottom surface of the trench).

[0018] Within the SiC layer 10, there are provided a plurality of semiconductor regions, namely, a drift region 11 of a first conductivity type, an anode region 12 of a second conductivity type, a Schottky characteristic adjustment portion 13 of the first conductivity type, a cathode region 14 of the first conductivity type, high-concentration anode regions 15, 15e of the second conductivity type, and a RESURF region 19 of the second conductivity type.

[0019] The first conductivity type semiconductor region contains, for example, nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb) as an n-type impurity, and the second conductivity type semiconductor region contains, for example, aluminum (Al) or boron (B) as a p-type impurity.

[0020] 1 and 2, the anode electrode 20 is provided on the upper surface 10a side of the SiC layer 10 so as to embed a plurality of protruding portions 10p therein. The anode electrode 20 forms a Schottky junction with the plurality of protruding portions 10p.

[0021] The anode electrode 20 includes titanium (Ti), molybdenum (Mo), vanadium (V), nickel (Ni), or a laminated film of titanium and aluminum (Ti / Al). The anode electrode 20 may have a conductive layer (not shown) made of a material different from the above material (copper, aluminum, etc.) on a conductive layer made of the above material.

[0022] The cathode electrode 30 is provided on the lower surface 10b of the SiC layer 10. The cathode electrode 30 forms an ohmic junction with the SiC layer 10 (the cathode region 14 in this embodiment). The anode electrode 20 is, for example, a laminated film of titanium and aluminum (Ti / Al).

[0023] The field oxide film 40 is provided on the upper surface 10a of the SiC layer 10 so as to cover the RESURF region 19. The field oxide film 40 is made of, for example, a silicon oxide film.

[0024] Next, each semiconductor region provided in the SiC layer 10 will be described.

[0025] The drift region 11 is a n-type semiconductor layer provided in the SiC layer 10. - The impurity concentration of the n-type impurity in the drift region 11 is, for example, 1×10 15 cm -3 More than 2×10 16 cm -3 The drift region 11 is an example of a first semiconductor region in the claims.

[0026] The anode region 12 is a p-type semiconductor region provided in the SiC layer 10 between the multiple protrusions 10p. The anode region 12 is located between the drift region 11 and the anode electrode 20. By providing the anode region 12, a depletion layer expands when a reverse bias is applied, making it possible to suppress leakage current. The anode region 12 is an example of a second semiconductor region in the claims.

[0027] The impurity concentration of the p-type impurity in the anode region 12 is, for example, 5×10 16 cm -3 More than 5× 10 18 cm -3 The anode region 12 is formed, for example, by forming a trench in the upper surface 10a of the SiC layer 10 and then ion-implanting a p-type impurity into the bottom surface of the trench.

[0028] The Schottky characteristic adjusting portion 13 is an n-type or n-type semiconductor provided on the side surface 10ps of the protruding portion 10p. + This n + The n-type semiconductor region is located between the anode electrode 20 and the drift region 11 in the protrusion 10p. The impurity concentration of the n-type impurity in the Schottky characteristic adjustment portion 13 is higher than the impurity concentration in the drift region 11, and is, for example, 1×10 16 cm -3 More than 1× 10 20 cm -3 The Schottky characteristic adjusting portion 13 is an example of a third semiconductor region in the claims.

[0029] The Schottky characteristic adjusting portion 13 adjusts the Schottky barrier height (φ B ) to approximate the Schottky barrier height at the top surface 10 pt. More details will be described later with reference to Figures 3 and 4.

[0030] The Schottky characteristic adjusting portion 13 is formed by ion-implanting an n-type impurity into the side surface 10ps (side surface of the trench) of the protrusion 10p by oblique ion implantation or the like. Alternatively, the Schottky characteristic adjusting portion 13 may be formed by forming a mask having an opening at the end of the protrusion 10p on the upper surface 10a of the SiC layer 10 and ion-implanting an n-type impurity into the opening.

[0031] The cathode region 14 is provided in the SiC layer 10 and is located between the drift region 11 and the cathode electrode 30. + The impurity concentration of the n-type impurity in the cathode region 14 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0032] The high concentration anode regions 15 and 15e are p + The impurity concentration of the p-type impurity in the high-concentration anode regions 15 and 15e is higher than the impurity concentration in the anode region 12, and is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The high-concentration anode regions 15, 15e are formed, for example, by forming the anode region 12 and then ion-implanting p-type impurities into the bottom surface of the trench using a mask that has an opening in part of the bottom surface of the trench. The high-concentration anode region 15 is provided, for example, in a rectangular shape in a plan view. The high-concentration anode region 15e is provided on the outer periphery of the anode region 12 so as to surround the element region including the high-concentration anode region 15 (see FIG. 9).

[0033] The resurf region 19 is a p-type GaN layer provided in the SiC layer 10 in order to improve the breakdown voltage of the semiconductor device 1. - The impurity concentration of the p-type impurity in the RESURF region 19 is lower than the impurity concentration of the p-type impurity in the anode region 12, and is, for example, 1×10 16 cm -3 More than 1×1018 cm -3 The RESURF region 19 is electrically connected to the anode electrode 20.

[0034] The silicide layer 16 is provided between the high-concentration anode regions 15, 15e and the anode electrode 20. The silicide layer 16 is made of, for example, nickel silicide. The silicide layer 16 is provided to reduce the resistance between the anode region 12 and the anode electrode 20. The silicide layer 16 is formed by a sputtering method or the like after the anode region 12 and the high-concentration anode regions 15, 15e are formed.

[0035] An n-type buffer layer (not shown) having an n-type impurity concentration between the impurity concentration of drift region 11 and the impurity concentration of cathode region 14 may be provided between drift region 11 and cathode region 14. High-concentration anode regions 15, 15e and / or silicide layer 16 may be omitted.

[0036] Next, the effect of the Schottky characteristic adjusting section 13 will be described with reference to Fig. 3 and Fig. 4. Fig. 3 shows the I F -V F In FIG. 3, characteristic C1 shows the I F -V F The characteristic C1 shows the I F -V F FIG. 4 shows the I F -V F The characteristics are shown.

[0037] In the SiC layer 10, the Schottky barrier height of the Schottky junction at the side surface 10ps is higher than that of the top surface 10pt of the silicon surface. For example, when the SiC layer 10 is made of 4H-SiC and the anode electrode 20 is made of titanium, the Schottky barrier height at the carbon surface is 1.30 eV, and the Schottky barrier height at the silicon surface is 1.17 eV. The Schottky barrier height at the side surface 10ps is a value between 1.17 eV and 1.30 eV. Since the Schottky barrier height at the side surface 10ps is higher than that at the top surface 10pt, in a structure without a Schottky characteristic adjustment unit 13, as shown in FIG. 3, the rise voltage V th2 is the SBD turn-on voltage V at the top surface of 10 pt. th1 The forward voltage is also greater for the side surface at 10ps than for the top surface at 10pt.

[0038] In contrast, in the semiconductor device 1 of this embodiment, the side surface 10ps has n + The Schottky characteristic adjusting portion 13 is made of a semiconductor region having a shape similar to that of the side surface 10ps. This reduces the Schottky barrier height at the side surface 10ps. As a result, as shown in FIG. th2 is the rising voltage V th1 is approximately equal to

[0039] Therefore, according to this embodiment, it is possible to reduce the variations in the rise voltage and forward voltage between the top surface 10pt and the side surface 10ps, and to provide a Schottky barrier diode having excellent uniformity in the rise voltage and forward voltage.

[0040] Second embodiment Next, a semiconductor device according to a second embodiment will be described with reference to Fig. 5. In this embodiment, the Schottky barrier height at the side surface 10ps is not reduced, but the Schottky barrier height at the top surface 10pt is increased.

[0041] The overall schematic configuration of the semiconductor device according to the second embodiment is the same as that of the first embodiment shown in Fig. 1. Fig. 5 is a cross-sectional view showing a characteristic portion (a region corresponding to Fig. 2) of the semiconductor device according to this embodiment.

[0042] As shown in Fig. 5, in the second embodiment, instead of the Schottky characteristic adjusting portion 13 described in the first embodiment, a Schottky characteristic adjusting portion 17 is provided on the top surface 10pt of the protrusion 10p. The Schottky characteristic adjusting portion 17 is a p-type or p + The protrusion 10p is a semiconductor region having a shape similar to that of a semiconductor substrate 10 and is located between the anode electrode 20 and the drift region 11 within the protrusion 10p.

[0043] The impurity concentration of the p-type impurity in the Schottky characteristic adjustment portion 17 is, for example, 1×10 16 cm -3 More than 1× 10 20 cm -3 The Schottky characteristic adjusting portion 17 is an example of a fourth semiconductor region in the claims. The Schottky characteristic adjusting portion 17 is formed, for example, by ion-implanting a p-type impurity into the top surface 10pt of the protrusion 10p.

[0044] FIG. 6 shows the I F -V F As shown in FIG. 6, by providing the Schottky characteristic adjusting portion 17, the Schottky barrier height at the top surface 10pt is increased, and as a result, the rise voltage V th1 is the SBD rise voltage V at 10ps th2 Therefore, according to this embodiment, it is possible to provide a Schottky barrier diode capable of suppressing variations in the rise voltage and the forward voltage.

[0045] (Third embodiment) Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 7. In this embodiment, a semiconductor region is not provided within the protruding portions 10p, but a conductive portion is provided between the protruding portions 10p (inside the trenches).

[0046] The overall schematic configuration of the semiconductor device according to the third embodiment is the same as that of the first embodiment shown in Fig. 1. Fig. 7 is a cross-sectional view showing a characteristic portion (a region corresponding to Fig. 2) of the semiconductor device according to this embodiment.

[0047] 7, in the third embodiment, instead of the Schottky characteristic adjustment portion 13 described in the first embodiment, a Schottky characteristic adjustment portion 18 is provided so as to cover the side surface 10ps of the protrusion 10p. The Schottky characteristic adjustment portion 18 is located between the anode electrode 20 and the drift region 11 in the protrusion 10p.

[0048] The Schottky characteristic adjusting portion 18 is a conductive portion made of a conductive material having a smaller work function than the anode electrode 20. The conductive portion is made of, for example, vanadium or titanium silicide. In this embodiment, the Schottky characteristic adjusting portion 18 is provided so as to cover the space between the protruding portions 10p (i.e., the inside of the trench) as shown in FIG.

[0049] The Schottky characteristic adjusting portion 18 of this embodiment is formed, for example, by forming the anode region 12, the high-concentration anode region 15, and the silicide layer 16, covering the upper surface 10a of the SiC layer 10 with a mask material having openings between the protrusions 10p, and depositing a conductive material using a sputtering method, a chemical vapor deposition (CVD) method, or the like. As shown in FIG. 7, a conductive portion is formed that covers the anode region 12 and the silicide layer 16 in addition to the side surface 10ps of the protrusion 10p. The Schottky characteristic adjusting portion 18 does not need to cover the anode region 12, and may be configured to cover at least the side surface 10ps of the protrusion 10p.

[0050] By providing the Schottky characteristic adjusting portion 18, the Schottky barrier height at the side surface 10ps of the protrusion 10p is lowered. Therefore, as in the first embodiment, the rise voltage V th2 The SBD rise voltage V th1Therefore, according to this embodiment, it is possible to provide a Schottky barrier diode capable of suppressing variations in the rise voltage and the forward voltage.

[0051] As described above, in the first to third embodiments, the Schottky characteristic adjusting parts 13, 17, and 18 that adjust the characteristics of the Schottky junction at the side surface 10ps of the protrusion 10p and the characteristics of the Schottky junction at the top surface 10pt are provided between the anode electrode 20 and the drift region 11 in the protrusion 10p. This makes it possible to reduce the variations in the rise voltage and forward voltage between the top surface 10pt and the side surface 10ps, and to provide a Schottky barrier diode having excellent uniformity in the rise voltage and forward voltage.

[0052] The Schottky characteristic adjustment units 13, 17, and 18 according to the first to third embodiments may be combined in any desired manner. For example, both the Schottky characteristic adjustment unit 13 and the Schottky characteristic adjustment unit 17 may be provided. Alternatively, at least one of the Schottky characteristic adjustment unit 13 and the Schottky characteristic adjustment unit 17 may be provided, and the Schottky characteristic adjustment unit 18 may also be provided. When the Schottky characteristic adjustment unit 13 is provided in this manner, the Schottky characteristic adjustment unit 13 is provided so as to be located between the Schottky characteristic adjustment unit 18 and the drift region 11 in the protrusion 10p.

[0053] Furthermore, the semiconductor device to which the Schottky characteristic adjustment portion is applied is not limited to the configuration shown in Fig. 1. Fig. 8 shows a partial cross section of another applicable semiconductor device. Fig. 9 is a plan view of the semiconductor device shown in Fig. 8. Fig. 8 is a cross section taken along line II in Fig. 9. In such a semiconductor device, Schottky characteristic adjustment portion 13 or Schottky characteristic adjustment portion 18 may be provided on the side surface of protrusion 10p, and Schottky characteristic adjustment portion 17 may be provided on the top surface of protrusion 10p.

[0054] 9, the high-concentration anode region 15 is provided in a rectangular shape in a plan view. The planar shape of the high-concentration anode region 15 is not limited to this, and may be, for example, a regular octagon as shown in FIG.

[0055] According to at least one of the semiconductor devices according to the embodiments described above, it is possible to provide a semiconductor device that has a high breakdown voltage and is capable of suppressing variations in the rise voltage and the forward voltage.

[0056] Although the embodiment of the present invention has been described, the embodiment and examples are presented as examples and are not intended to limit the scope of the invention. The embodiment and examples can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and examples and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0057] 1 Semiconductor device 10 SiC layer 10a top surface 10b Bottom side 10p protrusion 10pt top surface 10ps Side 11 Drift Region 12 Anode Region 13, 17, 18 Schottky characteristic adjustment section 14 Cathode Region 15,15e High concentration anode region 16 Silicide layer 19 Resurf Region 20 Anode electrode 30 Cathode Electrode 40 Field oxide Area A

Claims

1. a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface opposite to the first surface; a plurality of protrusions provided in the SiC layer, the protrusions having a top surface that is a part of the first surface and a side surface connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; a second electrode provided on the second surface; a first semiconductor region of a first conductivity type provided in the SiC layer; a second semiconductor region of a second conductivity type provided in the SiC layer between the plurality of protrusions and located between the first semiconductor region and the first electrode; a third semiconductor region of the first conductivity type provided on the side surface of the protrusion, located between the first electrode and the first semiconductor region in the protrusion, and having a higher impurity concentration of the first conductivity type than the first semiconductor region; A semiconductor device comprising:

2. a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface opposite to the first surface; a plurality of protrusions provided in the SiC layer, the protrusions having a top surface that is a part of the first surface and a side surface connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; a second electrode provided on the second surface; a first semiconductor region of a first conductivity type provided in the SiC layer; a second semiconductor region of a second conductivity type provided in the SiC layer between the plurality of protrusions and located between the first semiconductor region and the first electrode; a fourth semiconductor region of a second conductivity type provided on the top surface of the protrusion and located between the first electrode and the first semiconductor region within the protrusion; A semiconductor device comprising:

3. a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface opposite to the first surface; a plurality of protrusions provided in the SiC layer, the protrusions having a top surface that is a part of the first surface and a side surface connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; a second electrode provided on the second surface; a first semiconductor region of a first conductivity type provided in the SiC layer; a second semiconductor region of a second conductivity type provided in the SiC layer between the plurality of protrusions and located between the first semiconductor region and the first electrode; a conductive portion provided so as to cover at least the side surface of the protrusion and having a work function smaller than that of the first electrode; A semiconductor device comprising:

4. 4. The semiconductor device according to claim 3, wherein said conductive portion contains vanadium or titanium silicide.

5. 4. The semiconductor device according to claim 3, further comprising a fifth semiconductor region of a first conductivity type provided on the side surface of the protrusion, located between the conductive portion and the first semiconductor region within the protrusion, and having a higher impurity concentration of the first conductivity type than the first semiconductor region.

6. 4. The semiconductor device according to claim 3, further comprising a sixth semiconductor region of the second conductivity type provided on the top surface of the protrusion and located between the first electrode and the first semiconductor region within the protrusion.

7. 7. The semiconductor device according to claim 1, wherein the first electrode includes a layer of titanium, molybdenum, vanadium, nickel, or a laminated film of titanium and aluminum.

8. 7. The semiconductor device according to claim 1, further comprising a seventh semiconductor region of a second conductivity type provided within the second semiconductor region and having a higher impurity concentration of the second conductivity type than the second semiconductor region.

9. 9. The semiconductor device according to claim 8, further comprising a silicide layer provided between said seventh semiconductor region and said first electrode.

10. a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface opposite to the first surface; a plurality of protrusions provided in the SiC layer, the protrusions having a top surface that is a part of the first surface and a side surface connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; a second electrode provided on the second surface; a first semiconductor region of a first conductivity type provided in the SiC layer; a second semiconductor region of a second conductivity type provided in the SiC layer between the plurality of protrusions and located between the first semiconductor region and the first electrode; a Schottky characteristic adjustment section provided between the first electrode and the first semiconductor region in the protrusion, which adjusts the characteristics of the Schottky junction on the side surface of the protrusion and the characteristics of the Schottky junction on the top surface of the protrusion; A semiconductor device comprising:

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