Semiconductor device

Abstract

To provide a semiconductor device capable of reducing the risk of thermal destruction.SOLUTION: A semiconductor device includes a first electrode, a second electrode facing the first electrode in a first direction, a semiconductor layer of a first conductivity type provided between the first electrode and the second electrode, a plurality of first semiconductor regions of a second conductivity type that is provided on a first electrode side of the semiconductor layer and extends in a second direction perpendicular to the first direction, a plurality of second semiconductor regions that is provided on a surface side of the plurality of first semiconductor regions and has a higher impurity concentration of the second conductivity type than the first semiconductor regions, and a plurality of PIN diode regions that is provided on the first electrode side of the semiconductor layer, extends in a third direction perpendicular to the first and second directions, and is electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In a Junction Barrier Schottky Diode (JBS), which is one type of Schottky Barrier Diode (SBD), multiple p-type semiconductor regions are formed in a stripe pattern. In addition, in a JBS, PIN diode regions are distributed within an n-type semiconductor region. In the PIN diode region, a metal silicide layer is formed between the anode electrode and the p-type semiconductor region to reduce contact resistance. The PIN diode region can pass a large forward surge current through the n-type semiconductor region by utilizing conductivity modulation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6995725 Summary of the Invention [Problem to be solved by the invention]

[0004] In the n-type semiconductor region, holes that exist away from the PIN diode region have a long distance to the electrode and therefore have a high resistance, which can cause the element to be destroyed by the heat generated by the holes as they travel to the electrode.

[0005] An object of the present invention is to provide a semiconductor device capable of reducing the risk of thermal destruction. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a first electrode, a second electrode opposed to the first electrode in a first direction, a semiconductor layer of a first conductivity type provided between the first electrode and the second electrode, a plurality of first semiconductor regions of a second conductivity type provided on the first electrode side of the semiconductor layer and extending in a second direction perpendicular to the first direction, a plurality of second semiconductor regions provided on a surface side of the plurality of first semiconductor regions and having a higher impurity concentration of the second conductivity type than the first semiconductor regions, and a plurality of PIN diode regions provided on the first electrode side of the semiconductor layer and extending in a third direction perpendicular to the first and second directions, and electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. [Diagram 3] 10A to 10C are cross-sectional views illustrating a step of forming a p-type semiconductor region. [Figure 4] 1A to 1C are cross-sectional views for explaining a step of forming a p+ type semiconductor region. [Diagram 5] 11 is a cross-sectional view for explaining a step of forming a metal silicide layer. FIG. [Figure 6] FIG. 1 is a plan view of a semiconductor device according to a comparative example. [Figure 7] 7 is a cross-sectional view taken along the line BB shown in FIG. 6. [Figure 8] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Figure 9] 9 is a cross-sectional view taken along line CC shown in FIG. 8. [Figure 10] FIG. 13 is a plan view of a semiconductor device according to a third embodiment. [Figure 11] 11 is a cross-sectional view taken along the cutting line DD shown in FIG. [Figure 12] FIG. 13 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 13]13 is a cross-sectional view taken along line EE shown in FIG. 12. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0009] (First embodiment) Fig. 1 is a plan view of a semiconductor device according to a first embodiment. Fig. 2 is a cross-sectional view taken along the line AA shown in Fig. 1. The semiconductor device 1 according to this embodiment is an SBD, more specifically, a JBS. The semiconductor device 1 includes an n-type semiconductor layer 10, an anode electrode 20, and a cathode electrode 30. The n-type semiconductor layer 10, the anode electrode 20, and the cathode electrode 30 correspond to a first conductive type semiconductor layer, a first electrode, and a second electrode, respectively.

[0010] In the following description, the arrangement and configuration of each part of the semiconductor device may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction (third direction), Y-direction (second direction), and Z-direction (first direction), respectively. The Z-direction may be described as upward and the opposite direction as downward. In this embodiment, the X-direction and the Y-direction represent in-plane directions parallel to the semiconductor device 1, and the Z-direction represents an out-of-plane direction perpendicular to the semiconductor device 1. Also, p, p + The notation indicates that the p-type impurity concentration increases in this order.

[0011] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the semiconductor region, can also be obtained by, for example, SIMS.

[0012] The n-type semiconductor layer 10 is provided between the anode electrode 20 and the cathode electrode 30. The n-type semiconductor layer 10 is made of, for example, epitaxially grown SiC (silicon carbide). On the front surface side of the n-type semiconductor layer 10 in contact with the anode electrode 20, a plurality of p-type semiconductor regions 40 and a plurality of PIN diode regions 50 are provided as shown in FIG.

[0013] Each p-type semiconductor region 40 corresponds to a first semiconductor region. + A type semiconductor region 41 is provided. + The p-type semiconductor region 41 corresponds to a second semiconductor region having a higher p-type impurity concentration than the p-type semiconductor region 40.

[0014] p-type semiconductor region 40 and p + The type semiconductor region 41 is formed in a stripe shape extending in the Y direction as shown in FIG.

[0015] 1, each PIN diode region 50 extends in the X direction on the surface side of the n-type semiconductor layer 10. The planar shape of each PIN diode region 50 is a rectangle whose length in the X direction is longer than its length in the Y direction. Each PIN diode region 50 includes at least one of the multiple p-type semiconductor regions 40 and multiple p + The semiconductor region 41 is electrically connected to at least one of the first and second semiconductor regions 41 .

[0016] Furthermore, the multiple PIN diode regions 50 are evenly arranged so that the center distances d are equal to each other as shown in Fig. 1. For example, two PIN diode regions 50 arranged apart from each other in the X direction and one PIN diode region 50 arranged offset in the Y direction with respect to the two PIN diode regions 50 are arranged in an equilateral triangle shape.

[0017] Each PIN diode region 50 includes a p-type semiconductor region 51 and a p + The p-type semiconductor region 51 corresponds to a third semiconductor region having the same p-type impurity concentration as the p-type semiconductor region 40. +The p-type semiconductor region 52 has a higher p-type impurity concentration than the p-type semiconductor region 51. + The second semiconductor region corresponds to the fourth semiconductor region which is the same as the first semiconductor region 41 .

[0018] Each p-type semiconductor region 51 has the same thickness as the p-type semiconductor region 40. Furthermore, each p-type semiconductor region 51 contacts at least one of the multiple p-type semiconductor regions 40 within the PIN diode region 50.

[0019] each p + The p-type semiconductor region 52 is provided on the front surface side of the p-type semiconductor region 51. + The p-type semiconductor region 52 is + The thickness of each p + The p-type semiconductor region 52 is a p-type semiconductor region having a plurality of p-type + The semiconductor region 41 is in contact with at least one of the first and second semiconductor regions 41 .

[0020] Each metal silicide layer 53 is p + The metal silicide layer 53 is provided between the p-type semiconductor region 52 and the anode electrode 20. + The contact between the type semiconductor region 52 and the anode electrode 20 is an ohmic contact.

[0021] As shown in FIG. 2, the anode electrode 20 includes an n-type semiconductor layer 10, a p-type semiconductor region 40, + The anode electrode 20 contacts the n-type semiconductor region 41, the p-type semiconductor region 51, and the metal silicide layer 53. The anode electrode 20 is composed of a metal layer. The metal layer may have a single-layer structure or a multilayer structure in which titanium and aluminum are laminated, for example. The anode electrode 20 faces the cathode electrode 30 in the Z direction, with the n-type semiconductor layer 10 sandwiched therebetween.

[0022] The cathode electrode 30 is in contact with the rear surface (bottom surface) of the n-type semiconductor layer 10. The cathode electrode 30 is composed of a metal layer. The structure of this metal layer may be a single layer made of nickel silicide, titanium, nickel, silver, gold, or the like, or may be a layered structure in which a plurality of materials arbitrarily selected from this group of metals are layered.

[0023] Next, an example of a method for manufacturing the semiconductor device 1 configured as above will be described with reference to FIGS.

[0024] First, as shown in Fig. 3, p-type semiconductor region 40 and p-type semiconductor region 51 are simultaneously formed on the surface side of n-type semiconductor layer 10. P-type semiconductor region 40 and p-type semiconductor region 51 can be formed by ion-implanting p-type impurities into the surface of n-type semiconductor layer 10 using, for example, a mask having openings at the locations where each p-type semiconductor region is to be formed. In this case, the p-type impurity is, for example, aluminum. In this case, the p-type impurity concentration is 1 x 10 16 cm -3 The material of the mask is, for example, an oxide film or a resist.

[0025] Next, as shown in FIG. 4, a p + At the same time as forming the p-type semiconductor region 41, a p-type semiconductor region 51 is formed on the surface thereof. + The p-type semiconductor region 52 is formed. + Similarly to the p-type semiconductor regions 40 and 51, the p-type semiconductor regions 41 and 52 each have a p + The p-type semiconductor regions 52 can be formed by ion-implanting p-type impurities into the surface of each p-type semiconductor region using a mask having an opening where the p-type semiconductor region 52 is to be formed. However, the concentration of aluminum implanted at this time is higher than that when the p-type semiconductor regions 40 and 51 are formed, and is, for example, 1×10 20 cm -3 That's about it.

[0026] Next, as shown in Figure 5, +A metal silicide layer 53 is formed on the surface of the p-type semiconductor region 52. This completes the p-in diode region 50. When forming the metal silicide layer 53, first, the silicon film is converted to a p + A metal film made of nickel (Ni), titanium (Ti) or the like is then formed on the surface of the type semiconductor region 52. Then, a metal film made of nickel (Ni), titanium (Ti) or the like is formed by, for example, sputtering. After that, silicon and the metal are reacted by annealing treatment or the like to form a metal silicide layer 53.

[0027] 2, the semiconductor device 1 according to this embodiment is completed by forming an anode electrode 20 and a cathode electrode 30 on both sides of the n-type semiconductor layer 10. Note that the above-mentioned manufacturing process is an example of the manufacturing method of the semiconductor device 1 according to the first embodiment, and is not intended to limit the manufacturing method.

[0028] Now, a comparative example to be compared with this embodiment will be described with reference to FIGS.

[0029] Fig. 6 is a plan view of a semiconductor device according to a comparative example. Fig. 7 is a cross-sectional view taken along line BB shown in Fig. 6. In Fig. 6 and Fig. 7, components similar to those in the semiconductor device 1 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0030] In the semiconductor device 100 according to this comparative example, the multiple PIN diode regions 50 are not evenly arranged as shown in Fig. 6. For example, three PIN diode regions 50 are arranged so that their centers are the vertices of an isosceles triangle. In this case, the center distance d1 between two PIN diode regions 50 spaced apart in the X direction, i.e., the length of the base of the isosceles triangle, differs from the center distance d2 of the PIN diode regions 50, which corresponds to the length of the hypotenuse of the isosceles triangle.

[0031] In the semiconductor device 100 configured as described above, when a voltage is applied that sets the anode electrode 20 at a low potential and the cathode electrode 30 at a high potential, electrons e in the n-type semiconductor layer 10 move toward the cathode electrode 30.

[0032] On the other hand, the holes h in the n-type semiconductor layer 10 move toward the PIN diode region 50. At this time, the PIN diode regions 50 are not evenly arranged in the semiconductor device 100. Therefore, the distance to the PIN diode region 50 becomes long for some of the holes h. As a result, there is a concern that the semiconductor device 100 may be thermally destroyed by heat generated by the movement of the holes h.

[0033] In contrast, in the semiconductor device 1 according to the present embodiment, as shown in FIG. + A p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. In addition, the PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h that are away from the PIN diode region 50 move toward the p-type semiconductor region 40 as shown in FIG. 2. As a result, the moving distance of the holes h is shorter than in the comparative example, and heat is less likely to be generated.

[0034] Therefore, according to this embodiment, it is possible to reduce the risk of thermal destruction.

[0035] Second embodiment Fig. 8 is a plan view of a semiconductor device according to a second embodiment. Fig. 9 is a cross-sectional view taken along line CC shown in Fig. 8. In Fig. 8 and Fig. 9, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0036] 8, in the semiconductor device 2 according to this embodiment, the PIN diode regions 50 are evenly arranged similarly to the first embodiment. That is, three PIN diode regions 50 are arranged in the shape of an equilateral triangle.

[0037] On the other hand, in this embodiment, the shape of the PIN diode region 50 is different from that of the first embodiment. Specifically, the p-type semiconductor region 51 has a first region 51a and a second region 51b. The first region 51a is a region facing the metal silicide layer 53 in the Z direction. The second region 51b is a bridge region extending in the X direction from the outer periphery of the first region 51a. The length (vertical width) in the Y direction of the second region 51b is shorter than the length (vertical width) in the Y direction of the first region 51a.

[0038] In this embodiment, p + The type semiconductor region 52 has a first region 52a and a second region 52b. The first region 52a is a region provided between the first region 51a and the metal silicide layer 53. The second region 52b is a bridge region extending in the X direction from the outer periphery of the first region 52a on the second region 51b. The length (vertical width) in the Y direction of the second region 52b is shorter than the length (vertical width) in the Y direction of the first region 52a.

[0039] Furthermore, in this embodiment, the length (width) in the X direction of the metal silicide layer 53 is shorter than that in the first embodiment. + The p-type semiconductor region 41 + In order to be electrically connected to at least one metal silicide layer 53 via the type semiconductor region 52, the length (horizontal width) of the metal silicide layer 53 in the X direction is longer than the length (vertical width) in the Y direction.

[0040] On the other hand, in this embodiment, as shown in FIG. + A part of the p-type semiconductor region 41 + The p-type semiconductor region 41 is electrically connected to at least one metal silicide layer 53 through the first region 52a, and the remaining p + The type semiconductor region 41 is electrically connected to at least one metal silicide layer 53 via the second section 52b and the first section 52a. Therefore, the lateral width of the metal silicide layer 53 is shortened.

[0041] The semiconductor device 2 according to this embodiment can be manufactured by the same process as the semiconductor device 1 according to the first embodiment described above. However, when forming the p-type semiconductor region 51, p-type impurities (e.g., aluminum) are ion-implanted using a mask that conforms to the shapes of the first region 51a and the second region 51b. + When forming the p-type semiconductor region 52, p-type impurities (for example, aluminum) are ion-implanted using a mask that conforms to the shapes of the first region 52a and the second region 52b.

[0042] According to this embodiment, similar to the first embodiment, + A p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. The PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h that are away from the PIN diode region 50 move toward the p-type semiconductor region 40 as shown in FIG. 9. This shortens the moving distance of the holes h, making it difficult for heat to be generated. This makes it possible to reduce the risk of thermal destruction.

[0043] In this embodiment, the width of the metal silicide layer 53 is shorter than that of the first embodiment. Therefore, the area of ​​the metal silicide layer 53 is smaller than that of the first embodiment, and the effective area functioning as an SBD is increased. This makes it possible to improve the forward voltage characteristics.

[0044] Third embodiment Fig. 10 is a plan view of a semiconductor device according to a third embodiment. Fig. 11 is a cross-sectional view taken along line DD shown in Fig. 10. In Fig. 10 and Fig. 11, components similar to those in the first and second embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0045] In the semiconductor device 3 according to this embodiment, the PIN diode regions 50 are evenly arranged similarly to the second embodiment, as shown in Fig. 10. That is, three PIN diode regions 50 are arranged in the shape of an equilateral triangle.

[0046] In the semiconductor device 3 according to this embodiment, the p + The p-type semiconductor region 52 has a first region 52a and a second region 52b, similar to the second embodiment. The first region 52a is a region provided between the p-type semiconductor region 51 and the metal silicide layer 53.

[0047] Furthermore, in the semiconductor device 3 according to this embodiment, the length (width) of the metal silicide layer 53 in the X direction is shortened, similarly to the second embodiment.

[0048] On the other hand, in the semiconductor device 3 according to this embodiment, the second region 52b is provided inside the n-type semiconductor layer 10 as shown in FIG. + The second region 52b is electrically connected to the n-type semiconductor region 41 at a lower portion of each side surface. In addition, since the second region 52b is provided inside the n-type semiconductor layer 10, the n-type semiconductor layer 10 is interposed between the second region 52b and the anode electrode 20.

[0049] The semiconductor device 3 according to this embodiment can be manufactured in the same process as the semiconductor device 1 according to the first embodiment. + When forming the n-type semiconductor region 52, p-type impurities (e.g., aluminum) are ion-implanted into the first region 52a and the second region 52b at different times using different masks. When forming the first region 52a, the p-type impurities are ion-implanted into the surface of the n-type semiconductor layer 10 (p-type semiconductor region 51). On the other hand, when forming the second region 52b, the p-type impurities are ion-implanted into the interior of the n-type semiconductor layer 10.

[0050] According to this embodiment, similarly to the second embodiment, +A p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. The PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h that are away from the PIN diode region 50 move toward the p-type semiconductor region 40 as shown in FIG. 11. This shortens the moving distance of the holes h, making it difficult for heat to be generated. This makes it possible to reduce the risk of thermal destruction.

[0051] In this embodiment, p + Since the second region 52b of the n-type semiconductor region 52 is provided inside the n-type semiconductor layer 10, the n-type semiconductor layer 10 is interposed between the second region 52b and the anode electrode 20. Therefore, the area of ​​the n-type semiconductor layer 10 is smaller than that of the second embodiment, and the effective area functioning as an SBD is further increased. This makes it possible to further improve the forward voltage characteristics.

[0052] (Fourth embodiment) Fig. 12 is a plan view of the semiconductor device according to the fourth embodiment. Fig. 13 is a cross-sectional view taken along the line EE shown in Fig. 12. In Fig. 12 and Fig. 13, the same components as those in the first and second embodiments described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0053] In the semiconductor device 4 according to this embodiment, the PIN diode regions 50 are evenly arranged similarly to the second embodiment, as shown in Fig. 12. That is, three PIN diode regions 50 are arranged in the shape of an equilateral triangle.

[0054] In the semiconductor device 4 according to this embodiment, similarly to the second embodiment, + The type semiconductor region 52 has a first region 52a and a second region 52b. In addition, the length (horizontal width) of the metal silicide layer 53 in the X direction is shortened.

[0055] On the other hand, in the semiconductor device 4 according to this embodiment, the p-type semiconductor region 51 further includes a third region 51c in addition to the first region 51a and the second region 51b. The third region 51c is a region that protrudes from the bottom surface of the first region 51a toward the cathode electrode 30 directly below the metal silicide layer 53.

[0056] The semiconductor device 4 according to this embodiment can be manufactured by the same process as the semiconductor device 1 according to the first embodiment described above. However, when forming the p-type semiconductor region 51, in order to form the third region 51c, the p-type impurity is ion-implanted to a position deeper from the surface of the n-type semiconductor layer 10 than the first region 51a.

[0057] According to this embodiment, similarly to the second embodiment, + A p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. The PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h that are away from the PIN diode region 50 move toward the p-type semiconductor region 40 as shown in FIG. 13. This shortens the moving distance of the holes h, making it difficult for heat to be generated. This makes it possible to reduce the risk of thermal destruction.

[0058] In this embodiment, the third region 51c is provided at a deep position directly below the metal silicide layer 53 in the PIN diode region 50. Therefore, an electric field is concentrated in the third region 51c, and the voltage can be locally broken down directly below the metal silicide layer 53. As a result, the holes h can be efficiently discharged from the n-type semiconductor layer 10.

[0059] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0060] 1, 2, 3, 4: Semiconductor device 10: n-type semiconductor layer 20: Anode electrode (first electrode) 30: Cathode electrode (second electrode) 40: p-type semiconductor region (first semiconductor region) 41:p + Type semiconductor region (second semiconductor region) 50: PIN diode area 51: p-type semiconductor region (third semiconductor region) 52:p + Type semiconductor region (fourth semiconductor region) 52a: 1st area 52b:Second area 53: Metal silicide layer

Claims

1. A first electrode; a second electrode facing the first electrode in a first direction; a semiconductor layer of a first conductivity type provided between the first electrode and the second electrode; a plurality of first semiconductor regions of a second conductivity type provided on the first electrode side of the semiconductor layer and extending in a second direction perpendicular to the first direction; a plurality of second semiconductor regions provided on a surface side of the plurality of first semiconductor regions and having a second conductivity type impurity concentration higher than that of the first semiconductor regions; a plurality of PIN diode regions provided on the first electrode side in the semiconductor layer, extending in a third direction perpendicular to the first direction and the second direction, and electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions; A semiconductor device comprising:

2. Each of the plurality of PIN diode regions is a third semiconductor region of a second conductivity type in contact with at least one of the first semiconductor regions; a fourth semiconductor region provided on a surface side of the third semiconductor region, the fourth semiconductor region having a higher impurity concentration of the second conductivity type than the third semiconductor region; a metal silicide layer provided between the fourth semiconductor region and the first electrode; The semiconductor device according to claim 1 ,

3. 3. The semiconductor device according to claim 1, wherein said plurality of PIN diode regions are evenly arranged so that center distances between the regions are equal to each other.

4. The semiconductor device according to claim 3 , wherein three of said plurality of PIN diode regions are arranged in an equilateral triangle shape.

5. 3 . The semiconductor device according to claim 1 , wherein a plan view of said plurality of PIN diode regions is a rectangle whose length in said third direction is longer than its length in said second direction.

6. The fourth semiconductor region is a first area provided between the metal silicide layer and the third semiconductor region; a second region extending in the third direction from an outer periphery of the first region; The semiconductor device according to claim 2 ,

7. a part of the second semiconductor regions is electrically connected to the metal silicide layer via the first area; 7. The semiconductor device according to claim 6, wherein the remaining regions of said plurality of second semiconductor regions excluding said certain regions are electrically connected to said metal silicide layer via said second area and said first area.

8. The semiconductor device according to claim 6 , wherein the second area is provided inside the semiconductor layer.

9. 3. The semiconductor device according to claim 2, wherein said third semiconductor region has an area directly below said metal silicide layer that protrudes towards said second electrode.

10. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a Schottky barrier diode.

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