Semiconductor device

Abstract

To provide a semiconductor device capable of improving electrical characteristics.SOLUTION: A semiconductor device according to the embodiment includes a first nitride semiconductor layer provided on a substrate, a plurality of mask layers made of an insulating material provided on the first nitride semiconductor layer, a second nitride semiconductor layer provided on the plurality of mask layers, a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a band gap larger than that of the second nitride semiconductor layer, and first and second electrodes provided on the third nitride semiconductor layer and arranged spaced apart from each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device using a nitride semiconductor having a heterojunction interface, when a laminated structure of a nitride semiconductor layer is formed, threading dislocations that reach the surface of the nitride semiconductor layer from the heterojunction interface occur due to differences in constituent elements and lattice constants. If the direction in which the nitride semiconductor layer is formed is the Y direction and the direction perpendicular to the Y direction is the X direction, it is known that in a semiconductor device in which a current flows in the X direction, the threading dislocations in the region through which the current flows act as resistance.

[0003] FETs using nitride semiconductors such as gallium nitride (GaN) are known. In an FET, when a current flows between the source electrode and the drain electrode, if the dislocation density in the current-carrying region is high, the resistance increases and the efficiency of the FET deteriorates. For this reason, in FETs using two-dimensional electron gas, technology has been developed to reduce the dislocation density that causes resistance in order to increase the electron mobility and improve efficiency. However, when the dislocation density is reduced using conventional technology, the dislocation density remains the same over the entire surface of the wafer. Therefore, the electron mobility of the two-dimensional electron gas layer also remains at a constant value. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-261642 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device capable of improving electrical characteristics. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes a first nitride semiconductor layer provided on a substrate, a plurality of mask layers formed of an insulating material provided on the first nitride semiconductor layer, a second nitride semiconductor layer provided on the plurality of mask layers, a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a band gap larger than that of the second nitride semiconductor layer, and first and second electrodes provided on the third nitride semiconductor layer and spaced apart from each other. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a plan view illustrating the evaluation electrode 17. As shown in FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view illustrating dislocations formed in a nitride semiconductor layer included in a semiconductor device. [Figure 4] FIG. 4 is a graph illustrating the sheet resistance of a semiconductor device. [Diagram 5] FIG. 5 is a cross-sectional view of the semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a graph illustrating the resistance of the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device according to the third embodiment. [Figure 8] FIG. 8 is a graph showing the operating characteristics of a HEMT. [Figure 9] FIG. 9 is a cross-sectional view of a semiconductor device according to a first example of the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to a second example of the fourth embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to a third example of the fourth embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to a fourth example of the fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a first example of the fifth embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to a second example of the fifth embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to a third example of the fifth embodiment. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device according to a fourth example of the fifth embodiment. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the embodiments will be described with reference to the drawings. Some of the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention is not specified by the shape, structure, arrangement, etc. of the components. Each functional block can be realized as either hardware or software, or a combination of both. It is not essential that each functional block is distinguished as in the following example. For example, some functions may be executed by a functional block other than the functional block shown in the example. Furthermore, the functional block shown in the example may be divided into smaller functional sub-blocks. In the following description, elements having the same functions and configurations are given the same reference numerals, and duplicated descriptions are omitted.

[0009] [1] First embodiment [1-1] Configuration of semiconductor device 1 The semiconductor device 1 is a resistor element using a nitride semiconductor. Fig. 1 is a cross-sectional view of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a substrate 10, a first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13, a third buffer layer 14, a channel layer 15, a barrier layer 16, a plurality of electrodes 17, a first passivation film 18, and a second passivation film 19.

[0010] The substrate 10 is composed of a semiconductor substrate. As the substrate 10, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), gallium arsenide (GaAs), or sapphire (Al2O3), etc. are used. In this embodiment, the substrate 10 is composed of a substrate made of silicon carbide (SiC substrate).

[0011] A first buffer layer 11 is provided on the substrate 10. The first buffer layer 11 has a function of relaxing the strain caused by the difference in lattice constants and controlling the crystallinity. The first buffer layer 11 is composed of a nitride semiconductor layer. For example, aluminum gallium nitride Al W Ga 1-W N (0 < W ≦ 1). In this embodiment, the first buffer layer 11 is composed of aluminum nitride (AlN). The first buffer layer 11 may be composed of a nitride semiconductor layer containing indium (In), gallium (Ga), aluminum (Al), and nitrogen (N).

[0012] A second buffer layer 12 is provided on the first buffer layer 11. The second buffer layer 12 has a function of relaxing the strain caused by the difference in lattice constants and controlling the crystallinity. The second buffer layer 12 is composed of a nitride semiconductor layer. For example, aluminum gallium nitride (Al X Ga 1-X N (0 ≦ X < 1)). In this embodiment, the second buffer layer 12 is composed of gallium nitride (GaN). The second buffer layer 12 may be composed of a nitride semiconductor layer containing indium (In), gallium (Ga), aluminum (Al), and nitrogen (N).

[0013] A plurality of mask layers 13 are provided on the second buffer layer 12. The plurality of mask layers 13 are composed of an insulating material, for example, silicon oxide (SiO2). The plurality of mask layers 13 have a function of controlling the dislocation density of the upper layer thereof. The plurality of mask layers 13 are arranged in the region between two electrodes 17 described later. Note that the plurality of mask layers 13 may be further provided outside the region between the two electrodes 17.

[0014] A third buffer layer 14 is provided on the second buffer layer 12 and the plurality of mask layers 13. The third buffer layer 14 has a function of planarizing the upper surface of the stacked body. The third buffer layer 14 is made of a nitride semiconductor layer, for example, aluminum gallium nitride (Al X Ga 1-X N (0≦X<1)). In this embodiment, the third buffer layer 14 is made of gallium nitride (GaN). The third buffer layer 14 may be made of a nitride semiconductor layer containing indium (In), gallium (Ga), aluminum (Al), and nitrogen (N).

[0015] A channel layer 15 is provided on the third buffer layer 14. The channel layer 15 is made of a nitride semiconductor layer, and is made of a nitride semiconductor layer having good crystallinity (high quality). The channel layer 15 is made of, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0≦X<1)). Undoped means that impurities are not intentionally doped. For example, the amount of impurities that enter during the manufacturing process falls into the undoped category. In this specification, undoped means that the impurity concentration is 2×10 16 cm -3 This means that the following is true. In this embodiment, the channel layer 15 is made of undoped gallium nitride (GaN). The channel layer 15 may be made of a nitride semiconductor layer containing indium (In), gallium (Ga), aluminum (Al), and nitrogen (N).

[0016] A barrier layer 16 is provided on the channel layer 15. The band gap of the barrier layer 16 is larger than the band gap of the channel layer 15. The lattice constant of the barrier layer 16 is smaller than the lattice constant of the channel layer 15. The barrier layer 16 is, for example, made of undoped aluminum gallium nitride (Al Y Ga 1-YIt is composed of N(0 < Y ≤ 1, X < Y)). In this embodiment, the barrier layer 16 is composed of undoped aluminum gallium nitride (AlGaN). The barrier layer 16 may be composed of a nitride semiconductor layer containing indium (In), gallium (Ga), aluminum (Al), and nitrogen (N).

[0017] A two-dimensional electron gas layer 2DEG is provided at the interface between the channel layer 15 and the barrier layer 16. In the hetero-junction structure of the channel layer 15 and the barrier layer 16, since the lattice constant of the barrier layer 16 is smaller than that of the channel layer 15, strain occurs in the barrier layer 16. Due to the piezo-electric effect caused by this strain, piezo-polarization occurs in the barrier layer 16, and a two-dimensional electron gas (2DEG: two-dimensional electron gas) is generated near the interface between the channel layer 15 and the barrier layer 16. The two-dimensional electron gas layer 2DEG serves as a channel through which current flows.

[0018] A plurality of electrodes 17 are provided on the barrier layer 16. In FIG. 1, three electrodes 17 are shown as an example. The electrode 17 is in ohmic contact with the barrier layer 16. The electrode 17 is composed of, for example, a laminated structure of aluminum (Al) / titanium (Ti). In this embodiment, the electrode 17 is composed of a laminated structure of aluminum (Al) / titanium (Ti) / platinum (Pt) / gold (Au).

[0019] A first passivation film 18 is provided on the barrier layer 16. The first passivation film 18 is composed of, for example, silicon nitride (SiN).

[0020] A second passivation film 19 is provided on the first passivation film 18. The second passivation film 19 is composed of, for example, silicon nitride (SiN). The second passivation film 19 is also provided on the electrode 17, and a portion for contacting the evaluation probe is opened.

[0021] 2 is a plan view illustrating an electrode 17 for evaluation. The rectangular size of the electrode 17 is 50 μm×100 μm. In this embodiment, six types of inter-electrode distances are formed: 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, and 300 μm. By measuring the resistance between the electrodes 17, it can be confirmed that the semiconductor device 1 functions as a resistive element.

[0022] In the semiconductor device 1 configured as described above, when the laminated structure of the nitride semiconductor layers is formed, threading dislocations that reach the surface of the nitride semiconductor layers from the heterojunction interface are generated due to differences in constituent elements and lattice constants.

[0023] 3 is a schematic cross-sectional view illustrating dislocations formed in a nitride semiconductor layer included in the semiconductor device 1. A plurality of dislocations 20 are formed in the nitride semiconductor layer. The plurality of dislocations 20 are formed so as to extend in the stacking direction (thickness direction) of the nitride semiconductor layer. The plurality of mask layers 13 function to control the dislocation density.

[0024] In the region where the mask layer 13 is formed (region in the stacking direction), the dislocation density is relatively low. In the region where the mask layer 13 is not formed (region in the stacking direction), the dislocation density is relatively high. The mask layer 13 can reduce dislocations. In addition, the dislocation density can be controlled by changing the width and interval of the mask layer 13.

[0025] (Example of manufacturing method) Next, an example of a method for manufacturing the semiconductor device 1 will be described.

[0026] First, prepare a SiC substrate 10. An AlN layer 11 having a thickness of 10 nm is formed on the SiC substrate 10 at about 1100° C. by metal organic chemical vapor deposition (MOCVD) method, and a first GaN layer 12 having a thickness of 50 nm is formed on the AlN layer 11 at about 1000° C.

[0027] Next, the substrate is removed from the MOCVD furnace, and a 50 nm SiO2 layer is formed on the first GaN layer 12 by plasma CVD. Next, a resist layer is applied onto the SiO2 layer, and the resist layer is patterned by photolithography. Next, the SiO2 layer is etched using a hydrofluoric acid solution until the GaN layer 12 is exposed. This forms multiple SiO2 layers 13 having the desired shape. Then, the resist layer is peeled off.

[0028] Next, the substrate is returned to the MOCVD furnace, and a second GaN layer 14 is formed by MOCVD under film formation conditions for bending dislocations laterally at about 950°C to control dislocation density. Next, a third GaN layer 15 is formed by MOCVD at about 1000°C to flatten the surface of the substrate. Next, an AlGaN layer 16 with an Al composition of 0.25 is formed to a thickness of 25 nm on the third GaN layer 15 at about 1050°C.

[0029] Next, a first layer of SiN film 18 is formed as a passivation film to a thickness of 100 nm on the AlGaN layer 16 by plasma CVD. Next, a resist layer is applied onto the first layer of SiN film 18, and an opening is formed in the resist layer by photolithography in an area where the electrode 17 is to be formed. Next, the first layer of SiN film 18 is etched by RIE (Reactive Ion Etching) using CF4 gas, to expose the AlGaN layer 16.

[0030] Next, a laminated structure of Al: 300 nm / Ti: 20 nm / Pt: 50 nm / Au: 1000 nm is evaporated onto the AlGaN layer 16 exposed from the first SiN film 18 and onto the resist layer as the electrodes 17. The resist layer is then dissolved using an organic solvent such as acetone to remove the resist layer and the electrode material attached to the resist layer. As a result, a plurality of electrodes 17 are formed on the AlGaN layer 16. Next, the substrate is heated to about 600° C. in an inert gas atmosphere (e.g., a nitrogen atmosphere) to form ohmic contacts between the electrodes 17 and the AlGaN layer 16.

[0031] Next, by plasma CVD, a second-layer SiN film 19 is formed to a thickness of 100 nm as a passivation film on the electrode 17 and the first-layer SiN film 18. Next, a resist layer is applied onto the second-layer SiN film 19, and the resist layer is patterned by photolithography so as to expose an area where an evaluation probe will come into contact.

[0032] Next, the second-layer SiN film 19 is etched by RIE using CF4 gas to expose a part of the electrode 17. After that, the resist layer is peeled off. In this manner, the semiconductor device 1 capable of evaluating electrical characteristics using the electrode 17 is manufactured.

[0033] [1-2] Evaluation results Next, evaluation of the dislocation density and the sheet resistance of the nitride semiconductor layer will be described.

[0034] In order to evaluate the dislocation density of the nitride semiconductor layer, a number of semiconductor devices were manufactured with different mask patterns (width and spacing of the mask layer 13) of the mask layer 13. 6 / cm 2 About 5×10 7 / cm 2 About 5×10 8 / cm 2 Three types of mask layers 13 were formed so as to achieve approximately the same thickness.

[0035] A plurality of semiconductor devices having three types of mask patterns are formed on the same wafer. In order to calculate the dislocation density, the nitride semiconductor layer formed on the SiC substrate 10 up to the AlGaN layer 16 is dipped in a tetramethylammonium hydroxide (TMAH) solution to form pits due to threading dislocations. The number of pits is then observed to calculate the threading dislocations per unit area. As a result, the dislocation densities in the plurality of semiconductor devices corresponding to the three types of mask patterns were found to be 5×10 6 / cm 2 About 5×10 7 / cm 2 About 5×10 8 / cm 2 It was confirmed that the extent of this was

[0036] Next, electrodes were formed on the nitride semiconductor layer, and the sheet resistance between the electrodes was evaluated. The sheet resistance was evaluated using the transmission line method (TLM). The sheet resistance between the electrodes was measured by TLM. The sheet resistance was also measured for multiple distances between the electrodes.

[0037] 4 is a graph illustrating the sheet resistance of the semiconductor device 1. The horizontal axis of FIG. 4 is the dislocation density ( / cm 2 ), and the vertical axis represents the sheet resistance (arbitrary unit: AU).

[0038] As shown in Figure 4, the sheet resistance of the two-dimensional electron gas layer increases with increasing dislocation density. It can be confirmed that the resistance of the two-dimensional electron gas layer can be controlled by controlling the dislocation density. In addition, when the dislocation density is 5×10 6 / cm 2 About 5×10 7 / cm 2 About 5×10 8 / cm 2 It can be seen that the sheet resistance differs in degree.

[0039] [1-3] Effects of the first embodiment According to the first embodiment, the resistance of the two-dimensional electron gas layer 2DEG can be changed by using the mask layer 13. This makes it possible to use the semiconductor device 1 including the nitride semiconductor layer as a resistance element.

[0040] Moreover, the dislocation density of the nitride semiconductor layer can be controlled by changing the pattern (the width and interval of the mask layer 13) of the mask layer 13. Furthermore, the resistance of the resistor element can be changed by controlling the dislocation density of the nitride semiconductor layer.

[0041] Moreover, by changing the length between the electrodes, the resistance of the resistive element can be changed.

[0042] Moreover, a plurality of resistive elements can be formed in the semiconductor device 1.

[0043] Moreover, it is possible to realize a semiconductor device 1 capable of improving electrical characteristics.

[0044] [2] Second embodiment The second embodiment is another configuration example of a semiconductor device including a resistance element.

[0045] [2-1] Configuration of semiconductor device 1 The semiconductor device 1 is a resistor element using a nitride semiconductor. Fig. 5 is a cross-sectional view of the semiconductor device 1 according to the second embodiment. The semiconductor device 1 includes a first resistor element 2-1 and a second resistor element 2-2.

[0046] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13 (13-1, 13-2), a third buffer layer 14, a channel layer 15, a barrier layer 16, a first passivation film 18, and a second passivation film 19 are laminated in this order on a substrate 10. The configurations of the first buffer layer 11, the second buffer layer 12, the plurality of mask layers 13 (13-1, 13-2), the third buffer layer 14, the channel layer 15, the barrier layer 16, the first passivation film 18, and the second passivation film 19 are the same as those in the first embodiment.

[0047] Electrodes 17-1 to 17-4 are provided on the barrier layer 16. The first resistor element 2-1 includes electrodes 17-1 and 17-2. The second resistor element 2-2 includes electrodes 17-3 and 17-4. The resistor element 2-1 is formed by the resistance of the nitride semiconductor layer between the electrodes 17-1 and 17-2. The resistance of the resistor element 2-2 is formed by the resistance of the nitride semiconductor layer between the electrodes 17-3 and 17-4.

[0048] An element isolation region 21 is provided between the first resistor element 2-1 and the second resistor element 2-2. The element isolation region 21 is made of an insulating layer. The element isolation region 21 extends from the upper surface of the barrier layer 16 to near the center of the channel layer 15. The element isolation region 21 partially insulates the barrier layer 16 and the two-dimensional electron gas layer 2DEG, and also partially insulates the upper part of the channel layer 15. In this embodiment, the element isolation region 21 is made of the same material as the first passivation film 18 and the second passivation film 19. The first resistor element 2-1 and the second resistor element 2-2 are electrically insulated by the element isolation region 21.

[0049] The element isolation region 21 is formed by depositing the barrier layer 16, and then etching the barrier layer 16 and the channel layer 15 by RIE using chlorine, and then depositing an insulating layer in the opening formed by the etching.

[0050] A plurality of mask layers 13-1 are provided in the region of the first resistor element 2-1. The plurality of mask layers 13-1 are disposed in the region between the electrodes 17-1 and 17-2. The width of each of the plurality of mask layers 13-1 is the same, and the distance between each of the mask layers 13-1 is also the same. The plurality of mask layers 13-1 may be further provided outside the region between the electrodes 17-1 and 17-2.

[0051] A plurality of mask layers 13-2 are provided in the region of the second resistor element 2-2. The plurality of mask layers 13-2 are disposed in the region between the electrodes 17-3 and 17-4. The width of each of the plurality of mask layers 13-2 is the same, and the distance between each of the mask layers 13-2 is also the same. The plurality of mask layers 13-2 may be further provided outside the region between the electrodes 17-3 and 17-4.

[0052] The width and spacing of each of the multiple mask layers 13-1 are different from the width and spacing of each of the multiple mask layers 13-2. In this embodiment, for example, the width of the mask layer 13-1 is greater than the width of the mask layer 13-2. The spacing of the mask layer 13-1 is smaller than the spacing of the mask layer 13-2.

[0053] In this embodiment, the dislocation density in the first resistor element 2-1 is 5×10 6 / cm 2 The mask layer 13-1 is patterned so that the dislocation density in the second resistor element 2-2 is about 5×10 8 / cm 2 The mask layer 13-2 is patterned so as to have a thickness of about 100 nm.

[0054] [2-2] Evaluation results Dislocation density is 5×10 6 / cm 2 The resistor element 2-1 is formed so that the dislocation density is about 5×10 8 / cm 2 The resistance between the resistor element 2-1 and the resistor element 2-2 was evaluated. The length of the resistive wiring (that is, the distance between the electrodes) was set to 200 μm in each of the resistor elements 2-1 and 2-2.

[0055] 6 is a graph illustrating the resistance of the semiconductor device 1 according to the second embodiment. The horizontal axis of FIG. 6 represents the dislocation density ( / cm 2 ) and the vertical axis represents resistance (arbitrary unit: AU).

[0056] As shown in Figure 6, the resistance of the resistor element increased by about two times as the dislocation density increased. This result confirms that it is possible to form resistor elements with different resistances by controlling the dislocation density even with the same length of resistive wiring.

[0057] [2-3] Effects of the second embodiment According to the second embodiment, two electrically insulated resistance elements can be formed in the semiconductor device 1.

[0058] Moreover, the resistance of the two resistor elements can be changed by controlling the dislocation density of the nitride semiconductor layer.

[0059] [3] Third embodiment The third embodiment is an example of the configuration of a field effect transistor (FET).

[0060] [3-1] Configuration of semiconductor device 1 The semiconductor device 1 is a FET, and more specifically, a high electron mobility transistor (HEMT).

[0061] 7 is a cross-sectional view of the semiconductor device 1 according to the third embodiment. The semiconductor device 1 includes a first HEMT 3-1 and a second HEMT 3-2.

[0062] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13 (13-1, 13-2), a third buffer layer 14, a channel layer 15, a barrier layer 16, a first passivation film 18, and a second passivation film 19 are laminated in this order on a substrate 10. The configurations of the first buffer layer 11, the second buffer layer 12, the plurality of mask layers 13 (13-1, 13-2), the third buffer layer 14, the channel layer 15, the barrier layer 16, the first passivation film 18, and the second passivation film 19 are the same as those in the first embodiment.

[0063] Each of the first HEMT 3-1 and the second HEMT 3-2 includes a gate electrode 22, a source electrode 23, and a drain electrode 24. On the barrier layer 16, the source electrode 23 and the drain electrode 24 are provided at a distance from each other, and the gate electrode 22 is provided between the source electrode 23 and the drain electrode 24 at a distance from each other.

[0064] The source electrode 23 and the drain electrode 24 are in ohmic contact with the barrier layer 16. The source electrode 23 and the drain electrode 24 are configured, for example, with a laminated structure of aluminum (Al) / titanium (Ti). In this embodiment, the source electrode 23 and the drain electrode 24 are configured with a laminated structure of aluminum (Al) / titanium (Ti) / platinum (Pt) / gold (Au).

[0065] The gate electrode 22 is in a Schottky junction with the barrier layer 16. The gate electrode 22 is made of, for example, nickel (Ni). In this embodiment, the gate electrode 22 is made of a nickel (Ni) / gold (Au) laminated structure.

[0066] An element isolation region 21 is provided between the first HEMT 3-1 and the second HEMT 3-2.

[0067] A plurality of mask layers 13-1 are provided in the region of the first HEMT 3-1. The plurality of mask layers 13-1 are disposed in the region between the source electrode 23 and the drain electrode 24. The width of each of the plurality of mask layers 13-1 is the same, and the distances between each of the mask layers 13-1 are also the same. The plurality of mask layers 13-1 may be further provided outside the region between the source electrode 23 and the drain electrode 24.

[0068] A plurality of mask layers 13-2 are provided in the region of the second HEMT 3-2. The plurality of mask layers 13-2 are disposed in the region between the source electrode 23 and the drain electrode 24. The width of each of the plurality of mask layers 13-2 is the same, and the distances between the mask layers 13-2 are also the same. The plurality of mask layers 13-2 may be further provided outside the region between the source electrode 23 and the drain electrode 24.

[0069] The width and spacing of each of the multiple mask layers 13-1 are different from the width and spacing of each of the multiple mask layers 13-2. In this embodiment, for example, the width of the mask layer 13-1 is greater than the width of the mask layer 13-2. The spacing of the mask layer 13-1 is smaller than the spacing of the mask layer 13-2.

[0070] In this embodiment, the dislocation density in the first HEMT 3-1 is 5×10 6 / cm 2 The mask layer 13-1 is patterned so that the dislocation density in the second HEMT 3-2 is about 5×10 8 / cm 2 The mask layer 13-2 is patterned so as to have a thickness of about 100 nm.

[0071] (Example of manufacturing method) Next, an example of a method for manufacturing the semiconductor device 1 will be described.

[0072] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13 (13-1, 13-2), a third buffer layer 14, a channel layer 15, and a barrier layer 16 are formed in this order on a substrate 10. This manufacturing process is the same as in the first embodiment.

[0073] Next, in order to electrically insulate the first HEMT 3-1 and the second HEMT 3-2, an element isolation region 21 is formed. The manufacturing process of the element isolation region 21 is the same as that of the second embodiment.

[0074] Next, a first-layer SiN film 18 is formed as a passivation film to a thickness of 100 nm on the AlGaN layer 16 by plasma CVD. Next, a resist layer is applied onto the first-layer SiN film 18, and openings are formed in the resist layer by photolithography in regions for forming the source electrode 23 and the drain electrode 24. Next, the first-layer SiN film 18 is etched by RIE (Reactive Ion Etching) using CF4 gas to expose the AlGaN layer 16.

[0075] Next, a laminated structure of Al: 300 nm / Ti: 20 nm / Pt: 50 nm / Au: 1000 nm is evaporated onto the AlGaN layer 16 exposed from the first SiN film 18 and onto the resist layer as the source electrode 23 and the drain electrode 24. Next, the resist layer is dissolved using an organic solvent such as acetone to peel off the resist layer and the electrode material attached to the resist layer. As a result, the source electrode 23 and the drain electrode 24 are formed on the AlGaN layer 16. Next, the substrate to be processed is heated to about 600° C. in an inert gas atmosphere (for example, a nitrogen atmosphere) to form ohmic contacts between the source electrode 23 and the drain electrode 24 and the AlGaN layer 16.

[0076] Next, a resist layer is applied to the entire surface of the substrate to be processed, and an opening is formed in the resist layer by photolithography in a region for forming the gate electrode 22. Next, the first SiN film 18 is etched by RIE using CF4 gas to expose the AlGaN layer 16.

[0077] A laminated structure of Ni: 200 nm / Au: 1000 nm is evaporated onto the AlGaN layer 16 exposed from the first SiN film 18 and onto the resist layer as the gate electrode 22. The resist layer is then dissolved using an organic solvent such as acetone to remove the resist layer and the electrode material attached to the resist layer. As a result, the gate electrode 22 having a Schottky junction is formed on the AlGaN layer 16.

[0078] Next, by plasma CVD, a second-layer SiN film 19 is formed to a thickness of 100 nm as a passivation film on the electrodes (gate electrode 22, source electrode 23, and drain electrode 24) and on the first-layer SiN film 18. Next, a resist layer is applied onto the second-layer SiN film 19, and the resist layer is patterned by photolithography so as to expose an area where an evaluation probe will come into contact.

[0079] Next, the second-layer SiN film 19 is etched by RIE using CF4 gas to expose a part of the electrode. Then, the resist layer is peeled off. In this manner, the semiconductor device 1 capable of evaluating electrical characteristics using the electrode is manufactured.

[0080] [3-2] Evaluation results The dislocation density is 5×10 6 / cm 2 degree, and 5×10 8 / cm 2 A plurality of mask layers 13-1 and a plurality of mask layers 13-2 were formed so that the dislocation density was about 5×10 6 / cm 2 degree, and 5×10 8 / cm 2The first HEMT 3-1 and the second HEMT 3-2 were formed so that the dislocation density was about 1. The method of calculating the dislocation density is the same as in the first embodiment.

[0081] In each HEMT, a change in current Ids between the drain electrode 24 and the source electrode 23 with respect to a voltage Vds between the drain electrode 24 and the source electrode 23 for each gate voltage Vg is measured.

[0082] FIG. 8 is a graph showing the operating characteristics of a HEMT. The horizontal axis of FIG. 8 represents the voltage Vds (V), and the vertical axis represents the current Ids (A). The solid line in FIG. 8 represents the dislocation density of 5×10 6 / cm 2 The dashed line represents the operating characteristics of the first HEMT 3-1 having a dislocation density of 5×10 8 / cm 2 4 shows the operating characteristics of the second HEMT 3-2 having the gate voltage Vg of 0 (V), 1 (V), 2 (V), and 3 (V).

[0083] As can be seen from Figure 8, the current Igs at each gate voltage Vg is larger for the HEMT with a smaller dislocation density. This is believed to be because the reduced dislocation density improves the electron mobility in the two-dimensional electron gas layer.

[0084] [3-3] Effects of the third embodiment According to the third embodiment, two electrically insulated HEMTs can be formed in the semiconductor device 1.

[0085] In addition, the operating characteristics of the two HEMTs can be changed by controlling the dislocation density in the nitride semiconductor layer.

[0086] Moreover, it is possible to realize a semiconductor device 1 capable of improving electrical characteristics.

[0087] [4] Fourth embodiment The fourth embodiment is another configuration example of the resistance element. The configurations of first to fourth examples of the fourth embodiment will be described below.

[0088] 9 is a cross-sectional view of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes one resistance element.

[0089] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13, a third buffer layer 14, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated in this order on a substrate 10. The configurations of the first buffer layer 11, the second buffer layer 12, the plurality of mask layers 13, the third buffer layer 14, the channel layer 15, the barrier layer 16, and the passivation film 18 are the same as those in the first embodiment.

[0090] Electrodes 17-1 and 17-2 are provided on the barrier layer 16. The electrodes 17-1 and 17-2 are used as electrodes of a resistive element. A plurality of mask layers 13 are disposed in a region between the electrodes 17-1 and 17-2. The plurality of mask layers 13 may be further provided outside the region between the electrodes 17-1 and 17-2.

[0091] In order to thin the semiconductor device 1, the thickness of the substrate 10 may be set to 100 μm or less. In this embodiment, after all layers are formed on the substrate 10, the substrate 10 is polished from the bottom surface to make it thinner.

[0092] 10 is a cross-sectional view of a semiconductor device 1 according to Example 2. A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated on a substrate 10 in this order.

[0093] Compared to the first embodiment, the third buffer layer 14 is omitted. In other words, the third buffer layer 14 is integrally formed with the channel layer 15. As in the second embodiment, the channel layer 15 may be disposed on the mask layer 13. According to the second embodiment, the number of manufacturing steps can be reduced compared to the first embodiment.

[0094] 11 is a cross-sectional view of a semiconductor device 1 according to a third embodiment. In the third embodiment, a buffer layer 12 is disposed at the bottom layer. On the buffer layer 12, a plurality of mask layers 13, a buffer layer 14, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated in this order.

[0095] In the third embodiment, after manufacturing the semiconductor device 1 of the first embodiment, the substrate 10 and the first buffer layer 11 are removed, and further the second buffer layer 12 is partially removed so as to become thinner. According to the third embodiment, the semiconductor device 1 can be configured to be thin. The mask layer 13 may also be removed. In this embodiment, a buffer layer 14 is disposed as the bottom layer.

[0096] 12 is a cross-sectional view of a semiconductor device 1 according to a fourth embodiment. In the fourth embodiment, one mask layer 13 is provided in the region between electrodes 17-1 and 17-2. The position at which mask layer 13 is disposed is the same as in the first embodiment. According to the fourth embodiment, the dislocation density can be further reduced.

[0097] [5] Fifth embodiment The fifth embodiment is another configuration example of the HEMT. The configurations of first to fourth examples of the fifth embodiment will be described below.

[0098] 13 is a cross-sectional view of a semiconductor device 1 according to Example 1. The semiconductor device 1 includes one HEMT.

[0099] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13, a third buffer layer 14, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated in this order on a substrate 10. The configurations of the first buffer layer 11, the second buffer layer 12, the plurality of mask layers 13, the third buffer layer 14, the channel layer 15, the barrier layer 16, and the passivation film 18 are the same as those in the first embodiment.

[0100] A source electrode 23 and a drain electrode 24 are disposed spaced apart from each other, and a gate electrode 22 is disposed spaced apart from each other between the source electrode 23 and the drain electrode 24. A plurality of mask layers 13 are disposed in a region between the source electrode 23 and the drain electrode 24. A plurality of mask layers 13 may be further disposed outside the region between the source electrode 23 and the drain electrode 24.

[0101] In order to thin the semiconductor device 1, the thickness of the substrate 10 may be set to 100 μm or less. In this embodiment, after all layers are formed on the substrate 10, the substrate 10 is polished from the bottom surface to make it thinner.

[0102] 14 is a cross-sectional view of a semiconductor device 1 according to Example 2. A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated on a substrate 10 in this order.

[0103] Compared to the first embodiment, the third buffer layer 14 is omitted. In other words, the third buffer layer 14 is integrally formed with the channel layer 15. As in the second embodiment, the channel layer 15 may be disposed on the mask layer 13. According to the second embodiment, the number of manufacturing steps can be reduced compared to the first embodiment.

[0104] 15 is a cross-sectional view of a semiconductor device 1 according to a third embodiment. In the third embodiment, a buffer layer 12 is disposed at the bottom layer. On the buffer layer 12, a plurality of mask layers 13, a buffer layer 14, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated in this order.

[0105] In the third embodiment, after manufacturing the semiconductor device 1 of the first embodiment, the substrate 10 and the first buffer layer 11 are removed, and further the second buffer layer 12 is partially removed so as to become thinner. According to the third embodiment, the semiconductor device 1 can be configured to be thin. The mask layer 13 may also be removed. In this embodiment, a buffer layer 14 is disposed as the bottom layer.

[0106] 16 is a cross-sectional view of a semiconductor device 1 according to a fourth embodiment. In the fourth embodiment, one mask layer 13 is provided in a region between a source electrode 23 and a drain electrode 24. The position at which the mask layer 13 is disposed is the same as in the first embodiment. According to the fourth embodiment, the dislocation density can be further reduced.

[0107] [6] Sixth embodiment The sixth embodiment is a configuration example of a semiconductor device 1 including a resistance element and a HEMT.

[0108] 17 is a cross-sectional view of a semiconductor device 1 according to a sixth embodiment. The semiconductor device 1 includes a resistance element 2 and a HEMT 3.

[0109] A first buffer layer 11, a second buffer layer 12, a plurality of mask layers 13 (13-1, 13-2), a third buffer layer 14, a channel layer 15, a barrier layer 16, and a passivation film 18 are laminated in this order on a substrate 10. The configurations of the first buffer layer 11, the second buffer layer 12, the plurality of mask layers 13, the third buffer layer 14, the channel layer 15, the barrier layer 16, and the passivation film 18 are the same as those in the first embodiment.

[0110] Electrodes 17-1 and 17-2 are provided on the barrier layer 16 in the region of the resistor element 2. A plurality of mask layers 13-1 are provided in the region of the resistor element 2. The plurality of mask layers 13-1 are disposed in the region between the electrodes 17-1 and 17-2. The width and spacing of the mask layers 13-1 are appropriately set. The plurality of mask layers 13-1 may be further provided outside the region between the electrodes 17-1 and 17-2.

[0111] A source electrode 23 and a drain electrode 24 are arranged spaced apart from each other on the barrier layer 16 in the region of the HEMT3, and a gate electrode 22 is arranged spaced apart from each other between the source electrode 23 and the drain electrode 24. A plurality of mask layers 13-2 are provided in the region of the HEMT3. The plurality of mask layers 13-2 are arranged in the region between the source electrode 23 and the drain electrode 24. The width and intervals of the mask layers 13-2 are set appropriately. The plurality of mask layers 13-2 may be further provided outside the region between the source electrode 23 and the drain electrode 24.

[0112] An element isolation region 21 is provided between the resistance element 2 and the HEMT 3. The resistance element 2 and the HEMT 3 are insulated from each other by the element isolation region 21.

[0113] In this embodiment, a configuration example is shown in which the semiconductor device 1 includes one resistance element 2 and one HEMT 3, but it is also possible to arrange a plurality of resistance elements 2 and a plurality of HEMTs 3 on the same substrate 10. In addition, it is possible to arrange wiring above the illustrated electrodes via an insulating layer, and to electrically connect the resistance element 2 and the HEMT 3 using the wiring.

[0114] According to the sixth embodiment, the resistance element 2 and the HEMT 3 can be disposed on the same substrate 10. In addition, a circuit can be configured using the resistance element 2 and the HEMT 3.

[0115] In addition, the resistor element 2 and the HEMT 3 can be disposed closer to each other, which makes it possible to reduce the amount of wiring and the circuit area.

[0116] It is also possible to apply the examples shown in the fourth and fifth embodiments to the sixth embodiment.

[0117] In the above embodiment, a nitride semiconductor is used as the compound semiconductor constituting the semiconductor device 1. However, the present invention is not limited to this, and the stacked structure (including the buffer layer, the channel layer, and the barrier layer) constituting the semiconductor device 1 may be made of a compound semiconductor containing gallium arsenide (GaAs). Furthermore, the stacked structure may be made of a compound semiconductor containing indium (In), gallium (Ga), and arsenic (As).

[0118] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0119] 1...semiconductor device, 2...resistance element, 2DEG...dimensional electron gas layer, 10...substrate, 11...first buffer layer, 12...second buffer layer, 13...mask layer, 14...third buffer layer, 15...channel layer, 16...barrier layer, 17...electrode, 18...first passivation film, 19...second passivation film, 20...dislocation, 21...element isolation region, 22...gate electrode, 23...source electrode, 24...drain electrode.

Claims

1. A first nitride semiconductor layer provided on a substrate; a plurality of mask layers formed of an insulating material on the first nitride semiconductor layer; a second nitride semiconductor layer provided on the plurality of mask layers; a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a band gap larger than that of the second nitride semiconductor layer; a first electrode and a second electrode provided on the third nitride semiconductor layer and spaced apart from each other; A semiconductor device comprising:

2. The plurality of mask layers are disposed in a region between the first electrode and the second electrode. The semiconductor device according to claim 1 .

3. A first nitride semiconductor layer provided on a substrate; a plurality of mask layers formed of an insulating material on the first nitride semiconductor layer; a second nitride semiconductor layer provided on the plurality of mask layers; a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a band gap larger than that of the second nitride semiconductor layer; a source electrode and a drain electrode provided on the third nitride semiconductor layer and spaced apart from each other; a gate electrode provided on the third nitride semiconductor layer and disposed between the source electrode and the drain electrode; A semiconductor device comprising:

4. The mask layers are disposed in the region between the source electrode and the drain electrode. The semiconductor device according to claim 3 .

5. The mask layers are made of silicon oxide (SiO ２ ) The semiconductor device according to claim 1 .

6. In the second nitride semiconductor layer and the third nitride semiconductor layer, a region in which the plurality of mask layers are formed has a lower dislocation density than a region in which the plurality of mask layers are not formed. The semiconductor device according to claim 1 .

7. a substrate having a first region in which a resistor element is disposed and a second region in which a transistor is disposed; A first nitride semiconductor layer provided on the substrate; a plurality of first mask layers formed of an insulating material on the first nitride semiconductor layer in the first region; a plurality of second mask layers formed of an insulating material on the first nitride semiconductor layer in the second region; a second nitride semiconductor layer provided on the plurality of first mask layers and the plurality of second mask layers; a third nitride semiconductor layer provided on the second nitride semiconductor layer and having a band gap larger than that of the second nitride semiconductor layer; a first electrode and a second electrode provided on the third nitride semiconductor layer in the first region and spaced apart from each other; a source electrode and a drain electrode provided on the third nitride semiconductor layer in the second region and spaced apart from each other; a gate electrode provided on the third nitride semiconductor layer in the second region and disposed between the source electrode and the drain electrode; A semiconductor device comprising:

8. the first mask layers are disposed in a region between the first electrode and the second electrode; The plurality of second mask layers are disposed in a region between the source electrode and the drain electrode. The semiconductor device according to claim 7.

9. The patterns of the first mask layers are different from the patterns of the second mask layers. The semiconductor device according to claim 7.

10. The first mask layers and the second mask layers are made of silicon oxide (SiO ２ ) The semiconductor device according to claim 7.

11. a region of the second nitride semiconductor layer and the third nitride semiconductor layer in the first region, in which the plurality of first mask layers are formed, has a lower dislocation density than a region in which the plurality of first mask layers are not formed; In the second region, the region in which the plurality of second mask layers are formed has a lower dislocation density than a region in which the plurality of second mask layers are not formed, of the second nitride semiconductor layer and the third nitride semiconductor layer. The semiconductor device according to claim 7.

12. and an element isolation region disposed between the resistor element and the transistor, electrically insulating an interface between the second nitride semiconductor layer and the third nitride semiconductor layer. The semiconductor device according to claim 7.

13. The second nitride semiconductor layer and the third nitride semiconductor layer contain gallium (Ga) and nitrogen (N). The semiconductor device according to claim 1 , 3 or 7 .

14. The substrate is made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or sapphire. The semiconductor device according to claim 1 , 3 or 7 .

15. The thickness of the substrate is 100 μm or less. The semiconductor device according to claim 1 , 3 or 7 .

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