Semiconductor device

Abstract

To suppress defects of a semiconductor device.SOLUTION: A semiconductor device includes: a substrate 10; a case 20 which is provided on the substrate 10, and includes a resin layer 200 and a terminal 210; and a circuit board 100 which is provided on the substrate 10, and includes a semiconductor chip 110, and wiring 109 electrically connected to the semiconductor chip 110 and the terminal 210. The terminal 210 includes a first part 211 extending to the circuit board 100 from the resin layer 200, a second part 212 joined to the wiring 109, and a third part 213 between the first part 211 and the second part 212. The third part 213 is recessed to a side opposite to the substrate 100 side compared to the second part 212.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A power module is known as a semiconductor device that realizes high output. A power module is configured as a single package in which multiple power semiconductors are integrated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5972172 specification [Patent Document 2] Patent No. 6189798 specification [Patent Document 3] Patent No. 6805776 specification Summary of the Invention [Problem to be solved by the invention]

[0004] Defects in semiconductor devices are reduced. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a substrate, a case provided on the substrate and including a resin layer and a terminal, and a circuit board provided on the substrate and including a semiconductor chip and wiring electrically connected to the semiconductor chip and the terminal, the terminal including a first portion extending from the resin layer toward the circuit board, a second portion joined to the wiring, and a third portion between the first portion and the second portion, the third portion being recessed on the opposite side of the substrate than the second portion. [Brief description of the drawings]

[0006] [Figure 1]1 is a bird's-eye view showing an appearance of a semiconductor device according to an embodiment; [Diagram 2] 1 is a plan view showing an internal structure of a semiconductor device according to an embodiment; [Diagram 3] 1 is a cross-sectional view showing an internal structure of a semiconductor device according to an embodiment; [Figure 4] 3 is a cross-sectional view showing a structural example of a signal terminal and a case of the semiconductor device according to the embodiment; [Diagram 5] 3 is a cross-sectional view showing a structural example of a signal terminal and a case of the semiconductor device according to the embodiment; [Figure 6] 1 is a cross-sectional view showing an example of a structure of a signal terminal of a semiconductor device according to an embodiment; [Figure 7] 5A to 5C are cross-sectional process views showing a process of a manufacturing method of a semiconductor device according to an embodiment. [Figure 8] 5A to 5C are cross-sectional process views showing a process of a manufacturing method of a semiconductor device according to an embodiment. [Figure 9] FIG. 11 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A semiconductor device according to an embodiment will be described with reference to Figures 1 to 9. In the following description, elements having the same function and configuration are given the same reference numerals. In addition, in each of the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) given reference numerals with distinguishing numbers / letters at the end are not necessarily distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used. The dimensions and ratios of the components in the drawings are not necessarily the same as those in reality.

[0008] <Embodiment> (1) Configuration example An example of the configuration of a semiconductor device according to an embodiment will be described with reference to FIGS.

[0009] FIG. 1 is a bird's-eye view showing the appearance of a semiconductor device 1 according to the present embodiment.

[0010] As shown in FIG. 1, a semiconductor device 1 of the embodiment includes a base substrate 10, a case 20, lids 30A and 30B, and a plurality of connectors 219 and 319.

[0011] The base substrate 10, the case 20, and the lids 30A and 30B form a container for the semiconductor device 1. Inside the container for the semiconductor device 1, a configuration including a semiconductor element is provided.

[0012] The base substrate 10 is a support for the semiconductor device 1. The base substrate 10 has a flat plate shape. The base substrate 10 corresponds to the bottom of a container for the semiconductor device 1. The base substrate 10 has, for example, screw holes. The base substrate 10 can be fixed to an external device of the semiconductor device 1 through the screw holes. The base substrate 10 functions as, for example, a heat sink. For example, the base substrate 10 includes copper and / or ceramic.

[0013] The case 20 is provided on the upper surface of the base substrate 10. The case 20 is an insulator having a rectangular cylindrical shape. The case 20 corresponds to a side of a container of the semiconductor device 1. The case 20 is fixed to the base substrate 10. For example, the case 20 is adhered to the base substrate 10 by an adhesive (resin). The case 20 is a resin member. For example, the case 20 includes polyphenylene sulfide (PPS: Poly-Phenylene Sulfide).

[0014] The lids 30A and 30B are provided on the upper surface of the case 20. The lid 30 is an insulator having a plate shape. The lids 30A and 30B correspond to the upper part of the container of the semiconductor device 1. The lid 30 is fixed to the case 20. For example, the lids 30A and 30B include PPS.

[0015] By assembling the above-mentioned base substrate 10, case 20, and lids 30A and 30B, a space for arranging components (e.g., a semiconductor element) is formed inside the container of the semiconductor device 1. In the following, a plane parallel to the contact surface between the base substrate 10 and the case 20 is referred to as the XY plane. In the XY plane, the direction of one side of the base substrate 10 is referred to as the X direction, and the direction of the other side of the base substrate 10 is referred to as the Y direction. The direction perpendicular to the XY plane is referred to as the Z direction.

[0016] The semiconductor device 1 includes a plurality of connectors 219, 319 (319, 319B, 319C). Each of the plurality of connectors 219, 319 is electrically connected to an external device of the semiconductor device 1. Each of the plurality of connectors 219, 319 is electrically connected to a semiconductor element in a container of the semiconductor device 1. Each of the connectors 219, 319 is an end of each terminal (bus bar) in a container of the semiconductor device 1.

[0017] The connector 319 is used for inputting and outputting a voltage and / or a current to and from the semiconductor device 1. The connector 319 supplies a voltage (or a current) from an external device to the semiconductor element in the container of the semiconductor device 1, or supplies a voltage (or a current) generated by the semiconductor device 1 to the external device.

[0018] For example, two connectors 319A are arranged side by side in the Y direction on the upper part of the semiconductor device 1 (for example, on the upper surface of the case 20). The two connectors 319A correspond to input terminals of P (Positive) polarity. The two connectors 319A are electrically connected to each other.

[0019] For example, two connectors 319B are arranged side by side in the Y direction on the upper part of the semiconductor device 1 (for example, on the upper surface of the lid 30B). The two connectors 319B correspond to input terminals of N (negative) polarity. The two connectors 319B are electrically connected to each other.

[0020] For example, three connectors 319C are lined up in the Y direction on the upper part of the semiconductor device 1 (for example, on the upper surface of the case 20). The three connectors 319C correspond to output terminals. The three connectors 319C are electrically connected to each other.

[0021] The connector 219 is used to monitor the operating state of the semiconductor device 1. The connector 219 supplies a signal indicating a monitor result corresponding to the operating state of the semiconductor element in the container of the semiconductor device 1 to an external device of the semiconductor device 1. The connector 219 may also be used to supply a control signal for the semiconductor device 1. For example, the control connector 219 supplies a control signal from an external device of the semiconductor device 1 to the semiconductor element in the container of the semiconductor device 1.

[0022] For example, three connectors 219 are lined up in the X direction on the upper part (for example, on the upper surfaces of the case 20 and the lid 30) of the semiconductor device 1. The three connectors 219 are electrically isolated from one another.

[0023] One or more semiconductor chips are provided in a space surrounded by the base substrate 10, the case 20, and the lid 30.

[0024] The semiconductor device 1 of this embodiment is a power module, for example, an inverter, a converter, a regulator, a switch, or the like.

[0025] The internal structure of the semiconductor device 1 of this embodiment will be described with reference to FIGS.

[0026] Fig. 2 is a plan view showing an example of the internal structure of the semiconductor device 1 of this embodiment. Fig. 3 is a cross-sectional view showing a schematic example of the internal structure of the semiconductor device 1 of this embodiment. In Fig. 2, a connector 319 disposed above the base substrate 10 is indicated by a dashed line, a dotted line, a dashed line, etc.

[0027] 2 and 3, the case 20 surrounds a space on the upper surface of the base substrate 10. The case 20 includes a rectangular cylindrical resin layer 200. For example, an insulator (sealing material) 90 is filled in the space surrounded by the case 20 on the base substrate 10.

[0028] The semiconductor device 1 of this embodiment includes a plurality of semiconductor chips 110 provided on a circuit board 100. The number of semiconductor chips 110 in one semiconductor device 1 is, for example, 10 or more.

[0029] For example, four circuit boards 100 are provided on a base substrate 10. Each circuit board 100 is fixed to the base substrate 10 via solder or an adhesive. The circuit boards 100 and the semiconductor chips 110 are sealed with an insulator (sealant) 90.

[0030] The circuit board 100 includes two wiring layers 101, 103 and an insulating layer 102. The insulating layer 102 is sandwiched between the two wiring layers 101, 103. The wiring layers 101, 103 include a plurality of wirings 109. The wirings 109 are copper layers (Cu layers). The insulating layer 102 is a ceramic layer. For example, the wiring layer 103 is electrically isolated from the wiring layer 101 by the ceramic layer 102. However, the wiring layer 103 on the upper surface side of the insulating layer 102 may be electrically connected to the wiring layer 101 on the lower surface side of the insulating layer 102 via a through electrode (or plug) (not shown) in the insulating layer 102.

[0031] For example, two wirings 109 in a circuit board 100 are electrically connected to each other via a bonding wire 115. For example, two wirings 109 of adjacent circuit boards 100 are electrically connected to each other via a bonding wire 115.

[0032] A plurality of semiconductor chips 110 are provided on each circuit board 100. For example, 16 semiconductor chips 110 are provided on one circuit board 100.

[0033] The semiconductor chip 110 includes a plurality of nodes 111. Each node 111 is connected to a node 111 of another semiconductor chip 110 or to a corresponding one of a plurality of wirings 109 on the circuit board 100 via a bonding wire 119. The node 111 is, for example, a pad or an electrode.

[0034] For example, the semiconductor chip 110 includes an IGBT-FRD (Insulated gate bipolar transistor - fast recovery diode).

[0035] A semiconductor circuit is formed by the circuit board 100 and the semiconductor chips 110 on the circuit board 100. In this embodiment, the set of the circuit board 100 and the semiconductor chips 110 connected to the circuit board 100 is also called a semiconductor circuit.

[0036] A plurality of terminals (bus bars) 210, 310 are provided within the container of the semiconductor device 1.

[0037] Each of the terminals 210, 310 is a plate-shaped conductor. Each of the terminals 210, 310 contains copper. One end (lower end) of each of the terminals 210, 310 is electrically connected to the semiconductor chip 110 via the wiring 109 of the circuit board 100. The other end (upper end) of each of the terminals 210, 310 is electrically connected to a corresponding one of the multiple connectors 219, 319.

[0038] The terminals 310 (310A, 310B, 310C) are terminals for inputting and outputting a voltage or a current to and from the semiconductor chip 110. Hereinafter, the terminals 310 are referred to as input / output terminals.

[0039] The input / output terminal 310A is electrically connected to the connector 319A. The input / output terminal 310A is an input terminal of P polarity. The input / output terminal 310B is electrically connected to the connector 319B. The input / output terminal 310B is an input terminal of N polarity. The input / output terminal 310C is electrically connected to the connector 319C. The input / output terminal 310C is an output terminal.

[0040] Each input / output terminal 310 is electrically connected to a corresponding one of the multiple wirings 109 on the circuit board 100. The end (upper end) of the input / output terminal 310 on the lid 30 side is disposed higher in the Z direction than the end (upper end) of the terminal 210 on the lid 30 side.

[0041] The terminals 210 are terminals for monitoring or controlling the semiconductor device 1. Hereinafter, the terminals 210 are referred to as signal terminals. Each signal terminal 210 is electrically connected to a corresponding connector 219. The signal terminals 210 are conductors insert-molded in the case 20 (resin layer 200). For example, the signal terminals 210 are connected to wiring 109 connected to a control terminal (e.g., gate) and / or a current path (e.g., source / drain, emitter, or collector) of a transistor included in the semiconductor device 1.

[0042] An end (lower end, tip) of the signal terminal 210 on the circuit board 100 side is joined to the wiring 109 of the wiring layer 103. As a result, the signal terminal 210 is electrically connected to the semiconductor chip 110 via the wiring 109 and the bonding wire 119.

[0043] In the semiconductor device 1 of this embodiment, the surface (bottom surface) of the signal terminal 210 that comes into contact with the wiring 109 includes a step (depression) 290.

[0044] The structures of the case 20 and the signal terminals 210 of the semiconductor device 1 of this embodiment will be described with reference to FIGS.

[0045] Fig. 4 is a cross-sectional view showing a basic structure of the case 20 and the signal terminal 210 in the extending direction (first direction) of the signal terminal 210 in the semiconductor device 1 of this embodiment. Fig. 5 is a cross-sectional view showing a basic structure of the case 20 and the signal terminal 210 in the direction (second direction) intersecting the extending direction of the signal terminal 210 in the semiconductor device 1 of this embodiment. Fig. 5 shows a cross section of an opening of the resin layer 200 in a portion where the signal terminal of the case 20 is inserted. Figs. 4 and 5 also show a base substrate 10 and a circuit board 100.

[0046] As shown in Figures 4 and 5, the case 20 includes a slit 201 between a portion 214 of the signal terminal 210 and the resin layer 200 in an area near an opening 209 in the resin layer 200 for pulling the signal terminal 210 from the resin layer 200 into the inside of the container.

[0047] The slit 201 has a wedge-shaped cross-sectional shape. The cross-sectional shape of the slit 201 is not limited to a wedge shape, and may be a rectangle. The slit 201 makes the dimension of the opening 209 in the third direction (Z direction) larger than the thickness (dimension in the third direction) of the plate-shaped portion of the signal terminal 219 in the resin layer 200.

[0048] By providing the slits 201 in the resin layer 200, the movable range of the signal terminal 210 toward the base substrate 10 is expanded when pressure toward the base substrate 10 is applied to the signal terminal 210. In addition, the springiness of the portion of the signal terminal 210 protruding from the resin layer 200 is improved.

[0049] The signal terminal 210 extends from the case 20 toward the circuit board 100. The signal terminal 210 includes a plurality of portions 211, 212, 213, and 214. Hereinafter, the portion 214 of the signal terminal 210 in the resin layer 200 of the case 20 is referred to as an insert portion (or an embedded portion). The portion 213 of the signal terminal 210 that is joined to the wiring 109 of the circuit board 100 is referred to as a joint portion (or a foot portion). The portion 211 of the signal terminal 210 that extends from the insert portion 214 to the joint portion 212 is referred to as a leg portion (or a lead portion). The portion 213 of the signal terminal 210 that is connected to the lower end of the leg portion 211 and is between the leg portion 211 and the joint portion 212 is referred to as a heel portion.

[0050] The leg portion 211, the joint portion 212, the heel portion 213 and the insert portion 214 are one continuous plate-like conductor.

[0051] The insert portion 214 is covered with a resin layer 200. One end of the insert portion 214 is connected to the leg portion 211. The other end of the insert portion 214 is connected to a connector 219. The bottom of the insert portion 214 does not come into contact with the resin layer 200 due to the formation of the slit 201. For example, in the assembled semiconductor device 1, an insulator 90 is filled in the slit 201 between the bottom of the insert portion 214 and the resin layer 200.

[0052] Portions 211, 212, and 213 of the signal terminal 210 protrude from an opening 209 in the resin layer 200 into the space (insulator 90) within the container of the semiconductor device 1. The leg portion 211, the joint portion 212, and the heel portion 213 are exposed from the resin layer 200.

[0053] The heel portion 213 is provided between the leg portion 211 and the joint portion 212. The joint portion 212 is connected to the leg portion 211 via the heel portion 213.

[0054] The joint portion 212 is provided above the circuit board 100 in a direction (third direction) perpendicular to the upper surface of the base substrate 10. For example, a width W2 of the joint portion 212 in the width direction of the terminal 210 is wider than a width W1 of the leg portion 211 in the width direction of the terminal 210.

[0055] In the semiconductor device 1 of this embodiment, a step 290 is provided between the joint portion 212 and the heel portion 213 on the surface of the joint portion 212 and the heel portion 213 facing the base substrate 10 (the surface in contact with the wiring 109, the bottom surface of the signal terminal 210).

[0056] Due to step 290, the bottom surface of heel portion 213 (the surface facing wiring 109, the surface on the base substrate 10 side) is recessed further toward lid 30 (the upper part of semiconductor device 1) than the bottom surface of bonding portion 212.

[0057] The signal terminal 210 has a spring property in the portion between the leg portion 211 and the joint portion 212 due to the step 290 of the heel portion 213 .

[0058] By providing the step 290 at the bottom (bottom surface) of the signal terminal 210, uneven contact of the bottom of the signal terminal 210 with the circuit board 100 is suppressed.

[0059] The terminals having the shapes shown in FIGS. 4 and 5 may be used as the terminals 310 for inputting and outputting voltage / current to and from the semiconductor chip 110.

[0060] Depending on the layout and shape of the signal terminal 210, the joint portion 212 may be drawn out from the leg portion 211 (and the heel portion 213) in a direction (e.g., a second direction) intersecting the extending direction (e.g., a first direction) of the leg portion 211. Even in this case, the joint portion 212 is connected to the leg portion 211 via the heel portion 213 at the lower end of the leg portion 211. The leg portion 211 may extend in the second direction.

[0061] <Example of terminal structure> FIG. 6 is a schematic diagram showing a specific example of the shape of the signal terminal 210 in the semiconductor device 1 of the present embodiment.

[0062] Fig. 6(a) is a cross-sectional view showing an example of a specific structure of the signal terminal 210 in the semiconductor device 1 of this embodiment before bonding to the wiring 109. Fig. 6(b) is a cross-sectional view showing an example of a specific structure of the signal terminal 210 in the semiconductor device 1 of this embodiment after bonding to the wiring 109.

[0063] As shown in FIG. 6( a ), the signal terminal 210 includes a leg portion 211 , a joint portion 212 , and a heel portion 213 .

[0064] The leg portion 211 is a plate-shaped conductor. The leg portion 211 includes a portion that extends in a direction substantially perpendicular to the case 20 (insertion portion 214) toward the base substrate 10. The leg portion 211 may be inclined with respect to a direction perpendicular to the upper surface of the base substrate 10.

[0065] The joint portion 212 is a plate-shaped conductor. The joint portion 212 extends in a direction parallel to the upper surface of the base substrate 10. The joint portion 212 is connected to the leg portion 211 via the heel portion 213. The joint portion 212 is a portion of the signal terminal 210 that is joined to the wiring 109. The joint portion 212 corresponds to a tip region of a contact surface of the signal terminal 210 with the wiring 109.

[0066] The dimension (length) of the joint 212 in the direction from the heel portion 213 to the joint 212 (longitudinal direction of the joint 212) is "L1." The dimension (thickness) of the joint 212 in the direction perpendicular to the surface of the base substrate 10 (thickness direction of the joint 212) is "t1."

[0067] Heel portion 213 is a plate-shaped conductor. Heel portion 213 is located at the lower end of leg portion 211. Heel portion 213 connects joint portion 212 to leg portion 211. The bottom surface of heel portion 213 is located closer to the upper portion of semiconductor device 1 (lid 30 side) than the bottom surface of joint portion 211. Heel portion 213 corresponds to a base region of a contact surface of signal terminal 210 with wiring 109. Note that heel portion 213 can be regarded as the lower end portion of leg portion 211.

[0068] The dimension (length) of heel portion 213 in the direction from heel portion 213 to joint portion 212 is "L2." For example, dimension L2 of heel portion 213 is smaller than dimension L1 of joint portion 212. For example, dimension L2 is equal to or smaller than half of dimension L1.

[0069] The dimension (thickness) of heel portion 213 in a direction perpendicular to the surface of base substrate 10 (thickness direction of heel portion) is "t2." Dimension t2 of heel portion 213 is smaller than dimension t1 of joint portion 212. For example, dimension t2 is within a range of one-third or more of dimension t1 and one-half or less of dimension t1.

[0070] The step 290 is provided in the region (boundary) between the joint portion 212 and the heel portion 213. The size of the step 290 is "D1." The size D1 of the step corresponds to the difference (t1-t2) between the thickness t1 and the thickness t2.

[0071] As a result, in the semiconductor device 1 of this embodiment, the signal terminal 210 has a structure in which the heel portion 213 of the signal terminal 210 is recessed toward the lid 30 side of the semiconductor device 1 relative to the joint portion 212 .

[0072] For example, the step 290 between the joint portion 212 and the heel portion 213 is formed by striking the heel portion 213 with a die or by grinding the material of the heel portion 213 .

[0073] 6(b), the signal terminal 210 and the wiring 109 are bonded by applying ultrasonic waves and pressure. When the signal terminal 210 and the wiring 109 are each made of copper, the joint 212 and the wiring 109 are bonded by Cu-Cu bonding by applying ultrasonic waves and pressure.

[0074] When the signal terminal 210 is joined to the wiring 109 on the circuit board 100 by ultrasonic Cu-Cu bonding, the joint 212 is integrated with the wiring 109. Due to the high-speed vibration of the applied ultrasonic waves, an atomic bond is generated between the joint 212 and the wiring 109. Therefore, the joint 212 and the wiring 109 become conductors in which the boundary (interface) B1 between the joint 212 and the wiring 109 is not clear (there is practically no boundary). However, depending on the difference between the composition ratio of the material of the signal terminal 210 and the composition ratio of the material of the wiring 109, the boundary between the signal terminal 210 and the wiring 109 may be distinguishable.

[0075] For example, the bottom (bottom surface) of the joint 212 sinks into the wiring 109 due to pressure applied during ultrasonic bonding. As the joint 212 sinks, the upper surface of the wiring 109 is recessed in the region where the joint 212 and the wiring 109 contact each other. Note that in the region where the joint 212 and the wiring 109 contact each other, the position of the upper surface of the wiring 109 may be maintained, and the joint 212 may be crushed. When the joint 212 is crushed, the dimension of the lower surface (bottom surface, contact surface) side of the joint 212 is greater than the width of the upper surface side of the joint 212.

[0076] For example, the influence of ultrasonic waves and pressure on heel portion 213 is smaller than the influence of ultrasonic waves and pressure on joint 212. In this case, heel portion 213 is not integrated with wiring 109. Heel portion 213 only contacts wiring 109. For example, a boundary (interface) B2 exists between heel portion 213 and wiring 109. An insulating layer 295 such as an oxide may be provided between heel portion 213 and wiring 109. However, similar to joint 212, heel portion 213 and wiring 109 may become an integrated conductor.

[0077] In this manner, in the semiconductor device 1 of the present embodiment, the signal terminal 210 having the step 290 on the bonding surface with the wiring 109 can have the tip portion (bonding portion) 212 of the signal terminal 210 bonded to the wiring 109 of the circuit board 100 .

[0078] (2) Manufacturing method A method for manufacturing the semiconductor device 1 of this embodiment will be described with reference to Figures 7 and 8. Figures 7 and 8 are cross-sectional process views showing one process of the method for manufacturing the semiconductor device 1 of this embodiment.

[0079] 7, in the assembly process of the semiconductor device (power module) 1, a circuit board 100 including a plurality of semiconductor chips 110 is placed on a base substrate 10. A case 20 including an insert-molded signal terminal 210 is placed on the base substrate 10.

[0080] In order to join the signal terminals 210 of the case 20 and the wiring 109 of the circuit board 100, the base substrate 10 on which the circuit board 100 and the case 20 are arranged is mounted in the ultrasonic device 5.

[0081] The joints 212 of the signal terminals 210 are positioned on the traces 109 such that the positions of the joints 212 match the positions of the corresponding traces 109 of the circuit board 100 .

[0082] At this time, since the heel portion 213 of the signal terminal 210 is recessed as in this embodiment, the occurrence of uneven contact of the heel portion 213 of the signal terminal 210 is suppressed.

[0083] As a result, in this embodiment, the bottom surface of the joint portion 212 of the signal terminal 210 contacts the wiring 109 substantially parallel to the wiring 109 .

[0084] In the ultrasonic device 5, an ultrasonic capillary 51 connected to an ultrasonic horn 50 is applied to the signal terminal 210. The ultrasonic horn 50 generates ultrasonic waves of a certain amplitude and a certain frequency. The ultrasonic capillary 51 supplies ultrasonic waves from the ultrasonic horn 50 to the signal terminal 210 and applies pressure to the signal terminal 210.

[0085] 8, in order to supply ultrasonic waves to the signal terminal, the ultrasonic capillary 51 is pressed against the joint 212 of the signal terminal 210. The joint 212 of the signal terminal 210 is joined to the wiring 109 by the vibration caused by the ultrasonic waves and the pressure applied by the ultrasonic capillary 51.

[0086] When the ultrasonic capillary 51 is pressed against the signal terminal 210 , the signal terminal 210 moves down toward the base substrate 10 .

[0087] In this embodiment, a wedge-shaped slit 201 is provided in an opening 209 on the signal terminal 210 side of the case 20 between the resin layer 200 and the bottom (bottom surface) of the insert portion 214 of the signal terminal 210. This expands the movable range of the signal terminal 210 and improves the springiness of the signal terminal 210. As a result, in this embodiment, the signal terminal 210 is deflected toward the base substrate more than when the slit 201 is not provided.

[0088] Therefore, when the ultrasonic capillary 51 applies pressure to the signal terminal 210 toward the base substrate 10, the signal terminal 210 insert-molded in the case 20 is sufficiently crimped to the wiring 109. As a result, in this embodiment, the joint portion 212 of the signal terminal 210 can be reliably joined to the wiring 109.

[0089] Therefore, in this embodiment, the occurrence of poor bonding between the signal terminal 210 and the wiring 109 caused by the bottom of the signal terminal 210 hitting only one side of the circuit board 100 is suppressed.

[0090] When the signal terminal 210 is bent toward the base substrate 10 by the pressure of the ultrasonic capillary 51, a gap 99 may be generated between the upper part of the insert portion 214 and the resin layer 200. This gap 99 may remain in the semiconductor device 1 even after the manufacturing process of the semiconductor device 1 is completed.

[0091] As shown in FIG. 6(b), the joint 212 of the signal terminal 210 is integrated with the wiring 109 by Cu-Cu bonding through application of ultrasonic waves and pressure.

[0092] After each signal terminal 210 is bonded to the corresponding wiring 109, a plurality of input / output terminals 310 are disposed on the case 20. Each of the input / output terminals 310 is bonded to the corresponding wiring 109 on the circuit board 100 by, for example, ultrasonic bonding. After bonding the input / output terminals 310 and the wiring 109, the lid 30 is connected to the case 20.

[0093] Through the above steps, the semiconductor device 1 of the present embodiment is completed.

[0094] (3) Variations FIG. 9 is a cross-sectional view showing a modification of the semiconductor device of the present embodiment.

[0095] 9, a gap 299 may be provided between the heel portion 213 of the signal terminal 210 and the wiring 109 of the circuit board 100. For example, after the semiconductor device 1 is assembled, an insulator 90 is filled in the gap 299. The insulator 90 is provided between the heel portion 213 and the wiring 109.

[0096] Even in this case, the semiconductor device 1 of the modified example can suppress poor bonding between the signal terminal 210 and the wiring 109.

[0097] (4) Summary 2. Description of the Related Art In a semiconductor device such as a power module, terminals that are insert-molded into a case are joined to wiring of a circuit board on a base substrate.

[0098] If the signal terminal (or the case) is deformed by an external force when the case and the base substrate are attached, the joint between the signal terminal and the wiring may rise above the wiring. When the joint rises above the wiring, the bottom of the signal terminal, which has a flat contact surface, may come into contact with the wiring on one side.

[0099] If ultrasonic bonding is performed between a signal terminal and a wiring when the bottom of the signal terminal is in partial contact with the wiring, poor bonding between the signal terminal and the wiring may occur because the contact area between the bottom of the signal terminal and the wiring is small.

[0100] In the semiconductor device 1 of this embodiment, a heel portion 213 at the bottom of the signal terminal 210 is recessed. The recess of the heel portion 213 provides a step 290 between the heel portion 213 on the bottom surface of the signal terminal 210 and a joint portion 212 that is joined to the wiring 109.

[0101] Due to this step 290, in the semiconductor device 1 of this embodiment, a space for preventing uneven contact of the signal terminal 210 can be provided between the wiring 109 and the heel portion 213 of the signal terminal 210. Therefore, in this embodiment, it becomes difficult for the lower end (heel portion 213) of the leg portion 211 of the signal terminal 210 to come into contact with the wiring 109 before the joint portion 212 of the signal terminal 210 comes into contact with the wiring 109.

[0102] Therefore, the semiconductor device 1 of the present embodiment can prevent the heel portion 213 of the signal terminal 210 (the lower end of the leg portion 211) from contacting on one side.

[0103] The signal terminals located close to the resin layer of the case have a relatively high rigidity. When the signal terminals have high rigidity, the signal terminals are less likely to bend.

[0104] In the semiconductor device 1 of this embodiment, a wedge-shaped slit 201 is provided in a region of the signal terminal 210 between the resin layer 200 and the bottom of the insert portion 214 in the resin layer 200. This improves the spring characteristics of the signal terminal 210 in the vicinity of the opening 209 of the resin layer 200 (in the vicinity of the boundary between the leg portion 211 and the insert portion 214). In addition, the arrangement of the slit 201 expands the movable range of the signal terminal 210 toward the base substrate 10. Therefore, in this embodiment, the signal terminal 210 can be largely deflected toward the base substrate during the ultrasonic bonding process.

[0105] As a result, the semiconductor device 1 of this embodiment can bring the contact surface of the signal terminal 210 with respect to the wiring 109 (for example, the bottom surface of the bonding portion 212) into parallel contact with the wiring 109. This allows the semiconductor device 1 of this embodiment to perform ultrasonic bonding between the signal terminal 210 and the wiring 109 while ensuring a large contact surface between the signal terminal 210 and the wiring 109.

[0106] Therefore, the semiconductor device 1 of this embodiment can suppress poor bonding between the signal terminal 210 and the wiring 109.

[0107] Furthermore, in this embodiment, when the signal terminal expands due to heat, the stress generated between the resin layer 200 and the signal terminal 210 can be reduced by the slits 201. As a result, the semiconductor device 1 of this embodiment can suppress distortion and deterioration of the shape of the signal terminal caused by stress.

[0108] As described above, the semiconductor device of the present embodiment can suppress defects in the semiconductor device, and therefore can improve the manufacturing yield of the semiconductor device.

[0109] (5) Other The semiconductor device of this embodiment is not limited to a power module as long as it is a device in which a terminal insert-molded in a case is joined to a conductor on a substrate by ultrasonic bonding. Also, the device of this embodiment is not limited to a semiconductor device as long as it is a device in which a terminal insert-molded in a case is joined to a conductor on a substrate by ultrasonic bonding.

[0110] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0111] 1: semiconductor device, 10: base substrate, 20: case, 100: circuit board, 109: wiring, 110: semiconductor chip, 200: resin layer, 201: slit, 210: signal terminal, 211: leg portion, 212: joint portion, 213: heel portion, 290: step.

Claims

1. A substrate; a case provided on the substrate, the case including a resin layer and a terminal; a circuit board provided on the substrate, the circuit board including a semiconductor chip and wiring electrically connected to the semiconductor chip and the terminal; Equipped with The terminal is a first portion extending from the resin layer toward the circuit board; a second portion joined to the wiring; a third portion between the first portion and the second portion; and Including, The third portion is recessed toward an opposite side to the substrate side relative to the second portion. Semiconductor device.

2. The terminal includes a step between the second portion and the third portion. The semiconductor device according to claim 1 .

3. The terminal further includes a fourth portion provided in the resin layer, The resin layer further includes a slit provided between the fourth portion and the resin layer. The semiconductor device according to claim 1 .

4. a dimension of the third portion in a first direction perpendicular to a top surface of the substrate is smaller than a dimension of the second portion in the first direction; The semiconductor device according to claim 1 .

5. a dimension of the second portion in a second direction parallel to a top surface of the substrate is greater than a dimension of the third portion in the second direction; The semiconductor device according to claim 1 .

6. The second portion is continuous with the wiring. The semiconductor device according to claim 1 .

7. the third portion is in contact with the wiring and is not continuous with the wiring; The semiconductor device according to claim 1 .

8. Further comprising an insulator covering the circuit board; The insulator is provided between the third portion and the wiring. The semiconductor device according to claim 1 .

9. The terminal is a conductor insert-molded into the resin layer. The semiconductor device according to claim 1 .

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