Phase comparison circuit and PLL circuit

Abstract

To provide a phase comparison circuit and a PLL circuit that reduce current noise and phase comparison spurious while enhancing linearity.SOLUTION: A source current source 41 is connected to a loop filter 5 until a delay time Td has elapsed since a reference signal Φref, when the phase of the reference signal Φref is slower than the phase of a feedback signal Φfb, a sink current source 42 is connected to a loop filter 5 until (a delay time Td+time difference ΔT) has elapsed since the rise of the feedback signal Φfb, and when the phase of the feedback signal Φfb is slower than the phase of the reference signal Φref, the sink current source 42 is connected to the loop filter 5 until (the delay time Td-time difference ΔT) has elapsed since the rise of the feedback signal Φfb.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a phase comparison circuit and a PLL circuit. [Background technology]

[0002] The phase comparator circuit that constitutes the PLL (Phase Locked Loop) circuit controls the charge pump circuit so that when the phase of the reference signal is delayed compared to the phase of the feedback signal, it draws up a sink current from the loop filter, and when the phase of the feedback signal is delayed compared to the phase of the reference signal, it supplies a source current to the loop filter. The source current and the sink current are designed to have the same current value, but in reality there is a difference. For this reason, as shown in Figure 14, there is a problem that nonlinear distortion occurs in the average output current ICP characteristic of the charge pump circuit with respect to the phase difference, deteriorating the PLL characteristics. In particular, decimal point division type PLLs have high requirements for linearity.

[0003] Therefore, a current bleeding method has been proposed in the past, which generates a current offset to forcibly operate in a linear region (Non-Patent Document 1). According to Non-Patent Document 1, as shown in Fig. 7, when the phase of the reference signal Φref is delayed from the phase of the feedback signal Φfb, a sink current is drawn from the loop filter by a time difference ΔT corresponding to the phase difference from the rising edge of the feedback signal Φfb, and after the drawing of the sink current is completed, a source current is supplied for a bleed time Tb. Also, when the phase of the feedback signal Φfb is delayed from the phase of the reference signal Φref, a source current is supplied to the loop filter by a time difference ΔT + bleed time Tb from the rising edge of the reference signal Φref.

[0004] In the phase comparison circuit using the conventional current bleeding method described above, although the linearity is high, there are problems in that the current noise increases and the phase comparison spurious becomes large. To explain in detail, in the phase comparison circuit using the conventional current bleeding method, as shown by the diagonal lines, the output current output from the charge pump circuit increases by the amount of the current offset, and the current noise increases. In addition, since the source current is supplied after the sink current has been sucked up, the change in the control voltage output from the loop filter becomes large, and the phase comparison spurious becomes large. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] A. Homayoun, B. Razavi “Analysis of Phase Noise in Phase / Frequency Detectors”, IEEE Transactions on Circuits and Systems I:Regular Papers(Volume:60, Issue:3, March 2013) Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a phase comparison circuit and a PLL circuit which improve linearity while reducing current noise and phase comparison spurious. [Means for solving the problem]

[0007] In order to achieve the above object, a phase comparison circuit and a PLL circuit according to the present invention are characterized by the following [1] to [5]. [1] A phase comparison circuit for controlling a charge pump circuit having a source current source that supplies a source current to a loop filter and a sink current source that draws up a sink current from the loop filter in response to a time difference between rising edges of a first pulse signal and a second pulse signal, a first control can be executed in which one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a first predetermined time has elapsed, and when the phase of the first pulse signal is slower than the phase of the second pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time+the time difference) has elapsed, and when the phase of the second pulse signal is slower than the phase of the first pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time-the time difference) has elapsed. It is a phase comparison circuit. [2] In the phase comparison circuit according to [1], when the phase of the first pulse signal is slower than the phase of the second pulse signal, one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a second predetermined time has elapsed, and the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal to the rising edge of the first pulse signal; when a phase of the second pulse signal is delayed compared to a phase of the first pulse signal, a second control can be executed to connect one of the source current source and the sink current source to the loop filter during a period from a rising edge of the first pulse signal to a rising edge of the second pulse signal and during a period from a rising edge of the second pulse signal to a lapse of the second predetermined time, When the time difference is equal to or smaller than a predetermined value, the first control is executed, and when the time difference is larger than the predetermined value, the second control is executed. It is a phase comparison circuit. [3] In the phase comparison circuit according to [1], a first reset circuit that outputs a first reset signal after the first predetermined time has elapsed since the rising edge of the first pulse signal; a first D flip-flop circuit having a clock terminal to which the first pulse signal is input and a D terminal to which an H level is constantly input; a first AND circuit having an input connected to an output of the first reset circuit and a Q terminal of the first D flip-flop circuit, and an output connected to a reset terminal of the first D flip-flop circuit; a second D flip-flop circuit having a clock terminal to which the second pulse signal is input and a D terminal to which an H level is constantly input; a second AND circuit to which the output of the first reset circuit and a Q terminal of the second D flip-flop circuit are input and whose output is connected to a reset terminal of the second D flip-flop circuit; It is a phase comparison circuit. [4] In the phase comparison circuit according to [3], a lock detection circuit that detects a lock when the time difference is equal to or smaller than a predetermined value; a second reset circuit that outputs a second reset signal at a timing when one of the first pulse signal and the second pulse signal, whichever rises later, rises; a third reset circuit that outputs a third reset signal after a second predetermined time has elapsed since the second reset signal was output; a switching circuit for connecting an output of the first reset circuit to an input of the first AND circuit and the second AND circuit when the lock detection circuit detects a lock, and for connecting an output of the second reset circuit to an input of the second AND circuit and an output of the third reset circuit to an input of the first AND circuit when the lock detection circuit does not detect a lock. It is a phase comparison circuit. [5] a phase comparison circuit which sets one of the reference signal and the feedback signal as a first pulse signal and the other as a second pulse signal, and compares the phases of the first pulse signal and the second pulse signal; a charge pump circuit having a source current source for supplying a source current and a sink current source for drawing up a sink current, the charge pump circuit being controlled by the phase comparison circuit; a loop filter that converts the current output from the charge pump circuit into a voltage and outputs a control voltage; a VCO that outputs an output signal having a frequency corresponding to the control voltage; a frequency divider that divides the output signal and inputs the divided signal to the phase comparator as the feedback signal, a first control can be executed in which one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a first predetermined time has elapsed, and when the phase of the first pulse signal is slower than the phase of the second pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time+a time difference between the rising edges of the first pulse signal and the second pulse signal) has elapsed, and when the phase of the second pulse signal is slower than the phase of the first pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time-the time difference) has elapsed. It is a PLL circuit. Effect of the Invention

[0008] According to the present invention, it is possible to provide a phase comparison circuit and a PLL circuit that improve linearity while reducing current noise and phase comparison spurious.

[0009] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following description of the embodiment of the present invention (hereinafter, referred to as "embodiment") with reference to the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an embodiment of a PLL circuit incorporating a phase comparison circuit of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing a charge pump circuit constituting the PLL circuit shown in FIG. [Diagram 3] 3A to 3E are time charts of the reference signal Φref, the feedback signal Φfb, the source signal S1 and the sink signal S2 output from the phase comparison circuit shown in FIG. 1 and FIG. 2, and the output current output from the charge pump circuit. [Figure 4] FIG. 4 is a circuit diagram showing a phase comparison circuit constituting the PLL circuit shown in FIG. 1 in the first embodiment. [Diagram 5] FIG. 5 is a graph showing the results of measuring the output current characteristics of the charge pump circuit versus the phase difference of the PLL circuit in the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a phase comparison circuit constituting the PLL circuit shown in FIG. 1 in the second embodiment. [Figure 7] 7(A) to (E) are time charts of the reference signal Φref, the feedback signal Φfb, the source signal S1 and the sink signal S2 output from the phase comparison circuit, and the output current output from the charge pump circuit, which are input to a phase comparison circuit using a conventional current bleeding method. [Figure 8] FIG. 8 is a graph showing the results of FFT of the control voltage input to the VCO of a PLL circuit incorporating a phase comparison circuit using a conventional current bleeding method. [Figure 9] FIG. 9 is a graph showing the results of FFT of the control voltage input to the VCO when the VCO is locked in a PLL circuit incorporating the phase comparison circuit shown in FIG. [Figure 10] FIG. 10 is a graph showing the results of FFT of an output signal output from a VCO of a PLL circuit incorporating a phase comparison circuit using a conventional current breeding method. [Figure 11]FIG. 11 is a graph showing the result of performing FFT on the output signal output from the VCO when the PLL circuit incorporating the phase comparison circuit shown in FIG. 6 is locked. [Figure 12] FIG. 12 is a graph obtained by magnifying the vicinity of the oscillation frequency in FIG. 10. [Figure 13] FIG. 13 is a graph obtained by magnifying the vicinity of the oscillation frequency in FIG. 11. [Figure 14] FIG. 14 is a graph showing the average output characteristics of the charge pump circuit with respect to the conventional phase difference.

DETAILED DESCRIPTION OF THE INVENTION

[0011] Specific embodiments of the present invention will be described below with reference to the respective drawings.

[0012] (First Embodiment) First, the first embodiment will be described. FIG. 1 is a block diagram showing an embodiment of a PLL circuit incorporating the phase comparison circuit of the present invention. As shown in FIG. 1, the PLL circuit 1 of the present embodiment is a fractional-N type, and outputs an output signal Φout obtained by multiplying the frequency of the reference signal Φref obtained by dividing the input signal Φin by 1 / R by n times (N (N is an integer) <n <N + 1), and is a circuit that synchronizes the input signal Φin and the output signal Φout.

[0013] The PLL circuit 1 includes an input divider 2, a phase comparison circuit 3, a charge pump circuit 4, a loop filter 5, a VCO (Voltage-controlled oscillator) 6, a divider 7, and a ΔΣ modulator 8.

[0014] The input divider 2 outputs a reference signal Φref (= first pulse signal) obtained by dividing the frequency of the input signal Φin by 1 / R to the phase comparison circuit 3. The phase comparison circuit 3 outputs a source signal S1 or a sink signal S2 having a duty according to the phase difference between the reference signal Φref and the feedback signal Φfb (= second pulse signal) output from the divider 7. Details of the phase comparison circuit 3 will be described later.

[0015] The charge pump circuit 4 is a circuit that outputs a current corresponding to the source signal S1 and the sink signal S2 output from the phase comparison circuit 3 to the loop filter 5. As shown in Fig. 2, the charge pump circuit 4 has a source current source 41, a source side switch SW1, a sink current source 42, and a sink side switch SW2.

[0016] The source current source 41 is connected between the first power supply VDD and the loop filter 5, and supplies a source current I1 from the first power supply VDD to the loop filter 5. The source side switch SW1 is connected between the source current source 41 and the loop filter 5. When the source side switch SW1 is turned on, the loop filter 5 and the source current source 41 are connected, and the source current I1 is supplied to the loop filter 5. When the source side switch SW1 is turned off, the loop filter 5 is disconnected from the source current source 41, and the source current I1 is cut off. The source side switch SW1 is controlled to be turned on and off by a source signal S1. In this embodiment, the source side switch SW1 is turned on when an L-level source signal S1 is output.

[0017] The sink current source 42 is connected between the loop filter 5 and the second power supply VSS, which outputs a power supply voltage lower than the first power supply VDD, and draws up a sink current I2 from the loop filter 5 to the second power supply VSS. The sink side switch SW2 is connected between the sink current source 42 and the loop filter 5. When the sink side switch SW2 is turned on, the loop filter 5 and the sink current source 42 are connected, and the sink current I2 is drawn up from the loop filter 5. When the sink side switch SW2 is turned off, the loop filter 5 is disconnected from the sink current source 42, and the sink current I2 is cut off. The on / off of the sink side switch SW2 is controlled by a sink signal S2. In this embodiment, the sink side switch SW2 is turned on when an H-level sink signal S2 is output.

[0018] The loop filter 5 outputs a control voltage obtained by converting the source current I1 and sink current I2 output from the charge pump circuit 4 into a voltage. The loop filter 5 is composed of resistors and capacitors (not shown). In the loop filter 5, the capacitor is charged according to the output of the source current I1, and discharged according to the output of the sink current I2, generating a control voltage and outputting it to the VCO 6.

[0019] The VCO 6 oscillates at a frequency according to the control voltage, and outputs an output signal Φout having a frequency according to the control voltage. The frequency divider 7 divides the output signal Φout and inputs it to the phase comparison circuit 3 as a feedback signal Φfb. In this embodiment, the frequency divider 7 can switch the frequency division ratio between 1 / N and 1 / (N+1). The ΔΣ modulator 8 periodically switches the frequency division ratio of the frequency divider 7 between 1 / N and 1 / (N+1) to set the frequency division ratio 1 / n to 1 / N<1 / n<1 / (N+1).

[0020] In the above-mentioned charge pump circuit 4, the source current I1 and the sink current I2 are designed to have the same current value. However, in reality, a difference occurs between the source current I1 and the sink current I2, which causes nonlinear distortion in the average output current characteristic output from the charge pump circuit 4 with respect to the phase difference. In particular, the decimal point division type PLL circuit 1 requires high linearity because the phase difference varies every time the division ratio of the divider 7 is switched.

[0021] Therefore, the phase comparison circuit 3 of the first embodiment is configured to output a source signal S1 and a sink signal S2 as shown in Fig. 3. In Fig. 3, ΔT is the time difference between the rising edges of the reference signal Φref and the feedback signal Φfb. As shown in the figure, the phase comparison circuit 3 outputs a source signal S1 that is at an L level until a delay time Td (=first predetermined time) has elapsed since the rising edge of the reference signal Φref, thereby connecting the source current source 41 to the loop filter 5. That is, the pulse length of the source signal S1 is fixed to the delay time Td.

[0022] 3, when the phase of the reference signal Φref is delayed from the phase of the feedback signal Φfb, the phase comparison circuit 3 outputs a sink signal S2 that is at H level until (delay time Td+time difference ΔT) has elapsed since the rise of the feedback signal Φfb, to connect the sink current source 42 to the loop filter 5. As shown in the right side of FIG. 3, when the phase of the feedback signal Φfb is delayed from the phase of the reference signal Φref, the phase comparison circuit 3 outputs a sink signal S2 that is at H level until (delay time Td-time difference ΔT) has elapsed since the rise of the feedback signal Φfb, to connect the sink current source 42 to the loop filter 5. That is, the pulse length of the sink signal S2 is a length according to the phase difference between the reference signal Φref and the feedback signal Φfb, and the timing at which the pulses of the source signal S1 and the sink signal S2 end is the same.

[0023] 3, an output current described below is output from the charge pump circuit 4. When the phase of the reference signal Φref lags behind the phase of the feedback signal Φfb, a sink current I2 is drawn up from the loop filter 5 during the period from the rising edge of the feedback signal Φfb to the rising edge of the reference signal Φref. After the rising edge of the reference signal Φref, both the source current source 41 and the sink current source 42 are connected to the loop filter 5, and the difference between the source current I1 and the sink current I2 flows as the output current. Since the source current I1 and the sink current I2 have approximately the same current value, the output current at this time is small.

[0024] When the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref, a source current I1 is supplied to the loop filter 5 during the period from the rising edge of the reference signal Φref to the rising edge of the feedback signal Φfb. After the rising edge of the feedback signal Φfb, both the source current source 41 and the sink current source 42 are connected to the loop filter 5, and the difference between the source current I1 and the sink current I2 flows as the output current. Since the source current I1 and the sink current I2 have approximately the same current value, the output current at this time is small.

[0025] According to the above-mentioned phase comparison circuit 3, as in the conventional current bleeding, a current offset can be formed to forcibly operate in a linear region, and the linearity of the average output current characteristic from the charge pump circuit 4 with respect to the phase difference between the reference signal Φref and the feedback signal Φfb can be increased. Moreover, when the phase of the reference signal Φref lags behind the phase of the feedback signal Φfb, a large source current I1 is not supplied after being sucked up by the sink current I2. This makes it possible to reduce the change in the output current and the control voltage, and to reduce current noise and phase comparison spurious.

[0026] Next, an example of a detailed configuration of the phase comparison circuit 3 that outputs the source signal S1 and the sink signal S2 shown in Fig. 3 will be described with reference to Fig. 4. The phase comparison circuit 3 has a reset circuit 31 (=first reset circuit), a D flip-flop circuit 32 (=first D flip-flop circuit), an AND circuit 33 (=first AND circuit), a NOT circuit 34, a D flip-flop circuit 35 (=second D flip-flop circuit), and an AND circuit 36 ​​(=second AND circuit).

[0027] The reset circuit 31 outputs a reset signal Sr1 (=first reset signal) after a delay time Td from the rising edge of the reference signal Φref. In this embodiment, the reset circuit 31 has a delay circuit 311 to which the reference signal Φref is input, and a D flip-flop circuit 312 to which the output of the delay circuit 311 is connected to a clock (CK) terminal. The delay circuit 311 outputs a delay signal Sd obtained by delaying the reference signal Φref by the delay time Td to the D flip-flop circuit 312. The D flip-flop circuit 312 has a D terminal to which 1 (H level) is always input, and a reset (R) terminal and a Q terminal are connected. When the delay signal Sd rises with a delay of the delay time Td from the rising edge of the reference signal Φref, the D flip-flop circuit 312 outputs a reset signal Sr1, which is a one-shot pulse of H level, from the Q terminal.

[0028] The D flip-flop circuit 32 has a reference signal Φref input to its CK terminal and a value of 1 constantly input to its D terminal. The AND circuit 33 has two inputs connected to the output of the reset circuit 31 and the Q terminal of the D flip-flop circuit 32, respectively, and an output connected to the R terminal of the D flip-flop circuit 32. The D flip-flop circuit 32 outputs a signal from its Q terminal that goes to H level at the rising edge of the reference signal Φref and goes to L level when the reset signal Sr1 is output. This signal is inverted by the NOT circuit 34 and output as the source signal S1.

[0029] The D flip-flop circuit 35 receives the feedback signal Φfb at its CK terminal and constantly inputs 1 to its D terminal. The AND circuit 36 ​​has two inputs connected to the output of the reset circuit 31 and the Q terminal of the D flip-flop circuit 35, respectively, and its output connected to the R terminal of the D flip-flop circuit 35. The D flip-flop circuit 35 outputs a sink signal S2 that goes to H level at the rising edge of the feedback signal Φfb and goes to L level when the reset signal Sr1 is output.

[0030] According to the above configuration, it is possible to output the source signal S1 and the sink signal S2 as shown in FIG. 3 with a simple configuration.

[0031] Next, in order to confirm the effect of the above-mentioned PLL circuit 1, the inventors applied a difference of 10% between the source current I1 and the sink current I2 and measured the average output current of the charge pump circuit 4 with respect to the phase difference. The results are shown in Figure 5. As shown in the figure, the linearity of the average output current characteristic of the charge pump circuit 4 with respect to the phase difference can be improved.

[0032] Second embodiment Next, the second embodiment will be described. Incidentally, in the above-mentioned first embodiment, as shown in FIG. 5, the linearity of the average output current characteristic of the charge pump circuit 4 with respect to the phase difference can be increased. However, when the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref, if the time difference ΔT is larger than the delay time Td, (delay time Td-time difference ΔT) becomes negative, and the linearity deteriorates. To solve this problem, in the second embodiment, the phase comparison circuit 3B is configured as shown in FIG. 6. The phase comparison circuit 3B shown in FIG. 6 performs a first control to output the source signal S1 and the sink signal S2 of the first embodiment shown in FIG. 3 while the time difference ΔT is small, and performs a second control to output the source signal S1 and the sink signal S2 using the conventional current bleeding method shown in FIG. 7 while the time difference ΔT is large.

[0033] In the second control, the phase comparison circuit 3B of the second embodiment outputs a source signal S1 and a sink signal S2 as shown in Fig. 7. As shown in the figure, the phase comparison circuit 3B outputs a source signal S1 that connects the source current source 41 to the loop filter 5 during the period from the rising edge of the reference signal Φref to the lapse of a bleed time Tb (=second predetermined time) when the phase of the reference signal Φref is slower than the phase of the feedback signal Φfb, as shown on the left side of Fig. 7. Also, when the phase of the reference signal Φref is slower than the phase of the feedback signal Φfb, the phase comparison circuit 3B outputs a sink signal S2 that connects the sink current source 42 to the loop filter 5 during the period from the rising edge of the feedback signal Φfb to the rising edge of the reference signal Φref.

[0034] 7, when the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref, the phase comparator circuit 3B connects the source current source 41 to the loop filter 5 during the period from the rising edge of the reference signal Φref to the rising edge of the feedback signal Φfb and during the period from the rising edge of the feedback signal Φfb until the bleed time Tb has elapsed. Moreover, when the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref, the phase comparator circuit 3B does not connect the sink current source 42 to the loop filter 5.

[0035] 7, the charge pump circuit 4 outputs the output current shown below. When the phase of the reference signal Φref lags behind the phase of the feedback signal Φfb, the sink current I2 is drawn up from the loop filter 5 during the period from the rising edge of the feedback signal Φfb to the rising edge of the reference signal Φref. After the rising edge of the reference signal Φref, the source current I1 is supplied to the loop filter 5 until the bleed time Tb has elapsed.

[0036] When the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref, the source current I1 is supplied to the loop filter 5 not only from the rising edge of the reference signal Φref to the rising edge of the feedback signal Φfb, but also from the rising edge of the feedback signal Φfb until the bleed time Tb has elapsed.

[0037] Next, the details of the phase comparison circuit 3B will be described with reference to Fig. 6. In Fig. 6, the same components as those in the phase comparison circuit 3 in Fig. 4 already described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0038] The phase comparison circuit 3B includes a reset circuit 31, a D flip-flop circuit 32, an AND circuit 33, a NOT circuit 34, a D flip-flop circuit 35, an AND circuit 36, a lock detection circuit 37, an AND circuit (=second reset circuit) 38, a bleed circuit (=third reset circuit) 39, and switching circuits 310A and 310B. The reset circuit 31, the D flip-flop circuit 32, the AND circuit 33, the NOT circuit 34, the D flip-flop circuit 35, and the AND circuit 36 ​​are the same as those in the first embodiment, and therefore detailed description thereof will be omitted.

[0039] The lock detection circuit 37 detects a lock when the time difference ΔT is equal to or less than a predetermined value. In this embodiment, the predetermined value is set to a delay time Td, and the lock detection circuit 37 detects a lock by comparing the outputs of the AND circuits 33 and 36. To explain in more detail, when the time difference ΔT is equal to or less than the delay time Td while the first control is being executed, the AND circuits 33 and 36 output an H-level signal at the timing when the reset signal Sr1 is output.

[0040] On the other hand, if the phase of the feedback signal Φfb lags behind the phase of the reference signal Φref and the time difference ΔT is greater than the delay time Td, the feedback signal Φfb has not risen at the timing when the reset signal Sr1 is output, so no H-level signal is output from the AND circuit 36. Therefore, the lock detection circuit 37 can detect a lock by comparing the outputs of the AND circuits 33 and 36.

[0041] The Q terminals of the D flip-flop circuits 32 and 35 are connected to two inputs of the AND circuit 38. As a result, the AND circuit 38 outputs a reset signal Sr2 (= a second reset signal) of H level at the timing when the reference signal Φref or the feedback signal Φfb, whichever rises later, rises. The bleed circuit 39 outputs a reset signal Sr3 (= a third reset signal) after a bleed time Tb has elapsed since the reset signal Sr2 was output.

[0042] The switching circuit 310A switches the connection destination of the input of the AND circuit 33 between the output of the reset circuit 31 and the output of the bleed circuit 39. The switching circuit 310B switches the connection destination of the input of the AND circuit 36 ​​between the output of the reset circuit 31 and the output of the AND circuit 38. When the lock detection circuit 37 detects a lock while the first control is being executed, the switching circuits 310A and 310B connect the output of the reset circuit 31 to the inputs of the AND circuits 33 and 36. As a result, the source signal S1 and sink signal S2 shown in FIG. 3 are output from the phase comparison circuit 3B, and the phase comparison circuit 3B executes the first control.

[0043] When the lock detection circuit 37 does not detect a lock while the first control is being executed, the switching circuits 310A and 310B connect the output of the AND circuit 38 to the input of the AND circuit 36 ​​and connect the output of the bleed circuit 39 to the input of the AND circuit 33. This causes the phase comparison circuit 3B to output the source signal S1 and sink signal S2 shown in Fig. 6, and the phase comparison circuit 3B executes the second control.

[0044] This makes it possible to maintain high linearity in the characteristics of the average output current of the charge pump circuit 4 relative to the phase difference even if the time difference ΔT becomes larger than the delay time Td.

[0045] Next, in order to confirm the effect of this embodiment, the inventors created a PLL circuit 1 incorporating the phase comparison circuit 3B shown in Fig. 6, and a PLL circuit incorporating a phase comparison circuit using only a conventional current breeding method, and performed FFT (Fast Fourier Transform) on the control voltage input to the VCO 6 when locking was detected. The results are shown in Figs. 8 and 9. As shown in Figs. 8 and 9, in the conventional phase comparison circuit, large spurious signals (indicated by arrows) were generated during the phase comparison period, whereas in the phase comparison circuit 3B of this embodiment, the spurious signals can be reduced.

[0046] The inventors also created a PLL circuit 1 incorporating the phase comparison circuit 3B shown in Fig. 6, and a PLL circuit incorporating a phase comparison circuit using only a conventional current breeding method, and performed FFT on the output signal Φout, which is the output of VCO 6 when locked. The results are shown in Fig. 10 and Fig. 11. As shown in Fig. 10 and Fig. 11, in the conventional phase comparison circuit, the difference between the signal component at the oscillation frequency and the spurious is only -80 dBc, whereas in the phase comparison circuit 3B of this embodiment, the difference can be as large as -115 dBc.

[0047] FIG. 12 is an enlarged view of the vicinity of the oscillation frequency in FIG. 10, and FIG. 13 is an enlarged view of the vicinity of the oscillation frequency in FIG. 11. As is clear from FIGS. 12 and 13, the phase comparison circuit 3B of this embodiment can reduce noise components overall as compared to the conventional phase comparison circuit.

[0048] The present invention is not limited to the above-described embodiment, and can be appropriately modified, improved, etc. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiment are arbitrary as long as the present invention can be achieved, and are not limited.

[0049] In the above-described embodiment, the first pulse signal is the reference signal Φref and the second pulse signal is the feedback signal Φfb, but this is not limited to the above. The first pulse signal may be the feedback signal Φfb and the second pulse signal may be the reference signal Φref. In this case, the feedback signal Φfb may be supplied to the input of the delay circuit 311.

[0050] In the above-described embodiment, the output from the Q terminal of the D flip-flop circuit 32, which has a fixed pulse length, is inverted to output the source signal S1, and the output from the Q terminal of the D flip-flop circuit 33 corresponding to the time difference ΔT is output as the sink signal S2, but this is not limited to the above. For example, the output from the Q terminal of the D flip-flop circuit 32 may be output as the sink signal S2, and the output from the Q terminal of the D flip-flop circuit 33 may be inverted to output as the source signal S1.

[0051] The above-mentioned lock detection circuit 37 detects the time difference ΔT as being locked when it is equal to or less than the delay time Td, but this is not limited to this. The lock detection circuit 37 may also detect the time difference ΔT as being locked when it is equal to or less than a predetermined value set equal to or less than the delay time Td.

[0052] In the above-described embodiment, the phase comparator circuits 3 and 3B are applied to the PLL circuit 1 of the decimal point division type, but the present invention is not limited to this. They may be applied to the PLL circuit 1 whose division ratio is an integer. [Explanation of symbols]

[0053] 1 PLL circuit 3 Phase comparison circuit 4. Charge pump circuit 5 Loop Filter 6 VCO 7 Frequency divider 31 Reset circuit (first reset circuit) 32 D flip-flop circuit (first D flip-flop circuit) 33 AND circuit (first AND circuit) 35 D flip-flop circuit (second D flip-flop circuit) 36 AND circuit (second AND circuit) 37 Lock detection circuit 38 AND circuit (second reset circuit) 39 Bleed circuit (third reset circuit) 41 Source current source 42 Sink current source 310A, 310B switching circuit Sr1 Reset signal (first reset signal) Sr2 Reset signal (second reset signal) Sr3 Reset signal (third reset signal) Td Delay time (first predetermined time) ΔT Time difference Φref Reference signal (first pulse signal) Φfb Feedback signal (second pulse signal)

Claims

1. A phase comparison circuit for controlling a charge pump circuit having a source current source that supplies a source current to a loop filter and a sink current source that draws up a sink current from the loop filter in response to a time difference between rising edges of a first pulse signal and a second pulse signal, a first control can be executed in which one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a first predetermined time has elapsed, and when the phase of the first pulse signal is slower than the phase of the second pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time + the time difference) has elapsed, and when the phase of the second pulse signal is slower than the phase of the first pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time - the time difference) has elapsed. Phase comparison circuit.

2. 2. The phase comparison circuit according to claim 1, when the phase of the first pulse signal is delayed relative to the phase of the second pulse signal, one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a second predetermined time has elapsed, and the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal to the rising edge of the first pulse signal; when a phase of the second pulse signal is delayed compared to a phase of the first pulse signal, a second control can be executed to connect one of the source current source and the sink current source to the loop filter during a period from a rising edge of the first pulse signal to a rising edge of the second pulse signal and during a period from a rising edge of the second pulse signal to a time when the second predetermined time has elapsed; When the time difference is equal to or smaller than a predetermined value, the first control is executed, and when the time difference is larger than the predetermined value, the second control is executed. Phase comparison circuit.

3. 2. The phase comparison circuit according to claim 1, a first reset circuit that outputs a first reset signal after the first predetermined time has elapsed since the rising edge of the first pulse signal; a first D flip-flop circuit having a clock terminal to which the first pulse signal is input and a D terminal to which an H level is constantly input; a first AND circuit having an input connected to an output of the first reset circuit and a Q terminal of the first D flip-flop circuit, and an output connected to a reset terminal of the first D flip-flop circuit; a second D flip-flop circuit having a clock terminal to which the second pulse signal is input and a D terminal to which an H level is constantly input; a second AND circuit to which an output of the first reset circuit and a Q terminal of the second D flip-flop circuit are input and an output of the second AND circuit is connected to a reset terminal of the second D flip-flop circuit; Phase comparison circuit.

4. 4. The phase comparison circuit according to claim 3, a lock detection circuit that detects a lock when the time difference is equal to or smaller than a predetermined value; a second reset circuit that outputs a second reset signal at a timing when one of the first pulse signal and the second pulse signal, whichever rises later, rises; a third reset circuit that outputs a third reset signal after a second predetermined time has elapsed since the second reset signal was output; a switching circuit for connecting an output of the first reset circuit to an input of the first AND circuit and the second AND circuit when the lock detection circuit detects a lock, and for connecting an output of the second reset circuit to an input of the second AND circuit and an output of the third reset circuit to an input of the first AND circuit when the lock detection circuit does not detect a lock. Phase comparison circuit.

5. a phase comparison circuit which sets one of the reference signal and the feedback signal as a first pulse signal and the other as a second pulse signal, and compares the phases of the first pulse signal and the second pulse signal; a charge pump circuit having a source current source for supplying a source current and a sink current source for drawing up a sink current, the charge pump circuit being controlled by the phase comparison circuit; a loop filter that converts the current output from the charge pump circuit into a voltage and outputs a control voltage; a VCO that outputs an output signal having a frequency corresponding to the control voltage; a frequency divider that divides the frequency of the output signal and inputs the divided signal to the phase comparison circuit as the feedback signal, a first control can be executed in which one of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the first pulse signal until a first predetermined time has elapsed, and when the phase of the first pulse signal is slower than the phase of the second pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time+a time difference between the rising edges of the first pulse signal and the second pulse signal) has elapsed, and when the phase of the second pulse signal is slower than the phase of the first pulse signal, the other of the source current source and the sink current source is connected to the loop filter during a period from the rising edge of the second pulse signal until (the first predetermined time-the time difference) has elapsed. PLL circuit.

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