Semiconductor device and power conversion device

Abstract

To provide a semiconductor device and a power conversion device, capable of realizing a high-damage resistance amount while suppressing an increase of a conduction loss and an influence of a modulation of a threshold value voltage.SOLUTION: In a semiconductor chip 200, a selective crystal defect region 237 is provided in a drift layer 234 containing at least a main bonding region 224 so as to surround an active region 210. When a density of a crystal defect of the main bonding region 224 is higher than that of the crystal defect of the active region 210, or a depth that the density of the crystal defect becomes the maximum from a boundary surface of a front surface oxidation film 233 of the semiconductor device is d_max238, an average of the density of the crystal defect up to the depth d_max238 in the main bonding region 224 is higher than that of the density of the crystal defect of the active region 210, and the depth d_max238 is formed onto a back surface side from 40% of a thickness D of a drift layer of the semiconductor device.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a power conversion device. [Background technology]

[0002] IGBTs (Insulated Gate Bipolar Transistors), which can switch large currents at high speeds, are widely used as power conversion devices for driving electric motors and the like. IGBTs are required to have high current densities and high resistance to interrupt large currents flowing through them without destroying the elements. As the current density of IGBTs increases, there is a problem in that the resistance decreases when the IGBT is turned off. To address this problem, techniques are known that improve turn-off resistance by lifetime control through the introduction of crystal defects, as shown in Patent Documents 1 and 2.

[0003] IGBTs have the problem that the turn-off interruption capability (RBSOA) decreases due to high current density. In particular, in high-voltage IGBTs used in electric railways, the area of ​​the guard ring region for maintaining the withstand voltage, which is placed around the periphery of the device, becomes larger, and the carriers accumulated in the periphery increase, which causes the phenomenon of current concentration near the main junction on the surface when the device is turned off.

[0004] Patent Document 1 describes a technique for suppressing temperature distribution within a semiconductor chip by introducing crystal defects into the surface of the semiconductor chip that constitutes a semiconductor device.

[0005] Patent Document 2 describes a technique for providing a semiconductor device with high resistance to avalanche breakdown by introducing crystal defects into a limited irradiation area from the back surface of a semiconductor chip. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2005-197472 A [Patent Document 2] JP 2015-153784 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, the technologies described in Patent Documents 1 and 2 involve ion irradiation that includes the conductive region (active region) of the semiconductor chip to introduce crystal defects, which poses the risk of increased conduction loss (on-state voltage) and fluctuations in threshold voltage due to light ion irradiation of the gate oxide film in the active region.

[0008] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor device and a power conversion device that can achieve high breakdown resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage. [Means for solving the problem]

[0009] In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device comprising: an active region which vertically conducts current between a main surface and a back surface of a semiconductor substrate and which is a current conduction region; and a peripheral region which is arranged to surround the active region, the peripheral region having a main junction region, an FLR region, and an edge region, the main junction region being provided between the active region and the FLR region, the active region and the peripheral region having a drift layer made of an integral substrate, the drift layer having a selective crystal defect region caused by light ion irradiation, a crystal defect region is provided in a drift layer including at least the main junction region so as to surround the active region, and a density of crystal defects in the main junction region is higher than a density of crystal defects in the active region; or, when a depth from an interface of a surface oxide film of the semiconductor device to a depth d_max at which the density of crystal defects is maximum is defined as a depth d_max, an average density of crystal defects in the main junction region up to the depth d_max is higher than an average density of crystal defects in the active region, and the depth d_max is formed on the back surface side more than 40% of a thickness D of the drift layer of the semiconductor device. Effect of the Invention

[0010] According to the present invention, it is possible to provide a semiconductor device and a power conversion device that can realize high breakdown voltage resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing an overall configuration of an electric motor control system using a power conversion device to which a semiconductor device according to a first embodiment of the present invention is applied; [Diagram 2] 1 is a plan view of a semiconductor chip that constitutes a semiconductor device according to a first embodiment of the present invention. [Diagram 3] 1 is a cross-sectional view taken along line AB of a semiconductor chip according to a first embodiment of the present invention. [Figure 4]2 is a schematic diagram showing a transitional current path at the time of turn-off in a cross section taken along line AB of the semiconductor chip according to the first embodiment of the present invention. FIG. [Diagram 5] 3A to 3C are schematic diagrams showing the depth direction distribution of crystal defect density along the lines ab and cd of the semiconductor chip according to the first embodiment of the present invention. [Figure 6] FIG. 1 is a diagram showing the effect of the present invention. [Figure 7] FIG. 1 is a diagram showing the effect of the present invention. [Figure 8] FIG. 13 is a diagram showing a modified example of the first embodiment of the present invention. [Figure 9] FIG. 11 is a diagram showing the effect of the modified example of the first embodiment of the present invention. [Figure 10] 3 is an enlarged view of a region C in the semiconductor chip shown in FIG. 2. [Figure 11] 11A is a cross-sectional view taken along the DE of a semiconductor chip according to a second embodiment of the present invention, and a schematic diagram showing a transitional current path at the time of turn-off. FIG. [Figure 12] FIG. 11 is a diagram showing a modified example of the second embodiment of the present invention. [Figure 13] FIG. 11 is a plan view of a semiconductor chip according to a third embodiment of the present invention, and a diagram showing a connection form with a gate driver. [Figure 14] 11 is a cross-sectional view taken along PQ of a semiconductor chip according to a third embodiment of the present invention. FIG. [Figure 15] 11 is a cross-sectional view taken along the RS of a semiconductor chip according to a third embodiment of the present invention. FIG. [Figure 16] FIG. 11 is a diagram showing a drive sequence of a gate drive device according to a third embodiment of the present invention. [Figure 17] FIG. 13 is a diagram showing a structure of a unit cell in an active region of a semiconductor chip, which is a modified example of the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate. (First embodiment) 1 is a diagram showing the overall configuration of an electric motor control system 100 using a power conversion device according to a first embodiment of the present invention. The power conversion device is a device that converts electric power using power semiconductor devices. In this embodiment, the electric motor control system 100 using an inverter circuit to which IGBTs are applied as power semiconductor devices will be described as an example.

[0013] The motor control system 100 includes a DC power supply 10, an inverter circuit 20, and an electric motor 70. The inverter circuit 20 includes a smoothing capacitor 21, inverter units 30 for three phases, UVW (a U-phase inverter unit 30U, a V-phase inverter unit 30V, and a W-phase inverter unit 30W), and a command logic unit 22. The inverter circuit 20 outputs AC power based on DC power supplied from the DC power source to drive the electric motor 70. A smoothing capacitor 21 is provided between the DC power source 10 (power source voltage=Vcc) and the positive electrode connection line 23 and the negative electrode connection line 24 of the inverter circuit 20.

[0014] The inverter unit 30 is made up of upper and lower arms, and has a series circuit of semiconductor devices 31. Each of the semiconductor devices 31 in the upper and lower arms is composed of an IGBT. A gate signal is transmitted to the IGBT from a gate driver 40. A high potential terminal of the IGBT in the upper arm is connected to a first end (positive electrode connection line 23) of the smoothing capacitor 21. A low potential terminal of the IGBT in the upper arm is connected to a high potential terminal of the IGBT in the lower arm. A low voltage terminal of the IGBT in the lower arm is connected to a second end (negative electrode connection line 24) of the smoothing capacitor 21.

[0015] In each phase, a connection point 33 between the low potential side terminal of the IGBT in the upper arm and the high potential side terminal of the IGBT in the lower arm is connected to one end of a winding of a motor 70. The other end of the winding of each phase is connected to a neutral point. The motor 70 is, for example, an induction motor.

[0016] A freewheel diode 32 (freewheel diode) is connected in inverse parallel to each IGBT. As the freewheel diode 32, various diodes can be used, such as a pn junction diode, a Schottky barrier diode, or a diode that uses both a pn junction and a Schottky junction.

[0017] The command logic unit 22 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate drive device 40 as a drive command signal P for the semiconductor device 31. As a result, the command logic unit 22 alternately turns on the semiconductor device 31 of the upper arm and the semiconductor device 31 of the lower arm in each phase to control the control amount of the electric motor 70 to the command value. The control amount is, for example, the torque of the electric motor.

[0018] The gate driving devices 40 are provided corresponding to the respective semiconductor devices 31, and receive a driving command signal P from the command logic unit 22, and turn the semiconductor device 31 on or off based on the received driving command signal P.

[0019] Fig. 2 is a plan view of a semiconductor chip 200 constituting the semiconductor device 31 according to the first embodiment. Fig. 2 shows a semiconductor chip constituting a semiconductor device related to the lower arm of the U-phase in the inverter circuit 20 shown in Fig. 1. Other semiconductor devices in the upper arm of the U-phase and the upper and lower arms of the V-phase and W-phase have the same configuration. The semiconductor device 31 may be in the form of a power module (IGBT module) in which a plurality of semiconductor (IGBT) chips as shown in Fig. 2 are mounted in parallel.

[0020] In the following, the configuration and operation of the semiconductor device 31 of the lower arm of the U phase and its gate drive device 40 will be described, but the configurations and operations of the other semiconductor devices and their gate drive devices are similar.

[0021] The semiconductor chip 200 is composed of an active region 210 and a non-active region 220. The active region 210 is a region where a current flows, for example, a region where an emitter electrode is formed. The non-active region 220 is a region where a current does not flow, for example, an outer peripheral region 221 having a guard ring for maintaining a withstand voltage, a gate finger region 222 which is a wiring region for supplying power to the gate, and a gate pad 223 which is a pad region connected to the gate finger and supplies power to the gate.

[0022] FIG. 3 is a cross-sectional view taken along line AB of the semiconductor chip 200 of the first embodiment. As shown in Fig. 3, the active region 210 is a region inside the left end X of an electric field relaxation layer (main junction) 229 made of a p-type semiconductor, which is the region AX in Fig. 3. The peripheral region 221 is a region outside the left end X of the main junction 229, which is the region XB in Fig. 3. The peripheral region 221 is composed of a main junction region 224, an FLR region 225, and an edge region 226. The FLR region 225 is a region in which the guard ring 231 exists, extending from the right end Y of the main junction 229 to the left end Z of the electric field blocking layer (channel stopper) 232. The FLR region 225 is provided to maintain the breakdown voltage of the semiconductor chip 200 by electric field relaxation caused by the electric field relaxation layer (guard ring) 231 made of a plurality of p-type semiconductors.

[0023] 3, where a main junction 229 is located and is sandwiched between the active region 210 and the FLR region 225. The main junction region 224 is provided to suppress current concentration and electric field concentration when the semiconductor chip 200 is turned off. The edge region 226 is a region from the left end Z of the electric field blocking layer (channel stopper) 232 made of a high concentration n-type semiconductor to the chip end B, which is the region ZB in FIG.

[0024] As shown in FIG. 3, a collector electrode 212 is present over the entire back surface of the semiconductor chip 200. A high-concentration p-type semiconductor layer (p-emitter layer) 236, which is a hole injection layer, is present so as to contact the collector electrode 212. A high-concentration n-type semiconductor layer (n-buffer layer) 235 is present on the upper surface of the p-emitter layer 236. An n-type semiconductor layer (n-drift layer) 218 ​​having a lower concentration than the n-buffer layer region 235 is present on the upper surface of the n-buffer layer 235 in the active region 210. A p-type semiconductor layer (p-base layer) 217 ​​is present on the upper surface of the n-drift layer 218 in the active region 210. A trench-type gate electrode 213 is provided so as to straddle the p-base layer 217 and the n-drift layer 218 in the active region 210.

[0025] An emitter electrode 211 is present on the front surface side of the active region 210. A gate insulating film 215 is present between the gate electrode 213 and the emitter electrode 211. The gate electrode 213 is covered with a gate oxide film 214 and a gate insulating film 215, and is electrically insulated from the emitter electrode 211. A high-concentration n-type semiconductor layer (n+ emitter layer) 216 is present in a portion of the p-base layer 217 of the active region 210 that contacts the gate insulating film 215, so as to contact the gate oxide film 214.

[0026] A surface oxide film 233 is present on the surface side of the peripheral region 221. An n-drift layer 234 is also present on the n-buffer layer 235 in the peripheral region 221. The n-drift layer 218 and the n-drift layer 234 are formed as an integral substrate. A gate wiring 227 and a field plate (main junction FP) 228 are present on the surface oxide film 233 of the main junction region 224.

[0027] A main junction 229 exists under the surface oxide film 233 of the main junction region 224. A plurality of field plates 230 exist on the surface oxide film 233 of the FLR region 225. A plurality of guard rings 231 exist under the surface oxide film 233 of the FLR region 225.

[0028] In the n-drift layer 234 of the main junction region 224 and the FLR region 225 shown in Fig. 3, there exists a depth (d_max) 238 where the crystal defect density (density of crystal defects) is maximum, and the region from the surface oxide film 233 to d_max 238 (Fig. 5 described later) becomes a range region 237 (Fig. 5 described later). A channel stopper 232 exists under the surface oxide film 233 of the edge region 226 shown in Fig. 4.

[0029] [Operation description] The operation of the semiconductor chip 200 will now be described. When a positive voltage is applied to the collector electrode 212 (FIG. 3) of the semiconductor chip 200 with respect to the emitter electrode 211, power is supplied from the gate driver 40 of FIG. 1 to the gate electrode 213 of the semiconductor chip 200 of FIG. 3 via the gate pad 223 and gate finger region 222 of FIG. 2, and when a voltage exceeding the threshold voltage of the semiconductor chip 200 is applied between the gate electrode 213 and the emitter electrode 211, the semiconductor surface of the p-base layer 217 in contact with the gate oxide film 214 is strongly inverted, the electron concentration increases, and an n-type inversion layer is formed.

[0030] 3 are connected via an n-type inversion layer, and electrons are injected from the n+ emitter layer 216 into the n- drift layer 218. The injected electrons reach the vicinity of the n buffer layer 235 and the p emitter layer 236 on the back surface, forward biasing the pn junction between the p emitter layer 236 and the n buffer layer 235, and holes are injected from the p emitter layer 236. In this way, conductivity modulation occurs in the n- drift layer 218 of the active region 210, and the semiconductor chip 200 becomes conductive (ON state).

[0031] At this time, holes are also injected from p-emitter layer 236 on the back surface of peripheral region 221 shown in FIG. 3, so the injected holes are accumulated not only in n-drift layer 218 in active region 210 but also in n-drift layer 234 in the peripheral region.

[0032] When the voltage applied from gate driver 40 (FIG. 1) to gate electrode 213 of semiconductor chip 200 (FIG. 3) falls below the threshold voltage, the n-type inversion layer of semiconductor chip 200 disappears, injection of electrons from n+ emitter layer 216 into n- drift layer 218 stops, and semiconductor chip 200 begins to shut down (turn off).

[0033] Since semiconductor chip 200 is a bipolar device, even if the injection of electrons from n+ emitter layer 216 stops, the tail current continues to flow until the holes accumulated in n- drift layer 218 in active region 210 and n- drift layer 234 in the peripheral region are discharged from emitter electrode 211 on the surface, and turn-off does not end.

[0034] Fig. 4 is a schematic diagram showing a transient current path at the time of turn-off in a cross section taken along line AB of the semiconductor chip 200 shown in Fig. 2. Fig. 4 simulates a current path 700 through which holes accumulated in the n-drift layer 234 of the peripheral region 221 at the time of turn-off pass through to the emitter electrode 215, and equipotential lines 701 at the time of turn-off. Most of the holes accumulated in the outer periphery region 221 are discharged to the emitter electrode 211 through the electric field relaxation layer 229 of the main junction region 224 according to the potential gradient, as shown in FIG.

[0035] [Detailed explanation of the challenges in improving interruption resistance] 3 and 4 is covered with a surface oxide film 233, and no current flows through it. During turn-off, the depletion layer extends vertically in the active region 210 and horizontally in the peripheral region 221, so that equipotential lines in the main junction region 224 and the FLR (Field Limiting Ring) region 225 are distributed as shown in FIG. 4. As a result, as shown by the current path 700 in FIG. 4, most of the holes accumulated in the peripheral region 221 flow as a hole current as shown in FIG. 4 according to the potential gradient, and as a result, a current transiently concentrates in the electric field relaxation layer 229 of the main junction region 224.

[0036] Furthermore, in a transient state in which holes are being discharged during turn-off, the concentration of holes accumulated in n-drift layer 234 in the peripheral region is higher than that in the steady off state, and therefore the electric field is not sufficiently relaxed by electric field relaxation layer 231 in FLR region 225 and electric field relaxation layer 229 in main junction region 224. As a result, a dynamic avalanche occurs at the junction portion (253 in FIG. 4) between electric field relaxation layer 229 in main junction region 224 and n-drift layer 234, where the electric field and current are particularly concentrated.

[0037] The avalanche current generated by this dynamic avalanche locally heats the semiconductor chip 200, causing a parasitic npn transistor in the active region to operate, resulting in a latch-up state in which on / off control by the gate is no longer possible, and the semiconductor chip 200 is destroyed. In other words, there is a problem in that the turn-off resistance is reduced.

[0038] [Improvement method] In this embodiment, when holes accumulated in the n-drift layer 234 in the peripheral region are discharged at the time of turn-off, they flow via the electric field relaxation layer 229 in the main junction region 224, causing current concentration and reducing the turn-off resistance, which is an adverse effect of increasing the current density. This method is provided to improve this problem. The cross-sectional structure of a semiconductor chip 200 for solving this problem will be described with reference to FIG. Crystal defects are introduced by irradiating light ions from the surface so as to include the electric field relaxation layer 229 of the main junction region 224 where current concentration and electric field concentration occur. These crystal defects have a depth (d_max) 238 (see FIG. 5 below) at which the crystal defect density is maximum, and there is a region (crystal defect region) called the range region 237, which is the passage region of the light ions, where crystal defects exist due to the passage of the light ions, between the surface oxide film 233 and the depth (d_max) 238 at which the crystal defect density is maximum.

[0039] When introducing these crystal defects, the crystal defects are introduced by irradiating light ions from the surface so as to avoid the gate oxide film 214 in the active region 210, thereby making it possible to reduce the concentration of holes accumulated in the n-drift layer 234 in the peripheral region without increasing the on-voltage (Vcesat). In addition, since the gate oxide film 214 in the active region 210 is not affected by the irradiation of light ions, it is possible to suppress fluctuations in the threshold voltage.

[0040] FIG. 5 is a diagram showing the depth distribution of crystal defect density along ab in the main junction region 224 of the semiconductor chip 200 shown in FIG. 3 and the depth distribution of crystal defect density along cd in the active region 210. In FIG. Since the active region 210(cd) shown in Fig. 3 is not irradiated with light ions, the crystal defect density is almost constant at a low value from the front surface to the back surface. On the other hand, in the main junction region 224(ab), crystal defects are generated due to the irradiation of light ions from the front surface, and a region with a high crystal defect density due to the passage of light ions, that is, a range region 237 (Fig. 5), exists on the front surface side of the depth (d_max) 238 where the crystal defect density is maximum.

[0041] In the regions where the above crystal defects exist, i.e., the range region 237 (Fig. 5) and the depth (d_max) 238 (Fig. 3) where the crystal defect density is maximum, the carrier lifetime is shorter than in regions where crystal defects do not exist. In other words, carrier recombination occurs more easily than in other regions of the n-drift layer, and the number of accumulated holes can be suppressed.

[0042] In addition, since the region where crystal defects exist has a short lifetime and a relatively low carrier density, when comparing the resistivities of the substrate in the region where the n-drift layer exists in the semiconductor chip 200, the following magnitude relationship holds: That is, between the resistivity ρ1 in the n-drift layer 237 in the range region 237, the resistivity ρ2 at the depth (d_max) 238 where the crystal defect density is maximum, and the resistivity ρ3 in the n-drift layer 218 in the active region 210, ρ3<ρ1<ρ2 A magnitude relationship is established.

[0043] Furthermore, by forming the depth (d_max) 238 where the crystal defect density is maximum on the back side of the semiconductor chip 200, a light ion passage region (crystal defect region) 237, which is a range region where the carrier lifetime is short, is formed up to a region close to the back side. As a result, recombination of holes and electrons injected from the p emitter layer 236 in the peripheral region 221 can be promoted, and the transport efficiency of holes from the p emitter layer 236 to the emitter electrode 211 can be more effectively suppressed. Therefore, when holes accumulated in the n-drift layer 234 in the peripheral region are discharged at turn-off, current concentration caused by the holes flowing through the electric field relaxation layer 229 in the main junction region 224 can be more effectively suppressed, and the turn-off resistance can be improved.

[0044] As described above, when light ions are selectively irradiated from the surface of the peripheral region 221 of the semiconductor chip 200 so as to include at least the main junction region 224, a range region 237 in which carrier lifetime is short is formed on the surface side of the peripheral region 221 including at least the electric field relaxation layer 229 of the main junction region 224. As a result, the carrier concentration accumulated in the n-drift layer 234 of the peripheral region decreases, and the width of the depletion layer formed from the electric field relaxation layer 229 of the main junction region 224 to the n-drift layer 234 of the peripheral region at the time of turn-off increases, so that the interval between the equipotential lines 701 in the vicinity of the junction portion (253 in FIG. 4) between the electric field relaxation layer 229 and the n-drift layer 234 in FIG. 4 also increases, and the electric field intensity in the vicinity of the electric field relaxation layer 229 of the main junction region 224 is relaxed. Furthermore, due to the effect of the above-mentioned range region 237 where the carrier lifetime is short, holes accumulated in the n-drift layer 234 in the peripheral region are prevented from concentrating in the electric field relaxation layer 229 of the main junction region 224 at turn-off, so that current concentration in the vicinity of the electric field relaxation layer 229 can also be suppressed.

[0045] Since dynamic avalanche is caused by the concentration of electric field and current, these effects suppress dynamic avalanche occurring in the electric field relaxation layer 229 of the main junction region 224. As a result, it is possible to prevent a latch-up state in which the avalanche current generated by dynamic avalanche locally heats the semiconductor chip 200 and the parasitic npn transistor in the active region operates, making on / off control by the gate impossible, thereby improving the turn-off resistance and making the semiconductor chip 200 less likely to be destroyed.

[0046] Furthermore, since no crystal defects are introduced into the active region 210 or the gate oxide film 214 within the active region 210, the breakdown voltage can be improved without causing an increase in the on-voltage (Vcesat) or a change in the threshold voltage.

[0047] In the following, a method of selectively forming the range region 237 from the back surface side of the semiconductor chip 200 will be referred to as a conventional technique (τCC) and will be used for comparison. Fig. 6 is a diagram showing the effect of the semiconductor chip 200 of this embodiment. The vertical axis of Fig. 6 shows the maximum value of the current that can be cut off when the semiconductor chip 200 is turned off (maximum cut-off current), normalized with the maximum cut-off current when the conventional technology (τCC) is applied as 100%. The horizontal axis of Fig. 6 shows the amount of crystal defects (e.g., the amount of light ion irradiation) introduced into the semiconductor chip 200, normalized with the amount of crystal defects when the conventional technology (τCC) is applied as 100%. In this embodiment (τEC in FIG. 6), a range region 237 is selectively formed from the front side of the semiconductor chip 200 including at least the main junction region 224 so as to include the electric field relaxation layer 229 of the main junction region 224, which is an avalanche point where the electric field and current transiently concentrate at turn-off. Therefore, the same maximum cutoff current can be achieved with a smaller amount of crystal defects than in the conventional technology (τCC) in which the range region is formed from the back side and the electric field relaxation layer 229 is not included. In other words, current concentration in the main junction region can be more effectively suppressed, and a high breakdown resistance of the semiconductor chip can be achieved.

[0048] FIG. 7 is a diagram showing an example of an analysis result showing another effect of the present embodiment, particularly a trade-off between leakage current and the number of accumulated carriers in the outer peripheral region. The vertical axis in FIG. 7 shows the number of accumulated carriers in the outer peripheral region of the semiconductor chip 200, normalized with the case of applying the prior art (τCC) being 100%. The horizontal axis in FIG. 7 shows the leakage current of the semiconductor chip 200, normalized with the case of applying the prior art (τCC) being 1.

[0049] The number of accumulated carriers in the outer peripheral region indicates the number of holes accumulated in the outer peripheral region 221 immediately before the turn-off of the semiconductor chip 200. The smaller the number of accumulated carriers in the outer peripheral region, the lower the current density that transiently concentrates in the vicinity of the electric field relaxation layer 229 in the main junction region 224 at the time of turn-off, and thus the larger the maximum blocking current. That is, the number of accumulated carriers in the outer peripheral region is an index of the maximum blocking current. Also, generally, as the amount of crystal defects introduced into the semiconductor chip 200 increases, the carriers generated in the depletion region increase, resulting in an increase in leakage current and an increase in the heat generation amount when the semiconductor chip is turned off. Therefore, there is a trade-off relationship between leakage current and the number of accumulated carriers in the outer peripheral region.

[0050] In FIG. 7, the trade-off line determined by a semiconductor chip with no crystal defects introduced (without τ control) and a semiconductor chip with crystal defects introduced by irradiating light ions from the back side, which is the prior art (τCC), is shown by a dashed line. For this embodiment (τEC) in which crystal defects are introduced by irradiating light ions from the front side, with respect to this trade-off line, by setting the depth (d_max) at which the crystal defect density becomes maximum to 40% or more of the thickness D of the drift layer, that is, a depth of 0.4D or more, it is shown that the trade-off is improved. Furthermore, in this embodiment (τEC), by setting d_max to 0.5D or more, it is possible to reduce only the leakage current without substantially increasing the number of accumulated carriers in the outer peripheral region. For this purpose, it is preferable to irradiate light ions so as to satisfy the relationship 0.5D ≦ d_max < D.

[0051] [Modification Example of Semiconductor Switching Element] 8 is a diagram showing a modified example of the semiconductor chip according to the first embodiment, in which the same components as those in FIG. For example, when crystal defects are introduced into the main junction region 224 as in this embodiment, as shown in Fig. 8, the crystal defects may be introduced not only into the main junction region 224 but also so as to extend over a portion of the active region 210 adjacent to the main junction region 224. This can also alleviate current concentration in the active region 210, improving the withstand voltage.

[0052] However, if the area of ​​crystal defects introduced into the active region 210 is too wide, the accumulated carriers in the active region during conduction are more likely to disappear due to recombination, resulting in an increase in the on-voltage (Vcesat) and an increase in the conduction loss (Econd).

[0053] Fig. 9 is a diagram showing the effect of the modified example shown in Fig. 8. Fig. 9 shows an example of an analysis result of the dependency of the on-voltage and the number of accumulated carriers in the peripheral region immediately before turn-off on the region of crystal defects (width of the crystal defect region) (intrusion amount ΔX shown in Fig. 8) introduced into the active region 210. The horizontal axis of Fig. 9 shows the ratio of the intrusion amount ΔX of crystal defects into the active region to the thickness D of the drift layer. The left vertical axis of Fig. 9 shows the on-voltage (Vcesat), and the right vertical axis of Fig. 9 shows the number of accumulated carriers in the peripheral region immediately before turn-off, both normalized to the case of ΔX=0. According to the inventors' study, the more the penetration amount ΔX into the active region 210 increases, the more Vcesat increases and the number of accumulated carriers in the peripheral region immediately before turn-off decreases. In order to keep the increase rate of Vcesat to 1% or less, it is preferable that the penetration amount ΔX of the crystal defects into the active region 210 is 40% or less of the thickness D of the drift layer.

[0054] [Effects of the first embodiment] As described above, the semiconductor chip 200 (FIGS. 2 to 7) according to the first embodiment conducts current vertically between the main surface and the back surface of the semiconductor substrate, and includes an active region (210) which is a current conduction region, and a peripheral region (221) arranged to surround the active region (210). The peripheral region (221) has a main junction region (224), an FLR region (225), and an edge region (226). The main junction region (224) is provided between the active region (210) and the FLR region (225). The active region (210) and the peripheral region (221) have drift layers (218, 234) made of an integral substrate, and the drift layers (218, 234) have selective crystal defect regions (237) formed by light ion irradiation. The semiconductor device is characterized in that the selective crystal defect region (237) is provided in a drift layer (234) including at least a main junction region (224) so ​​as to surround the active region (210), and the crystal defect density of the main junction region (224) is higher than the crystal defect density of the active region (210), or, when the depth at which the crystal defect density becomes maximum from the interface of a surface oxide film (233) of the semiconductor device is defined as d_max (238), the average crystal defect density up to the depth d_max (238) in the main junction region (224) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed on the back surface side of 40% of a thickness D of the drift layer of the semiconductor device (d_max≧0.4×D).

[0055] As mentioned in the problem to be solved, in high-voltage IGBTs, the area of ​​the guard ring region arranged around the periphery of the device to maintain the breakdown voltage becomes larger, and the carriers accumulated in the periphery increase, resulting in a phenomenon of current concentration near the main junction on the surface at turn-off. When the carriers accumulated in the periphery are discharged at turn-off, they flow through the main junction on the surface, causing current concentration, lowering the RBSOA and hindering higher current densities.

[0056] In this embodiment, protons are selectively irradiated from the surface of the IGBT element so as to avoid the gate oxide film including the gate wiring. In particular, protons are selectively irradiated to the main junction (including the gate finger portion) where current transiently concentrates at turn-off, without irradiating the active region, to form a low lifetime region from the front side of the chip. That is, by introducing crystal defects from the surface to the inactive region while avoiding the gate oxide film, the lifetime of the region where current concentrates at turn-off is made shorter than that of the active region. This makes it possible to alleviate current concentration by selectively reducing the lifetime near the main junction where current transiently concentrates at turn-off while avoiding adverse effects on the on-voltage and threshold voltage. The RBSOA is improved by suppressing current concentration and electric field concentration at turn-off while preventing an increase in the on-voltage.

[0057] As a result, it is possible to achieve high breakdown resistance while suppressing the effects of increased conduction loss and fluctuations in threshold voltage. Because it is possible to achieve both low loss performance and high breakdown voltage performance, it is ideal for systems that require low loss and high reliability, such as EVs and railways, where low loss and high reliability are required for power conversion devices.

[0058] The semiconductor chip 200 according to the first embodiment is characterized in that the inner end of the selective crystal defect region (light ion passage region 237) is closer to the FLR region (225) than the center of the main junction region (224).

[0059] In the semiconductor chip 200 of the first embodiment, the outer end of the selective crystal defect region (light ion passage region 237) is characterized in that it exists in the region from the electric field relaxation layer (231) that is closest to the active region in the FLR region (225) to the edge region (226).

[0060] In the semiconductor chip 200 of the first embodiment, the selective crystal defect region (light ion passage region 237) is characterized in that it is the entire peripheral region (221) including the main junction region (224), the FLR region (225), and the edge region (226).

[0061] In the semiconductor device according to the first embodiment, a part of the selective crystal defect region (237) penetrates into the active region (210) adjacent to the main junction region (224), and the width (ΔX) of the crystal defect region penetrating into the active region (210) is 40% or less of the thickness D of the drift layer (0 ≦ ΔX ≦ 0.4 × D).

[0062] In the semiconductor device according to the first embodiment, when comparing the resistivity of the substrates of the drift layers (218, 234), the resistivity ρ2 of the selective crystal defect region (237), the resistivity ρ2 at the depth d_max (238) where the crystal defect density is maximum, and the resistivity ρ3 of the active region (210), the magnitude relationship of ρ3 < ρ1 < ρ2 holds.

[0063] In the semiconductor device according to the first embodiment, the depth d_max (238) exists in the range of 0.5 × D ≦ d_max < D with respect to the chip thickness D of the semiconductor device.

[0064] (Second Embodiment) FIG. 10 is an enlarged view of a region C in the semiconductor chip according to the second embodiment of the present invention. FIG. 10 is a plan view showing an enlarged view of the region C in FIG. 2, that is, the vicinity of the gate finger region 222 (the region of the gate finger). As shown in FIG. 10, the gate finger region 222 is composed of a gate wiring 227 and a surface oxide film 250 of the gate finger region provided thereunder. The gate finger region 222 exists at a position sandwiched between both sides of the active region 210. FIG. 10 schematically shows the planar positional relationship between the emitter electrode 211 of the active region 210 and the gate electrode 213 thereunder on both sides of the gate wiring 227 of the gate finger region 222.

[0065] FIG. 11 is a cross-sectional view of the semiconductor chip according to the second embodiment along D-E in FIGS. 2 and 10. FIG. 11 is a schematic diagram showing a transient current path during turn-off. 11, the gate finger region 222 is a part of the components of the semiconductor chip 200, and therefore the presence of the collector electrode 212, the high concentration p-type semiconductor layer (p emitter layer) 236, the high concentration n-type semiconductor layer (n buffer layer) 235, and the low concentration n-type semiconductor layer (n-drift layer) 218 ​​is similar to that of the first embodiment in FIG 2. The active regions 210 present on both sides of the gate finger region 222 are also similar to that of the first embodiment.

[0066] A gate electrode 227 is present on the surface of the gate finger region 222. A surface oxide film 250 of the gate finger region is present below the gate electrode 227, and the gate wiring 227 is electrically insulated from the emitter electrode 211 and the n-drift layer of the active region 210. An electric field relaxation layer 251 of the gate finger region is present below the surface oxide film 250 of the gate finger region, and is formed deeper than the p-base layer 217 of the active region 210. An n-drift layer 252 in the gate finger region exists between the electric field relaxation layer 251 in the gate finger region and the n-buffer layer 235. In the n-drift layer 252 in the gate finger region, there exists a depth (d_max) 238 where the crystal defects become maximum, and the region from the surface oxide film 233 to d_max 238 becomes a range region 237.

[0067] Current flow lines 700 represent the path of current around gate finger region 222 during turn-off. The difference from the first embodiment is that a crystal defect region (range region 237) is formed by irradiation of light ions from the chip surface not only in the peripheral region 221 of the semiconductor chip 200 but also in the gate finger region 222 located between the active regions 210 on both sides.

[0068] [Operation description] The operation at turn-off will be described focusing on the difference from the first embodiment. 11, an emitter electrode 211 is present on the surface of an active region 210, but no emitter electrode 211 is present in a gate finger region 222, and an n-drift layer 252 in the gate finger region and the emitter electrode 211 are separated by a surface oxide film 250 in the gate finger region. For this reason, there is no path for a current to flow directly upward from the gate finger region 222.

[0069] On the other hand, since the p emitter layer 236, which is the hole injection source, is present over the entire back surface side of the semiconductor chip 200 including the gate finger region 222, the holes injected into the gate finger region 222 from the back surface flow toward the emitter electrode 211 in the active region 210. At this time, there is a problem that the current flow lines 700 are concentrated near the electric field relaxation layer 251 in the gate finger region (253 in FIG. 11), which causes localized heat generation and reduces the withstand capability.

[0070] In addition, the junction (254 in FIG. 11) between the deepest part of the electric field relaxation layer 251 in the gate finger region, which is formed deeper than the p-base layer 217 in the active region 210, and the n-drift layer 252 is a region where an electric field is concentrated. Since the dynamic avalanche is caused by the concentration of an electric field and a current, the dynamic avalanche is likely to occur near the electric field relaxation layer 251 in the gate finger region 222 at the time of turn-off, which is a factor in reducing the breakdown resistance of the semiconductor chip 200.

[0071] 11, when light ions are selectively irradiated from the surface of the gate finger region 222, a range region 237 in which the carrier lifetime is short is formed on the surface side of the gate finger region 222. As a result, the carrier concentration accumulated in the n-drift layer 252 in the gate finger region is reduced, and holes accumulated in the n-drift layer 252 in the gate finger region are prevented from concentrating on the electric field relaxation layer 251 in the gate finger region at the time of turn-off, so that current concentration can be suppressed. In addition, the carrier concentration accumulated in the n-drift layer 252 in the gate finger region is reduced, and the width of the depletion layer formed from the electric field relaxation layer 251 in the gate finger region to the active region 210 is expanded, so that the electric field intensity in the vicinity of the electric field relaxation layer 251 in the gate finger region 222 is reduced.

[0072] Since dynamic avalanche is caused by the concentration of electric field and current, these effects can suppress dynamic avalanche occurring in the electric field relaxation layer 251 in the gate finger region. As a result, localized heat generation can be prevented, and the breakdown resistance of the semiconductor chip 200 can be improved.

[0073] [Modification of semiconductor switching element] Fig. 12 is a diagram showing a modified example of the second embodiment, in which the same components as those in Fig. 11 are given the same reference numerals. As shown in FIG. 12, in the second embodiment, when introducing crystal defects into the gate finger region 222, the crystal defects may be introduced not only into the gate finger region 222 but also so as to extend partially into the active region 210 adjacent to the gate finger region 222 where the current flow lines 700 are concentrated. This also alleviates current concentration in the active region 210, improving the withstand voltage.

[0074] However, if the area of ​​the crystal defects introduced into the active region 210 is too large, as described in the modified example of the first embodiment (FIG. 8), the accumulated carriers in the active region during conduction are likely to disappear due to recombination. This increases the on-state voltage (Vcesat), resulting in an increase in the conduction loss (Econd). Therefore, in order to keep the increase rate of Vcesat to 1% or less, it is preferable that the amount of penetration ΔX of the crystal defects into the active region 210 is 40% or less of the thickness D of the drift layer, even in this embodiment.

[0075] [Effects of the second embodiment] The semiconductor chip 200 according to the second embodiment (FIGS. 2, 8 to 11) conducts current vertically between the main surface and the back surface of a semiconductor substrate, and includes an active region (210) which is a current conduction region, a peripheral region (221) arranged to surround the active region (210), and a gate finger region (222) sandwiched on both sides by the active region (210). The peripheral region (221) includes a main junction region (224), an FLR region (225), The gate finger region (222) has a p-well region (251) provided in contact with the main surface, the p-well region (251) being provided between the active regions (210), and the active region (210) and the gate finger region (222) have a drift layer (218, 252) formed of an integral substrate. The semiconductor device has a selective crystal defect region (237) formed in the drift layer (218, 252) by light ion irradiation, the selective crystal defect region (237) is provided in the drift layer (252) including at least a gate finger region (222) so as to be sandwiched between the active region (210), and the crystal defect density of the gate finger region (222) is higher than the crystal defect density of the active region (210), or, when the depth at which the crystal defect density becomes maximum from the interface of the surface oxide film (233) of the semiconductor device is defined as d_max (238), the average crystal defect density up to the depth d_max (238) in the gate finger region (222) is higher than the average crystal defect density of the active region (210), and the depth d_max (238) is formed on the back surface side of 40% of the thickness D of the drift layer of the semiconductor device (d_max≧0.4×D).

[0076] In this way, the semiconductor chip 200 according to the second embodiment can prevent holes accumulated in the n-drift layer 252 in the gate finger region from concentrating in the electric field relaxation layer 251 in the gate finger region at the time of turn-off, thereby suppressing current concentration. In addition, the width of the depletion layer formed from the electric field relaxation layer 251 in the gate finger region to the active region 210 is expanded, thereby reducing the electric field intensity in the vicinity of the electric field relaxation layer 251 in the gate finger region 222. It is possible to suppress dynamic avalanche occurring in the electric field relaxation layer 251 in the gate finger region. As a result, localized heat generation can be prevented, and the breakdown resistance of the semiconductor chip 200 can be improved.

[0077] Furthermore, by setting the amount of intrusion ΔX of crystal defects into the active region 210 to 40% or less of the thickness D of the drift layer, the rate of increase in the on-state voltage (Vcesat) can be suppressed to 1% or less.

[0078] In the semiconductor chip 200 according to the second embodiment, the gate finger region (222) is a region that does not include the n+ emitter (216) in the active region (210).

[0079] In the semiconductor device of the second embodiment, the gate finger region (222) is a p-well region (251) sandwiched between active regions (210), and the junction depth of the p-well region (251) is deeper than the bottom depth of a gate electrode (213) formed by a trench gate within the active region (210).

[0080] Third embodiment 13 is a plan view of a semiconductor chip 200 according to a third embodiment of the present invention, and shows a schematic diagram of a connection with a gate driver. The third embodiment differs from the first embodiment in the following respects. First, the semiconductor chip 200 of the third embodiment has two gate pads (321a and 322a, 321b and 322b), and has a first gate pad 321 and a second gate pad 322 that are electrically insulated from each other and can be controlled independently.

[0081] Next, the semiconductor chip 200 is characterized in that two semiconductor chips 200a and 200b having different crystal defect structures are connected in parallel and driven. Also, FIG. 13 shows the connection between the two semiconductor chips 200a and 200b and the gate drive devices that drive them. The first gate pad 321a and the second gate pad 322a of the semiconductor chip 200a and the first gate pad 321b of the semiconductor chip 200b are connected to the first gate drive device 41. Also, the second gate pad 322b of the semiconductor chip 200b is connected to the second gate drive device 42.

[0082] Fig. 14 is a cross-sectional view taken along PQ of the semiconductor chip 200a shown in Fig. 13. The difference from the cross-sectional view of the first embodiment shown in Fig. 3 is that the first gate electrode 239a is connected to the first gate pad 321a shown in Fig. 13, and the second gate electrode 240a is connected to the second gate pad 322a shown in Fig. 13. In this embodiment, the first gate pad 321a and the second gate pad 322a are connected to the first gate drive device 41 and have the same potential, so that the electrical connection form in the semiconductor chip 200a is substantially the same as that in the first embodiment.

[0083] Fig. 15 is a cross-sectional view taken along RS of the semiconductor chip 200b shown in Fig. 13. The difference from the cross-sectional view of the first embodiment shown in Fig. 3 is that there are two types of gate electrodes that can be controlled independently. The differences from Fig. 14 are as follows. First, the second gate electrode 240b is connected to the second gate pad 322b which is connected to the second gate driver 42 shown in Fig. 13. The first gate electrode 239b is connected to the first gate pad 321b shown in Fig. 13. In other words, the first gate electrode 239b and the second gate electrode 240b are independently controlled by separate gate drivers 41 and 42, respectively.

[0084] Next, a difference is that second crystal defect regions (237b, 241b) are formed on the back surface side of the semiconductor chip 200b, across the entire active region 210b and the outer periphery region 221b. The second crystal defect region has a depth (d_max2) 241b where the second defect density is maximum, and a second range region 237b (light ion passage region) is located between the collector electrode 212b and the depth (d_max2) 241b where the second crystal defect density is maximum, which is a region where crystal defects exist due to the passage of light ions.

[0085] In the region where the crystal defects exist, i.e., the second range region 237b and the depth (d_max2) 241b where the second crystal defect density is maximum, the carrier lifetime is shorter than in the region where the crystal defects do not exist, i.e., carrier recombination occurs more easily in this region than in other regions of the n-drift layer.

[0086] In the first embodiment, the purpose of irradiating light ions from the surface of the semiconductor chip 200 was to reduce the number of accumulated holes in the semiconductor chip 200. However, in addition to that purpose, the purpose of irradiating light ions in this embodiment in FIG. 15 is to more effectively suppress current concentration in the main junction region 224b by suppressing the amount of holes injected from the p emitter layer 236b, so that light ions are irradiated over the entire area of ​​the semiconductor chip 200b where the p emitter layer 236b is present.

[0087] 15, the closer the depth (d_max2) 241b at which the second crystal defect density is maximum is to the p-emitter layer 236b, which is the hole injection source, the more effectively the hole injection can be suppressed. Therefore, the depth (d_max2) 241b at which the second crystal defect density is maximum satisfies the condition d_max≦d_max2 <D It is preferable that the following relationship is satisfied.

[0088] As in the first embodiment, the active region 210a of the semiconductor chip 200a does not have any crystal defects, so that the breakdown voltage can be improved without increasing the on-state voltage (Vcesat). In other words, the semiconductor chip has a small loss (Econd) during conduction. On the other hand, the semiconductor chip 200b used in this embodiment has a second crystal defect region over the entire back side of the chip including the active region, so the amount of holes injected from the p emitter layer 236b is reduced, and an increase in the on-voltage (Vcesat) is unavoidable. Now, in this embodiment, the number of holes injected and accumulated in the semiconductor chip 200b is reduced, so the discharge speed of the accumulated carriers during switching is increased, and high-speed switching can be performed. That is, the loss during conduction (Econd) is larger than that of the semiconductor chip 200a, but the loss during switching (turn-off loss: Eoff) is smaller than that of the semiconductor chip 200a.

[0089] 16 is a diagram showing a drive sequence of the first gate drive device 41 and the second gate drive device 42 in this embodiment. The first gate pad 321a and the second gate pad 322a of the semiconductor chip 200a and the first gate pad 321b of the semiconductor chip 200b are connected to the first gate drive device 41. The second gate drive device 42 is connected to the second gate pad 322b of the semiconductor chip 200b.

[0090] When the semiconductor chip 200a and the semiconductor chip 200b are conductive and until just before they are turned off, the first gate driver 41 and the second gate driver 42 apply a voltage (Von) that is equal to or higher than the threshold voltage of the semiconductor chip 200a and the semiconductor chip 200b (see Gs and Gc in Figure 16).

[0091] At the time of turn-off, the output voltage Gc of the first gate driver 41 turns off before the output voltage Gs of the second gate driver 42 and becomes equal to or lower than the threshold voltage Vth of the semiconductor chip 200a (Voff≦Vth), so that the gate of the semiconductor chip 200a, which is a chip with a large amount of accumulated holes and small conduction loss, turns off first, and the extraction of accumulated carriers begins. On the other hand, the semiconductor chip 200b, which is a chip with a small amount of accumulated holes and can be switched at high speed, continues to allow a current to flow through the semiconductor chip 200b, because the output voltage Gs of the second gate driver 42 connected to the second gate pad 322b is equal to or higher than the threshold voltage Vth (Von>Vth). After the delay time (Td_off) between Gc off and Gs off, the output voltage Gs of the second gate driver 42 becomes lower than the threshold voltage (Voff≦Vth), causing the semiconductor chip 200b to turn off, completing the turn-off of the entire semiconductor device consisting of the semiconductor chip 200a and the semiconductor chip 200b connected in parallel.

[0092] [Effects of the third embodiment] The semiconductor chip 200 of the third embodiment (Figures 12 to 16) has a second crystal defect region (237, 241) that includes all of the active region (210), the peripheral region (221), and the gate finger region (222) at a depth d_max (238) or on the back side of the depth d_max (238).

[0093] In the semiconductor chip 200 according to the third embodiment, the semiconductor device is composed of a plurality of semiconductor devices having different on-voltages (Vcesat) or crystal defect densities, and the semiconductor device according to the first embodiment is applied to the semiconductor device of one or more of the components.

[0094] The semiconductor chip 200 according to the third embodiment is composed of a first semiconductor device (Hc chip 200a) to which the semiconductor device of the first embodiment is applied, and a second semiconductor device (Hs chip 200b), the first semiconductor device (Hc chip 200a) and the second semiconductor device (Hs chip 200b) have their respective main surfaces and back surfaces connected to each other (parallel connection), the first semiconductor device (200a) has a first gate electrode (321a, 322a), the second semiconductor device (200b) has a first gate electrode (321b) and a second gate electrode (322b), the first gate electrode (321a, 322a, 321b) is driven and controlled independently by a first gate driver (41), and the second gate electrode (322b) is driven and controlled independently by a second gate driver (42).

[0095] In this way, in the third embodiment, a semiconductor chip 200 having a plurality of gate electrodes is combined with chips (semiconductor chip 200a and semiconductor chip 200b) each having different crystal defects, and a plurality of gate drivers (gate driver 41 and gate driver 42) are driven with a time difference, so that a current mainly flows through the semiconductor chip 200a having a small conduction loss during conduction, thereby realizing a low conduction loss (Econd), and at the time of switching (turn-off), the semiconductor device is cut off (turned off) by the semiconductor chip 200b having a small amount of hole accumulation and capable of switching at high speed, thereby reducing switching loss (turn-off loss: Eoff). In other words, by driving two semiconductor chips having different crystal defect structures with two independent gate drivers with a time difference, it is possible to achieve both reduction in conduction loss and reduction in switching loss, and it is possible to achieve both high breakdown resistance and low loss more effectively than by applying a single semiconductor device and gate driver.

[0096] In addition to introducing different crystal defects into the semiconductor chips connected in parallel, more flexible control of output characteristics is possible by appropriately changing the concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a and the concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b, respectively, and it is not necessarily required that the impurity concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a and the impurity concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b are the same.

[0097] [Modification of semiconductor switching element] For example, by making the impurity concentration of the p emitter layer 236a of the highly conductive semiconductor chip 200a higher than the impurity concentration of the p emitter layer 236b of the high-speed semiconductor chip 200b, the on-voltage of the entire semiconductor device consisting of the semiconductor chips 200a and 200b connected in parallel is further reduced, making it possible to control the output characteristics to an appropriate level depending on the application of the power conversion device to be applied.

[0098] FIG. 17 is a diagram showing a structure of a unit cell in an active region of a semiconductor chip, which is a modification of the third embodiment. The semiconductor device in FIG. 17 is made up of a semiconductor chip 200a and a semiconductor chip 200b connected in parallel. Specifically, the first semiconductor chip 200a (Hc chip 200a), which is a semiconductor chip with high efficiency of hole injection from the collector side, and the second semiconductor chip 200b (Hs chip 200b), which is a semiconductor chip with low efficiency of hole injection from the collector side, are driven in a parallel connected state. That is, the collector electrodes (212a, 212b) and the emitter electrodes (211a, 211b) shown in FIG. 17 are connected to each other.

[0099] The components of the Hc chip 200a and the Hs chip 200b are similar to the components of the active region 210b in FIG. 15 of the third embodiment, except for the impurity concentrations of the p emitter layers (236a, 236b).

[0100] In the third embodiment, the impurity concentrations of the p emitter layers (236a, 236b) of the two semiconductor chips are the same. In contrast, in this modification, the impurity concentration of the p emitter layer 236a of the Hc chip 200a, which is a high conductivity chip, is higher than the impurity concentration of the p emitter layer 236b of the Hs chip 200b, which is a high-speed chip.

[0101] In this modification, the gate electrodes (239a, 239b, 240a, 240b) have a side gate shape that has a small gate parasitic capacitance and enables high-speed switching. However, the gate electrodes (239a, 239b, 240a, 240b) may have a trench gate shape as in Example 3 shown in Figs. 14 and 15.

[0102] The first gate electrode 239a and the second gate electrode 240b of the Hc chip 200a, which is a high conductivity chip, are connected to the first gate driver 41 (Gc). The first gate electrode 239b of the Hs chip 200b, which is a high speed chip, is connected to the first gate driver 41 (Gc), and the second gate electrode 240b is connected to the second gate driver 42 (Gs). In other words, the Hc chip 200a, which is a high conductivity chip, is controlled only by the first gate driver 41 (Gc), and the Hs chip 200b, which is a high speed chip, is independently controlled by both the first gate driver 41 (Gc) and the second gate driver 42 (Gs).

[0103] In this modification, the Hc chip 200a with high conductivity and small conduction loss and the Hs chip 200b with high speed and small switching loss are connected in parallel, and the efficiency of hole injection from the back surface is spatially divided by controlling the impurity concentration of the p emitter layer (236a, 236b). In combination with the drive in which a delay (Td_off) is provided between turning off the Gc gate electrode (239a, 240a, 239b) and turning off the second gate electrode (240b) by the two gate drive devices (41, 42) of this embodiment, the amount of accumulated carriers in the entire drift region from the collector side (back surface) to the emitter side (front surface) can be dynamically (temporally) controlled. As a result, there is an advantage in that the effect of reducing both the conduction loss and the switching loss is enhanced, and the effect of reducing the loss generated in the semiconductor device is further enhanced.

[0104] The present invention is not limited to the above-described embodiments, and includes other modified examples and application examples without departing from the gist of the present invention described in the claims. For example, the above-described embodiments have been described in detail to aid in understanding the present invention, and the present invention is not necessarily limited to those having all of the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another example, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0105] 10 DC power supply 20 Inverter circuit 21 Smoothing capacitor 22 Command logic section 23 Positive connection wire 24 Negative connection wire 30 Inverter unit 31 Semiconductor Devices 32 Freewheeling diode 33 Connection points 40 Gate driver (gate driver circuit) 41 First gate driver 42 Second gate driver 70 Electric motor 100 Motor control system 200, 200a, 200b Semiconductor chip (semiconductor device) 210, 210a, 210b Active Area 211, 211a, 211b Emitter electrode 212, 212a, 212b Collector electrodes 213 Gate electrode 214, 214a, 214b Gate oxide film 215, 215a, 215b Gate insulating film in active area 216, 216a, 216b n+ emitter layer of active area 217, 217a, 217b p-base layer in active area 218, 218a, 218b n-drift layer in active area 220 Inactive Area 221,221a,221b outer area 222,222a,222b Gate finger region 223 Gate Pad 224,224a,224b Main joint area 225,225a,225b FLR area 226, 226a, 226b Edge Region 227, 227a, 227b Gate wiring 228, 228a, 228b Field plate of the main junction region (main junction FP) 229, 229a, 229b Electric field relaxation layer in the main junction region (main junction FP) 230, 230a, 230b Field plate (FP) in FLR region 231, 231a, 231b Electric field relaxation layer (guard ring) in FLR region 232, 232a, 232b Field blocking layer (channel stopper) in edge region 233, 233a, 233b Surface oxide film in the peripheral region 234, 234a, 234b N-drift layer in the peripheral region 235, 235a, 235b n-buffer layer 236, 236a, 236b p emitter layer 237, 237a, 237b Light ion passing region (crystal defect region) 238,238a,238b Depth at which crystal defect density is maximum (d_max) 239, 239a, 239b First gate electrode 240, 240a, 240b Second gate electrode 241b Depth at which the second crystal defect density is maximum (d_max2) 250 Surface oxide film on gate finger region 251 Electric field relaxation layer in gate finger region 252 n-drift layer in gate finger region 253 Current Concentration Point 254 Points where electric fields are concentrated 321, 321a, 321b First gate pad 322, 322a, 322b Second gate pad 700 Current flow line 701 Equipotential Lines

Claims

1. an active region that vertically conducts current between a main surface and a rear surface of the semiconductor substrate and is a current conducting region; a peripheral region disposed so as to surround the active region; The outer periphery region has a main junction region, a field limiting ring (FLR) region, and an edge region, the main junction region is provided between the active region and the FLR region; the active region and the peripheral region have a drift layer formed of an integral substrate; The semiconductor device has a selective crystal defect region formed in the drift layer by light ion irradiation, The selective crystal defect region is a drift layer including at least the main junction region, the drift layer being provided in such a way as to surround the active region; a density of crystal defects in the main junction region is higher than a density of crystal defects in the active region; or When the depth at which the density of crystal defects becomes maximum from the interface of the surface oxide film of the semiconductor device is d_max, The average density of crystal defects up to the depth d_max in the main junction region is higher than the average density of crystal defects in the active region; The depth d_max is formed on the back surface side of 40% of the thickness D of the drift layer of the semiconductor device. A semiconductor device comprising:

2. an active region that vertically conducts current between a main surface and a rear surface of the semiconductor substrate and is a current conducting region; a peripheral region disposed so as to surround the active region; a gate finger area flanked on either side by the active area; The outer periphery region has a main junction region, a field limiting ring (FLR) region, and an edge region, the main junction region is provided between the active region and the FLR region; the gate finger region has a p-well region provided in contact with a main surface, the p-well region is provided between the active regions; the active region and the gate finger region have a drift layer formed of an integral substrate; A semiconductor device having a selective crystal defect region formed by light ion irradiation in the drift layer, The selective crystal defect region is a gate electrode provided in a drift layer including at least a gate finger region so as to be sandwiched between the active regions; a density of crystal defects in the gate finger region is higher than a density of crystal defects in the active region; or When the depth at which the density of crystal defects becomes maximum from the interface of the surface oxide film of the semiconductor device is d_max, The average density of crystal defects in the gate finger region up to the depth d_max is the density of crystal defects in the active region is higher than the average density of crystal defects in the active region, and the depth d_max is formed on the rear surface side of 40% of a thickness D of the drift layer of the semiconductor device. A semiconductor device comprising:

3. The end portion on the inner periphery side of the selective crystal defect region is The FLR region side is closer to the center of the main junction region.

2. The semiconductor device according to claim 1,

4. The end of the selective crystal defect region on the outer periphery side is The FLR region is present in a region extending from the electric field relaxation layer closest to the active region to the edge region.

2. The semiconductor device according to claim 1,

5. The selective crystal defect region is The entire outer periphery region including the main bonding region, the FLR region, and the edge region.

2. The semiconductor device according to claim 1,

6. a portion of the selective crystal defect region extends into the active region adjacent to the main junction region; A width ΔX of a crystal defect region invading the active region is 40% or less of a thickness D of the drift layer.

2. The semiconductor device according to claim 1,

7. When comparing the resistivity of the substrate of the drift layer, The resistivity ρ2 of the selective crystal defect region, the resistivity ρ2 at the depth d_max where the density of crystal defects is maximum, and the resistivity ρ3 of the active region satisfy the following magnitude relationship: ρ3<ρ1<ρ2 2. The semiconductor device according to claim 1,

8. The depth d_max is in the range of the following formula with respect to the chip thickness D of the semiconductor device: 0.5×D≦d_max<D 2. The semiconductor device according to claim 1,

9. A second crystal defect region including all of the active region, the outer periphery region, and the gate finger region is provided on the depth d_max or on the back surface side of the depth d_max.

2. The semiconductor device according to claim 1,

10. A power conversion device comprising the semiconductor device according to claim 1 .

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