Semiconductor device

Abstract

To provide a semiconductor device in which a metallic heat-conductive material is installed below a semiconductor element.SOLUTION: A semiconductor device includes a substrate, a copper layer installed on the substrate, a metal layer installed on the copper layer with an area smaller than the area of the copper layer, and a semiconductor element installed on the metal layer of which area is smaller than the area of the metal layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a metallic thermally conductive material is provided below a semiconductor element. [Background technology]

[0002] Currently, in the semiconductor industry, ceramic substrates are often used as semiconductor element carriers, but when high-power semiconductor elements are mounted, local hot spots tend to occur on the ceramic substrate underneath, making it difficult for heat to dissipate. Summary of the Invention [Problem to be solved by the invention]

[0003] A semiconductor device is provided in which a metal thermally conductive material is disposed below a semiconductor element. [Means for solving the problem]

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided that includes a substrate, a copper layer disposed on the substrate, a metal layer disposed on the copper layer and having an area smaller than an area of ​​the copper layer, and a semiconductor element disposed on the metal layer and having an area smaller than an area of ​​the metal layer.

[0005] In some embodiments, the material of the substrate comprises aluminum oxide. In some embodiments, the material of the metal layer comprises copper, silver, or aluminum. In some embodiments, the shape of the metal layer comprises a rectangle, a circle, a polygon, or a trapezoid. In some embodiments, the metal layer and the copper layer are in contact. In some embodiments, the semiconductor element is a voltage control element. In some embodiments, the semiconductor element and the metal layer are in contact.

[0006] According to one embodiment of the present disclosure, a semiconductor device is provided that includes a substrate, a copper layer disposed on the substrate, a semiconductor element disposed on the copper layer, and a metal layer disposed on the copper layer, surrounding the semiconductor element, and having an area smaller than an area of ​​the copper layer.

[0007] In some embodiments, the semiconductor device and the metal layer have different thicknesses. In some embodiments, the semiconductor device and the metal layer are in contact with the copper layer. In some embodiments, the semiconductor device and the metal layer are in contact.

[0008] According to one embodiment of the present disclosure, a semiconductor device is provided that includes a substrate, a copper layer disposed on the substrate, a first metal layer disposed on the copper layer and having an area smaller than that of the copper layer, a second metal layer disposed on the copper layer and having an area smaller than that of the copper layer and spaced apart from the first metal layer, a first semiconductor element disposed on the first metal layer and having an area smaller than that of the first metal layer, and a second semiconductor element disposed on the second metal layer and having an area smaller than that of the second metal layer.

[0009] In some embodiments, the shape of the first metal layer and the second metal layer comprises a rectangle, a circle, a polygon, or a trapezoid. In some embodiments, the shapes of the first metal layer and the second metal layer are different. In some embodiments, the thicknesses of the first metal layer and the second metal layer are different. In some embodiments, the first metal layer and the second metal layer are in contact with the copper layer. In some embodiments, the first semiconductor element and the first metal layer are in contact. In some embodiments, the second semiconductor element and the second metal layer are in contact.

[0010] Generally, the thickness of the copper layer on the ceramic substrate must be limited because of the need to consider the etching ability of the process and the problem of warping due to thermal expansion. However, when a high-power semiconductor element is mounted, a copper layer that is too thin is likely to cause local hot spots and makes it difficult to dissipate heat. In the semiconductor device disclosed herein, a metal layer having high thermal conductivity and electrical conductivity is additionally installed under (or around) the semiconductor element, so that the copper layer on the substrate is locally thickened, and heat is first uniformly transferred onto the metal layer, and then the heat dissipation area is enlarged, and then the heat is transferred downward more efficiently. The disclosed metal layer belongs to an accessory for the semiconductor element that amplifies its heat source, and can achieve the purpose of uniform heat dissipation and increasing the heat dissipation area, and is connected to the copper layer on the substrate.

[0011] In this disclosure, a metal layer with an area larger than that of the heat source is used to contact the heat source so that the temperature is transferred uniformly. The so-called uniform transfer means that the temperature difference between the center point and the end of the metal layer is smaller, that is, the metal layer is more likely to be isothermal (the formation of a uniform temperature plate). In addition, the bonding of the metal layer and the upper copper layer can increase the bending strength of the substrate and reduce the degree of warping of the substrate.

[0012] The disclosed metal layers can be locally thickened according to the circuit layout, and simultaneously multiple metal layers can be provided on a copper layer, and each metal layer can be designed with different shapes and thicknesses according to product requirements.

[0013] In the present disclosure, the main purpose is to add a metal layer between the semiconductor element and the substrate, so that the heat source of the semiconductor element can be uniformly spread during the transfer process, and the problem of local high temperature can be avoided, and the heat dissipation area can be effectively increased to cool the semiconductor element. In summary, the advantages of the present disclosure include: increasing the heat dissipation effect of the semiconductor element, reducing the warpage of the substrate, increasing the elastic thickness of the local copper layer, and saving the use of copper material.

[0014] The present invention may be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: In accordance with standard industry practice, various features have not been drawn to scale, and in fact dimensions of various features have been arbitrarily expanded or reduced for clarity of illustration. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. [Figure 2A] FIG. 2A is a perspective view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a perspective view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2C] FIG. 2C is a perspective view of a semiconductor device according to one embodiment of the present disclosure. [Diagram 3] FIG. 3 is a perspective view of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a perspective view of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The following disclosure provides various different embodiments for implementing different features of the present disclosure. The following disclosure describes specific examples of each component and its arrangement for the sake of simplicity, and these specific examples are not intended to be limiting. For example, when a first feature component is described as being formed on or above a second feature component in an embodiment of the present disclosure, this means that it may include an embodiment in which the first feature component and the second feature component are in direct contact with each other, and also means that it may include an embodiment in which an additional feature component is formed between the first feature component and the second feature component so that the first feature component and the second feature component are not in direct contact with each other.

[0017] It should be understood that additional operational steps may be performed before, during, or after the above-described methods, and that in other embodiments of the above-described methods, some of the operational steps may be replaced or omitted.

[0018] Additionally, (in the detailed description below) spatially relative terms such as "lower", "below", "bottom", "up", "upper", "top" and the like are used for brevity of description to describe the relationship of one element or feature to another element(s) and feature(s) in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 45 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly. In some embodiments of the present disclosure, terms related to bonding, coupling, and the like, such as "bonded" or "interconnected", may refer to structures that are in direct contact with each other or may not be in direct contact with each other, unless otherwise defined, and may include a relationship in which the two structures are movable or the two structures are fixed.

[0019] As used herein, the terms "about", "approximately", "approximately", "substantially", "same", and "similar" generally indicate a range in which a property value is within + / - 15%, or within + / - 10%, or within + / - 5%, or within + / - 3%, or within + / - 2%, or within + / - 1%, or within + / - 0.5% of a stated value. Values ​​stated herein are approximate values, i.e., in the absence of a specific description of "about", "approximately", "approximately", "nearly", or "substantially", the meaning of "about", "approximately", "approximately", "nearly", or "substantially" may be implied.

[0020] In this specification, terms such as "first", "second", "third" and the like are used to describe various components, parts, regions, layers and / or sections, but it should be understood that these terms should not be limited by these terms. These terms may be used only to distinguish one component, part, region, layer or section from another component, part, region, layer or section. Therefore, hereinafter, a first component, part, region, layer or section may be referred to as a second component, part, region, layer or section, without departing from the technology of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that fits the relative skill of this disclosure and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner unless otherwise defined.

[0022] A semiconductor device according to an embodiment of the present disclosure is provided, as shown in Figure 1. Figure 1 is a schematic cross-sectional view of a semiconductor device 10.

[0023] As shown in FIG. 1, the semiconductor device 10 includes a substrate 12, a first copper layer 14, a second copper layer 16, a metal layer 18, and a semiconductor element 20. The first copper layer 14 is disposed on a first surface 12a of the substrate 12. The second copper layer 16 is disposed on a second surface 12b of the substrate 12, the second surface 12b facing the first surface 12a. The metal layer 18 is disposed on the first copper layer 14. The semiconductor element 20 is disposed on the metal layer 18. It should be noted that the area A1 of the metal layer 18 is smaller than the area A2 of the first copper layer 14, and the area A3 of the semiconductor element 20 is smaller than the area A1 of the metal layer 18.

[0024] In some embodiments, the material of the substrate 12 includes aluminum oxide, but the present disclosure is not limited thereto and other suitable substrate materials may be applied to the present disclosure. In some embodiments, when the material of the substrate 12 is aluminum oxide (a ceramic material), the composite plate composed of the substrate 12, the first copper layer 14, and the second copper layer 16 is called a ceramic substrate, which is a carrier for the semiconductor device 20 and has high thermal conductivity and electrical insulation.

[0025] In some embodiments, the material of the metal layer 18 includes a metal material having high thermal and electrical conductivity, such as, for example, copper, silver, or aluminum, but the present disclosure is not limited thereto and other suitable metal materials can be applied to the present disclosure. In some embodiments, the shape of the metal layer 18 includes a rectangular, circular, polygonal, or trapezoidal shape, but the present disclosure is not limited thereto and other suitable metal layer shapes can be applied to the present disclosure. The shape of the metal layer 18 will be further described with reference to the drawings (FIGS. 2A-2C).

[0026] In some embodiments, the metal layer 18 is in contact with (bonded to) the first copper layer 14. In some embodiments, the metal layer 18 is bonded to the first copper layer 14 by a method such as soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 18 is bonded to the first copper layer 14 by a solder paste 22.

[0027] In some embodiments, semiconductor device 20 is a voltage controlled device, such as a high power component.

[0028] In some embodiments, the semiconductor element 20 is in contact with (bonded to) the metal layer 18. In some embodiments, the semiconductor element 20 and the metal layer 18 are bonded together by a silver paste 24. For example, the semiconductor element 20 and the metal layer 18 are bonded together by a pressureless sintered silver paste.

[0029] As shown in Figure 2A, a semiconductor device 110 according to an embodiment of the present disclosure is provided. Figure 2A is a perspective view of the semiconductor device 110, and mainly shows the shape of metal layers in the semiconductor device 110.

[0030] As shown in Fig. 2A, the semiconductor device 110 includes a substrate 112, a first copper layer 114, a second copper layer 116, a metal layer 118, and a semiconductor element 120. The first copper layer 114 and the second copper layer 116 are disposed on two opposite sides of the substrate 112. The metal layer 118 is disposed on the first copper layer 114. The semiconductor element 120 is disposed on the metal layer 118. As can be seen from Fig. 2A, the area of ​​the metal layer 118 is smaller than that of the first copper layer 114, and the area of ​​the semiconductor element 120 is smaller than that of the metal layer 118.

[0031] In some embodiments, the material of the substrate 112 includes aluminum oxide, but the present disclosure is not limited thereto and other suitable substrate materials may be applied to the present disclosure. In some embodiments, when the material of the substrate 112 is aluminum oxide (a ceramic material), the composite plate composed of the substrate 112, the first copper layer 114, and the second copper layer 116 is called a ceramic substrate, which serves as a carrier for the semiconductor device 120 and has high thermal conductivity and electrical insulation.

[0032] In some embodiments, the material of the metal layer 118 includes a metal material having high thermal and electrical conductivity, such as, for example, copper, silver, or aluminum, although the present disclosure is not limited thereto and other suitable metal materials may also be applied to the present disclosure.

[0033] In FIG. 2A, the shape of the metal layer 118 located below the semiconductor element 120 is rectangular, but the present disclosure is not limited thereto, and other suitable metal layer shapes, such as circular, polygonal, or trapezoidal, may also be applied to the present disclosure.

[0034] In some embodiments, the metal layer 118 is in contact with (bonded to) the first copper layer 114. In some embodiments, the metal layer 118 is bonded to the first copper layer 114 by a method such as soldering or diffusion bonding. In some embodiments, in a soldering bonding method, the metal layer 118 is bonded to the first copper layer 114 by a solder paste 122.

[0035] In some embodiments, the semiconductor device 120 is a voltage controlled device, such as a high power component.

[0036] In some embodiments, the semiconductor element 120 is in contact with (bonded to) the metal layer 118. In some embodiments, the semiconductor element 120 is bonded to the metal layer 118 by a silver paste 124. For example, the semiconductor element 120 is bonded to the metal layer 118 by a pressureless sintering silver paste.

[0037] As shown in Figure 2B, a semiconductor device 210 according to an embodiment of the present disclosure is provided. Figure 2B is a perspective view of the semiconductor device 210, and mainly shows the shape of metal layers in the semiconductor device 210.

[0038] As shown in FIG. 2B, the semiconductor device 210 includes a substrate 212, a first copper layer 214, a second copper layer 216, a metal layer 218, a semiconductor element 220, a solder paste 222, and a silver paste 224. The configurations, materials, dimensional relationships between the components, and bonding methods between the components of the semiconductor device 210 shown in FIG. 2B are similar to those of the semiconductor device 110 shown in FIG. 2A, and therefore will not be described again here. The main difference between the embodiment shown in FIG. 2B and the embodiment shown in FIG. 2A is the shape of the metal layer. In FIG. 2B, the shape of the metal layer 218 located under the semiconductor element 220 is circular, but the present invention is not limited thereto, and other suitable shapes of the metal layer can also be applied to the present disclosure.

[0039] As shown in Figure 2C, a semiconductor device 310 according to an embodiment of the present disclosure is provided. Figure 2C is a perspective view of the semiconductor device 310, and mainly illustrates the shape of metal layers in the semiconductor device 310.

[0040] As shown in FIG. 2C, the semiconductor device 310 includes a substrate 312, a first copper layer 314, a second copper layer 316, a metal layer 318, a semiconductor element 320, a solder paste 322, and a silver paste 324. The configurations, materials, dimensional relationships between the components, and bonding methods between the components of the semiconductor device 310 shown in FIG. 2C are similar to those of the semiconductor device 110 shown in FIG. 2A, and therefore will not be described again here. The main difference between the embodiment shown in FIG. 2C and the embodiment shown in FIG. 2A is the shape of the metal layer. In FIG. 2C, the shape of the metal layer 318 located below the semiconductor element 320 is a trapezoid, but the present invention is not limited thereto, and other suitable shapes of the metal layer can also be applied to the present disclosure.

[0041] As shown in FIG. 2C, when the shape of the metal layer 318 of the semiconductor device 310 is trapezoidal, the heat spreading area gradually expands from the contact surface between the semiconductor element 320 and the metal layer 318 toward the first copper layer 314.

[0042] According to one embodiment of the present disclosure, a semiconductor device 410 is provided, as shown in Fig. 3. Fig. 3 is a perspective view of the semiconductor device 410.

[0043] As shown in Fig. 3, the semiconductor device 410 includes a substrate 412, a first copper layer 414, a second copper layer 416, a metal layer 418, and a semiconductor element 420. The first copper layer 414 and the second copper layer 416 are disposed on two opposite sides of the substrate 412. The semiconductor element 420 is disposed on the first copper layer 414. The metal layer 418 is disposed on the first copper layer 114 and surrounds the semiconductor element 420. Also, as can be seen from Fig. 3, the area of ​​the metal layer 418 is smaller than the area of ​​the first copper layer 414.

[0044] In some embodiments, the material of the substrate 412 includes aluminum oxide, but the present disclosure is not limited thereto and other suitable substrate materials may also be applied to the present disclosure. In some embodiments, when the material of the substrate 412 is aluminum oxide (a ceramic material), the composite plate composed of the substrate 412, the first copper layer 414, and the second copper layer 416 is called a ceramic substrate, which is a carrier for the semiconductor element 420 and has high thermal conductivity and electrical insulation.

[0045] In some embodiments, the semiconductor device 420 is a voltage controlled device, such as a high power component.

[0046] In some embodiments, the semiconductor element 420 is in contact with (bonded to) the first copper layer 414. In some embodiments, the semiconductor element 420 is bonded to the first copper layer 414 by a silver paste (not shown). For example, the semiconductor element 420 is bonded to the first copper layer 414 by a pressureless sintering silver paste.

[0047] In some embodiments, the material of the metal layer 418 includes a metal material having high thermal and electrical conductivity, such as, for example, copper, silver, or aluminum, but the present disclosure is not limited thereto and other suitable metal materials may also be applied to the present disclosure. Also, as shown in FIG. 3, the shape of the metal layer 418 surrounding the semiconductor element 420 in the semiconductor device 410 is polygonal, but the present disclosure is not limited thereto and other suitable metal layer shapes, such as, for example, rectangular, circular, or trapezoidal, may also be applied to the present disclosure.

[0048] In some embodiments, the metal layer 418 is in contact with (bonded to) the first copper layer 414. In some embodiments, the metal layer 418 is bonded to the first copper layer 414 by a method such as soldering or diffusion bonding. In some embodiments, in a soldering bonding method, the metal layer 418 is bonded to the first copper layer 414 by a solder paste (not shown).

[0049] In some embodiments, the thickness T1 of the semiconductor element 420 is the same as the thickness T2 of the metal layer 418. In some embodiments, the thickness T1 of the semiconductor element 420 is different from the thickness T2 of the metal layer 418, e.g., as shown in FIG. 3, the thickness T1 of the semiconductor element 420 is less than the thickness T2 of the metal layer 418, or the thickness T1 of the semiconductor element 420 is greater than the thickness T2 of the metal layer 418 (not shown).

[0050] In some embodiments, as shown in FIG. 3, the semiconductor element 420 and the metal layer 418 are in contact.

[0051] As shown in Figure 4, a semiconductor device 510 according to an embodiment of the present disclosure is provided. Figure 4 is a perspective view of the semiconductor device 510.

[0052] As shown in FIG. 4, the semiconductor device 510 includes a substrate 512, a first copper layer 514, a second copper layer 516, a plurality of metal layers (e.g., a first metal layer 518a, a second metal layer 518b, a third metal layer 518c, a fourth metal layer 518d, and a fifth metal layer 518e), and a plurality of semiconductor elements (e.g., a first semiconductor element 520a, a second semiconductor element 520b, a third semiconductor element 520c, a fourth semiconductor element 520d, and a fifth semiconductor element 520e). The first copper layer 514 and the second copper layer 516 are disposed on two opposing surfaces of the substrate 512. The first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are disposed on the first copper layer 514, respectively, and are separated from each other. A first semiconductor element 520a is disposed on a first metal layer 518a, a second semiconductor element 520b is disposed on a second metal layer 518b, a third semiconductor element 520c is disposed on a third metal layer 518c, a fourth semiconductor element 520d is disposed on a fourth metal layer 518d, and a fifth semiconductor element 520e is disposed on a fifth metal layer 518e. As can be seen from FIG. 4, the areas of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are smaller than the area of ​​the first copper layer 514, the area of ​​the first semiconductor element 520a is smaller than the area of ​​the first metal layer 518a, the area of ​​the second semiconductor element 520b is smaller than the area of ​​the second metal layer 518b, the area of ​​the third semiconductor element 520c is smaller than the area of ​​the third metal layer 518c, the area of ​​the fourth semiconductor element 520d is smaller than the area of ​​the fourth metal layer 518d, and the area of ​​the fifth semiconductor element 520e is smaller than the area of ​​the fifth metal layer 518e.

[0053] In some embodiments, the material of the substrate 512 includes aluminum oxide, but the present disclosure is not limited thereto, and other suitable substrate materials may also be applied to the present disclosure. In some embodiments, when the material of the substrate 512 is aluminum oxide (a ceramic material), the composite plate composed of the substrate 512, the first copper layer 514, and the second copper layer 516 is called a ceramic substrate, which is a carrier for the first semiconductor element 520a, the second semiconductor element 520b, the third semiconductor element 520c, the fourth semiconductor element 520d, and the fifth semiconductor element 520e, and has high thermal conductivity and electrical insulation.

[0054] In some embodiments, the material of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e includes a metal material having high thermal and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto and other suitable metal materials can be applied to the present disclosure. In some embodiments, the shape of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e includes a rectangular, circular, polygonal, or trapezoidal shape, but the present disclosure is not limited thereto and other suitable metal layer shapes can be applied to the present disclosure. In some embodiments, the shape of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are the same. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are different. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partly the same and partly different. For example, as shown in FIG. 4, the shape of the first metal layer 518a is circular, the shape of the second metal layer 518b is rectangular, the shape of the third metal layer 518c is rectangular, the shape of the fourth metal layer 518d is polygonal, and the shape of the fifth metal layer 518e is rectangular.

[0055] In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are each in contact with (bonded to) the first copper layer 514. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are each bonded to the first copper layer 514 by a method such as soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are each bonded to the first copper layer 514 by a solder paste (not shown).

[0056] In some embodiments, the first semiconductor device 520a, the second semiconductor device 520b, the third semiconductor device 520c, the fourth semiconductor device 520d, and the fifth semiconductor device 520e are voltage controlled devices, such as high power components.

[0057] In some embodiments, the first semiconductor element 520a is in contact with the first metal layer 518a, the second semiconductor element 520b is in contact with the second metal layer 518b, the third semiconductor element 520c is in contact with the third metal layer 518c, the fourth semiconductor element 520d is in contact with the fourth metal layer 518d, and the fifth semiconductor element 520e is in contact with the fifth metal layer 518e. In some embodiments, the semiconductor elements and the metal layers are bonded by a silver paste (not shown). For example, the semiconductor elements are bonded to the metal layers by a pressureless sintering silver paste.

[0058] In some embodiments, the thicknesses of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are the same. In some embodiments, the thicknesses of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are different. In some embodiments, the thicknesses of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partly the same and partly different. For example, as shown in FIG. 4, the thickness H1 of the first metal layer 518a is the same as the thickness H4 of the fourth metal layer 518d, the thickness H2 of the second metal layer 518b, the thickness H3 of the third metal layer 518c, and the thickness H5 of the fifth metal layer 518e are the same, and the thickness H1 of the first metal layer 518a is different from the thickness H2 of the second metal layer 518b, the thickness H3 of the third metal layer 518c, and the thickness H5 of the fifth metal layer 518e.

[0059] Generally, the thickness of the copper layer on the ceramic substrate must be limited because of the need to consider the etching ability of the process and the problem of warping due to thermal expansion. However, when a high-power semiconductor element is mounted, a copper layer that is too thin is likely to cause local hot spots and makes it difficult to dissipate heat. In the semiconductor device disclosed herein, a metal layer having high thermal conductivity and electrical conductivity is additionally installed under (or around) the semiconductor element, so that the copper layer on the substrate is locally thickened, and heat is first uniformly transferred onto the metal layer, and then the heat dissipation area is enlarged, and then the heat is transferred downward more efficiently. The disclosed metal layer belongs to an accessory for the semiconductor element that amplifies its heat source, and can achieve the purpose of uniform heat dissipation and increasing the heat dissipation area, and is connected to the copper layer on the substrate.

[0060] In this disclosure, a metal layer with an area larger than that of the heat source is used to contact the heat source so that the temperature is transferred uniformly. The so-called uniform transfer means that the heat between the center point and the end of the metal layer has a smaller temperature, that is, the metal layer is prone to be isothermal (the formation of a uniform temperature plate). In addition, the bonding of the metal layer and the upper copper layer can increase the bending strength of the substrate and reduce the degree of warping of the substrate.

[0061] The disclosed metal layers can be locally thickened according to the circuit layout, and simultaneously multiple metal layers can be provided on a copper layer, and each metal layer can be designed with different shapes and thicknesses according to product requirements.

[0062] In the present disclosure, the main purpose is to add a metal layer between the semiconductor element and the substrate, so that the heat source of the semiconductor element can be uniformly spread during the transfer process, and the problem of local high temperature can be avoided, and the heat dissipation area can be effectively increased to cool the semiconductor element. In summary, the advantages of the present disclosure include: increasing the heat dissipation effect of the semiconductor element, reducing the warpage of the substrate, increasing the elastic thickness of the local copper layer, and saving the use of copper material.

[0063] Some components of the above-mentioned embodiments outline the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art can easily understand that the present disclosure can be used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection should be determined through the claims. Moreover, although some embodiments of the present disclosure have been disclosed above, they are not intended to limit the scope of the present disclosure.

[0064] References to features, advantages, or similar terms throughout this specification do not mean that all features and advantages that may be realized in the present disclosure should or can be realized in any single embodiment of the present disclosure. Rather, terms referring to features and advantages are understood to mean that the particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages and similar terms throughout this specification may, but do not necessarily, refer to the same embodiment.

[0065] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, one skilled in the art will recognize that the present disclosure can be practiced without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the present disclosure. [Explanation of symbols]

[0066] 10, 110, 210, 310, 410, 510 Semiconductor device 12, 112, 212, 312, 412, 512 board 12a First side of the substrate 12b Second side of the board 14, 114, 214, 314, 414, 514 Copper 1 layer 16, 116, 216, 316, 416, 516 second copper layer 18, 118, 218, 318, 418 metal layer 20, 120, 220, 320, 420 Semiconductor elements 22, 122, 222, 322 solder paste 24, 124, 224, 324 Silver paste 518a 1st metal layer 518b 2nd metal layer 518c 3rd metal layer 518d 4th metal layer 518e 5th metal layer 520a First semiconductor element 520b Second semiconductor element 520c Third semiconductor element 520d Fourth semiconductor element A1 Metal layer area A2 Area of ​​the first copper layer A3 Area of ​​semiconductor element H1 Thickness of the first metal layer H2 Thickness of second metal H3 Thickness of third metal H4 Thickness of 4th metal H5 Thickness of the fifth metal T1 Thickness of semiconductor element T2 Metal layer thickness

Claims

1. substrate, a copper layer disposed on the substrate; a metal layer disposed on the copper layer and having an area smaller than that of the copper layer; and A semiconductor device including a semiconductor element disposed on the metal layer and having an area smaller than an area of ​​the metal layer.

2. 2. The semiconductor device according to claim 1, wherein the material of the substrate includes aluminum oxide.

3. The semiconductor device according to claim 1 , wherein the material of the metal layer includes copper, silver, or aluminum.

4. The semiconductor device according to claim 1 , wherein the shape of the metal layer includes a rectangle, a circle, a polygon, or a trapezoid.

5. The semiconductor device according to claim 1 , wherein the metal layer and the copper layer are in contact with each other.

6. 2. The semiconductor device according to claim 1, wherein the semiconductor element is a voltage controlled element.

7. The semiconductor device according to claim 1 , wherein the semiconductor element and the metal layer are in contact with each other.

8. substrate, a copper layer disposed on the substrate; a semiconductor element disposed on the copper layer; and The semiconductor device further comprises a metal layer disposed on the copper layer, surrounding the semiconductor element and having an area smaller than that of the copper layer.

9. The semiconductor device according to claim 8 , wherein the semiconductor element and the metal layer have different thicknesses.

10. The semiconductor device of claim 8 , wherein the semiconductor element and the metal layer are in contact with the copper layer.

11. The semiconductor device according to claim 8 , wherein the semiconductor element and the metal layer are in contact with each other.

12. substrate, a copper layer disposed on the substrate; a first metal layer disposed on the copper layer and having an area smaller than that of the copper layer; a second metal layer disposed on the copper layer, the second metal layer having an area smaller than that of the copper layer and spaced apart from the first metal layer; a first semiconductor element disposed on the first metal layer and having an area smaller than an area of ​​the first metal layer; A semiconductor device including a second semiconductor element disposed on the second metal layer and having an area smaller than an area of ​​the second metal layer.

13. The semiconductor device according to claim 12 , wherein the first metal layer and the second metal layer have a shape including a rectangle, a circle, a polygon, or a trapezoid.

14. The semiconductor device according to claim 12 , wherein the first metal layer and the second metal layer have different shapes.

15. The semiconductor device according to claim 12 , wherein the first metal layer and the second metal layer have different thicknesses.

16. The semiconductor device of claim 12 , wherein the first metal layer and the second metal layer are in contact with the copper layer.

17. The semiconductor device according to claim 12 , wherein the first semiconductor element and the first metal layer are in contact with each other.

18. The semiconductor device according to claim 12 , wherein the second semiconductor element and the second metal layer are in contact with each other.

Images