Semiconductor device

Abstract

To provide a highly reliable semiconductor device having good electric characteristics and a display device using the semiconductor device as a switching element.SOLUTION: In a transistor using an oxide semiconductor layer, on at least one surface side of the oxide semiconductor layer, a c-axis growth is performed in a direction perpendicular to the surface, and a needle crystal group having an a-b plane parallel to the surface is provided, and with a portion other than the needle crystal group is amorphous or a structure in which amorphous and microcrystals are mixed, a highly reliable semiconductor device having good electric characteristics can be manufactured.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Oxide semiconductor film, a semiconductor device using the oxide semiconductor film, and a display using the semiconductor device Regarding the device. [Background technology]

[0002] In recent years, semiconductor thin films (thicknesses between several nm and several hundred nm) formed on substrates with insulating surfaces have become popular. The technology of constructing thin film transistors (TFTs) using a thin film transistor (TFT) is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices, especially in image display devices. There is a wide variety of metal oxides, and their development as switching elements is being rushed. Indium oxide is a well-known material used in applications such as liquid crystal displays. It is used as a transparent electrode material required in

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include Examples of such oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin-film transistors that use metal oxides exhibiting such semiconducting properties in the channel formation region are already known. It has been reported (Patent Document 1 and Patent Document 2).

[0004] In addition, a transistor using an oxide semiconductor is different from a transistor using an amorphous semiconductor. As a transistor, it has a relatively high field effect mobility. It is also possible to configure a driving circuit for a device, etc. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] When forming a plurality of different circuits on an insulating surface, for example, a pixel section and a driver circuit are formed on the same substrate. In this case, the transistor used in the pixel portion should have excellent switching characteristics, e.g. A large on / off ratio is required, and the transistors used in the driver circuits must operate at high speed. In particular, the higher the resolution of the display device, the longer the time it takes to write the display image. Since the driving circuit has a short circuit, it is preferable that the transistors used in the driving circuit operate at high speed.

[0007] One embodiment of the present invention is a semiconductor device having favorable electrical characteristics and high reliability, and a method for switching the semiconductor device. It is an object of the present invention to provide a display device using the same as an etching element. [Means for solving the problem]

[0008] One embodiment of the present invention is a method for manufacturing an oxide semiconductor layer in which a channel formation region is formed. On the other hand, the c-axis grows perpendicular to one surface and the ab plane is parallel to the surface. The region other than the needle-like crystal group is amorphous or a mixture of amorphous and microcrystalline. The semiconductor device is characterized in that

[0009] In one embodiment of the present invention, a crystal is grown on at least one surface side in a direction perpendicular to the surface, and a flat surface is formed on the surface. The needle crystals in the needle crystal group have an a-axis direction or a-b plane. The length in the c-axis direction is five times or more the length in the axial direction, and the area other than the group of needle-shaped crystals is amorphous. Alternatively, the oxide semiconductor film is characterized in that an amorphous region and a microcrystalline region are mixed. .

[0010] Another embodiment of the present invention is a method for manufacturing a gate electrode layer over a substrate having an insulating surface, and a gate insulating film over the gate electrode layer. a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and an oxide semiconductor layer on the gate insulating layer. A source electrode layer and a drain electrode layer which overlap with each other, and and an oxide insulating layer in contact with the oxide semiconductor layer. The crystals have a group of needle-like crystals that have grown along their c-axes in a direction perpendicular to the surface and have ab planes parallel to the surface. The length of the needle crystals in the group of needle crystals is longer in the c-axis direction than in the a-axis direction or the b-axis direction. is 5 times or more, and the area other than the group of needle-like crystals is amorphous or a mixture of amorphous and microcrystalline. The semiconductor device is characterized in that the

[0011] The length of the needle-like crystals in the a-axis or b-axis direction is 2 nm to 50 nm. The crystal structure of the needle-like crystal group is preferably represented by In2Ga2ZnO7. In addition, the composition of the amorphous or amorphous / microcrystalline region is preferably InGaO3. (ZnO) m It is preferable that m is a non-natural number (m>0). The molar ratio of the amorphous and microcrystalline regions is In:Ga:Zn=1:1:0. 5. The oxide semiconductor layer has a thickness of 10 nm to 200 nm. It is preferable to have

[0012] Another embodiment of the present invention is a method for forming a gate electrode layer over a substrate having an insulating surface, a gate insulating layer is formed over the oxide semiconductor layer; and an oxide semiconductor layer is formed over the gate insulating layer. After the oxide semiconductor layer is formed, a heat treatment is performed at a temperature of 400° C. or more and 700° C. or less to form the oxide semiconductor layer. The surface of the crystal has a c-axis grown in a direction perpendicular to the surface, an ab-plane parallel to the surface, and an a-axis A needle consisting of needle-shaped crystals whose length in the c-axis direction is 5 times or more longer than their length in the b-axis direction. a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer; An oxide insulating layer is formed on the source electrode layer and the drain electrode layer so as to be in contact with a part of the oxide semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device.

[0013] The heat treatment is preferably performed by the RTA method. It is preferable to carry out the reaction under a nitrogen atmosphere.

[0014] As one embodiment of the present invention, a transistor having a bottom gate structure is used. The present invention relates to a transistor having a structure in which an oxide semiconductor layer overlaps a source electrode layer and a drain electrode layer. or a transistor having a structure in which a source electrode layer and a drain electrode layer overlap with an oxide semiconductor layer. There are two types of registers, and either can be used.

[0015] In addition, a transistor having a structure in which a source electrode layer and a drain electrode layer overlap with an oxide semiconductor layer In this case, the surface portion of the oxide semiconductor layer is not etched above the channel formation region, and the A structure in which the crystalline groups remain is preferred.

[0016] In the above structure, the gate electrode layer, the source electrode layer, and the drain electrode layer of the transistor are Aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, A film mainly composed of a metal element selected from scandium or an alloy film of such a metal element is used. The gate electrode layer, the source electrode layer, and the drain electrode layer are each a single layer containing the above-mentioned element. Without limitation, a stack of two or more layers can be used.

[0017] In addition, indium oxide, indium oxide tin oxide alloy, indium oxide zinc oxide alloy, acid zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, etc. A light-transmitting oxide conductive layer is used for a source electrode layer, a drain electrode layer, and a gate electrode layer. This improves the light transmittance of the pixel portion, and the aperture ratio can also be increased.

[0018] In addition, the source electrode layer and the drain electrode layer are formed of a film mainly composed of the above metal element. The oxide conductive layer is formed between each of the oxide semiconductor layers, and high-speed operation with reduced contact resistance is achieved. It is also possible to configure a transistor that is

[0019] In the above structure, the transistor includes an oxide semiconductor layer. The oxide insulating layer is in contact with a channel formation region of the oxide semiconductor layer. It acts as a protective layer.

[0020] In the above structure, the oxide insulating layer functioning as a channel protective layer of the transistor is An inorganic insulating film formed by sputtering is used, typically a silicon oxide film or a silicon nitride oxide film. An aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0021] The oxide semiconductor layer is InMO3(ZnO) m A thin film expressed as (m>0) A transistor is manufactured using the thin film as an oxide semiconductor layer. Indicates one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, Ga and Ni, Ga and Fe, etc. In the oxide semiconductor, M may contain any of the above metal elements. In addition to the metal elements contained, impurity elements include Fe, Ni, other transition metal elements, or Some contain oxides of transition metals. In this specification, InMO3(ZnO ) m Among the oxide semiconductor layers represented by (m>0), an oxide semiconductor containing Ga as M is It is called an In-Ga-Zn-O oxide semiconductor, and its thin film is also called an In-Ga-Zn-O film. Call.

[0022] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-O, I n-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al- Zn-O, In-O, Sn-O, or Zn-O metal oxides can be used. Silicon oxide may be contained in the oxide semiconductor layer made of the above metal oxide.

[0023] In addition, the oxide semiconductor layer is subjected to dehydration or dehydrogenation treatment at high temperature for a short time by an RTA method or the like. By this heat treatment process, the surface portion of the oxide semiconductor layer is a group of needle-like crystals which have grown along their c-axes in a direction perpendicular to the surface and have ab-planes parallel to the surface; The region other than the needle-like crystal group of the oxide semiconductor layer is an amorphous region or a region in which amorphous and microcrystalline are mixed. This becomes an area.

[0024] By using an oxide semiconductor layer having such a structure, it is possible to prevent the formation of a dielectric film from the surface of the oxide semiconductor layer. It is possible to prevent the deterioration of electrical characteristics due to N-type conversion caused by the re-intrusion of moisture and the desorption of oxygen. The surface portion of the oxide semiconductor layer is on the back channel side and is made of a microcrystalline layer. The presence of needle-like crystals can suppress the occurrence of parasitic channels. In a transistor having a structure in which a source electrode layer and a drain electrode layer are overlapped on a semiconductor layer, The crystal group enables contact between the surface portion of the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The contact resistance can be reduced.

[0025] In addition, when the oxide semiconductor layer is formed into an island shape after dehydration or dehydrogenation, a needle-like shape is formed on the side surface. No crystal group was formed, and needle-shaped crystal groups were formed only in the upper layer except for the side surface. The ratio is small and does not interfere with the above effects.

[0026] In addition, a driver circuit portion and a pixel portion can be formed over the same substrate using a transistor according to one embodiment of the present invention. and producing a display device using an EL element, a liquid crystal element, an electrophoretic element, or the like. can be done.

[0027] In the display device according to one embodiment of the present invention, a plurality of transistors are provided in a pixel portion. In the case of a transistor, the gate electrode and the source wiring or drain of another transistor are In addition, the display device according to one embodiment of the present invention has a driving circuit. In the circuit, the gate electrode of a transistor and the source wiring of the transistor, or It has a portion for connecting the in-wiring.

[0028] In addition, since transistors are easily damaged by static electricity, etc., On the other hand, it is preferable to provide a protection circuit for protecting the transistor in the pixel portion on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer.

[0029] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0030] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. Effect of the Invention

[0031] In a transistor including an oxide semiconductor layer, at least one surface side of the oxide semiconductor layer The crystals have a group of needle-like crystals that grow along the c-axis in a direction perpendicular to the surface and have an ab-plane parallel to the surface. The portion other than the group of needle-like crystals is amorphous or a mixture of amorphous and microcrystalline. In this way, a semiconductor device having favorable electrical characteristics and high reliability can be manufactured. [Brief description of the drawings]

[0032] [Figure 1] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Diagram 2] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional process views illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a plan view illustrating one embodiment of the present invention. [Diagram 5] FIG. 1 is a plan view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a plan view illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a plan view illustrating one embodiment of the present invention. [Figure 8] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 9] FIG. 1 is a plan view illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 11] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 12] FIG. 1 is an external view showing an example of an electronic book. [Figure 13] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a block diagram of a semiconductor device. [Figure 15] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating the operation of the signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are a diagram for explaining the configuration of a shift register and a timing chart for explaining the operation thereof; [Figure 18] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 19] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 20] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 21] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 22] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of the present invention. [Figure 23] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 24] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 25] FIG. 1 is an external view showing an example of a mobile phone. [Figure 26] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 27] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 28] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 29]4 shows a cross-sectional TEM photograph and an electron diffraction pattern of an oxide semiconductor layer. [Diagram 30] EDX analysis spectrum of oxide semiconductor layer. [Diagram 31] X-ray diffraction chart of the oxide semiconductor layer. [Diagram 32] SIMS analysis depth profile of oxide semiconductor layer. [Diagram 33] A diagram explaining the overview of scientific computing. [Diagram 34] A diagram explaining the overview of scientific computing. [Diagram 35] A diagram explaining the results of scientific calculations. [Diagram 36] 1A to 1C are diagrams illustrating the crystal structure of an oxide semiconductor. [Figure 37] -IV characteristics of transistor before and after BT test. [Figure 38] SIMS analysis depth profile of oxide semiconductor layer. [Figure 39] SIMS analysis depth profile of oxide semiconductor layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation thereof will be omitted.

[0034] (Embodiment 1) In this embodiment, a transistor is taken as an example of a semiconductor device using an oxide semiconductor. The structure of a transistor using a nitride semiconductor layer will be described with reference to FIG.

[0035] A bottom-gate transistor of this embodiment mode is shown in FIG. 1. FIG. 1(A) is a cross-sectional view. FIG. 1(A) shows the plan view of the same in FIG. 1(B). It is a cross-sectional view.

[0036] The transistor shown in FIG. 1 includes a gate electrode layer 101 and a gate A gate insulating layer 102 is formed on the gate electrode layer 101, and an oxide semiconductor layer 1 is formed on the gate insulating layer 102. 03, and a source electrode layer 102 overlapping a part of the oxide semiconductor layer 103 on the gate insulating layer 102. 5a and the drain electrode layer 105b, and the source electrode layer 105a and the drain electrode layer 105b An oxide insulating layer 107 in contact with the oxide semiconductor layer 103 is provided over the oxide semiconductor layer 103. The conductor layer 103 grows in the direction perpendicular to at least one surface side, and in the direction parallel to the surface. The needle crystals in the needle crystal group 106 have an a-axis direction. The length in the c-axis direction is 5 times or more the length in the b-axis direction, and the needle-shaped crystal group is 106 or less. The other regions are amorphous or a mixture of amorphous and microcrystalline regions.

[0037] The gate electrode layer 101 may be made of aluminum, copper, molybdenum, titanium, chromium, tantalum, or tantalum. Metallic materials such as tinsten, neodymium, scandium, etc., or materials that mainly contain these metallic materials The alloy material or the nitride containing these metal materials is used to form a single layer or a multilayer. It is preferable to form the insulating layer using a low-resistance metal material such as aluminum or copper. However, due to problems with heat resistance and corrosion, it is recommended to use it in combination with high melting point metal materials. The melting point metal materials include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Examples of the usable materials include zinc, scandium, and the like.

[0038] In order to improve the aperture ratio of the pixel portion, the gate electrode layer 101 is formed of indium oxide, Indium oxide tin oxide alloy, Indium oxide zinc oxide alloy, Zinc oxide, Zinc oxide aluminum oxide A light-transmitting oxide conductor such as zinc aluminum oxynitride or zinc gallium oxide. A conductive layer may also be used.

[0039] The gate insulating layer 102 is made of silicon oxide, silicon oxynitride, or nitride formed by a CVD method or a sputtering method. Silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, etc. are used as single layer or laminated film. There can be.

[0040] The oxide semiconductor layer 103 is an In-Ga-Zn-O based film containing In, Ga, and Zn. , InMO3(ZnO) m The composition is expressed as (m>0). Note that M is gallium ( Ga), iron (Fe), nickel (Ni), manganese (Mn) and cobalt (Co). It indicates one or more metallic elements that are identified. For example, M may be Ga. In addition, the above metal elements other than Ga may be contained, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M in the oxide semiconductor, Some contain Fe, Ni and other transition metal elements, or oxides of these transition metals.

[0041] The oxide semiconductor layer 103 is formed by a sputtering method. or less, and preferably, from 10 nm to 40 nm.

[0042] The oxide semiconductor layer 103 is a layer that has been subjected to dehydration or dehydrogenation treatment at high temperature for a short time by an RTA method or the like. The dehydration or dehydrogenation process is carried out using a hot gas (nitrogen or an inert gas such as a rare gas). Gas) or light at temperatures between 400℃ and 700℃ (or below the distortion point of the glass substrate) at 650°C for 1 to 10 minutes, preferably at RT for 3 to 6 minutes A (Rapid Thermal Anneal) process can be used. By using this method, dehydration or dehydrogenation can be performed in a short time, so the temperature exceeds the distortion point of the glass substrate. But it can be processed.

[0043] The oxide semiconductor layer 103 is an amorphous layer having many dangling bonds when it is deposited. However, by carrying out the heating step of the dehydration or dehydrogenation treatment, dangling bonds that are close to each other are broken down into can bond together to form an ordered amorphous structure. The mixture of amorphous and microcrystalline regions is formed, with microcrystalline regions intermixed with amorphous regions. Or the entire structure is made up of microcrystals. The grain size of the microcrystals is 1 nm or more. These are so-called nanocrystals with a diameter of 20 nm or less, and are generally called microcrystals. The size is smaller than that of the crystal grains.

[0044] In addition, the surface portion of the oxide semiconductor layer 103 is a crystalline region. A group of needle-shaped crystals 106, which are needle-shaped microcrystal layers that grow in the c-axis direction perpendicular to the surface of the substrate, are formed. Here, the needle crystal group 106 is preferably c-axially oriented, and has an a-axis perpendicular to the c-axis. The needle-shaped crystals in the needle-shaped crystal group 106 have an a-plane having an a-axis or a b-axis. The length in the c-axis direction (long axis) is more than 5 times that of the short axis, and the short axis is 2 nm The thickness is from 3 nm to 50 nm, and more preferably from 3 nm to 10 nm.

[0045] The oxide semiconductor layer 103 having such a structure is used as a channel formation region of a transistor. As a result, the surface portion of the oxide semiconductor layer 103 is made of dense needle-shaped crystals. The presence of crystal group 106 prevents the re-intrusion of moisture from the surface layer and the desorption of oxygen, resulting in N-type formation. In addition, the surface portion of the oxide semiconductor layer 103 can be prevented from being deteriorated due to the heat treatment. The back channel side, preventing the N-type is also effective in suppressing parasitic channels. By having the crystalline group 106, the surface portion of the oxide semiconductor layer 103 and the source electrode layer 105a or This can reduce the contact resistance with the drain electrode layer 105b.

[0046] Here, the In-Ga-Zn-O based film is formed by varying the composition of the oxide semiconductor film-forming target used. The crystal structure that grows easily during the heating process differs. For example, the molar ratio of In2O3:Ga A substrate for forming oxide semiconductor films containing In, Ga, and Zn with a ratio of 2O3:ZnO=1:1:1. When an In-Ga-Zn-O film is formed using a target and crystallized through a heating process, Hexagonal layers with one or two oxide layers containing Ga and Zn interspersed between In oxide layers. In this case, the crystal structure of the needle-like crystal group 106 is In2 In addition, the amorphous or The molar ratio of the structure in which amorphous and microcrystalline regions are mixed is In:Ga:Zn=1:1. :0.5. Also, the molar ratio of In2O3:Ga2O3:ZnO=1:1:2 When a film is formed using an oxide semiconductor film formation target having the following structure and crystallized through a heating process, In the case of In-oxide layers, the oxide layers containing Ga and Zn tend to be two layers. Stable crystal structure The latter has two oxide layers containing Ga and Zn, and crystal growth is likely to occur. The film was formed using a target with a numerical ratio of In2O3:Ga2O3:ZnO=1:1:2, and then heated. When crystallization is performed through a process, crystals that are connected from the surface layer to the gate insulating film interface are formed. In this case, the composition formula of the needle crystal group 106 is likely to be InGaZnO4. The molar ratio may be rephrased as the atomic ratio.

[0047] As shown in FIG. 10A, depending on the order of steps, the side surface of the oxide semiconductor layer 103 may be damaged. The needle-like crystal group 106 is formed only in the upper layer portion excluding the side surface portion. However, the area ratio of the side surface is small, and the above-mentioned effect is maintained even in this case.

[0048] The source electrode layer 105a and the drain electrode layer 105b are formed by the first conductive layers 112a and 112b. , a three-layer structure consisting of first conductive layers 113a and 113b, and third conductive layers 114a and 114b. The materials used for these layers are the same as those for the gate electrode layer 101 described above. In this embodiment, the source electrode layer 105a and the drain electrode layer 1 However, the present invention is not limited to this. The inner electrode layer 105b is a single layer or a multilayer structure using the same material as the gate electrode layer 101 described above. It may be appropriately formed.

[0049] In addition, similarly to the gate electrode layer 101, the above-mentioned light-transmitting oxide conductive layer is formed on the source electrode layer 1 By using this for the drain electrode layer 105a and the drain electrode layer 105b, the light-transmitting property of the pixel portion can be improved and the aperture ratio can be increased. It can also be made taller.

[0050] The above-mentioned metal material that becomes the source electrode layer 105a and the drain electrode layer 105b is used as a main component. The oxide conductive layer is formed between the film and the oxide semiconductor layer 103, and the contact resistance is reduced. It is also possible to reduce the resistance.

[0051] A chalcogenide film was formed over the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b. The oxide insulating layer 107 functions as a protective layer for the panel. An inorganic insulating film formed by a photolithography method is used. Representative examples include a silicon oxide film, a silicon nitride oxide film, and an oxide film. An aluminum film, an aluminum oxynitride film, or the like is used.

[0052] The materials of each part are the same, and the transistor has a bottom contact structure as shown in FIG. A transistor can also be formed.

[0053] The transistor shown in FIG. 10B has a gate electrode layer 10 on a substrate 100 having an insulating surface. 1, a gate insulating layer 102 on the gate electrode layer 101, and a source electrode 103 on the gate insulating layer 102. The source electrode layer 105a and the drain electrode layer 105b are formed on the gate insulating layer 102. the oxide semiconductor layer 103 overlapping with a part of the drain electrode layer 105b; The oxide semiconductor layer 103 is disposed over the source electrode layer 105a and the drain electrode layer 105b. An oxide insulating layer 107 is provided in contact with the transistor 102. Similarly to the transistor, the oxide semiconductor layer 103 has a surface on which a semiconductor layer is formed in a direction perpendicular to the surface. a group of needle-like crystals 106 which have grown along the c-axis and have an ab-plane parallel to the surface, The needle-like crystals in 106 are more than five times longer in the c-axis direction than in the a-axis or b-axis direction. The region other than the group of needle-like crystals 106 is amorphous or a region in which amorphous and microcrystalline materials are mixed. It is.

[0054] The oxide semiconductor layer 103 having such a structure is used as a channel formation region of a transistor. As a result, the oxide semiconductor layer 10 is formed in the same manner as the bottom gate transistor shown in FIG. Since the surface layer of 3 contains dense needle-shaped crystals 106 composed of needle-shaped microcrystals, This prevents the deterioration of electrical characteristics due to N-type conversion caused by the re-intrusion of moisture from the semiconductor and the desorption of oxygen. In addition, the surface portion of the oxide semiconductor layer 103 is on the back channel side and is an N-type semiconductor. Preventing this is also effective in suppressing parasitic channels.

[0055] By using the above-described structure, a transistor having high reliability and improved electrical characteristics can be obtained. can be provided.

[0056] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0057] (Embodiment 2) In this embodiment, a display device including the bottom-gate transistor described in Embodiment 1 is The manufacturing process of the device will be described with reference to Figs. 2 to 9. Figs. 2 and 3 are cross-sectional views, and Fig. 4 is a schematic diagram of the device. 4 to 7 and 9 are plan views, and the lines A1-A2 and B 1-B2 corresponds to the cross-sectional views A1-A2 and B1-B2 in FIG. 2 and FIG.

[0058] First, a substrate 100 having an insulating surface is prepared. The substrate 100 is a substrate having a temperature suitable for the subsequent heat treatment. It is preferable to use a material having a high strain point rather than a high hardness. Glass, aluminoborosilicate glass, or aluminosilicate glass, etc. A non-alkali glass substrate manufactured by the float method or the annealing method can be used. By containing more barium oxide (BaO) than acid, a more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3. .

[0059] Instead of the above glass substrate, a ceramic substrate, a quartz glass substrate, a quartz substrate, a safa substrate, etc. Alternatively, a substrate made of an insulating material such as a metal substrate may be used. Alternatively, crystallized glass may be used. This can be done.

[0060] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed by using a sputtering method or the like. The substrate 100 may be a sodium substrate such as a glass substrate. When using a substrate containing mobile ions such as silicon nitride or silicon oxynitride as an undercoat film, By using a film containing nitrogen, such as a nitrogen-containing film, mobile ions can penetrate into the oxide semiconductor layer. This can be prevented.

[0061] Next, the gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 are A conductive film for forming the conductive film is formed on the entire surface of the substrate 100 by sputtering or vacuum deposition. A first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching. The wiring and electrodes (gate wiring including the gate electrode layer 101, capacitance wiring 108 , and the first terminal 121). In order to prevent the step from being broken, at least the end of the gate electrode layer 101 is formed in a tapered shape. It is preferable to etch the substrate so that the etching is performed in such a way that the thickness of the substrate is reduced. The cross-sectional view at this stage is shown in FIG. The plan view at this stage corresponds to Figure 4.

[0062] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Metallic materials such as scandium, or alloy materials mainly composed of these metallic materials, or The nitride containing these metal materials can be used to form a single layer or a multilayer structure. It is preferable to use low-resistance metal materials such as aluminum and copper. Due to food habit, it is recommended to use it in combination with high melting point metal materials. High melting point metal materials include: Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. There can be.

[0063] For example, the gate electrode layer 101 may have a laminated structure in which molybdenum is laminated on aluminum. Two-layer structure with molybdenum on copper, or two-layer structure with titanium nitride or molybdenum on copper. The two-layer structure is made up of a laminate of tantalum nitride and a laminate of titanium nitride and molybdenum. The three-layer laminate structure is preferably made of aluminum, aluminum and silicon. alloy of aluminum and titanium or alloy of aluminum and neodymium as the intermediate layer. tungsten, tungsten nitride, titanium nitride or titanium is laminated as upper and lower layers. It is preferable to use this structure.

[0064] At this time, the aperture ratio is improved by using a light-transmitting oxide conductive layer for a part of the electrode layer and the wiring layer. For example, the oxide conductive layer may be made of indium oxide, indium oxide tin oxide, or the like. Alloy, Indium Oxide Zinc Oxide Alloy, Zinc Oxide, Zinc Aluminum Oxide, Zinc Aluminum Oxynitride For example, zinc gallium oxide or zinc oxide gallium can be used.

[0065] Next, a gate insulating layer 102 is formed on the entire surface to cover the gate electrode layer 101 .

[0066] The gate insulating layer 102 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. , silicon nitride, silicon oxynitride, or silicon oxynitride. For example, the plasma CVD method can be used with SiH4, oxygen and nitrogen as the deposition gas. The thickness of the gate insulating layer 102 is 50 nm or more and 50 nm or less. In the case of a multilayer structure, the first gate electrode has a thickness of, for example, 50 nm to 200 nm. a gate insulating layer and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; The edge layers are laminated.

[0067] In this embodiment, a gate electrode having a thickness of 100 nm, which is a silicon oxide film, is formed by plasma CVD. An insulating layer 102 is formed.

[0068] The gate insulating layer 102 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two of the following compounds are used: A single layer or a laminated film of the above-mentioned compounds may also be used.

[0069] In this specification, an oxynitride is a compound having a composition in which oxygen atoms are more abundant than nitrogen atoms. Nitrogen oxide refers to a substance that has more nitrogen atoms than oxygen atoms. It refers to a substance that is abundant.

[0070] Note that before an oxide semiconductor film for forming the oxide semiconductor layer 103 is formed, an argon gas is A gas is introduced to generate plasma and reverse sputtering is performed to deposit a layer on the surface of the gate insulating layer 102. It is preferable to remove the dust adhering to the target. Instead, a voltage was applied to the substrate side using an RF power source in an argon atmosphere to generate plasma near the substrate. This is a method to modify the surface by forming a sintered layer. Note that the argon atmosphere can be replaced by nitrogen or helium. After the reverse sputtering process, an oxide semiconductor film is formed without being exposed to the air. As a result, the interface between the gate insulating layer 102 and the oxide semiconductor layer 103 is resistant to water and hydrochloric acid. It is not contaminated by atmospheric components or impurities floating in the air, so it is safe. This makes it possible to reduce the variation in transistor characteristics.

[0071] Next, a film having a thickness of 10 nm to 200 nm, preferably 10 nm to 200 nm, is formed on the gate insulating layer 102. An oxide semiconductor film having a thickness of m to 40 nm is formed.

[0072] The oxide semiconductor films include In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- An O-based or Zn—O-based oxide semiconductor film can be used. The method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) atmosphere. The film can be formed by sputtering in a mixed atmosphere of argon and oxygen. When using the sputtering method, a target containing SiO2 of 2% by weight or more and 10% by weight or less is used. The oxide semiconductor film may contain SiOx (X>0) which inhibits crystallization. .

[0073] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (having a molar ratio of In 2O3:Ga2O3:ZnO=1:1:0.5, In2O3:Ga2O3:ZnO=1: 1:1, or In2O3:Ga2O3:ZnO=1:1:2) to separate the substrate and the target. The distance between the get and the target was 100 mm, the pressure was 0.6 Pa, the direct current (DC) power was 0.5 kW, and oxygen was The film is formed in an atmosphere (oxygen flow rate 100%). A pulsed direct current (DC) power supply is used. This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and improves the film thickness distribution. In this embodiment, the oxide semiconductor film is an In-Ga-Z Using a nO-based oxide semiconductor film formation target, a 30 nm thick In- A Ga-Zn-O film is formed.

[0074] The relative density of the oxide semiconductor in the oxide semiconductor film formation target is preferably 80% or more. The oxide semiconductor formed by this is preferably 95% or more, more preferably 99.9% or more. The impurity concentration in the conductive film can be reduced, resulting in a transistor with high electrical characteristics and reliability. can be obtained.

[0075] The sputtering method uses a high-frequency power supply as the sputtering power source, while the RF sputtering method uses a DC power supply. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which uses a pulsed bias. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used when:

[0076] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0077] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0078] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0079] In addition, before the oxide semiconductor film is formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheat treatment to remove any moisture or hydrogen remaining in the material. The preheating process involves heating the deposition chamber to 200℃ to 600℃ under reduced pressure. There are two methods: preheating, or repeatedly introducing and exhausting nitrogen or inert gas while heating. After the treatment, cool the substrate or the sputtering device, then immerse the oxide semiconductor in a vacuum without exposing it to the air. Conductive film is deposited. In this case, it is better to use oil or fat as the target cooling liquid instead of water. Repeated nitrogen introduction and exhaust without heating can produce a certain effect, but it is more effective to do this while heating. It's even better.

[0080] In addition, a cryopump is used before, during, or after the formation of the oxide semiconductor film. It is preferable to remove moisture remaining in the sputtering device using a vacuum cleaner.

[0081] Next, a second photolithography process is performed to form a resist mask and an In-Ga-Z The etching is performed on the nO-based film. For etching, organic acids such as citric acid and oxalic acid are used. It can be used as a chant. Here, ITO07N (manufactured by Kanto Chemical Co., Ltd.) was used. By wet etching, unnecessary parts are removed to make the In-Ga-Zn-O film into islands. Then, an oxide semiconductor layer 103 is formed. The end portion of the oxide semiconductor layer 103 is etched to have a tapered shape. By doing this, it is possible to prevent the wiring from being cut off due to the step shape. The etching is not limited to wet etching, and dry etching may also be used.

[0082] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The first heat treatment is performed by using high-temperature gas (nitrogen or inert gas such as rare gas) and light. 00°C to 700°C (or a temperature below the distortion point of the substrate 100) for 1 minute to 10 minutes RTA (Rapid Threshold Annealing) is preferably performed at 650°C for 3 to 6 minutes. The RTA method can be used to remove the Since hydration or dehydrogenation can be performed, processing can be performed even at temperatures exceeding the strain point of the glass substrate. The cross-sectional view at this stage is shown in Figure 2(B). The plan view at this stage corresponds to Figure 5. The first heat treatment is not limited to this timing, and may be performed during a photolithography process or a film formation process. This may be done multiple times before and after the procedure.

[0083] Here, the surface portion of the oxide semiconductor layer 103 is crystallized by the first heat treatment and is formed into needle-like crystals. The oxide semiconductor layer 10 has a group of needle-like crystals 106 formed of a microcrystalline layer. The other regions of 3 are amorphous regions or regions where amorphous and microcrystalline are mixed, or The entire region is a group of microcrystals. Note that the group of needle-like crystals 106 is a part of the oxide semiconductor layer 103. Hereinafter, the oxide semiconductor layer 103 will be referred to as including the needle-like crystal group 106. do.

[0084] In this specification, the heat treatment in an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is called heat treatment for dehydrogenation. Dehydrogenation does not only mean that hydrogen is removed by hydrogenation, but also that H, OH, etc. are removed. For convenience, this process is referred to as dehydration or dehydrogenation.

[0085] When the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated, The water or hydrogen is extracted using the same furnace as the hydration or dehydrogenation, without exposing it to the atmosphere. It is important not to mix the oxide semiconductor layer again. Resistance, that is, n-type (n - , n + After that, the resistance is increased to make the oxide semiconductor i-type. When a transistor is fabricated using a dielectric layer, the threshold voltage of the transistor becomes positive. This makes it possible to realize a switching element with what is called a normally-off characteristic. It is shown that the channel is formed at a gate voltage as close as possible to 0V. It is desirable for devices. Note that if the threshold voltage of a transistor is negative, the gate voltage Even if the voltage is 0V, a current flows between the source and drain electrodes. This is called a normally-on characteristic. In active matrix display devices, the transistors that make up the circuits The electrical characteristics of the transistor are important and affect the performance of the display device. Among the electrical properties of a transistor, the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit will not be able to control the In addition, even if the threshold voltage is positive, it is difficult to obtain a transistor with a large absolute value. In the case of a transistor, when the driving voltage is low, it does not function as a transistor. In the case of an n-channel transistor, the gate Only when a positive voltage is applied does a channel form and drain current begin to flow. It is desirable to use a transistor that does not form a channel unless the driving voltage is high. A transistor in which a channel is formed and drain current flows even under a negative voltage condition. However, such a transistor is not suitable for use in circuits.

[0086] In addition, the gas atmosphere for lowering the temperature from the heating temperature T is different from the gas atmosphere for raising the temperature to the heating temperature T. For example, a large amount of hydrogen may be added to the same furnace in which dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew) without exposing the Cooling is performed by filling the container with water to a temperature of -40°C or lower, preferably -60°C or lower.

[0087] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0088] When the heat treatment is performed in an inert gas atmosphere, the oxide semiconductor layer is It becomes oxygen deficient and has low resistance, i.e., it becomes n-type (n - , n + Then, the oxide semiconductor By forming an oxide insulating layer in contact with the semiconductor layer, the oxide semiconductor layer is made into an oxygen-excess state. This makes the material highly resistant, i.e. i-type. This results in good electrical properties and high reliability. This makes it possible to fabricate highly reliable transistors.

[0089] The first heat treatment of the oxide semiconductor layer is performed before the oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer 103. In that case, the oxide semiconductor film is removed from the heating apparatus after the first heat treatment. The substrate is removed and a second photolithography step is performed. In this case, the island-shaped oxide semiconductor No needle-like crystals are formed on the side surface of the layer 103, and the needle-like crystals are formed only in the upper layer portion excluding the side surface. 106 is formed (see FIG. 10(A)).

[0090] Next, a third photolithography process is performed to form a resist mask and to perform etching. By removing unnecessary parts, the contacts reaching the wiring and electrode layer made of the same material as the gate electrode layer 101 are formed. This contact hole is used for direct connection with the conductive film to be formed later. For example, in the driver circuit portion, a gate electrode layer and a source electrode layer or a drain electrode layer are provided. The transistor that is in direct contact with the electrode layer and the terminal that is electrically connected to the gate wiring of the terminal part are formed. In this case, a contact hole is formed.

[0091] Next, a first conductive layer made of a metal material is formed on the oxide semiconductor layer 103 and the gate insulating layer 102. The layer 112, the second conductive layer 113, and the third conductive layer 114 are formed by sputtering or vacuum deposition. The cross-sectional view at this stage is shown in Figure 2(C).

[0092] The materials for the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are the same as those described above. A material similar to that of the gate electrode layer 101 can be used.

[0093] Here, the first conductive layer 112 and the third conductive layer 114 are made of a heat-resistant conductive material, i.e., The first conductive layer 113 is made of an aluminum alloy containing neodymium. This structure reduces the occurrence of hillocks while taking advantage of the low resistance of aluminum. In this embodiment, the first conductive layer 112 to the third conductive layer 114 can be formed by However, the present invention is not limited to this structure, and may be a single-layer structure or a two-layer structure. For example, a single-layer structure of titanium film may be Alternatively, a single layer structure of an aluminum film containing silicon may be used.

[0094] In addition, similarly to the gate electrode layer 101, the above-mentioned light-transmitting oxide conductive layer is formed on the source electrode layer 1 By using this for the drain electrode layer 105a and the drain electrode layer 105b, the light-transmitting property of the pixel portion can be improved and the aperture ratio can be increased. It can also be made taller.

[0095] Next, a fourth photolithography process is performed to form a resist mask 131 and etch the The unnecessary portions are removed by etching to form the source electrode layer 105a, the drain electrode layer 105b, and the connection The connecting electrode 120 is formed by wet etching or dry etching. For example, titanium is applied to the first conductive layer 112 and the third conductive layer 114. When an aluminum alloy containing neodymium is used for the second conductive layer 113, hydrogen peroxide is used. This can be wet etched using water or heated hydrochloric acid as an etchant. A cross-sectional view at this stage is shown in Fig. 3(A). The plan view at this stage corresponds to Fig. 6.

[0096] At this time, the first conductive layer 112 to the third conductive layer 114 and the oxide semiconductor layer 103 (needle-shaped It is preferable to carry out the etching process under conditions that provide a sufficient etching selectivity for the crystal group 106). This is preferable. The needle-like crystal group 106 in the surface portion of the oxide semiconductor layer 103 is thus etched. This can prevent the data from being removed.

[0097] In addition, the needle-like crystals 106 are formed on the surface of the oxide semiconductor layer 103, so that the amorphous The first conductive layer 112 to the third conductive layer 114 are etched away from the oxide semiconductor layer 103. Since the etching selectivity can be easily obtained, the oxide semiconductor layer 103 can be easily etched even if the thickness of the oxide semiconductor layer 103 is thin. This can prevent part of the oxide semiconductor layer 103 from being removed by the etching treatment.

[0098] In addition, since wet etching is used, the etching is performed isotropically, and the source electrode layer 1 The ends of the drain electrode layer 105a and the drain electrode layer 105b are recessed from the resist mask 131. In the above process, the oxide semiconductor layer 103 and the needle-like crystal group 106 are used as a channel formation region. You can create a Zysta 170.

[0099] The above-mentioned metal material that becomes the source electrode layer 105a and the drain electrode layer 105b is used as a main component. The oxide conductive layer is formed between the film and the oxide semiconductor layer 103, and the contact resistance is reduced. It is also possible to reduce the resistance.

[0100] In the fourth photolithography step, the source electrode layer 105a and the drain The second terminal 122 made of the same material as the electrode layer 105b is left in the terminal portion. 22 is a source wiring (a source wiring including a source electrode layer 105a or a drain electrode layer 105b). ) is electrically connected to

[0101] In addition, in the terminal portion, the connection electrode 120 is connected to a contact formed in the gate insulating layer 102. It is directly connected to the first terminal 121 of the terminal portion through a hole. However, the source wiring or drain wiring of the transistor of the driving circuit is formed through the same process as described above. The gate electrode is directly connected to the gate wiring.

[0102] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of resist masks can be reduced, simplifying the process and reducing costs. Cost reduction is possible.

[0103] Next, the resist mask 131 is removed, and the gate insulating layer 102, the oxide semiconductor layer 103, A layer that covers the source electrode layer 105a and the drain electrode layer 105b and a part of the oxide semiconductor layer 103 The oxide insulating layer 107 is formed by a sputtering method or the like. The resulting oxide films, such as silicon oxide film, silicon oxynitride film, aluminum oxide film, and tantalum oxide film, A material insulating layer can be used.

[0104] The oxide insulating layer 107 is formed by removing impurities such as water or hydrogen from the oxide insulating layer 107 by a method such as a sputtering method. In this embodiment, the oxide insulating film is formed by using a method that does not mix with other substances. A silicon oxide film is formed as the edge layer 107 by sputtering. The substrate temperature during the film formation is The temperature may be from room temperature to 300° C., and in this embodiment, the temperature is set to 100° C. In order to prevent the inclusion of impurities such as water and hydrogen, the film is heated at 150°C or higher (35°C) under reduced pressure before deposition. Pre-bake at a temperature of 0°C or less for 2 to 10 minutes, and then remove the film from the oven without exposing it to air. It is desirable to form a silicon oxide insulating layer. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The target is silicon oxide. A silicon target or a silicon target can be used. For example, a silicon target can be used. A silicon oxide film is formed by sputtering in a mixed atmosphere of oxygen and rare gas. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen. Ions and OH - It does not contain impurities such as nicotinamide, and blocks them from entering from the outside. An inorganic insulating film is preferred.

[0105] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm. Pressure: 0.4 Pa, DC power: 6 kW, oxygen (oxygen flow rate: 100%) atmosphere The film is formed by DC sputtering to a thickness of 300 nm.

[0106] Next, a second heat treatment is performed in an inert gas atmosphere (preferably at 200° C. or higher and 400° C. or lower, For example, the heating is performed at 250°C for 1 hour in a nitrogen atmosphere. A second heat treatment is performed. Alternatively, a high-temperature short-time RTA treatment is performed in the same manner as the first heat treatment. In the second heat treatment, the oxide semiconductor layer 103 overlapping with the oxide insulating layer 107 may be in contact with the oxide insulating layer 107. The second heat treatment is performed to reduce the resistance of the semiconductor device that has been subjected to the first heat treatment. The oxide semiconductor layer 103 becomes in an oxygen-excess state, and the resistance of the oxide semiconductor layer 103 becomes high ( It is possible to make it i-type.

[0107] In this embodiment, the second heat treatment was performed after the oxide insulating layer 107 was formed. The timing is fine as long as it is after the oxide insulating layer 107 is formed. It is not limited to the latter.

[0108] In addition, when a heat-resistant material is used for the source electrode layer 105a and the drain electrode layer 105b, In this case, a step using the first heat treatment conditions may be performed at the timing of the second heat treatment. In this case, the heat treatment may be performed only once after the silicon oxide film is formed.

[0109] Next, a fifth photolithography process is performed to form a resist mask, and the oxide insulating layer 1 A contact hole 125 reaching the drain electrode layer 105b is formed by etching in step 07. In addition, the contact hole 12 reaching the second terminal 122 is formed by the etching. 7. A contact hole 126 reaching the connection electrode 120 is also formed. Shown in Figure 3(B).

[0110] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or an indium oxide tin oxide alloy. (In2O3-SnO2, abbreviated as ITO) and other materials can be used. The etching process for such materials is carried out using a hydrochloric acid based solution. However, since ITO etching is particularly prone to leaving residues, In order to improve workability, indium oxide zinc oxide alloy (In2O3-ZnO, abbreviated as IZO) (to do) may also be used.

[0111] Next, a sixth photolithography process is performed to form a resist mask and to form a An unnecessary portion of the light-transmitting conductive film is removed to form the pixel electrode layer 110.

[0112] In the sixth photolithography step, the gate insulating layer 102 in the capacitance section The oxide insulating layer 107 serves as a dielectric, and the capacitance wiring 108 and the pixel electrode layer 110 form a storage capacitance. A quantity is formed.

[0113] In the sixth photolithography process, the first terminal 121 and the second terminal 1 22 is covered with a resist mask, and the light-transmitting conductive films 128 and 129 formed on the terminal portions are The light-transmitting conductive films 128 and 129 are electrodes or wiring used for connection with an FPC. The light-transmitting layer 124 is formed on the connection electrode 120 that is directly connected to the first terminal 121. The conductive film 128 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The light-transmitting conductive film 129 formed on the second terminal 122 is connected to the input terminal of the source wiring. The terminal electrodes function as connection terminals.

[0114] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The plan view at this stage is shown in FIG.

[0115] FIG. 8(A1) and FIG. 8(A2) are a plan view and a cross-sectional view of the gate line terminal portion at this stage. 8(A1) is a cross-sectional view taken along line C1-C2 in FIG. 8(A2). In FIG. 8(A1), a protective insulating film 154 and a connection electrode 153 are formed on the protective insulating film 154. The light-transmitting conductive film 155 is a terminal electrode for connection that functions as an input terminal. In addition, in FIG. 8(A1), the first wiring layer is made of the same material as the gate wiring. The terminal 151 and a connection electrode 153 made of the same material as the source wiring are connected to the gate insulating layer 15 2, they are overlapped and directly in contact with each other for electrical continuity. The conductive film 155 is in direct contact with the protective insulating film 154 through a contact hole provided therein, and is electrically connected to the protective insulating film 154. It is possible.

[0116] FIG. 8(B1) and FIG. 8(B2) are a plan view and a cross-sectional view of a source line terminal portion, respectively. FIG. 8(B1) is a cross-sectional view taken along line D1-D2 in FIG. 8(B2). In FIG. 8B1, a protective insulating film 154 and a connection electrode 153 are formed on the protective insulating film 154. The light-transmitting conductive film 155 is a connection terminal electrode that functions as an input terminal. In addition, in FIG. 8(B1), in the terminal portion, an electrode 15 made of the same material as the gate wiring is provided. 6, a gate insulating layer 152 is formed under a second terminal 150 electrically connected to the source wiring. The electrode 156 is not electrically connected to the second terminal 150. If the potential of the second terminal 150 is set to a different potential, for example, floating, GND, 0V, etc. For example, a capacitance for noise countermeasures or a capacitance for static electricity countermeasures can be formed. The second terminal 150 is electrically connected to a light-transmitting conductive film 155 via a protective insulating film 154. are actively connected.

[0117] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0118] In this way, six photolithography steps were performed using six photomasks to produce the bottom The gate structure of the transistor 170 and the storage capacitor can be completed. These are arranged in a matrix corresponding to each pixel to form a pixel section, The present invention can be used as one of the substrates for manufacturing a display device of a positive matrix type. For convenience, such a substrate is called an active matrix substrate.

[0119] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for

[0120] In addition, the present embodiment is not limited to the pixel configuration of FIG. 7. In FIG. 9, no capacitance wiring is provided, and the pixel electrode is protected and insulated from the gate wiring of the adjacent pixel. In this example, a storage capacitor is formed by stacking a film and a gate insulating layer. The third terminal connected to the capacitance wiring can be omitted. The same parts will be described using the same reference numerals.

[0121] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0122] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0123] In addition, the response speed can be improved by increasing the normal vertical synchronization frequency by 1.5 times or more, preferably by increasing it by 2 times or more. In addition, the gray scale to be written for each divided field in each frame is selected. There is also a driving technology called double speed driving, in which the speed is increased by 100 ps.

[0124] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source independently within one frame period. When using ED, three or more types of LEDs may be used as a surface light source, or white light may be emitted. LEDs may also be used. Since multiple LEDs can be controlled independently, the switching of optical modulation of the liquid crystal layer is possible. It is also possible to synchronize the LED lighting timing with the switching timing. The dynamic technology can turn off some of the LEDs, making it particularly effective for black areas that occupy the entire screen. In the case of video display with a high ratio of the area, the power consumption can be reduced.

[0125] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0126] The transistor obtained in this embodiment has an In-Ga-Zn-O based film as a channel forming region. These drive technologies can be combined due to their good dynamic characteristics. do.

[0127] In addition, when a light-emitting display device is manufactured, the electrode (also called the cathode) on the low power supply potential side of the organic light-emitting element is (called a low-potential power supply) is set to, for example, GND or 0V by connecting the cathode to the terminal. For example, a fourth terminal is provided for setting the voltage to GND, 0 V, etc. In the case of manufacturing a pixel, a power supply line is provided in addition to a source line and a gate line. The terminal portion is provided with a fifth terminal that is electrically connected to a power supply line.

[0128] Note that in this embodiment, a structure in which a source electrode layer and a drain electrode layer overlap with an oxide semiconductor layer is used. The fabrication method was explained using a transistor with this structure as an example, but by changing the order of the steps, A transistor having a structure in which an oxide semiconductor layer overlaps a source electrode layer and a drain electrode layer is fabricated. It is also possible to manufacture

[0129] By the above steps, a transistor having good electrical characteristics and high reliability and a semiconductor device using the transistor can be manufactured. It is possible to provide a display device having such a configuration.

[0130] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0131] (Embodiment 3) In this embodiment, at least a part of the driver circuit and a transistor disposed in the pixel portion are formed on the same substrate. An example of how to fabricate a transistor is described below.

[0132] The transistors arranged in the pixel portion are formed according to the first and second embodiments. The transistors shown in the first and second embodiments are n-channel transistors, and therefore, In other words, a part of the driver circuit that can be configured with n-channel transistors is It is formed on the same substrate as the resistor.

[0133] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. A signal line driver circuit 5303 and a signal line driver circuit 5304 are provided in the pixel portion 5301. A signal line is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit 5305. The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. At the intersections of the scan lines and the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is made of a flexible printed circuit board (FPC). A timing control circuit 5305 (controller, control circuit) and other connecting parts are connected to the timing control circuit 5305. The power supply is connected to the power supply IC (also called the control IC).

[0134] As shown in FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, The signal line driver circuit 5304 is formed over the same substrate 5300 as the pixel portion 5301. Therefore, the number of externally provided parts such as drive circuits can be reduced, leading to cost reduction. In addition, the number of connections (such as FPCs) between the substrate 5300 and the external drive circuit can be reduced. Therefore, it is possible to improve the reliability or the yield.

[0135] The timing control circuit 5305 is, for example, The first scanning line driving circuit start signal (GSP1) (the start signal is a start pulse Also, the timing The control circuit 5305 controls the second scanning line driver circuit 5303 to control the second scanning line Provides the start signal (GSP2) for the driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit is supplied to the signal line driver circuit 5304. Clock signal for the driver circuit (SCK), data for the video signal (DATA) (simply video signal Each clock signal has a period of It may be multiple clock signals with different timings, or it may be an inverted clock signal (CKB) and The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be supplied to the same circuit. It is possible to omit one of the line driver circuits 5302 and 5303 .

[0136] In FIG. 14B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to the structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The transistors can be used to configure the driving circuits formed on the substrate 5300. This allows for the enlargement of display devices, the reduction of the number of steps, the reduction of costs, and the improvement of yields. It is possible.

[0137] The transistors described in Embodiments 1 and 2 are n-channel transistors. 15(A) and 15(B) show the configuration of a signal line driver circuit configured with n-channel transistors. An example of the configuration and operation will be described below.

[0138] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a , multiple transistors 5603_1 to 5603_k (k is a natural number) The transistors 5603_1 to 5603_k are n-channel transistors. An example will be described.

[0139] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to , and are connected to signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are , and is connected to wiring 5605_1.

[0140] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0141] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function of controlling the conduction state between the wirings S1 to Sk, that is, the wirings 5604_1 to 5604_k. The transistor 5603_1 has a function of supplying a potential to the signal lines S1 to Sk. . . 5603_k each have a function as a switch.

[0142] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0143] Next, the operation of the signal line driver circuit of FIG. 15(A) will be described with reference to the timing chart of FIG. 15(B). FIG. 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0144] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0145] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 The transistor 5601 outputs a high-level signal to the wiring 5605_1. 03_1 to 5603_k will be turned on, so wires 5604_1 to 5604_k and signal lines At this time, the wirings 5604_1 to 5604_k are connected to Da ta(S1)~Data(Sk) are input. Data(S1)~Data(Sk) are , each of which is connected to a pixel in a selected row via a transistor 5603_1 to 5603_k. In this manner, during the periods T1 to TN, the selected pixels are written into the pixels in the first to k-th columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. can be.

[0146] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. A) is written to the pixels in multiple columns at a time, which allows the writing time to be extended. This makes it possible to prevent insufficient writing of video signal data (DATA).

[0147] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment and It is possible to use a circuit consisting of transistors shown in FIG. All the transistors in the resistor 5601 can be made of unipolar transistors. can.

[0148] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 16 and FIG. 17.

[0149] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the clock signal (CK) and the start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, The capacitor used is capable of carrying a large current.

[0150] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), the pulse output A signal from the circuit (called the previous stage signal OUT(n-1)) is input. Also, the first pulse output The output circuit 10_1 receives a signal from a third pulse output circuit 10_3, which is two stages behind. Similarly, in the n-th pulse output circuit 10_n in the second or subsequent stage, the (n+2)-th The signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs a signal to the pulse output circuit of the following stage and / or the preceding stage. A first output signal (OUT(1)(SR) to OUT(N)(SR)) for inputting another The second output signals (OUT(1) to OUT(N)) are outputted to be inputted to a circuit or the like. As shown in FIG. 16A, the last two stages of the shift register are connected to the rear stage signal OUT Since (n+2) is not input, for example, the second start pulse SP2 and the third The start pulse SP3 may be input to each of the first and second inputs.

[0151] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK depending on the input drive circuit. It is sometimes called SCK, but here we will use CK for explanation.

[0152] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 16A to 14. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 is The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third input terminal 23 is electrically connected to the fourth wiring 14. is.

[0153] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0154] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal transformers. In addition to the transistor, the four-terminal transistor described in the above embodiment can be used. Regarding the symbol of the four-terminal transistor 28 described in the above embodiment, The symbol of the transistor 28 shown in FIG. 16C denotes a four-terminal transistor. The transistor 28 has a first gate electrode connected to the input terminal. A first control signal G1 input to the gate electrode and a second control signal G2 input to the second gate electrode are used to This is an element that can perform electrical control between the In terminal and the Out terminal.

[0155] When an oxide semiconductor is used for the channel layer of a transistor, the threshold voltage Therefore, the oxide in the channel layer may shift to the negative or positive side. In the case of a transistor using a semiconductor, a structure in which the threshold voltage can be controlled is preferable. The threshold voltage of the transistor 28 shown in FIG. Gate electrodes are provided above and below the panel formation region via gate insulating films, and By controlling the potential of the gate electrode, it can be controlled to a desired value.

[0156] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. This will be explained using (D).

[0157] The pulse output circuit shown in FIG. 16(D) includes a first transistor 31 to a thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied is provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is supplied to the first transistor 31 to the thirteenth transistor 43 from a power supply line 53 connected to the The power supply potential is supplied to each of the power supply lines in FIG. The first high power supply potential VDD is a power supply potential equal to or higher than the second high power supply potential VCC. The potential VCC is set to a potential higher than the third low power supply potential VSS. (CK1) through the fourth clock signal (CK4) alternate between H and L levels at regular intervals. The signal that is returned is VDD when it is H level and VSS when it is L level. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without imparting As a result, the shift in the threshold voltage of the transistor can be reduced, and degradation can be suppressed. As shown in (D), among the first transistor 31 to the thirteenth transistor 43, The first transistor 31 and the sixth to ninth transistors 36 to 39 are shown in FIG. It is preferable to use a four-terminal transistor 28 shown in FIG. 16(C). The operation of the sixth transistor 31, the sixth transistor 36 to the ninth transistor 39 is The potential of the node to which one of the drain electrodes is connected is controlled by the gate electrode control signal. A transistor that is required to switch in response to a control signal input to its gate electrode. The fast response (the rise of the on-current is steep) reduces malfunction of the pulse output circuit. Therefore, the four-terminal transistor shown in FIG. By using the transistor 28, the threshold voltage can be controlled, and malfunctions are further reduced. In FIG. 16(D), the first control signal G1 and The first control signal G1 and the second control signal G2 are the same control signal, but different control signals may be input. Good too.

[0158] In FIG. 16D, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode (first gate electrode and The gate electrode of the seventh transistor (2) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a first gate electrode and a second gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the first gate electrode and the second gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the first gate electrode and the second gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 are electrically connected to the are electrically connected.

[0159] In FIG. 16D, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 40 and the second terminal of the ninth transistor 39 is defined as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is a node Let us call it B (see FIG. 17(A)).

[0160] FIG. 17A shows the pulse output circuit described in FIG. 16D as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0161] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0162] A transistor is defined as an element having at least three terminals including a gate, a drain, and a source. In addition, a semiconductor in which a channel region is formed in a region overlapping with a gate is used as the element. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain is controlled by the Since it depends on the structure and operating conditions, it is not possible to determine which is the source or drain. Therefore, it is difficult to form the regions that function as the source and drain into a single region. In some cases, they are not called the first terminal or the drain. It may be written as 2 terminals.

[0163] In FIG. 16(D) and FIG. 17(A), node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0164] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 17(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0165] As shown in FIG. 17A, the ninth transistor in which the second power supply potential VCC is applied to the gate electrode By providing the transistor 39, the following can be achieved before and after the bootstrap operation: The advantages are as follows:

[0166] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large voltage is applied, which causes a large stress and can lead to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing a resistor 39, the potential of node A rises due to the bootstrap operation. However, the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, the first transistor 3 The negative voltage applied between the gate and source of 1 can be reduced. By using the circuit configuration of this embodiment, the gate and source of the first transistor 31 Since the negative voltage applied between the first transistor 31 and the second transistor 32 can be reduced, the stress-induced damage to the first transistor 31 can be reduced. Deterioration can be suppressed.

[0167] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0168] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-state current of a transistor is reduced, and the on-state current and electric field The effective mobility can be increased and the degree of deterioration can be reduced, so In addition, a transistor using an oxide semiconductor can reduce malfunctions in the circuit. Compared to transistors using rufus silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0169] The gate electrodes (first gate electrode and second gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; A second input terminal 22 supplies a potential to the first gate electrode and the second gate electrode. The clock signal is applied to the gate electrode of the seventh transistor 37 (the gate electrode of the first transistor and the gate electrode of the second transistor). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The third input terminal 23 is connected to the gate electrodes (the first gate electrode and the second gate electrode) of the transistor 38. The same effect can be obtained by swapping the wiring so that the clock signal is supplied by In the shift register shown in FIG. The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor The potential at node B is decreased by the third input 38 being turned on and off. When the potential of the input terminal 23 is decreased, the voltage applied to the gate electrode of the seventh transistor 37 is decreased. The potential at the second input terminal 22 is decreased, so that the gate of the eighth transistor 38 is turned on. This occurs twice due to the decrease in the potential applied to the electrode. In the shift register shown in FIG. 1, a seventh transistor 37 and an eighth transistor 38 From a state where both are on, the seventh transistor 37 is on and the eighth transistor 38 is off. Then, the seventh transistor 37 is turned off and the eighth transistor 38 is turned off. As a result of the sequential change, the potentials of the second input terminal 22 and the third input terminal 23 decrease. The potential drop at node B caused by this is applied to the gate electrode of the eighth transistor 38. Therefore, the seventh transistor 37 A clock signal is input from the third input terminal 23 to the gate electrodes (first gate electrode and second gate electrode). A clock signal CK3 is supplied to the gate electrode of the eighth transistor 38 (the first gate electrode and and the second gate electrode) are connected to a clock signal CK2 from the second input terminal 22. This is because the number of times the potential of the node B changes is reduced, and the noise level is reduced. This is because it is possible to reduce noise.

[0170] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0171] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0172] (Embodiment 4) The transistor described in Embodiments 1 and 2 is manufactured, and the transistor is used in a pixel portion and a driving By using the semiconductor device in the operating circuit, a semiconductor device having a display function (also called a display device) can be manufactured. In addition, the transistor described in any one of Embodiments 1 and 2 may be used as a part or an entire driver circuit. The display unit can be integrally formed on the same substrate as the display unit to form a system-on-panel.

[0173] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0174] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0175] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit) inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0176] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 20A1 and 20A2 show a structure of a semiconductor device formed on a first substrate 4001. The In-Ga-Zn-O based film shown in the first and second embodiments is included as an oxide semiconductor layer. The transistors 4010 and 4011 and the liquid crystal element 4013 are formed on the second substrate. 20(a) is a top view of the panel sealed with a sealant 4005 between the panel 4006 and the panel 4007. 20B) corresponds to a cross-sectional view taken along line MN in FIG. 20(A1)(A2).

[0177] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0178] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method. FIG. 20(A2) shows a signal line driver circuit 4003 mounted by the TAB method. In this example, the signal line driver circuit 4003 is implemented by the above.

[0179] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 20B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. do.

[0180] The transistors 4010 and 4011 are made of an In-Ga-Zn-O-based film as an oxide semiconductor layer. The highly reliable transistors described in Embodiments 1 and 2 can be used in the present embodiment. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. .

[0181] The channel of the oxide semiconductor layer of the transistor 4011 for the driver circuit is formed on the insulating layer 4044. A conductive layer 4040 is provided in a position overlapping the hole formation region. By placing the conductor layer at a position that overlaps with the channel formation region, The amount of change in the threshold voltage of the transistor 4011 can be reduced. The potential of the gate electrode layer of the transistor 4011 may be the same as or different from that of the gate electrode layer of the transistor 4011. In addition, the conductive layer 4040 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0182] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 is formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033. However, the color filters are provided on either the first substrate 4001 or the second substrate 4006. is also good.

[0183] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film You can also use aluminum foil with PVF film or polyester film. Alternatively, a sheet having a structure in which the sheet is sandwiched between two films may be used.

[0184] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. The common connection portion is used to connect the opposing electrode layers via conductive particles disposed between the pair of substrates. The conductive particles can be used as a sealing material. Include in 4005.

[0185] In addition, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs. c. or more and 100 μsec or less. It is optically isotropic, so no alignment process is required. The viewing angle dependency is small. When using a blue phase, the configuration is not limited to that shown in FIG. The electrode layer corresponding to the polar layer 4031 is formed on the same substrate side as the pixel electrode layer 4030. A so-called in-plane electric field mode configuration may also be used.

[0186] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. The present invention can also be applied to semi-transmissive liquid crystal display devices.

[0187] In the liquid crystal display device of the present embodiment, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and In the example shown, a colored layer (color filter) and an electrode layer used for a display element are provided in this order. The plate may be provided on the inner side of the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment. The thickness can be appropriately set depending on the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. A light-shielding film that functions as a rack matrix may be provided.

[0188] In this embodiment, in order to reduce surface irregularities caused by transistors, In order to improve the reliability of the transistor, the transistor obtained in the second embodiment is It is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as an insulating film. The protective film prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor suspended in the air. The protective film is made of silicon oxide by sputtering. Con film, silicon nitride film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film a single layer of an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, the protective film is formed by a sputtering method. However, there is no particular limitation and various methods may be used for forming the insulating layer.

[0189] Here, an insulating layer 4020 having a laminated structure is formed as a protective film. The first layer of the silicon oxide film is formed by sputtering. By using a silicon film, the hysteresis of the aluminum film used as the source electrode layer and the drain electrode layer can be improved. It is effective in preventing lockup.

[0190] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. A silicon nitride film is used as a protective film. When this happens, mobile ions such as sodium penetrate into the semiconductor region, affecting the electrical properties of the transistor. It is possible to suppress the change.

[0191] After forming the protective film, the oxide semiconductor layer is annealed (at 300° C. or higher and 400° C. or lower). may be carried out.

[0192] In addition, an insulating layer 4021 is formed as a planarizing insulating film. Heat-resistant resins such as styrene resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass) In addition, it is possible to laminate multiple insulating films made of these materials. In this manner, the insulating layer 4021 may be formed.

[0193] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0194] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, At the same time, the oxide semiconductor layer is annealed (at 300°C to 400°C). The baking process of the insulating layer 4021 may be performed in combination with the annealing process of the oxide semiconductor layer, so that the efficiency can be improved. This makes it possible to quickly manufacture a semiconductor device.

[0195] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0196] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0197] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0198] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0199] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive film as the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0200] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0201] In FIG. 20, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0202] FIG. 21 shows a transistor substrate manufactured by using the transistors shown in the first and second embodiments. 26 shows an example of a liquid crystal display module formed as a semiconductor device using a board 2600.

[0203] FIG. 21 shows an example of a liquid crystal display module, which includes a transistor substrate 2600 and an opposing substrate 260. 1 is fixed by a sealing material 2602, and a pixel portion 2603 including a transistor and the like is provided between them. A display element 2604 including a liquid crystal layer and a colored layer 2605 are provided to form a display area. The color layer 2605 is necessary for color display. In the case of the RGB method, it is red, green, and blue. A colored layer corresponding to each color is provided for each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outer side of the counter substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and is mounted on a circuit board 2612. The wiring circuit section 260 of the transistor substrate 2600 is connected to the flexible wiring substrate 2609. 8 and incorporates external circuits such as a control circuit and a power supply circuit. The optical plate and the liquid crystal layer may be laminated with a retardation plate between them.

[0204] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid uid Crystal) mode, AFLC(AntiFerroelectric L iquid Crystal mode etc. can be used.

[0205] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0206] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0207] (Embodiment 5) In this embodiment, a semiconductor device to which the transistor described in Embodiments 1 and 2 is applied is An example of electronic paper is shown.

[0208] FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the transistor shown in Embodiments 1 and 2. can be applied.

[0209] The electronic paper in FIG. 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0210] The transistor 581 formed on the substrate 580 is a bottom-gate transistor. , a first electrode layer 587 and insulating layers 583 and 584 are formed by a source electrode layer or a drain electrode layer. 4 and 585 are in contact with each other and electrically connected to each other. Between the second electrode layer 588 formed on the substrate 596 and the first electrode layer 588, there are black areas 590a and white areas A spherical particle 58 having a region 590b and including a cavity 594 filled with liquid therearound. 9 is provided, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin ( (See FIG. 13.) In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a pixel electrode. The second electrode layer 588 corresponds to a common electrode. The common connection portion is electrically connected to a common potential line provided on the same substrate. The second electrode layer 588 and the common potential line are electrically connected via conductive particles disposed between the substrates. It can continue.

[0211] Also, instead of the twist ball, an electrophoretic element can be used. and a 2-cell sphere with a diameter of 10 μm or more that contains positively charged white particles and negatively charged black particles. The microcapsules are placed between the first and second electrode layers. The microcapsules are subjected to an electric field by the first and second electrode layers. When this happens, the white particles and the black particles move in opposite directions, resulting in a white or black display. A display element that applies this principle is an electrophoretic display element. The device is generally called electronic paper. Electrophoretic display elements are liquid crystal display elements. Because it has a higher reflectivity than the children, auxiliary lights are not required, and it consumes less power and is dim. The display can be recognized even in a place where the power is not supplied to the display. Even if the image is displayed, it is possible to retain the image once it has been displayed, so the device with the display function can be easily moved away from the radio wave source. The semiconductor device (also referred to simply as a display device or a semiconductor device equipped with a display device) was kept away from the Even if the image is not displayed correctly, it is possible to store the displayed image.

[0212] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0213] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0214] (Embodiment 6) In this embodiment, a semiconductor device to which the transistor described in Embodiments 1 and 2 is applied is An example of a light-emitting display device is shown. Here, an electroluminescent device is used as a display element of the display device. The following uses a light-emitting element that utilizes electroluminescence. Devices are classified according to whether the light-emitting material is an organic compound or an inorganic compound. The former are called organic EL elements and the latter inorganic EL elements.

[0215] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0216] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0217] FIG. 18 shows a display device to which digital time gray scale driving can be applied as an example of a semiconductor device to which the present invention is applied. FIG. 2 is a diagram illustrating an example of an element configuration.

[0218] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The oxide semiconductor layer (In-Ga-Zn-O-based film) shown in the first and second embodiments is This shows an example in which two n-channel transistors are used in the panel formation region in one pixel. .

[0219] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0220] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0221] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as A capacitance may be formed between the region and the gate electrode.

[0222] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0223] Also, when analog gray scale driving is used instead of digital time gray scale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 18 can be used.

[0224] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 plus the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0225] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0226] Next, the configuration of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an example in which the capacitor is of n-type. C) Transistors 7001 and 701 which are driving transistors used in the semiconductor device 1 and 7021 can be manufactured in the same manner as the transistors shown in the first and second embodiments. -A highly reliable transistor that contains a Zn-O based film as an oxide semiconductor layer.

[0227] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission is from the top surface, the bottom emission is from the surface on the substrate side, and the bottom emission is from the surface on the substrate side and the opposite side to the substrate. There is a light-emitting element having a dual-side emission structure in which light is emitted from both sides. The present invention can be applied to any light emitting element with any emission structure.

[0228] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0229] The driving transistor 7011 is an n-type transistor, and light emitted from the light emitting element 7012 is incident on the first electrode 7013. FIG. 19(A) shows a cross-sectional view of a pixel when light is emitted to the 7013 side. A conductive film 7017 having a light-transmitting property and electrically connected to the drain electrode layer of the transistor 7011 is A first electrode 7013 of the light emitting element 7012 is formed on the first electrode 7013. An L layer 7014 and a second electrode 7015 are laminated in this order.

[0230] The light-transmitting conductive film 7017 can be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, oxide carbide A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0231] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a relatively small work function, specifically For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr. , and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth elements such as Yb and Er. Metal or the like is preferable. In FIG. 19A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through. (Preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is A silicon film is used as the first electrode 7013 .

[0232] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the light-transmitting conductive film 7017 and the first electrode 7013 may be formed. This is preferable because the same mask can be used for etching.

[0233] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7019 is formed by using a photosensitive resin material. 13, and an opening is formed on the surface of the substrate 13, and the side wall of the opening is an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7019, In this case, the step of forming a resist mask can be omitted.

[0234] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. When the EL layer 7014 is composed of a plurality of layers, An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole transport layer, and a hole transport layer are formed on a first electrode 7013 that functions as a light emitting layer. It is not necessary to provide all of these layers except for the light emitting layer.

[0235] In addition, the stacking order is not limited to the above, and the first electrode 7013 may function as an anode. A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a By stacking the layers in the order of insertion, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0236] In addition, the second electrode 7015 formed on the EL layer 7014 can be made of various materials. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0237] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0238] In FIG. 19A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7030, and The light is then emitted through the substrate 7010.

[0239] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0240] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 19A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as an acrylic resin, and is colored. It has the function of flattening unevenness caused by the -filter layer 7033.

[0241] In addition, a protective insulating layer 7035, an overcoat layer 7034, a color filter layer 7033, an insulating layer A contact hole is formed on the edge layer 7032 and the oxide insulating layer 7031 and reaches the drain electrode layer. The contact hole is disposed at a position overlapping with the partition wall 7019 .

[0242] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0243] In FIG. 19B, the drain electrode layer of the driving transistor 7021 is electrically connected to A first electrode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027. An EL layer 7024 and a second electrode 7025 are laminated in this order on a first electrode 7023. There are.

[0244] The light-transmitting conductive film 7027 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, oxide carbide A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0245] In addition, various materials can be used for the first electrode 7023. For example, When using 23 as a cathode, a material with a relatively small work function, specifically, for example, Li Alkaline metals such as Ca and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing Mg (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment mode, the first electrode 7023 is used as a cathode, and its thickness is set to a thickness that allows light to pass through. For example, the thickness of the 20 nm thick film is set to a value of about 5 nm to 30 nm. An aluminum film is used as the cathode.

[0246] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the light-transmitting conductive film 7027 and the first electrode 7023 may be formed by the same method. It is preferable that the same mask be used for etching.

[0247] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7029 is formed by using a photosensitive resin material. 23, and an opening is formed on the surface of the substrate 23, and the side wall of the opening is an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0248] In addition, the EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is sufficient if the material is made up of a single layer or multiple layers are laminated. Either is acceptable. When the EL layer 7024 is composed of multiple layers, it functions as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer It is not necessary to provide all of these layers except for the light-emitting layer.

[0249] In addition, the stacking order is not limited to the above. The first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. In this case, power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because

[0250] In addition, the second electrode 7025 formed on the EL layer 7024 can be made of various materials. For example, when the second electrode 7025 is used as an anode, the work function is relatively large. It is preferable to use a transparent conductive material such as ITO, IZO, or ZnO. In this embodiment, the second electrode 7025 is used as an anode, and an I Form a TO film.

[0251] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. The light emitted from 7022 is incident on the second electrode 7025 side and the first electrode 70 as shown by the arrow. 23 It is fired on both sides.

[0252] In FIG. 19B, the light emitted from the light-emitting element 7022 to the first electrode 7023 side One light passes through the color filter layer 7043, the insulating layer 7042, and the oxide insulating layer 704 1, through the first gate insulating layer 7040 and the substrate 7020.

[0253] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0254] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0255] In addition, a protective insulating layer 7045, an overcoat layer 7044, a color filter layer 7043, an insulating layer A contact hole is formed on the edge layer 7042 and the oxide insulating layer 7041 and reaches the drain electrode layer. The contact hole is disposed at a position overlapping with the partition wall 7029 .

[0256] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is used. It is preferable that a sealing substrate having a -filter layer is provided above the second electrode 7025.

[0257] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0258] In FIG. 19C, a transistor 7001 which is a driving transistor is an n-type light-emitting element 7 7 shows a cross-sectional view of a pixel in the case where light emitted from 002 exits to the second electrode 7005 side. In FIG. 19C, the drain electrode layer of the driving transistor 7001 is electrically connected to A first electrode 7003 of the light emitting element 7002 is formed, and E An L layer 7004 and a second electrode 7005 are laminated in this order.

[0259] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a relatively small work function, specifically, for example, Li Alkaline metals such as Ca and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing Mg (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. stomach.

[0260] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7009 is formed by using a photosensitive resin material. 03, an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7009, In this case, the step of forming a resist mask can be omitted.

[0261] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. When the EL layer 7004 is composed of a plurality of layers, On the first electrode 7003 used for the above-mentioned purpose, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole It is not necessary to provide all of these layers except for the light emitting layer.

[0262] The stacking order is not limited to the above, and the hole injection layer 7002 may be formed on the first electrode 7003 used as an anode. Alternatively, the layer may be laminated in the following order: a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.

[0263] In FIG. 19(C), a hole injection was performed on a laminated film in which a Ti film, an aluminum film, and a Ti film were laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0264] However, when the transistor 7001 is an n-type transistor, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the driving circuit. This is preferable because it is possible to suppress a voltage rise and reduce power consumption.

[0265] The second electrode 7005 is formed using a light-transmitting conductive material, for example, an oxide. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Permeable materials such as indium tin oxide, indium zinc oxide, and indium tin oxide doped with silicon oxide A conductive film having optical properties may be used.

[0266] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 19C, the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0267] In FIG. 19C, the drain electrode layer of the transistor 7001 is formed of an oxide insulating layer. Through contact holes provided in the protective insulating layer 7051, the protective insulating layer 7052, and the insulating layer 7055, The planarization insulating layer 7053 is made of polyimide, acrylic, or the like. Examples of the resin material that can be used include polystyrene, benzocyclobutene, polyamide, and epoxy. In addition to the above resin materials, low-dielectric constant materials (low-k materials), siloxane resins, and PSG are also available. (phosphorus glass), BPSG (boron phosphorus glass), etc. can be used. The planarization insulating layer 7053 can be formed by stacking a plurality of insulating films made of the above material. The method for forming the planarization insulating layer 7053 is not particularly limited. method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method , screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater A coater, knife coater, etc. can be used.

[0268] In addition, a partition wall 700 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition wall 7009 is made of an organic resin such as polyimide, acrylic, polyamide, or epoxy. The partition wall 7009 is formed by using an oil film, an inorganic insulating film, or an organic polysiloxane. An opening is formed on the first electrode 7003 using a photosensitive resin material, and the side wall of the opening is It is preferable to form the partition wall 700 so as to have an inclined surface having a continuous curvature. When a photosensitive resin material is used as 9, the step of forming a resist mask can be omitted. can be done.

[0269] In the structure of FIG. 19C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added, making a total of four. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0270] In the structure of FIG. 19(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0271] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0272] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0273] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0274] In addition, the transistor (driving transistor) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control transistor may be connected between the driving transistor and the light emitting element. A transistor may be connected.

[0275] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications are possible based on the technical concept according to one aspect of the present invention.

[0276] Next, a semiconductor device according to one embodiment of the present invention to which the transistor described in Embodiments 1 and 2 is applied will be described. The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) will be described with reference to FIG. FIG. 22 shows a structure in which a transistor and a light-emitting element formed on a first substrate are bonded to a second substrate. FIG. 22(B) is a top view of the panel sealed with a sealant between the panels. This corresponds to the cross-sectional view taken along line HI of FIG.

[0277] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0278] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. In FIG. 22B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0279] The transistors 4509 and 4510 are made of an In-Ga-Zn-O-based film as an oxide semiconductor layer. The highly reliable transistors described in Embodiments 1 and 2 can be used in the present embodiment. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. .

[0280] A channel of an oxide semiconductor layer of a transistor 4509 for a driver circuit is formed over an insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. By placing the conductor layer at a position that overlaps with the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. 40 may have the same potential as the gate electrode layer of the transistor 4509 or may have a different potential. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0281] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is determined according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0282] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0283] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0284] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon oxide nitride film, a DLC film, etc.

[0285] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0286] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source and drain electrode layers in the second transistor 10 are formed from the same conductive film as those in the second transistor 10.

[0287] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0288] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a film is used.

[0289] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler. The substance was used.

[0290] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0291] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the circuit or only a part of the circuit may be separately formed and mounted. In this embodiment, the circuit shown in FIG. Not limited.

[0292] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0293] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0294] (Embodiment 7) The semiconductor device to which the transistor described in Embodiments 1 and 2 is applied is suitable for electronic paper. Electronic paper can be used in any field as long as it displays information. For example, electronic paper can be used to display electronic books (e-books) ), posters, in-car advertisements on trains and other vehicles, and on various cards such as credit cards It can be applied to displays, etc. An example of an electronic device is shown in Figures 11 and 12.

[0295] FIG. 11(A) shows a poster 2631 made of electronic paper. When the advertisements are printed on paper, they are replaced manually. You can change the display of your ad in a short time. Also, the display is stable and the image does not collapse. The poster may be configured to transmit and receive information wirelessly.

[0296] FIG. 11B shows an advertisement 2632 on a train or other vehicle. When using printed paper, advertisements are replaced manually, but with electronic paper, This allows you to change the display of your ads in a short time without a lot of manual labor. The in-car advertisement system is structured to transmit and receive information wirelessly. It is also possible to use the following.

[0297] FIG. 12 shows an example of an electronic book. For example, an electronic book 2700 has a housing 27 The device is made up of two housings, housing 2701 and housing 2703. 3 is integrated with an axis portion 2711, and performs opening and closing operations around the axis portion 2711. With this configuration, it becomes possible to operate like a paper book.

[0298] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 12) and An image can be displayed on the display unit 2707 in FIG.

[0299] FIG. 12 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0300] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0301] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0302] (Embodiment 8) The semiconductor device using the transistor described in Embodiments 1 and 2 can be used in various electronic devices (play The present invention can be applied to electronic devices such as television sets ( Televisions, also known as television receivers, computer monitors, digital Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, mobile (also called telephone equipment), portable game machines, personal digital assistants, audio playback devices, pachinko machines, etc. Examples include large game consoles.

[0303] FIG. 23A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0304] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0305] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0306] FIG. 23B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0307] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0308] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0309] FIG. 24(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 24(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the present invention is It is sufficient that the device is provided with the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable game machine shown in FIG. 24(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading the program or data and displaying it on the display unit, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 24(A) has the following functions: The function is not limited to this and may have various functions.

[0310] FIG. 24(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and it is sufficient that the present invention is provided with at least the semiconductor device according to the present invention. The configuration may be such that appropriate equipment is provided.

[0311] FIG. 25A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002, the operation buttons 1003, the external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0312] The mobile phone 1000 shown in FIG. 25A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an e-mail can be performed by using the display. This can be done by touching 1002 with a finger or the like.

[0313] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0314] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0315] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0316] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0317] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0318] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0319] FIG. 25B is also an example of a mobile phone. The mobile phone in FIG. 25B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 and a housing 9401 An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in the two directions shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400, and the display device The communication device 9400 and the display device 9410 may be used alone. Images or input information can be sent and received via wireless or wired communication, and each can be recharged with a rechargeable battery. Has Terry.

[0320] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0321] (Embodiment 9) When the oxide semiconductor layer comes into contact with the metal layer or the oxide insulating layer, a phenomenon occurs in which oxygen is transferred. In this embodiment, the difference between the case where the oxide semiconductor layer is amorphous and the case where the oxide semiconductor layer is crystalline will be described. Explain the results of scientific calculations on phenomena.

[0322] FIG. 33 illustrates a structure of a transistor according to one embodiment of the present invention, in which an oxide semiconductor layer and a source FIG. 1 is a schematic diagram showing a state in which a metal layer that will become a drain electrode and an oxide insulating layer are in contact with each other. The arrows indicate the direction of oxygen transfer when the two are in contact or heated. It indicates the direction.

[0323] When oxygen vacancies occur in an I-type oxide semiconductor layer, the layer exhibits N-type conductivity. An oxide semiconductor layer that is N-type due to defects becomes I-type when oxygen is supplied in excess. In actual device processes, this effect is utilized, and the metals that become the source and drain electrodes are In the oxide semiconductor layer in contact with the metal layer, oxygen is attracted to the metal side, and the part of the contact area (thickness If the thickness is thin, oxygen vacancies occur throughout the entire thickness direction, causing the material to become N-type, and good contact with the metal layer is obtained. In addition, the oxide semiconductor layer in contact with the oxide insulating layer can be formed by removing the oxide Oxygen is supplied to the semiconductor layer, and part of the contact area (or the entire thickness direction if the film thickness is thin) The oxygen in the region becomes excessive, becoming an I-type region and functioning as a channel formation region of a transistor. do.

[0324] In one embodiment of the present invention, a metal layer and an oxide semiconductor layer which are to be a source electrode and a drain electrode are In the region where the oxide insulating layer comes into contact, a crystalline region consisting of needle-shaped crystals is formed, and the amorphous Scientific calculations were used to verify whether there were any differences in the state of the material and the form of oxygen transfer.

[0325] The model used for the scientific calculations is a rectangular parallelepiped of In-Ga-Zn-O system amorphous and crystalline structure. A specimen with 10% oxygen loss on one side of the longitudinal direction was used (see Figure 34). Calculation details The figure compares the distribution of oxygen after 10 nsec under accelerated conditions at 650°C. The respective conditions are shown in Tables 1 and 2.

[0326] [Table 1]

[0327] [Table 2]

[0328] As a result of the calculation under the above conditions, the oxygen distribution when an amorphous material is used is shown in FIG. The distribution of oxygen when the crystal is used is shown in Fig. 35(B). The dotted line indicates the initial state, and the actual state indicates the The line shows the results (after 10 nsec.). The change in distribution indicates that oxygen is moving regardless of whether it is amorphous or crystalline. I know it's moving.

[0329] In the region with oxygen vacancies, the increase in oxygen atoms before and after the calculation was 15.9% in the amorphous state and 15.9% in the crystalline state. In other words, oxygen is more mobile in the amorphous material than in the crystalline material, and oxygen vacancies can be filled more easily. In other words, oxygen is relatively less mobile in crystals than in amorphous materials. This will result in...

[0330] Therefore, the oxide semiconductor layer according to one embodiment of the present invention has a crystal region made of a group of needle-shaped crystals. It was confirmed that oxygen transfer occurs in the same way when the oxide semiconductor layer is amorphous. In addition, oxygen is less mobile in crystals than in amorphous materials, so the needle-shaped crystals It was confirmed that the crystalline region having the effect of suppressing the desorption of oxygen from the oxide semiconductor layer. Ta. EXAMPLES

[0331] In this embodiment, an oxide semiconductor film was dehydrated or dehydrogenated at high temperature for a short time by an RTA method. The state of the material was analyzed using TEM analysis, TEM-EDX analysis, X-ray diffraction, and SIMS analysis. The results of the analysis will be explained below.

[0332] The sample used for the analysis was an oxide with a molar ratio of In2O3:Ga2O3:ZnO=1:1:1. An In-Ga-Zn-O based film produced according to the second embodiment using a semiconductor target. The sample was heated at 650℃ for 6 minutes in a nitrogen gas atmosphere using an RTA device. For comparison, a heating process was performed at 450°C for 1 hour in a nitrogen gas atmosphere using an electric furnace. The three types are sample B, sample C (as-depo), and sample B (unheated).

[0333] First, to examine the crystalline state of each sample, a high-resolution transmission electron microscope (Hitachi The cross section was observed at an accelerating voltage of 300 kV using a TEM (H9000-NAR, manufactured by Eppendorf). Figure 26 shows cross-sectional photographs of sample A, Figure 27 shows cross-sectional photographs of sample B, and Figure 28 shows cross-sectional photographs of sample C. In this figure, (A) is a low-magnification photograph (2 million times), and (B) is a high-magnification photograph (4 million times).

[0334] Specimen A, which was heated at 650°C for 6 minutes by the RTA method shown in Figure 26, has the following characteristics in its cross section: A continuous lattice image was observed in the surface layer. In particular, in the high-magnification photograph of Figure 26(B), the area enclosed in a white frame A clear lattice image was observed in the region, suggesting the presence of aligned microcrystals. The surface of the In-Ga-Zn-O system film was heated at 650℃ for about 6 minutes using the RTA method. It was found that the layer was crystallized and had a crystalline region. In other regions, no clear continuous lattice image was observed, and only small amorphous regions were observed. It was confirmed that the crystal particles were floating. The particle size of the microcrystals was between 2nm and 4nm. These were so-called nanocrystals.

[0335] On the other hand, the cross-sectional photographs of FIG. 27 (sample B) and FIG. 28 (sample C) show that in any region in the film thickness direction, No clear lattice image was observed, confirming that the material was amorphous.

[0336] 29(A) and (B) show the surface layer of sample A, which was heated at 650°C for 6 minutes by the RTA method. The enlarged photograph of the surface layer and the electron diffraction pattern of the crystalline region are shown in Fig. 29(A). ) are shown with arrows 1 to 5 indicating the direction in which the lattice images are aligned, and the direction perpendicular to the film surface. The electron diffraction pattern shown in Figure 29(B) shows that needle-like crystals grow in the direction of the crystal. The observation was made at the position indicated by the arrow number 3, and the orientation in the c-axis direction was confirmed. The electron diffraction pattern of the In2 It turned out to be Ga2ZnO7.

[0337] FIG. 36 shows the top and side views of In2Ga2ZnO7, a hexagonal layered compound. , the top view is a view of a plane parallel to the a-axis and b-axis, and the side view is a view of a plane parallel to the c-axis. In this figure, the c-axis is perpendicular to the a-axis and the b-axis, and the angle between the a-axis and the b-axis is 120°. 36 shows possible sites 201 for In atoms in the top view, In atoms 202 and G The a atom 203, the Ga or Zn atom 204, and the O atom 205 are shown. As shown in FIG. In2Ga2ZnO7 is a Ga oxide layer between two In oxide layers. The two oxide layers between them are one Ga oxide layer and one Zn oxide layer. , and have an alternating layered structure.

[0338] Figure 30 shows the results of TEM-EDX (energy dispersive X-ray spectroscopy) analysis of the cross section of the surface layer of sample A. The results are shown in Fig. 1. The molar ratio of the raw material target was In2O3:Ga2O3:ZnO = 1:1:1. In contrast, the composition ratio of the surface layer was 1:1 for In or Ga, and 0.3 to 0.4 for Zn. The following ratios were obtained, indicating a slight Zn deficiency.

[0339] Next, the crystal state of the same three samples was analyzed by X-ray diffraction method, and the results are shown in Figure 31. In the charts of each sample, the peaks seen at 2θ=30~36° are In-G This information is derived from a-Zn-O-based materials, and the broadness of the spectrum reflects the amorphous state. However, sample A, which was heated at 650°C for 6 minutes by the RTA method, The peak position is at a lower angle than that of sample C, and the strongest diffraction peak is in the In-Ga-Zn-O crystal material. This suggests the presence of diffraction peaks from the (009) and (101) planes, which show high intensity. Therefore, the presence of crystalline regions in sample A was also confirmed by X-ray diffraction.

[0340] Next, the hydrogen concentration, carbon concentration, and nitrogen concentration in the films of sample A and sample C were measured using SIMS. The results of the analysis (secondary ion mass spectrometry) are shown in Figure 32. The horizontal axis indicates the depth from the sample surface. The position at a depth of 0 nm on the left edge corresponds to the outermost surface of the sample (the outermost surface of the oxide semiconductor layer). is performed from the surface side.

[0341] FIG. 32(A) shows the hydrogen concentration profile. The profile of sample A is the same as that of sample C. It was found that the hydrogen concentration was reduced by more than one order of magnitude compared to the profile. It was confirmed that dehydration or dehydrogenation was effectively achieved by heating for 6 minutes. The profiles of sample A and sample C are the same In-Ga-Z The quantitative determination was performed using a standard sample made of an nO-based oxide semiconductor layer.

[0342] In principle, SIMS analysis can only measure data near the sample surface or near the interface of a multilayer film made of different materials. It is known that it is difficult to obtain accurate data on the In order to obtain accurate data, the profile was taken from a depth of 15 nm to 35 nm of the film thickness of about 40 nm. The files were the subject of evaluation.

[0343] From the profile of sample C, it was found that hydrogen was approximately 3× 10 20 atoms / cm 3 That's about 5 x 10 20 atoms / cm 3 The average hydrogen concentration is as follows: Approximately 4 x 10 degrees 20 atoms / cm 3 It can be seen that the proton of sample A is included. From the file, it was found that the average hydrogen concentration in the oxide semiconductor layer was reduced to about 2 × 10 by dehydrogenation. 19 at oms / cm 3 It can be seen that the noise level has been reduced to .

[0344] Fig. 32(B) shows the carbon concentration profile, and Fig. 32(C) shows the nitrogen concentration profile. Unlike the hydrogen concentration profile, no clear difference was observed between sample A and sample C. The RTA method was used to measure the desorption or incorporation of carbon and nitrogen components by heating at 650°C for 6 minutes. In addition, the secondary ion intensity of H+O is shown in Figure 38, and the secondary ion intensity of H2+O is shown in Figure 39. The secondary ion intensity detection results for both are shown in Fig. 1. The intensity was lower in the sample treated at a higher temperature. Even when heated at 650℃ for 6 minutes using the RTA method, moisture or OH is efficiently removed. It was discovered that this was the case.

[0345] From the above analysis results, it was found that the sample heated to 650℃ for 6 minutes by RTA method had the following characteristics: It was confirmed that a crystalline region consisting of a group of needle-shaped crystals was present in the layer. It was confirmed that the hydrogen concentration in the fuel cell could be reduced to less than one-tenth of its original level. EXAMPLES

[0346] In this example, the transistor described in Embodiment 1 was manufactured, and the results of a -BT test were I will explain it below.

[0347] One of the methods for checking the reliability of transistors is the bias-thermal stress test (hereinafter, The BT test is a type of accelerated test that tests for the deterioration of the battery caused by long-term use. The change in transistor characteristics caused by the BT test can be evaluated in a short time. The amount of change in the threshold voltage of a transistor during the test is an important index for examining reliability. The smaller the change in threshold voltage before and after BT testing, the more reliable the transistor is. It can be said that.

[0348] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is kept constant. The source and drain of the transistor are at the same potential, and the gate is connected to a different potential than the source and drain. The substrate temperature may be appropriately set depending on the purpose of the test. When the potential applied to the gate is higher than the potentials of the source and drain, this is called a +BT test. The case where the potential applied to the gate is lower than the potentials of the source and drain is called the -BT test. say.

[0349] The test strength of the BT test depends on the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film can be determined by the following equation: The potential difference between the drain and the source is divided by the thickness of the gate insulating film. If you want to apply an electric field strength of 2MV / cm to a gate insulating film of 2 nm, the potential difference should be 20V This can be done as follows.

[0350] Voltage refers to the potential difference between two points, and potential refers to the potential at a certain point in a static electric field. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a Generally, it is the potential difference between the potential at a certain point and a reference potential (e.g., ground potential). This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or "voltage". Voltage may be read as electric potential.

[0351] The -BT test was performed at a substrate temperature of 150°C and an electric field strength of 2MV / cm applied to the gate insulating film. The application time was set to 1 hour.

[0352] First, in order to measure the initial characteristics of the transistors to be tested using -BT, the substrate temperature was set to 40°C. The source-drain voltage (hereinafter referred to as drain voltage or Vd) is 1 V. The source-gate voltage (hereinafter referred to as gate voltage or Vg) is set to -20V to +20V. The source-drain current (hereinafter referred to as drain current or Id) when The change in the Vg-Id characteristic, i.e., the Vg-Id characteristic when Vd is 1 V, was measured. The temperature is set at 40°C to prevent moisture absorption on the substrate surface, but if there are no particular problems, the substrate temperature can be set to room temperature ( It is acceptable to measure at 25°C.

[0353] Next, a similar measurement was performed with Vd set to 10 V, and the Vg-Id characteristics were measured when Vd was 10 V. did.

[0354] Next, the substrate temperature was raised to 150° C., and the source and drain voltages of the transistor were The electric field strength applied to the gate insulating film was then set to 2 MV / cm. A voltage was applied to the gate. Here, the thickness of the gate insulating film of the transistor is 100 nm. Therefore, -20V was applied to the gate and held there for 1 hour. Although the time is set to 1 hour, the time may be changed depending on the purpose.

[0355] Next, while keeping the voltage applied to the gate, source, and drain, the substrate temperature was lowered to 40°C. If the voltage application is stopped before the substrate temperature drops completely, the residual heat -The voltage should not be applied because the damage done to the transistor during the BT test would be repaired. After the substrate temperature reaches 40°C, the voltage application is stopped. Strictly speaking, the temperature drop time must be added to the application time, but in practice, the temperature rise to 40°C in a few minutes. Since this was considered to be within the margin of error, the temperature drop time was added to the application time. do not have.

[0356] Next, under the same conditions as the measurement of the initial characteristics, the Vg-Id characteristics were measured when Vd was 1 V and 10 V. The Vg-Id characteristics after the -BT test were obtained.

[0357] FIG. 37(A) shows the Vg-Id characteristics of the transistor before and after the -BT test. The horizontal axis of (A) is the gate voltage (Vg), and the vertical axis is the drain current (Id) versus gate voltage. is shown on a logarithmic scale.

[0358] FIG. 37B is an enlarged view of the portion 900 shown in FIG. 37A. The initial characteristic 901 is , Vg-Id characteristics of the transistor before the -BT test when Vd is 1V. 1 shows the Vg-Id characteristics of the transistor before the -BT test when Vd is 10 V. -BT902 is the Vg-Id characteristic of a transistor when Vd is 1V after the -BT test. -BT912 is the Vg-Id characteristic of the transistor when Vd is 10V after -BT test. It is sexuality.

[0359] From FIG. 37, compared with the initial characteristics 901 and 911, -BT902 and -BT912 It can be seen that the whole is slightly shifted in the positive direction. However, the shift amount is The transistor fabricated in the first embodiment has a very small -BT test It was confirmed that this transistor has high reliability in this application. [Explanation of symbols]

[0360] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 28 Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 Substrates 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 106 Needle-shaped crystals 107 Oxide insulating layer 108 Capacitance wiring 110 Pixel electrode layer 112 Conductive layer 113 Conductive Layer 114 Conductive layer 120 Connection electrode 121 Terminal 122 Terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Light-transmitting conductive film 129 Light-transmitting conductive film 131 Resist mask 150 Terminals 151 Terminal 152 Gate Insulation Layer 153 Connection electrode 154 Protective insulating film 155 Light-transmitting conductive film 156 Electrode 170 Transistors 201 Possible sites for In atoms 202 In atoms 203 Ga or Zn atoms 204 O atoms 580 Substrate 581 Transistor 585 Insulation Layer 583 Insulating Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Board 900 parts 901 Initial Characteristics 902-BT 911 Initial Characteristics 912-BT 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 105a Source electrode layer 105b Drain electrode layer 112a conductive layer 113a conductive layer 114a conductive layer 2600 Transistor Board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4044 Insulation layer 4501 Board 4502 Pixel section 4505 Sealing material 4506 Board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 590a black area 590b White area 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Transistor 7002 Light emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 Substrate 7011 Driving transistor 7012 Light emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Light-transmitting conductive film 7019 Bulkhead 7020 Substrate 7021 Driving transistor 7022 Light emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Light-transmitting conductive film 7029 Bulkhead 7030 Gate insulation layer 7031 Oxide film insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulation layer 7041 Oxide film insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide film insulation layer 7052 Protective insulation layer 7053 Planarizing insulating layer 7055 Insulation layer 9400 Communication Equipment 9401 Case 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4518a FPC

Claims

[Claim 1] a gate electrode layer on the insulating surface; a gate insulating layer on the gate electrode layer; an oxide semiconductor layer on the gate insulating layer; a source electrode layer and a drain electrode layer which are formed on the gate insulating layer and overlap a part of the oxide semiconductor layer; an oxide insulating layer that is in contact with the oxide semiconductor layer and is provided over the source electrode layer and the drain electrode layer; the oxide semiconductor layer has a group of needle-like crystals on at least one surface side which grow in a c-axis direction perpendicular to the surface and have an a-b plane parallel to the surface; the length of each of the needle-like crystals in the group of needle-like crystals in the c-axis direction is at least 5 times the length in the a-axis direction or the b-axis direction; The region other than the group of needle-like crystals is amorphous or a mixture of amorphous and microcrystalline regions.

Images