Semiconductor device

Abstract

To provide a semiconductor device suitable for high integration.SOLUTION: A semiconductor device includes a first layer where a first transistor including an oxide semiconductor is provided on a substrate, a second layer on the first layer, a third layer where a second transistor including an oxide semiconductor is provided on the second layer, a fourth layer between the first layer and the second layer, and a fifth layer between the second layer and the third layer. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction. The total internal stress of the second layer acts in a direction opposite to the first direction. The fourth layer and the fifth layer include a film with a barrier property.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] Technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0005] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with high reliability.Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics.Another object of one embodiment of the present invention is to provide a semiconductor device with large on-state current.Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention includes a first layer having a first transistor having an oxide semiconductor over a substrate, a second layer over the first layer, and a third layer having a second transistor having an oxide semiconductor over the second layer, in which the total internal stress of the first layer and the total internal stress of the third layer act in a first direction, and the total internal stress of the second layer acts in a direction opposite to the first direction.

[0011] One embodiment of the present invention includes a first layer having a first transistor having an oxide semiconductor over a substrate, a second layer over the first layer, a third layer having a second transistor having an oxide semiconductor over the second layer, a fourth layer between the first layer and the second layer, and a fifth layer between the second layer and the third layer, wherein the total internal stress of the first layer and the total internal stress of the third layer act in a first direction and the total internal stress of the second layer act in a direction opposite to the first direction, and the fourth layer and the fifth layer include films having barrier properties.

[0012] In the above, the total internal stress of the fourth layer and the total internal stress of the fifth layer act in the first direction.

[0013] In the above, the film having a barrier property suppresses the diffusion of hydrogen and impurities.

[0014] In the above, the fourth layer seals the first layer and the fifth layer seals the third layer.

[0015] In the above, the second layer has a conductor that functions as wiring.

[0016] In the above, the oxide semiconductor is an In-Ga-Zn oxide. Effect of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A, 2B, 2C, and 2D are cross-sectional views and a top view of a semiconductor device according to one embodiment of the present invention. [Diagram 3] 3A, 3B, 3C, and 3D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 4A, 4B, 4C, and 4D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5] 5A, 5B, 5C, and 5D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A, 6B, 6C, and 6D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A, 7B, 7C, and 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8]8A, 8B, 8C, and 8D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A, 9B, 9C, and 9D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A, 10B, and 10C are a cross-sectional view and a top view of a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A, 11B, 11C, and 11D are cross-sectional and top views of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 15] 15A and 15B are a block diagram and a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 16] 16A, 16B, 16C, 16D, 16E, 16F, 16G, and 16H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 17] 17A and 17B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A, 18B, 18C, 18D, and 18E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 19] 19A, 19B, 19C, 19D, 19E, 19F, 19G, and 19H are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 20] 20A and 20B are diagrams illustrating the results of cross-sectional STEM observation of the sample in this example. [Figure 21] FIG. 21 is a diagram for explaining the results of cross-sectional STEM observation of the sample in this example. [Figure 22]22A and 22B are diagrams illustrating the Id-Vg measurement results of the transistors included in the samples in this example. [Diagram 23] 23A and 23B are diagrams for explaining the influence of the variation in threshold voltage of the transistor included in the sample in this embodiment on the field effect mobility (μFEs) of each transistor 200. FIG. [Figure 24] 24A and 24B are diagrams illustrating the Id-Vg measurement results and the mobility measurement results of the transistors included in the samples of this example. [Diagram 25] FIG. 25 is a diagram illustrating the measurement results of the off-leak current of the transistor included in the sample in this embodiment. [Figure 26] 26A and 26B are diagrams illustrating the writing speed of the transistor included in the sample in this embodiment. [Figure 27] FIG. 27 is a diagram illustrating the results of a write operation and a retention test when the transistors in the sample of this embodiment function as a multi-valued memory. [Figure 28] FIG. 28 is a diagram illustrating the write time and the erase time in the multi-value operation of the transistor included in the sample of this embodiment. [Figure 29] FIG. 29 is a diagram illustrating the results of a write endurance test in a binary operation of the transistor included in the sample in this embodiment. [Diagram 30] FIG. 30 is a diagram for explaining the evaluation of the cutoff frequency fT of the transistor included in the sample in this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0021] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0022] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0023] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0024] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0025] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0027] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0028] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0029] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0030] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0031] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0032] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0033] Note that the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When an impurity is contained, for example, the density of defect states in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, oxygen vacancies may be formed in the oxide semiconductor due to the inclusion of an impurity.

[0034] In this specification and the like, silicon oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and silicon nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0035] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0036] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0037] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0038] In this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0039] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described.

[0040] <Example of semiconductor device configuration> 1 is a cross-sectional view of a semiconductor device including a transistor 200 according to one embodiment of the present invention. Note that some elements are omitted from the semiconductor device shown in FIG. 1 for clarity.

[0041] 1A, a semiconductor device 10 according to one embodiment of the present invention includes a substrate 11, an adjustment layer 12 on the substrate, a layer 14 including a transistor, an adjustment layer 16, and a layer 18 including a transistor, and each layer has a stacked structure. The layer 14 including a transistor includes at least one transistor 200_1, and the layer 18 including a transistor includes at least one transistor 200_2.

[0042] Note that the transistor 200_1 and the transistor 200_2 may have different structures or the same structure. In the following specification, the transistor 200_1 and the transistor 200_2 may be collectively referred to as the transistor 200.

[0043] Here, in the transistor 200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for a semiconductor including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0044] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. As the oxide semiconductor, In-Ga-Zn oxide, In-Ga oxide, or In-Zn oxide may be used.

[0045] The transistor 200 using an oxide semiconductor for a channel formation region has an extremely small leakage current in an off-state; therefore, a low-power semiconductor device can be provided.

[0046] In addition, by using an oxide semiconductor, various elements can be stacked and integrated three-dimensionally. In other words, since an oxide semiconductor can be deposited by a sputtering method or the like, it is possible to form a three-dimensional integrated circuit in which circuits are laid out not only on the plane of a substrate but also in the vertical direction.

[0047] On the other hand, as semiconductor devices become more highly integrated, the precision of mask alignment required in the exposure process also becomes higher, and the alignment margin in the design tends to become smaller.

[0048] Furthermore, in the case of high integration, the total number of films forming the laminated structure increases, and the internal stress generated from the thin films formed on the substrate also increases. When the internal stress of the parallel component acts on the substrate, distortion occurs in the substrate and the semiconductor device provided on the substrate, causing a focus shift in the exposure process, which may result in focus blurring. Furthermore, if the substrate is distorted, when the substrate is inserted into the device, it may not be possible to adsorb the substrate, or even if it is adsorbed, the substrate may be in an unstable state. Furthermore, a shift in alignment may occur.

[0049] Here, internal stress has two directions: tensile stress and compressive stress. For example, tensile stress acts on the film at the interface between the substrate and the thin film in a direction that causes it to expand, and acts on the substrate in a direction that causes it to contract. Therefore, if the substrate is thin and does not have sufficient mechanical strength, the substrate will deform so that the surface on which the film is to be formed becomes concave. On the other hand, if the substrate is thick or has sufficient mechanical strength and the thin film cannot withstand the tensile stress, cracks may occur on the film surface.

[0050] In addition, the compressive stress acts on the film at the interface between the substrate and the thin film in a compressive direction, and acts on the substrate in an expanding direction. Therefore, if the substrate is thin and does not have a sufficiently strong mechanical strength, the substrate will deform so that the surface on which the film is to be formed becomes convex. On the other hand, if the substrate is thick or the mechanical strength is strong enough and the thin film cannot withstand the tensile stress, the film will lift off the substrate surface, cracks will appear all over the surface, and the peeled films may overlap each other.

[0051] Therefore, while high integration requires strict alignment in the design, distortion of the substrate can easily cause misalignment.

[0052] In particular, when a semiconductor device has a repeated laminated structure, the internal stress of the layer structure of the repeating unit, i.e., the combined internal stress of all films constituting the layer structure of the repeating unit (also called the total internal stress), is in the same direction. Therefore, the more the layer structures of the repeating units are laminated, the greater the total internal stress acting in one direction becomes.

[0053] Therefore, in a laminate structure having a repeating layer structure of n (n is a natural number of 2 or more) layers, it is preferable to provide an adjustment layer between the n-1th layer structure and the nth layer structure. The adjustment layer has an internal stress in the opposite direction to the total internal stress of the layer structure of the repeating unit. Specifically, when the total internal stress acts in a compressive direction in the layer structure of the repeating unit, it is preferable to use a layer structure in which the total internal stress of the adjustment layer acts in a tensile direction.

[0054] Therefore, as shown in the semiconductor device 10 shown in FIG. 1A, an adjustment layer 16 may be provided between the layer 14 including a transistor and the layer 18 including a transistor.

[0055] Specifically, the total internal stress acts in the same direction in the transistor-containing layer 14 and the transistor-containing layer 18. On the other hand, the total internal stress in the adjustment layer 16 acts in the opposite direction to the transistor-containing layer 14 or the transistor-containing layer 18.

[0056] Here, the adjustment layer 16 only needs to have a total internal stress in the opposite direction to the total internal stress of the transistor-containing layer 14 and the transistor-containing layer 18. In other words, when the adjustment layer 16 has a laminated structure, it is not necessary for all layers of the adjustment layer 16 to act in the opposite direction to the transistor-containing layer 14 and the transistor-containing layer 18. It is sufficient that the internal stress when the adjustment layer 16 is regarded as one layer acts in the opposite direction to the transistor-containing layer 14 and the transistor-containing layer 18. Therefore, the adjustment layer 16 may include a film that functions as a buffer as a film in contact with the transistor-containing layer. The internal stress of the buffer film may act in the same direction as the transistor-containing layer 14 and the transistor-containing layer 18.

[0057] The adjustment layer 16 can also serve as a wiring layer. Therefore, the adjustment layer 16 may include a conductor. Specifically, the adjustment layer 16 may have a conductor that electrically connects the transistor 200_1 and the transistor 200_2. A wiring that electrically connects the transistor 200_1 or the transistor 200_2 may be routed.

[0058] The adjustment layer 12 may be disposed as necessary and is not an essential component. Although not shown, an adjustment layer may also be provided on the layer 18 including the transistor.

[0059] With the above structure, in a three-dimensional integrated circuit in which the circuit is expanded in the vertical direction as well, the substrate does not warp, making it possible to reduce the alignment margin and increasing the degree of design freedom.

[0060] <Applications of semiconductor devices> An example of a semiconductor device including a transistor 200 of one embodiment of the present invention will be described below with reference to FIG. 1B.

[0061] 1B, a semiconductor device 20 according to one embodiment of the present invention includes a substrate 21, an insulator 23 having a barrier property, a layer 24 including a transistor, an adjustment layer 26, an insulator 27 having a barrier property, and a layer 28 including a transistor, each of which has a stacked structure. The layer 24 including a transistor includes at least one transistor 200_1, and the layer 28 including a transistor includes at least one transistor 200_2.

[0062] In the transistor 200, an oxide semiconductor, which is easy to stack, is used for a semiconductor including a region in which a channel is formed.

[0063] On the other hand, the electrical characteristics of the oxide semiconductor included in the transistor 200 are likely to change due to impurities such as hydrogen, water, or metal oxide; therefore, it is preferable to prevent entry of impurities from the outside.

[0064] Therefore, it is preferable to seal the layer 24 including a transistor and the layer 28 including a transistor with the insulator 23 having a barrier property or the insulator 27 having a barrier property.

[0065] In this specification, the function of suppressing impurities refers to the function of suppressing the diffusion of any one or all of the impurities. A film having the function of suppressing the diffusion of impurities may be called a film through which impurities are unlikely to permeate, a film with low impurity permeability, a film having barrier properties against impurities, a barrier film against impurities, etc. In addition, when a barrier film has conductivity, the barrier film may be called a conductive barrier film.

[0066] The insulator 23 having a barrier property is provided in contact with a lower surface, an upper surface, and a side surface of the layer 24 having a transistor. The insulator 23 having a barrier property can be formed by depositing an insulator having a barrier property multiple times.

[0067] For example, the insulator 23 can be formed of at least three layers. Specifically, after forming an insulating film having a first barrier property, a layer having a transistor is formed. An insulating film having a second barrier property is formed on the layer having the transistor. Then, the layer having the transistor and a part of the insulating film having the second barrier property are removed to expose the insulating film having the first barrier property. Next, a film having a third barrier property may be formed so as to be in contact with the exposed surface of the insulating film having the first barrier property, the side surface of the layer having the transistor, and the upper surface and side surface of the insulating film having the second barrier property.

[0068] With the above structure, the transistor 200_1 can be sealed with the insulator 23 having a barrier property.

[0069] Specifically, metal oxides such as aluminum oxide and nitrides such as silicon nitride may have a function of suppressing the diffusion of oxygen (hereinafter also referred to as barrier properties) as insulators having barrier properties. In particular, aluminum oxide and silicon nitride have a function of suppressing the diffusion of oxygen or impurities such as water and hydrogen, as compared with silicon oxide.

[0070] Therefore, for example, silicon nitride can be used as the insulator 23 having a barrier property or the insulator 27 having a barrier property. In addition, for example, metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, and nitrides such as silicon nitride oxide can be used.

[0071] In addition, the above-mentioned films having the barrier properties generally tend to have high internal stress.

[0072] Therefore, when the total internal stress of the insulator 23 having barrier properties acts in the same direction as the total internal stress of the layer 24 having transistors, the provision of the adjustment layer 26 can reduce distortion of the substrate 21. Therefore, in the process of producing a laminated structure of the insulator 23 having barrier properties provided on the adjustment layer 26 and the layer 28 having transistors, the alignment margin can be made small.

[0073] That is, in the exposure process, the focus shift is suppressed, and as a result, the occurrence of focus blurring can be reduced. Furthermore, when the substrate is inserted into the device, it can be attracted in a stable state. Furthermore, the deviation from the alignment can be suppressed.

[0074] In addition, in three-dimensional integrated circuits (3D integrated circuits) in which the circuit is expanded vertically, the substrate does not warp, allowing for greater freedom in design. In addition, when a stacked structure of n or more layers is provided, even when the top layer is provided, film damage is unlikely to occur, allowing semiconductor devices to be manufactured with a high yield.

[0075] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0076] (Embodiment 2) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described. A semiconductor device including a transistor according to one embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region.

[0077] Here, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described in detail with reference to drawings.

[0078] <Example of semiconductor device configuration> FIG. 2 is a top view and a cross-sectional view of a semiconductor device including a transistor 200 according to one embodiment of the present invention. FIG. 2A is a top view of the semiconductor device. Also, FIGS. 2B and 2C are cross-sectional views of the semiconductor device. Here, FIG. 2B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 2A. Also, FIG. 2C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 2A. Also, FIG. 2D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 2A. Note that some elements are omitted from the top view of FIG. 2A for clarity.

[0079] A semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator 214, an insulator 216, an insulator 280, an insulator 282, and an insulator 284 which function as interlayer films. Note that the insulator 280 is provided in contact with at least the oxide 230.

[0080] [Transistor 200] As shown in FIG. 2, transistor 200 is disposed on a substrate (not shown) and has conductor 205 disposed so as to be embedded in insulator 216, insulator 222 disposed on insulator 216 and on conductor 205, insulator 224 disposed on insulator 222, oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on insulator 224, insulator 250 disposed on oxide 230, conductor 260 (conductor 260a and conductor 260b) disposed on insulator 250, conductor 240a and conductor 240b in contact with a portion of the upper surface of oxide 230b, insulator 245a on conductor 240a, and insulator 245b on conductor 240b.

[0081] In addition, the transistor 200 uses a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0082] Note that the oxide semiconductor functioning as a channel formation region preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using an oxide semiconductor with a wide band gap in this manner, the off-state current of the transistor can be reduced.

[0083] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, the atomic ratio of element M to In in the metal oxide used for the oxide 230a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 230b.

[0084] Furthermore, the oxide 230c can be made of any of the metal oxides that can be used for the oxide 230a or the oxide 230b.

[0085] For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like.

[0086] Moreover, the oxide 230b and the oxide 230c are preferably crystalline. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.), and have a dense structure with high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0087] Note that, in the transistor 200, the oxide 230 has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked, but the present invention is not limited to this. For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. Each of the oxide 230a, the oxide 230b, and the oxide 230c may have a stacked structure.

[0088] 2D, it is preferable that at least the side surface of oxide 230b and the side surface of conductor 240 (conductor 240a, conductor 240b) are approximately perpendicular to the surface where insulator 224 and oxide 230a contact each other. Specifically, in FIG. 2D, it is preferable that the side surface of oxide 230b and the side surface of conductor 240 are inclined at an angle of 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees or less, to the surface where insulator 224 and oxide 230a contact each other.

[0089] 2C, the upper end of the oxide 230 in the channel formation region is preferably curved. That is, in the channel formation region, the upper surface and the side surface of the oxide 230 are preferably curved so as to be smoothly connected without forming corners. Since the channel formation region does not have corners, electric field concentration due to the electric field of either or both of the conductor 260 functioning as the first gate electrode and the conductor 205 functioning as the second gate electrode does not occur, and deterioration of the oxide 230 can be suppressed.

[0090] 2D, the upper end of the oxide 230 in the region overlapping with the conductor 240 preferably has a shape with a smaller curvature than the upper end of the oxide 230 in the channel formation region. The above structure can be formed by processing the oxide 230b and the conductor 240 using the same mask. Therefore, since the conductor 240 overlaps within the projected area of ​​the oxide 230b, a fine transistor can be created.

[0091] The conductor 260 functions as a first gate (also called a top gate) electrode.

[0092] Here, the transistor 200 is provided by filling the conductor 260 in an opening formed in the insulator 280 or the like. In the process of providing the opening, a part of the conductive layer to be the conductor 240 is exposed at the bottom of the opening provided in the insulator 280. By removing a region of the conductive layer to be the conductor 240 that overlaps with the bottom of the opening provided in the insulator 280, the conductor 240a and the conductor 240b are formed.

[0093] Therefore, the end of the conductor 240a and the end of the conductor 240b are on the same plane as the side surface of the opening. By embedding the conductor 260 in the opening provided in the insulator 280 via the insulator 250 or the like, the conductor 260 can be self-aligned in the region between the conductor 240a and the conductor 240b without alignment.

[0094] Also, as shown in FIG. 2B or 2C, the top surface of the conductor 260 is approximately flush with the top surface of the insulator 250 and the top surface of the oxide 230c.

[0095] 2C , in a region where the conductor 260 and the oxide 230 do not overlap, the shortest distance between the surface where the conductor 260 and the insulator 250 contact and the upper surface of the insulator 222 is preferably shorter than the shortest distance between the surface where the oxide 230b and the oxide 230a contact and the upper surface of the insulator 222. In other words, in the channel width direction of the transistor 200, the side surface of the oxide 230b is covered by the conductor 260 at least via the insulator 250.

[0096] The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 acts on the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0097] It is preferable that the conductor 260 has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b.

[0098] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0099] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0100] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0101] In FIG. 2, the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b, but it may have a single-layer structure or a laminated structure of three or more layers.

[0102] The conductor 205 functions as a second gate (also called a bottom gate) electrode.

[0103] Furthermore, when the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0104] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulator 214 or the insulator 216.

[0105] In addition, in the channel width direction, the conductor 205 is preferably provided to be larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 2C, it is preferable that the conductor 205 extends to intersect with the channel width direction of the oxide 230.

[0106] Here, it is preferable that the conductor 205 and the conductor 260 overlap with an insulator interposed between them on the outer side of the side surface in the channel width direction of the oxide 230. With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as a first gate electrode and the electric field of the conductor 205 functioning as a second gate electrode.

[0107] 2, the conductor 205 is shown as a laminate of a first conductor and a second conductor, but the present invention is not limited to this. For example, the conductor 205 may be configured as a single layer or a laminate structure of three or more layers. When the structure has a laminate structure, ordinal numbers may be given to indicate the order of formation to distinguish them.

[0108] Here, the first conductor of the conductor 205 is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0109] By using a conductive material having a function of suppressing oxygen diffusion for the first conductor of the conductor 205, it is possible to suppress the second conductor of the conductor 205 from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, the first conductor of the conductor 205 may be a single layer or a multilayer of the above conductive material. For example, the first conductor of the conductor 205 may be a multilayer of tantalum, tantalum nitride, ruthenium, or ruthenium oxide, and titanium or titanium nitride.

[0110] Moreover, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the second conductor of the conductor 205. Although the second conductor of the conductor 205 is illustrated as a single layer, it may have a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material.

[0111] 2C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0112] The conductor 240 (conductor 240a and conductor 240b) functions as a source electrode or a drain electrode.

[0113] The conductor 240 is, for example, TaNx O y It is preferable to use TaN x O y may contain aluminum. In addition, for example, titanium nitride, a nitride containing titanium and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0114] It is also a good idea to provide an insulator 245 over the conductor 240 to function as a barrier layer.

[0115] 2B, the insulator 245 is preferably in contact with the top surface of the conductor 240. This structure can suppress the absorption of excess oxygen contained in the insulator 280 by the conductor 240. Furthermore, suppressing oxidation of the conductor 240 can suppress an increase in contact resistance between the transistor 200 and the wiring. Thus, the transistor 200 can have good electrical characteristics and reliability.

[0116] Therefore, it is preferable that the insulator 245 has a function of suppressing the diffusion of oxygen. For example, it is preferable that the insulator 245 has a function of suppressing the diffusion of oxygen more than the insulator 280.

[0117] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 245. Alternatively, for example, an insulator containing aluminum nitride may be used as the insulator 245.

[0118] Insulator 250 serves as the first gate insulator.

[0119] The insulator 250 is preferably disposed in contact with the oxide 230c. The insulator 250 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0120] After the insulator 250 is formed, a microwave-excited plasma treatment may be performed under an atmosphere containing oxygen. By performing the microwave-excited plasma treatment, hydrogen, water, or impurities in the insulator 250 can be removed. Furthermore, by performing the microwave-excited plasma treatment, the film quality of the insulator 250 can be modified, thereby suppressing the diffusion of hydrogen, water, impurities, and the like. Therefore, the diffusion of hydrogen, water, or impurities into the oxide 230 through the insulator 250 can be suppressed by a post-process such as the formation of a conductive film that becomes the conductor 260, or a post-treatment such as a heat treatment.

[0121] For example, in solid silicon oxide, the bond energy between hydrogen atoms and silicon atoms is 3.3 eV, the bond energy between carbon atoms and silicon atoms is 3.4 eV, and the bond energy between nitrogen atoms and silicon atoms is 3.5 eV. Therefore, to remove hydrogen atoms bonded to silicon atoms, the bonds between the hydrogen atoms and silicon atoms can be broken by colliding radicals or ions with an energy of at least 3.3 eV with the bonds between the hydrogen atoms and silicon atoms.

[0122] Similarly, for other impurities such as nitrogen and carbon, the bond between the impurity atom and the silicon atom can be broken by colliding a radical or ion having energy at least equal to the bond energy with the bond between the impurity atom and the silicon atom.

[0123] Here, the radicals and ions generated by the microwave-excited plasma are the ground state O(3 P), the first excited state of the oxygen radical O( 1 D), and the monovalent cation of the oxygen molecule, O2 + etc. O( 3 P) energy is 2.42 eV, O( 1 D) The energy is 4.6 eV. Also, O2 + Since the electron has a charge, it is accelerated by the potential distribution in the plasma and the bias, so its energy is not uniquely determined. However, even with only the internal energy, it is possible to determine the energy of the electron. 1 D) have higher energy.

[0124] In other words, O( 1 D), and O2 + The radicals and ions such as can cut bonds between hydrogen, nitrogen, and carbon atoms and silicon atoms in the insulator 250, and can remove the hydrogen, nitrogen, and carbon bonded to the silicon atoms. Furthermore, impurities such as hydrogen, nitrogen, and carbon can be reduced by thermal energy or the like applied to the substrate when performing microwave excited plasma processing.

[0125] On the other hand, O( 3 P) has low reactivity, so it does not react with the insulator 250 and diffuses deep into the film. 3 P) reaches the oxide 230 through the insulator 250 and diffuses into the oxide 230. 3 When P) approaches an oxygen vacancy with hydrogen, the hydrogen in the oxygen vacancy is released from the oxygen vacancy and replaced by O( 3 P) enters the oxygen vacancy, thereby compensating for the oxygen vacancy. Therefore, the generation of electrons, which are carriers, in the oxide 230 can be suppressed.

[0126] In addition, the total radical and ion species O( 3 The proportion of O(P) is increased by performing the microwave excited plasma treatment under high pressure conditions. 3It is preferable that the ratio of oxygen (O2 / O2+Ar) is high. Therefore, the pressure of the microwave excited plasma treatment is set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, the oxygen flow rate ratio (O2 / O2+Ar) is set to 50% or less, preferably 10% or more and 30% or less.

[0127] Moreover, it is preferable that the insulator 250 is made of an oxide material from which some oxygen is released when heated. The oxide material from which oxygen is released when heated is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0128] By providing an insulator that releases oxygen when heated as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b, and oxygen vacancies in the channel formation region of the oxide 230b can be reduced. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided. In addition, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.

[0129] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0130] The metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is possible to form a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0131] Specifically, it is possible to use a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0132] The metal oxide may function as a part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In this case, the conductor 260 is formed by a sputtering method, whereby the electrical resistance value of the metal oxide can be reduced to make it a conductor.

[0133] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the effect of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, it is possible to suppress leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, it is possible to easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0134] Insulator 222 and insulator 224 function as a second gate insulator.

[0135] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0136] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with the insulator 224 and the oxygen contained in the oxide 230.

[0137] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0138] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0139] It is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating, similar to the insulator 250. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0140] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0141] Insulators 214, 216, 280, 282, and 284 function as interlayer films.

[0142] The insulator 214 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. Therefore, the insulator 214 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0143] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side of the insulator 214 to the transistor 200 side. Alternatively, it can suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side of the insulator 214. Note that the insulator 214 may have a stacked structure of two or more layers. In this case, the insulator 214 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, a stacked structure of aluminum oxide and silicon nitride may be used.

[0144] For example, it is preferable to use a silicon nitride film formed by a sputtering method as the insulator 214. This can reduce the hydrogen concentration in the insulator 214 and can further suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side relative to the insulator 214.

[0145] The insulator 216 functioning as an interlayer film preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 216 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0146] The insulator 216 preferably has a region where the hydrogen concentration is low and where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region), or oxygen that is released by heating (hereinafter also referred to as excess oxygen). For example, it is preferable to use silicon oxide formed by a sputtering method as the insulator 216. This can suppress the mixing of hydrogen into the oxide 230, or can supply oxygen to the oxide 230 and reduce oxygen vacancies in the oxide 230. Therefore, a transistor with suppressed fluctuations in electrical characteristics, stable electrical characteristics, and improved reliability can be provided.

[0147] The insulator 216 may have a laminated structure. For example, the insulator 216 may have an insulator similar to the insulator 214 provided at least in a portion that contacts the side surface of the conductor 205. With such a structure, it is possible to prevent the conductor 205 from being oxidized by the oxygen contained in the insulator 216. Alternatively, it is possible to prevent the amount of oxygen contained in the insulator 216 from being reduced by the conductor 205.

[0148] The insulator 280 is disposed on the insulator 224, the oxide 230, and the conductor 240. Additionally, the top surface of the insulator 280 may be planarized.

[0149] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0150] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The insulator 280 also preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen, and may be formed using a material similar to that of the insulator 216, for example. The insulator 280 may have a stacked structure of two or more layers.

[0151] Like the insulator 214, the insulator 282 preferably functions as an insulating barrier film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. Also, like the insulator 214, the insulator 282 preferably has a low hydrogen concentration and a function of suppressing diffusion of hydrogen.

[0152] 2B, the insulator 282 is preferably in contact with the top surfaces of the conductor 260, the insulator 250, and the oxide 230c. This can prevent impurities such as hydrogen contained in the insulator 284 from being mixed into the insulator 250. This can prevent adverse effects on the electrical characteristics and reliability of the transistor.

[0153] It is preferable to provide an insulator 284 functioning as an interlayer film over the insulator 282. The insulator 284 preferably has a low dielectric constant, similar to the insulator 216. It is also preferable that the insulator 284 has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224.

[0154] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0155] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements provided thereon may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0156] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0157] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0158] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0159] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0160] Furthermore, the transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 245, and the insulator 282) having a function of suppressing the transmission of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride may be used.

[0161] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0162] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0163] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0164] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0165] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0166] <<Metal oxides>> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 according to the present invention will be described.

[0167] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0168] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there are cases where the element M may be a combination of multiple elements mentioned above.

[0169] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0170] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0171] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0172] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. In CAAC-OS, it is difficult to confirm clear grain boundaries even near the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of dense arrangement of oxygen atoms in the ab-plane direction and the change in the bond distance between atoms due to the substitution of metal elements.

[0173] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be expressed as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be expressed as an (In, M) layer.

[0174] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to confirm clear crystal boundaries in CAAC-OS, so it can be said that the decrease in electron mobility caused by crystal boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be a metal oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0175] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0176] In-Ga-Zn oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it may be structurally more stable when made into small crystals (for example, the above-mentioned nanocrystals) rather than large crystals (here, crystals of several mm or several cm).

[0177] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0178] Oxide semiconductors (metal oxides) have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0179] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0180] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into a channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor are likely to fluctuate, and the reliability may be reduced. Furthermore, when oxygen vacancies are included in the channel formation region, the transistor is likely to have normally-on characteristics.

[0181] The defect levels may include trap levels. Charges trapped in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor having a channel formation region made of a metal oxide with a high density of trap levels may have unstable electrical characteristics.

[0182] Furthermore, when impurities are present in a channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may be reduced, or the crystallinity of an oxide provided in contact with the channel formation region may be reduced. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to be degraded. When the crystallinity of an oxide provided in contact with the channel formation region is low, an interface state may be formed, which may degrade the stability or reliability of the transistor.

[0183] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the concentration of impurities in and around a channel formation region of an oxide semiconductor. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0184] Specifically, the concentration of the impurities in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by SIMS, is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3or less. Alternatively, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity, which is obtained by elemental analysis using EDX, is set to 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in the channel formation region of the oxide semiconductor and its vicinity is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the concentration ratio may be the concentration in the same region as the region where the concentration of the impurity is calculated, or may be the concentration in the oxide semiconductor.

[0185] Furthermore, since a metal oxide with a reduced impurity concentration has a low defect state density, the trap state density may also be low.

[0186] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention shown in FIG. 2 will be described with reference to FIGS.

[0187] 3 to 9, A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of A in each figure, some elements are omitted for clarity.

[0188] First, a substrate (not shown) is prepared, and the insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0189] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0190] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0191] In addition, the ALD method utilizes the self-regulating nature of atoms and can deposit atoms one layer at a time, which has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The ALD method also includes the PEALD (Plasma Enhanced ALD) method, which uses plasma. By using plasma, films can be formed at lower temperatures, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0192] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0193] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0194] In this embodiment, an aluminum oxide film is formed by sputtering as the insulator 214. Alternatively, the insulator 214 may have a multilayer structure.

[0195] Next, the insulator 216 is formed on the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is formed by a CVD method as an insulating film to be the insulator 216.

[0196] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be an area where an opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0197] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0198] After the opening is formed, a conductive film that becomes the first conductor of the conductor 205 is formed. The conductive film desirably contains a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0199] In this embodiment, a tantalum nitride film or a film in which titanium nitride is laminated on tantalum nitride is formed by sputtering as a conductive film to be the first conductor of conductor 205. By using such a metal nitride as the first conductor of conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of conductor 205 described later, the metal can be prevented from diffusing out of the first conductor of conductor 205.

[0200] Next, a conductive film that will be a second conductor of the conductor 205 is formed on the conductive film that will be the first conductor of the conductor 205. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film.

[0201] Next, a chemical mechanical polishing (CMP) process is performed to remove a portion of the conductive film that will become the first conductor of the conductor 205 and a portion of the conductive film that will become the second conductor of the conductor 205, thereby exposing the insulator 216. As a result, the conductive film that will become the first conductor of the conductor 205 and the conductive film that will become the second conductor of the conductor 205 remain only in the opening. This makes it possible to form the conductor 205, which has a flat upper surface and includes the first conductor of the conductor 205 and the second conductor of the conductor 205 (see FIG. 3).

[0202] Note that after forming the conductor 205, a process may be performed in which a part of the second conductor of the conductor 205 is removed to form a groove in the second conductor of the conductor 205, a conductive film is formed on the conductor 205 and the insulator 216 so as to fill the groove, and a CMP process is performed. The CMP process removes a part of the conductive film to expose the insulator 216. Note that a part of the second conductor of the conductor 205 may be removed by using a dry etching method or the like.

[0203] Through the above process, the conductor 205 including the conductive film and having a flat top surface can be formed. By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of the oxide 230a, the oxide 230b, and the oxide 230c can be improved. Note that the conductive film may be made of a material similar to that of the first conductor of the conductor 205 or the second conductor of the conductor 205.

[0204] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0205] A conductive film that becomes the conductor 205 is formed on the insulator 214. The conductive film that becomes the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film that becomes the conductor 205 can be a multilayer film. For example, a tungsten film is formed as the conductive film that becomes the conductor 205.

[0206] Next, the conductive film that becomes the conductor 205 is processed by lithography to form the conductor 205 .

[0207] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.

[0208] Also, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When using a hard mask, an insulating film or a conductive film that is to be a hard mask material is formed on the conductive film that is to be the conductor 205, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the conductive film that is to be the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the conductive film that is to be the conductor 205, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily necessary to remove the hard mask.

[0209] Next, an insulating film to be the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to be in contact with the upper surface and side surfaces of the conductor 205. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0210] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is 1 or more and 3 or less.

[0211] Next, a part of the insulating film that becomes the insulator 216 is removed by performing CMP processing on the insulating film that becomes the insulator 216, thereby exposing the surface of the conductor 205. This makes it possible to form the conductor 205 and the insulator 216 that have flat upper surfaces. The above is a different method for forming the conductor 205.

[0212] Next, the insulator 222 is formed over the insulator 216 and the conductor 205. The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide or aluminum oxide is formed as the insulator 222 by an ALD method.

[0213] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C to 650°C, preferably 300°C to 500°C, more preferably 320°C to 450°C. The heat treatment is carried out in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere.

[0214] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the formation of the insulator 222, and then in an oxygen atmosphere at 400° C. for 1 hour. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. The heat treatment can also be performed at a timing such as after the formation of the insulator 224.

[0215] Next, the insulator 224 is deposited over the insulator 222. The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is deposited as the insulator 224 by a CVD method.

[0216] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies RF (Radio Frequency) to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment does not need to be performed.

[0217] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, a CMP process may be performed until the insulator 224 is reached. The CMP process can planarize and smooth the surface of the insulator 224. By disposing the aluminum oxide on the insulator 224 and performing the CMP process, it becomes easy to detect the end point of the CMP process. In addition, the CMP process may polish a part of the insulator 224, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage rate of the oxide to be formed later and to prevent a decrease in the yield of the semiconductor device. In addition, it is preferable to form an aluminum oxide film on the insulator 224 by a sputtering method, since oxygen can be added to the insulator 224.

[0218] Next, oxide film 230A and oxide film 230B are sequentially formed on insulator 224 (see FIG. 3). Note that oxide film 230A and oxide film 230B are preferably formed successively without exposure to the air environment. By forming the films without exposure to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0219] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0220] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0221] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0222] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0223] In this embodiment, the oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0224] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere, for example, by using a multi-chamber type film forming apparatus.

[0225] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. The heat treatment may remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour, followed by another heat treatment in an oxygen atmosphere at 400° C. for 1 hour.

[0226] Next, the conductive film 240A is formed on the oxide film 230B. The conductive film 240A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 3). Note that a heat treatment may be performed before the conductive film 240A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 240A may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0227] Next, an insulating film 245A that functions as a barrier layer is formed (see FIG. 3).

[0228] For example, aluminum oxide may be formed by an ALD method as the insulating film 245A. By forming the insulating film by the ALD method, a dense film with reduced defects such as cracks and pinholes or a uniform thickness can be formed.

[0229] Next, a film 290A to be a hard mask is formed over the insulating film 245A (see FIG. 3). For example, the film 290A to be a hard mask may be formed of tungsten or tantalum nitride by a sputtering method.

[0230] Next, a resist mask 292 is formed on the film 290A to be the hard mask by photolithography. The film 290A to be the hard mask and the insulating film 245A are selectively removed using the resist mask 292 to form a hard mask 290B and an insulating layer 245B (FIG. 4).

[0231] Next, a part of the conductive film 240A is selectively removed using the hard mask 290B and the insulating layer 245B to form an island-shaped conductive layer 240B (FIG. 5). At this time, a part or the whole of the hard mask 290B may be removed.

[0232] Next, the oxide film 230A and a part of the oxide film 230B are selectively removed using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as a mask (FIG. 6). Note that in this process, a part of the insulator 224 may also be removed at the same time. Thereafter, the hard mask 290B is removed to form a layered structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B (FIG. 6).

[0233] In addition, in this step, by processing the conductive film 240A using the hard mask 290, the formation of unnecessary etching (also called CD loss) in the shape of the conductor 240 can be suppressed.

[0234] For example, when a resist mask is used, the mask may be side-etched during etching, exposing the end surface of the workpiece and causing the corners to become rounded. If the defect is large in the conductor 240, the volume of the conductor 240 may be reduced below the design value, and the on-current may become small.

[0235] Therefore, by using a hard mask and using a material with a large etch rate selectivity to the hard mask as the workpiece, the shape of the hard mask is maintained during etching, and the workpiece can be prevented from becoming deformed. Specifically, when the etch rate of the material used for the hard mask is 1, the etch rate of the workpiece should be 5 or more, preferably 10 or more, as the mask.

[0236] Next, an insulating film 280A is formed on the stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B. The insulating film 280A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulating film 280A by a CVD method or a sputtering method. Note that a heat treatment may be performed before the insulating film 280A is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be continuously formed without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 224 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The above-mentioned heat treatment conditions can be used.

[0237] The insulating film 280A may have a multi-layer structure, for example, a silicon oxide film formed by sputtering, and another silicon oxide film formed on the silicon oxide film by CVD.

[0238] Next, the insulating film 280A is subjected to a CMP process to form an insulator 280 having a flat upper surface (see FIG. 6).

[0239] Next, a part of the insulator 280 and a part of the conductive layer 240B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205. By forming the opening, the conductor 240a, the conductive layer 240B, the insulator 245a, and the insulating layer 245B are formed. At this time, the thickness of the oxide 230b in the region overlapping with the opening may be thin (see FIG. 7).

[0240] Furthermore, a part of the insulator 280, a part of the insulating layer 245B, and a part of the conductive layer 240B may be processed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulating layer 245B may be processed by a wet etching method, and a part of the conductive layer 240B may be processed by a dry etching method.

[0241] Here, it is preferable to remove impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused inside. The impurities include those originating from components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0242] A cleaning process may be performed to remove the above-mentioned impurities, etc. Examples of the cleaning method include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be appropriately combined.

[0243] As the wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Also, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Also, these cleaning methods may be appropriately combined.

[0244] Next, a heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing oxygen. The heat treatment may also be performed under reduced pressure to continuously form the oxide film 230C without exposure to the atmosphere (see FIG. 8). By performing such a treatment, it is possible to remove moisture and hydrogen adsorbed on the surface of the oxide 230b, and further reduce the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0245] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C may be formed by the same film forming method as the oxide film 230A or the oxide film 230B according to the desired characteristics of the oxide film 230C. In this embodiment, the oxide film 230C is formed by sputtering using an In-Ga-Zn oxide target with In:Ga:Zn=1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio]. Alternatively, the oxide film 230C is formed by sputtering using an In-Ga-Zn oxide target with 4:2:4.1 [atomic ratio], and then formed thereon using an In-Ga-Zn oxide target with In:Ga:Zn=1:3:4 [atomic ratio].

[0246] In particular, when the oxide film 230C is formed, a part of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

[0247] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. By performing such a treatment, the moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0248] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 8). In this embodiment, silicon oxynitride is formed as the insulating film 250A by CVD. The film formation temperature for forming the insulating film 250A is preferably 350° C. or higher and lower than 450° C., particularly about 400° C. By forming the insulating film 250A at 400° C., an insulating film with fewer impurities can be formed.

[0249] Next, the conductive film 260A and the conductive film 260B are formed in this order. The conductive film 260A and the conductive film 260B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film 260A is formed by using the ALD method, and the conductive film 260B is formed by using the CVD method (see FIG. 8).

[0250] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 9). As a result, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the opening that reaches the oxide 230b. The insulator 250 is disposed so as to cover the inner wall of the opening via the oxide 230c. The conductor 260 is disposed so as to fill the opening via the oxide 230c and the insulator 250.

[0251] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for one hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280.

[0252] Next, the insulator 282 is formed over the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, an aluminum oxide film or a silicon nitride film is preferably formed by a sputtering method. By forming an aluminum oxide film or a silicon nitride film by a sputtering method, it is possible to suppress the diffusion of hydrogen contained in the insulator 284 to the oxide 230. Furthermore, it is preferable to form the insulator 282 so as to be in contact with the conductor 260, because the oxidation of the conductor 260 can be suppressed.

[0253] Furthermore, by forming an aluminum oxide film by sputtering as the insulator 282, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 may be supplied to a channel formation region of the oxide 230b through the oxide 230c. Furthermore, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 282 may be supplied to the channel formation region of the oxide 230b through the oxide 230c.

[0254] The insulator 282 may have a multi-layer structure. For example, an aluminum oxide film is formed by a sputtering method, and a silicon nitride film is formed over the aluminum oxide film by a sputtering method.

[0255] Next, heat treatment may be performed. The heat treatment can be performed under the above-mentioned heat treatment conditions. The heat treatment can reduce the moisture and hydrogen concentrations in the insulator 280. In addition, oxygen contained in the insulator 282 can be injected into the insulator 280.

[0256] Before forming the insulator 282, an aluminum oxide film may be formed by sputtering on the insulator 280, etc., followed by a heat treatment under the above-mentioned heat treatment conditions, and then a process of removing the aluminum oxide film by CMP may be performed. This process allows more excess oxygen regions to be formed in the insulator 280. In this process, a part of the insulator 280, a part of the conductor 260, a part of the insulator 250, and a part of the oxide 230c may be removed.

[0257] Alternatively, an insulator may be provided between the insulator 280 and the insulator 282. For example, a silicon oxide film formed by a sputtering method may be used as the insulator. By providing the insulator, an excess oxygen region can be formed in the insulator 280.

[0258] Next, the insulator 284 may be formed on the insulator 282. The insulator 284 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).

[0259] Through the above steps, a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured.

[0260] After the transistor 200 is formed, an opening may be formed to surround the transistor 200, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 200 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 200 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 200, for example, it is preferable to form an opening that reaches the insulator 214 or the insulator 222 and form the insulator having a high barrier property in contact with the insulator 214 or the insulator 222, since this can serve as part of the manufacturing process of the transistor 200. Note that as the insulator having a high barrier property against hydrogen or water, for example, a material similar to that of the insulator 222 may be used.

[0261] According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0262] <Modifications of the semiconductor device> An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below with reference to FIG.

[0263] Here, Fig. 10A shows a top view. Fig. 10B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 10A. Fig. 10C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 10A. In the top view of Fig. 10A, some elements are omitted for clarity.

[0264] 10 differs from the semiconductor device illustrated in FIG 2 in that the oxide 230b has a layered structure, the oxide 230c has a layered structure, and the insulators 273 and 274 are included.

[0265] The oxide 230c may have a laminated structure of two or more layers. For example, in FIG. 10, the oxide 230c has a first oxide and a second oxide disposed on the first oxide of the oxide 230c.

[0266] Specifically, the first oxide of the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230b, and more preferably contains all of the metal elements. For example, the first oxide of the oxide 230c may be an In-Ga-Zn oxide, and the second oxide of the oxide 230c may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide. This structure can reduce the defect state density at the interface between the oxide 230b and the first oxide of the oxide 230c.

[0267] Moreover, the second oxide of the oxide 230c is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the first oxide of the oxide 230c. By providing the second oxide of the oxide 230c between the insulator 250 and the first oxide of the oxide 230c, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the insulator 250. Therefore, the oxygen is easily supplied to the oxide 230b via the first oxide of the oxide 230c.

[0268] In addition, by making the atomic ratio of In to the main component metal element in the metal oxide used for the second oxide of the oxide 230c smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the first oxide of the oxide 230c, it is possible to suppress the diffusion of In to the insulator 250. Since the insulator 250 functions as a gate insulator, if In gets mixed into the insulator 250, the transistor characteristics will be poor. Therefore, by making the oxide 230c a stacked structure, it is possible to provide a highly reliable semiconductor device.

[0269] In addition, the oxide 230b may have a laminated structure of two or more layers. For example, in FIG. 10, the oxide 230b has a first oxide and a second oxide of the oxide 230b disposed on the first oxide of the oxide 230b.

[0270] Specifically, the second oxide of the oxide 230b is preferably provided between the first oxide of the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) functioning as a source electrode or a drain electrode. In this structure, the second oxide of the oxide 230b preferably has a function of suppressing oxygen permeation.

[0271] Therefore, it is preferable to place the second oxide of the oxide 230b, which has a function of suppressing oxygen permeation, between the conductor 240 that functions as a source electrode or drain electrode and the first oxide of the oxide 230b, because this reduces the electrical resistance between the conductor 240 and the first oxide of the oxide 230b. With this structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0272] In other words, since the conductor 240 and the first oxide of the oxide 230b are not in contact with each other, it is possible to prevent the conductor 240 from absorbing oxygen from the first oxide of the oxide 230b. By preventing the oxidation of the conductor 240, it is possible to prevent a decrease in the conductivity of the conductor 240.

[0273] A metal oxide having element M may be used as the second oxide of the oxide 230b. In particular, the element M may be aluminum, gallium, yttrium, or tin. The second oxide of the oxide 230b preferably has a higher concentration of element M than the first oxide of the oxide 230b. Gallium oxide may be used as the second oxide of the oxide 230b. A metal oxide such as In-M-Zn oxide may be used as the second oxide of the oxide 230b.

[0274] Specifically, in the metal oxide used for the second oxide of the oxide 230b, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the first oxide of the oxide 230b. In addition, the film thickness of the second oxide of the oxide 230b is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. In addition, the second oxide of the oxide 230b is preferably crystalline. When the second oxide of the oxide 230b is crystalline, it is possible to reduce the release of oxygen in the first oxide of the oxide 230b. For example, if the second oxide of the oxide 230b has a crystal structure such as a hexagonal crystal structure, it may be possible to suppress the release of oxygen in the first oxide of the oxide 230b.

[0275] Furthermore, when the conductor 240 (conductor 240a and conductor 240b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 240, causing the conductor 240 to oxidize. When the conductor 240 oxidizes, there is a high probability that the conductivity of the conductor 240 decreases. The diffusion of oxygen in the oxide 230 into the conductor 240 can be rephrased as the conductor 240 absorbing the oxygen in the oxide 230.

[0276] Furthermore, oxygen in the oxide 230 (typically the oxide 230b) may diffuse into the conductor 240, forming a foreign layer between the conductor 240 and the oxide 230. Since the foreign layer contains more oxygen than the conductor 240, the foreign layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 240, the foreign layer, and the oxide 230 can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure, or a diode junction structure mainly based on the MIS structure.

[0277] Furthermore, an insulator 273 having barrier properties may be provided so as to cover the top surface of the conductor 240, the oxide 230a, the oxide 230b, and the side surfaces of the conductor 240. When the insulator 273 is provided, the insulator 245 is not necessarily provided.

[0278] For example, in the region of the oxide 230 overlapping with the conductor 240, a metal element of the conductor 240 is added, or oxygen is absorbed by the conductor 240, causing oxygen deficiency. In other words, the resistance may be locally reduced near the surface of the oxide 230 in contact with the conductor 240. The on-current of the transistor 200 can be improved by reducing the resistance of the region of the oxide 230 overlapping with the conductor 240.

[0279] On the other hand, excess oxygen in insulator 280 diffuses into oxide 230 from the side of oxide 230 in the region overlapping with conductor 240, which may reduce the localized low-resistance region in oxide 230 in the region overlapping with conductor 240, thereby reducing the on-current of transistor 200.

[0280] Therefore, by providing the insulator 273, it is possible to suppress the supply of excess oxygen contained in the insulator 280 from the side surface of the oxide 230 in the region overlapping with the conductor 240. On the other hand, the excess oxygen contained in the insulator 280 can be supplied to the channel formation region of the oxide 230b via the oxide 230c. Therefore, the oxygen vacancies occurring in the channel formation region of the oxide 230 can be efficiently compensated for without reducing the low-resistance region occurring near the surface of the oxide 230 in contact with the conductor 240.

[0281] Furthermore, when the insulator 224 has an excess oxygen region, the excess oxygen in the insulator 224 diffuses to the oxide 230b through the oxide 230a in the oxide 230. In other words, the excess oxygen can be supplied from the oxide 230a side. Therefore, the oxygen vacancies occurring in the channel formation region of the oxide 230 can be compensated for while suppressing the reduction of the low resistance region occurring near the surface of the oxide 230 in contact with the conductor 240.

[0282] Note that an aluminum oxide film formed using a sputtering apparatus is preferably used as the insulator 273. By forming an aluminum oxide film as the insulator 273 under an oxygen gas atmosphere, excess oxygen can be introduced into the insulator 224 while the insulator 273 is being formed.

[0283] Further, an insulator 274 may be provided over the insulator 273. Note that, like the insulator 273, the insulator 274 preferably has a function of suppressing oxygen diffusion.

[0284] Specifically, the insulator 273 formed by the sputtering method has low film coverage. Therefore, it is preferable to form the insulator 274 by the ALD method. The ALD method can form a film with excellent step coverage and thickness uniformity, so it is less affected by the shape of the workpiece and has good step coverage.

[0285] <Applications of semiconductor devices> Below, an example in which a stacked structure of interlayer films and a plug according to one embodiment of the present invention are applied to a semiconductor device including a transistor 200 according to this embodiment will be described with reference to FIGS.

[0286] Here, Fig. 11A shows a top view. Fig. 11B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 11A. Fig. 11C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 11A. Fig. 11D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 11A. In the top view of Fig. 11A, some elements are omitted for clarity.

[0287] 11, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 have openings that expose the transistor 200. The openings include a conductor 246 (conductor 246a and conductor 246b) that functions as a plug connected to the transistor 200. An insulator 247 is provided on a side surface of the opening.

[0288] Note that the conductor 246 functions as a plug or a wiring that is electrically connected to the transistor 200 .

[0289] 11 has insulators 212 and 283 functioning as barrier layers above and below the transistor 200. The insulators 212 and 283 are in contact with each other in a region that is a side surface of the transistor 200 or an end portion of the substrate. In other words, the semiconductor device shown in FIG. 11 has a structure in which the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.

[0290] The region where the insulator 212 and the insulator 283 contact each other may be provided along a scribe line. For example, when multiple transistors 200 are arranged in a matrix, the region where the insulator 212 and the insulator 283 contact each other may be provided along the matrix in which the multiple transistors are arranged.

[0291] Note that when the region where the insulator 212 and the insulator 283 are in contact with each other is provided at the edge of the substrate, the region may overlap with a scribe line.

[0292] The insulator 283 is provided on the insulator 282. The insulator 284 is made of a material that has a high etching rate selectivity with respect to the conductor 248 when processing the conductor 248. Therefore, the insulator 284 may be provided on the insulator 283 as necessary.

[0293] The insulator 247 is preferably in contact with the insulator 283. When the insulator 247 and the insulator 283 are in contact with each other, a structure is formed in which the transistor 200 and the insulator 280 including the excess oxygen region are sealed by a barrier layer.

[0294] Specifically, insulator 247 is provided in contact with the side walls of the openings of insulators 283, 282, and 280, and conductor 246 is formed in contact with the side surface of insulator 247. Transistor 200 is located at least partially in the bottom of the opening, and conductor 246 is in contact with transistor 200.

[0295] In the <Modifications of Semiconductor Device> and <Application Examples of Semiconductor Device>, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Examples of Semiconductor Device> are denoted by the same reference numerals. In these items, the materials described in detail in <Configuration Examples of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0296] As described above, a semiconductor device with good reliability can be provided. A semiconductor device having good electrical characteristics can be provided. A semiconductor device that can be miniaturized or highly integrated can be provided. A semiconductor device with low power consumption can be provided.

[0297] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes or examples.

[0298] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0299] [Storage device 1] 12 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 200. It is preferable that the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This can reduce the area occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment. Note that the semiconductor device according to this embodiment can be applied to, for example, a logic circuit typified by a central processing unit (CPU) or a graphics processing unit (GPU), or a memory circuit typified by a dynamic random access memory (DRAM) or a non-volatile memory (NVM).

[0300] Note that the transistor 200 described in the above embodiment can be used as the transistor 200. Thus, the description in the above embodiment can be referred to for the transistor 200 and a layer including the transistor 200.

[0301] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, the use of the transistor 200 in a memory device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. Furthermore, the transistor 200 has good electrical characteristics at high temperatures compared to a transistor using silicon in the semiconductor layer. For example, the transistor 200 also exhibits good electrical characteristics in a temperature range of 125° C. to 150° C. Furthermore, in a temperature range of 125° C. to 150° C., the transistor 200 has an on / off ratio of 10 digits or more. In other words, compared to a transistor using silicon in the semiconductor layer, the transistor 200 has excellent characteristics such as an on-state current and a frequency characteristic, which are examples of transistor characteristics, as the temperature increases.

[0302] 12, a wiring 1001 is electrically connected to a source of a transistor 300, a wiring 1002 is electrically connected to a drain of the transistor 300, and a wiring 1007 is electrically connected to a gate of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The other of the source and the drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0303] The semiconductor device shown in FIG. 12 has a characteristic that the charge stored in one of the electrodes of the capacitor element 100 can be held by switching the transistor 200, and thus information can be written, held, and read. The transistor 200 is an element provided with a back gate in addition to a source, a gate (top gate), and a drain. That is, since it is a four-terminal element, it has a characteristic that independent control of input and output can be easily performed compared to two-terminal elements represented by magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), and phase-change memory using magnetic tunnel junction (MTJ) characteristics. In addition, MRAM, ReRAM, and phase-change memory may undergo structural changes at the atomic level when information is rewritten. On the other hand, the semiconductor device shown in FIG. 12 operates by charging or discharging electrons using a transistor and a capacitor element when information is rewritten, and therefore has characteristics such as excellent durability against repeated rewriting and little structural change.

[0304] The semiconductor device shown in FIG. 12 can be arranged in a matrix to form a memory cell array. In this case, the transistor 300 can be used as a read circuit or a drive circuit connected to the memory cell array. The semiconductor device shown in FIG. 12 forms a memory cell array as described above. When the semiconductor device shown in FIG. 12 is used as a memory element, for example, an operating frequency of 200 MHz or more can be achieved when the drive voltage is 2.5 V and the evaluation environment temperature is in the range of −40° C. to 85° C.

[0305] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 consisting of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or drain region.

[0306] Here, an insulator 315 is disposed over a semiconductor region 313, and a conductor 316 is disposed over the insulator 315. The transistors 300 formed in the same layer are electrically isolated by an insulator 312 that functions as an element isolation insulating layer. The insulator 312 can be an insulator similar to an insulator 326 described later. The transistor 300 may be either a p-channel type or an n-channel type.

[0307] The substrate 311 preferably contains a semiconductor such as a silicon-based semiconductor in the region where the channel of the semiconductor region 313 is formed, the region nearby, the low resistance region 314a which becomes the source region or the drain region, and the low resistance region 314b, and preferably contains single crystal silicon. Alternatively, it may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. It may be configured using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0308] Low resistance region 314a and low resistance region 314b contain, in addition to the semiconductor material applied to semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0309] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, such as silicon, containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material.

[0310] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated form, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0311] Here, in the transistor 300 shown in FIG. 12, a semiconductor region 313 (part of a substrate 311) in which a channel is formed has a convex shape. In addition, a conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. In addition, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0312] Note that the transistor 300 illustrated in FIG. 12 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0313] 12, the semiconductor device has a transistor 300 and a transistor 200 stacked. For example, the transistor 300 can be made of a silicon-based semiconductor material, and the transistor 200 can be made of an oxide semiconductor. In this way, the semiconductor device shown in FIG. 12 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. The semiconductor device shown in FIG. 12 can be manufactured by a process similar to that of a manufacturing device used for a silicon-based semiconductor material, and can be highly integrated.

[0314] <Capacitive element> The capacitive element 100 has an insulator 114 on an insulator 160, an insulator 140 on the insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, an insulator 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the opening formed in the insulator 114 and the insulator 140.

[0315] The conductor 110 functions as the lower electrode of the capacitance element 100, the conductor 120 functions as the upper electrode of the capacitance element 100, and the insulator 130 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface at the openings of the insulators 114 and 140, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0316] The insulator 114 and the insulator 150 may be made of an insulator that can be used for the insulator 280. The insulator 140 preferably functions as an etching stopper when forming an opening in the insulator 114, and may be made of an insulator that can be used for the insulator 214.

[0317] The shape of the openings formed in the insulator 114 and the insulator 140 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the openings overlapping with the transistor 200 when viewed from above is large. With such a structure, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0318] The conductor 110 is disposed in contact with the insulator 140 and an opening formed in the insulator 114. The upper surface of the conductor 110 preferably approximately coincides with the upper surface of the insulator 140. The lower surface of the conductor 110 is in contact with the conductor 152 provided on the insulator 160. The conductor 110 is preferably formed by using an ALD method or a CVD method, and may be, for example, a conductor that can be used for the conductor 205.

[0319] The insulator 130 is disposed so as to cover the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by ALD or CVD. The insulator 130 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and may be provided as a stacked layer or a single layer. For example, the insulator 130 may be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0320] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 130. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0321] Examples of insulators made of high dielectric constant (high-k) materials (materials with high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 130 is made thick. By making the insulator 130 thick, the leakage current occurring between the conductor 110 and the conductor 120 can be suppressed.

[0322] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) in that order can be used. By using such an insulator having a high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

[0323] The conductor 120 is arranged to fill the openings formed in the insulator 140 and the insulator 114. The conductor 120 is electrically connected to the wiring 1005 via the conductor 112 and the conductor 153. The conductor 120 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0324] In addition, the transistor 200 includes an oxide semiconductor and is therefore compatible with the capacitor 100. Specifically, the transistor 200 including an oxide semiconductor has a small off-state current and can retain stored data for a long time when used in combination with the capacitor 100.

[0325] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, the conductor functioning as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0326] For example, over the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.

[0327] The insulators 322, 324, and 326 may each function as an adjustment layer as described in the previous embodiment.

[0328] Conductors 328 and 330, which are electrically connected to the conductor 153 functioning as a terminal, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wiring.

[0329] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0330] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 12, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.

[0331] The insulators 350, 352, and 354 may function as the adjustment layers described in the previous embodiments.

[0332] Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0333] On the insulator 354 and the conductor 356, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are stacked in this order.

[0334] The insulators 210, 212 and 214 can function as the adjustment layers described in the previous embodiments.

[0335] A conductor 218, a conductor constituting the transistor 200 (the conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. The conductor 218 functions as a plug or wiring electrically connected to the transistor 300.

[0336] The conductor 112 and conductors (the conductor 120 and the conductor 110) constituting the capacitor 100 are embedded in the insulators 114, 140, 130, 150, and 154. The conductor 112 functions as a plug or wiring that electrically connects the capacitor 100, the transistor 200, or the transistor 300 to the conductor 153 that functions as a terminal.

[0337] In addition, the conductor 153 is provided over the insulator 154 and is covered with the insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 112 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0338] Insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each having insulating properties. For example, the insulator that functions as the interlayer film can reduce the parasitic capacitance generated between wirings by using a material with a low relative dielectric constant. Therefore, it is advisable to select a material according to the function of the insulator.

[0339] For example, the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 212, the insulator 114, the insulator 150, the insulator 156, and the like preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, resin, and the like. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, and the like), polyimide, polycarbonate, and acrylic.

[0340] In addition, the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 is 1.0×10 12 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more 5.0×10 13 It is preferable that the resistivity of the insulator provided above or below the conductor 152 or conductor 153 is in the above-mentioned range, the insulator can disperse electric charge accumulated between wirings of the transistor 200, the transistor 300, the capacitor 100, the conductor 152, etc. while maintaining insulating properties, and can suppress poor characteristics and electrostatic breakdown of the transistor and the semiconductor device including the transistor due to the electric charge, which is preferable. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of the insulator 160 or the insulator 154 may be in the above-mentioned range.

[0341] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used for the insulator 324, the insulator 350, the insulator 210, and the like.

[0342] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0343] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0344] For example, the conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, conductor 152, conductor 153, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0345] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0346] 12, for example, an insulator 247 may be provided between the insulator 280 having excess oxygen and the conductor 248. When the insulator 247 and the insulator 282 are provided in contact with each other, a structure can be achieved in which the conductor 248 and the transistor 200 are sealed with an insulator having barrier properties.

[0347] In other words, the insulator 247 can prevent excess oxygen in the insulator 280 from being absorbed by the conductor 248. Furthermore, the insulator 247 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 248.

[0348] Here, the conductor 248 functions as a plug or wiring that electrically connects to the transistor 200 or the transistor 300.

[0349] Specifically, insulator 247 is provided in contact with the side walls of the openings of insulators 284, 282, and 280, and conductor 248 is formed in contact with the side surface of insulator 247. Conductor 240 is located on at least a portion of the bottom of the opening, and conductor 248 is in contact with conductor 240.

[0350] The conductor 248 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 248 may have a layered structure. Note that in the transistor 200, the conductor 248 has a two-layered structure, but the present invention is not limited to this. For example, the conductor 248 may have a single layer or a layered structure of three or more layers.

[0351] In addition, when the conductor 248 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor that contacts the conductor 240 and contacts the insulators 280, 282, and 284 via the insulator 247. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. It is also possible to suppress the diffusion of impurities such as water and hydrogen contained in layers above the insulator 284 to the oxide 230 through the conductor 248.

[0352] As the insulator 247, for example, an insulator that can be used for the insulator 214, etc. can be used. The insulator 247 can suppress impurities such as water and hydrogen contained in the insulator 280, etc. from diffusing to the oxide 230 through the conductor 248. In addition, the insulator 247 can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.

[0353] Although not shown, a conductor 152 functioning as wiring may be disposed in contact with the upper surface of the conductor 248. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0354] The above is a description of the configuration example. By using this configuration, a semiconductor device including a transistor having an oxide semiconductor can be miniaturized or highly integrated. In addition, in a semiconductor device including a transistor having an oxide semiconductor, a change in electrical characteristics can be suppressed and reliability can be improved. Furthermore, a transistor including an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0355] [Storage device 2] An example of a semiconductor device (memory device) using the semiconductor device of one embodiment of the present invention is shown in Fig. 13. The semiconductor device shown in Fig. 13 includes a transistor 200, a transistor 300, and a capacitor 100, similar to the semiconductor device shown in Fig. 12. However, the semiconductor device shown in Fig. 13 differs from the semiconductor device shown in Fig. 12 in that the capacitor 100 is a planar type and the transistor 200 and the transistor 300 are electrically connected to each other.

[0356] In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. It is preferable that the capacitor 100 or the transistor 300 at least partially overlaps with the transistor 200. This can reduce the areas occupied by the capacitor 100, the transistor 200, and the transistor 300 in a top view, thereby enabling miniaturization or high integration of the semiconductor device according to this embodiment.

[0357] Note that the above-described transistors 200 and 300 can be used as the transistors 200 and 300. Thus, the above description can be referred to for the transistors 200 and 300 and layers including these.

[0358] In the semiconductor device shown in FIG. 13, a wiring 2001 is electrically connected to a source of the transistor 300, and a wiring 2002 is electrically connected to a drain of the transistor 300. A wiring 2003 is electrically connected to one of the source and drain of the transistor 200, a wiring 2004 is electrically connected to a first gate of the transistor 200, and a wiring 2006 is electrically connected to a second gate of the transistor 200. A gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and a wiring 2005 is electrically connected to the other electrode of the capacitor 100. Note that hereinafter, a node to which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitor 100 are connected may be referred to as a node FG.

[0359] The semiconductor device in FIG. 13 has a characteristic that the potential of the gate (node ​​FG) of the transistor 300 can be held by switching of the transistor 200, thereby enabling writing, holding, and reading of data.

[0360] Moreover, the semiconductor device shown in FIG. 13 can be arranged in a matrix to form a memory cell array.

[0361] Since the layer including the transistor 300 has a structure similar to that of the semiconductor device shown in FIG. 12, the above description can be referred to for the structure below the insulator 354.

[0362] The insulator 210, the insulator 212, the insulator 214, and the insulator 216 are disposed over the insulator 354. Here, the insulator 210 may be an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, similar to the insulator 350 and the like.

[0363] A conductor 218 is embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 functions as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. For example, the conductor 218 is electrically connected to a conductor 316 that functions as a gate electrode of the transistor 300.

[0364] The conductor 248 functions as a plug or a wiring electrically connected to the transistor 200 or the transistor 300. For example, the conductor 248 electrically connects a conductor 240b which functions as the other of the source and drain of the transistor 200 to a conductor 110 which functions as one of the electrodes of the capacitor 100 through the conductor 248.

[0365] The planar capacitor 100 is provided above the transistor 200. The capacitor 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Note that the conductor 110, the conductor 120, and the insulator 130 can be those described in the memory device 1 above.

[0366] The conductor 153 and the conductor 110 are provided in contact with the top surface of the conductor 248. The conductor 153 is in contact with the top surface of the conductor 248 and functions as a terminal of the transistor 200 or the transistor 300.

[0367] The conductor 153 and the conductor 110 are covered with the insulator 130, and the conductor 120 is disposed so as to overlap the conductor 110 with the insulator 130 interposed therebetween. Furthermore, the insulator 114 is disposed on the conductor 120 and the insulator 130.

[0368] 13 shows an example in which a planar type capacitor element is used as the capacitor element 100, but the semiconductor device described in this embodiment is not limited to this. For example, a cylindrical capacitor element 100 as shown in FIG. 12 may be used as the capacitor element 100.

[0369] [Storage device 3] An example of a memory device using a semiconductor device according to one embodiment of the present invention is shown in Fig. 14. The memory device shown in Fig. 14 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 13.

[0370] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the second gate of the transistor 200 is held at a negative potential in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0 V is very small, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows the memory device including the transistor 200 and the transistor 400 to hold stored contents for a long time.

[0371] 14, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate (backgate) of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the second gate (backgate) of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected to each other.

[0372] 12 and 13, the memory device illustrated in Fig. 14 can be arranged in a matrix to form a memory cell array. Note that one transistor 400 can control the second gate voltages of the multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than the transistors 200.

[0373] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be fabricated in parallel. The transistor 400 has a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate electrode, a conductor 405 functioning as a second gate electrode, an insulator 222, an insulator 224, and an insulator 450 functioning as gate insulating layers, an oxide 430c having a region where a channel is formed, a conductor 440a, an oxide 431a, and an oxide 431b functioning as one of a source or a drain, a conductor 440b, an oxide 432a, and an oxide 432b functioning as the other of a source or a drain, and insulators 445a and 445b functioning as barrier layers.

[0374] In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b. The conductor 440 (the conductor 440a and the conductor 440b) is in the same layer as the conductor 240. The insulator 445 (the insulator 445a and the insulator 445b) is in the same layer as the insulator 245. The oxide 430c is in the same layer as the oxide 230c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260.

[0375] Note that structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing the oxide film that will become the oxide 230c.

[0376] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made extremely small.

[0377] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes and examples.

[0378] (Embodiment 4) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 15 and 16. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0379] <Storage device configuration example> 15A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0380] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0381] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0382] The control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0383] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0384] 15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 15B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0385] FIG. 16 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0386] [DOSRAM] 16A to 16C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 shown in FIG. 16A includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0387] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring LL.

[0388] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, the wiring LL may be at ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0389] Here, the memory cell 1471 shown in Fig. 16A corresponds to the memory device shown in Fig. 12. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA corresponds to the capacitor 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring LL corresponds to the wiring 1005. Note that the transistor 300 in Fig. 12 corresponds to a transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in Figs. 15A and 15B.

[0390] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 16B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell including a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 16C.

[0391] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0392] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0393] [NOSRAM] 16D to 16G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. 16D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0394] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0395] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data and when reading data, it is preferable to apply a high-level potential to the wiring CAL. Also, when data is being held, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0396] Here, the memory cell 1474 shown in Fig. 16D corresponds to the memory device shown in Fig. 13. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 2003, the wiring WOL corresponds to the wiring 2004, the wiring BGL corresponds to the wiring 2006, the wiring CAL corresponds to the wiring 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

[0397] Moreover, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 16E. For example, the memory cell MC may be configured such that the transistor M2 has a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 16F. For example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 16G.

[0398] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely low. As a result, written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0399] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. By using a Si transistor as the transistor M3, the transistor M2 can be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0400] In addition, the transistor M3 may be an OS transistor. When the transistors M2 and M3 are OS transistors, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0401] 16H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 16H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to a wiring RBL and a wiring WBL instead of the wiring BIL.

[0402] The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. The backgate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have to have a backgate.

[0403] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0404] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be significantly reduced.

[0405] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.

[0406] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, or the like.

[0407] (Embodiment 5) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to Fig. 17. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0408] As shown in FIG. 17A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0409] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 17B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0410] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be the DOSRAM described in the above embodiment. For example, the flash memory 1222 may be the NOSRAM described in the above embodiment.

[0411] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiplication and accumulation with low power consumption.

[0412] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0413] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the analog calculation unit 1213 may be provided with the above-mentioned product-sum calculation circuit.

[0414] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0415] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0416] The network circuit 1216 includes a circuit for a network such as a local area network (LAN), and may also include a circuit for network security.

[0417] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0418] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be referred to as a GPU module 1204.

[0419] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0420] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes, examples, or the like.

[0421] (Embodiment 6) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and reproducing devices, navigation systems, and the like). Note that the computer here includes a large computer such as a server system, in addition to tablet computers, notebook computers, and desktop computers. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). FIG. 18 shows several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0422] 18A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0423] FIG. 18B is a schematic diagram of the appearance of an SD card, and FIG. 18C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

[0424] FIG. 18D is a schematic diagram of the appearance of an SSD, and FIG. 18E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the board 1153. The memory chip 1155 is a work memory for the controller chip 1156, and may be, for example, a DOSRAM chip. The capacity of the SSD 1150 can be increased by providing a memory chip 1154 on the back side of the board 1153. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 of the board 1153.

[0425] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like.

[0426] (Embodiment 7) The semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. A specific example of an electronic device including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention is shown in FIG.

[0427] <Electronic equipment and systems> The GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, portable information terminals, and audio playback devices. Moreover, by providing the GPU or chip according to one embodiment of the present invention in an electronic device, it is possible to mount artificial intelligence on the electronic device.

[0428] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0429] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0430] An electronic device according to one embodiment of the present invention can have various functions. For example, the electronic device can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc. An example of an electronic device is shown in FIG. 19.

[0431] [Information terminal] 19A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0432] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5102 and displays them on the display unit 5102, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0433] 19B illustrates a notebook type information terminal 5200. The notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0434] The notebook type information terminal 5200 can execute an application using artificial intelligence by applying a chip according to one embodiment of the present invention, similar to the above-described information terminal 5100. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, the notebook type information terminal 5200 can be used to develop new artificial intelligence.

[0435] In the above description, a smartphone and a notebook type information terminal are illustrated in Fig. 19A and Fig. 19B as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0436] [Game consoles] FIG. 19C illustrates a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection unit 5305 of the housing 5301 to another housing (not shown), a video output to the display unit 5304 can be output to another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows a plurality of players to play a game at the same time. The chips described in the above embodiments can be incorporated in the chips provided on the substrates of the housings 5301, 5302, and 5303.

[0437] 19D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0438] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0439] Furthermore, by applying a GPU or a chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0440] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5300, it becomes possible to express things that are not limited to the program of the game. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0441] In addition, when playing a game on the portable game console 5300 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0442] 19C and 19D show a portable game machine and a stationary game machine as examples of game machines, but the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0443] [Mainframe computers] The GPU or chip of one embodiment of the present invention can be applied to a large computer.

[0444] 19E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 19F is a diagram showing a rack-mounted calculator 5502 included in the supercomputer 5500.

[0445] A supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the board.

[0446] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, and therefore power consumption is high and chips generate a lot of heat. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0447] 19E and 19F show a supercomputer as an example of a large computer, but the large computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of large computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0448] [Mobile object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0449] Fig. 19G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body, Fig. 19G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0450] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items and layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0451] The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0452] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for an automobile. The chip can also be used in a system that performs road guidance, risk prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and risk prediction.

[0453] In the above description, an automobile is described as an example of a moving object, but the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and the chip of one embodiment of the present invention may be applied to these moving objects to provide a system using artificial intelligence.

[0454] [electric appliances] 19H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0455] An electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of the ingredients, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0456] Although an electric refrigerator-freezer has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0457] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0458] This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes, examples, and the like. EXAMPLES

[0459] In this example, a semiconductor device including a first transistor and a second transistor stacked was fabricated as Sample 1A. Then, a cross section of the semiconductor device was observed. Note that the transistor 200 shown in FIG. 2 was fabricated as the first transistor and the second transistor.

[0460] <Sample preparation method> A method for preparing Sample 1A will be described below.

[0461] First, a first layer having a first transistor 200 was formed on a base layer.

[0462] Specifically, in the sample 1A, as the first oxide (oxide film 230A) to be the oxide 230a, In-Ga-Zn oxide was formed by sputtering using a target of In:Ga:Zn=1:3:4 [atomic ratio]. Next, as the second oxide (oxide film 230B) to be the oxide 230b, In-Ga-Zn oxide was formed by sputtering using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] on the first oxide, and then In-Ga-Zn oxide was formed by sputtering using a target of In:Ga:Zn=1:3:4 [atomic ratio] to form a two-layer laminate structure. The first oxide and the second oxide were formed continuously.

[0463] Next, in sample 1A, a tungsten film that becomes the conductor 240 was formed on the second oxide. Then, the conductor, the second oxide, and the first oxide were processed using a hard mask to form the oxide 230a, the oxide 230b, the conductive layer 240B, and an insulating layer that becomes the insulating layer 245.

[0464] Next, in Sample 1A and Sample 1B, a silicon oxynitride film was formed to be the insulator 280. Subsequently, CMP treatment was performed to polish the silicon oxynitride film and planarize the surface of the silicon oxynitride film, thereby forming the insulator 280.

[0465] Next, in Sample 1A, an opening was formed in the silicon oxynitride film that was to become the insulator 280. Next, the conductive layer 240B exposed at the bottom of the opening was removed, and the conductor 240a and the conductor 240b were formed.

[0466] Next, in sample 1A, as a third oxide (oxide film 230C) which becomes oxide 230c, an In-Ga-Zn oxide was formed by sputtering using a target with an atomic ratio of In:Ga:Zn=4:2:4.1, and then an In-Ga-Zn oxide was formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4, thereby forming a two-layer stacked structure.

[0467] Next, in the sample 1A, a silicon oxynitride film (insulating film 250A) to become the insulator 250 was formed.

[0468] Next, in sample 1A, a titanium nitride film was formed as a conductive film (conductive film 260A) to be the conductor 260a on the silicon oxynitride film to be the insulator 250. Then, a tungsten film was formed as a conductive film (conductive film 260B) to be the conductor 260b. Note that the titanium nitride film and the tungsten film were formed by successive film formation.

[0469] Next, in sample 1A, conductive film 260A, conductive film 260B, insulating film 250A, and oxide film 230C were partially removed to form conductor 260, insulator 250, and oxide 230c.

[0470] Next, a plug electrically connected to the transistor 200, a film having a stacked structure of an aluminum oxide film and a hafnium oxide film as the insulator 282, and a film having silicon oxynitride as the insulator 284 were formed.

[0471] Through the above steps, a first layer was formed having the first transistor 200. Then, an interlayer film was formed between the first transistor and the second transistor.

[0472] As the interlayer film, a film having a stress in the opposite direction to the warping direction of the first layer was formed. In other words, when the combined stress of all the films constituting the first layer (also called the total stress of the first layer) is compressive stress, a layer having tensile stress is used as the interlayer film. On the other hand, when the total stress of the first layer is tensile stress, a layer having compressive stress is used as the interlayer film.

[0473] In this embodiment, the total stress of the first layer was compressive stress. Therefore, the interlayer film used a layer having tensile stress as the total stress. Specifically, a silicon oxide film having compressive stress and a silicon oxide film having tensile stress were laminated, and the silicon oxide film having tensile stress was formed to be thicker than the silicon oxide film having compressive stress.

[0474] Next, a second layer having a second transistor 200 was formed on the interlayer film. The second layer was formed in the same process as the first layer.

[0475] Through the above steps, Sample 1A was fabricated.

[0476] <Cross-section observation of sample 1A and evaluation results of transistor characteristics> First, a cross-sectional observation was performed on Sample 1A. The cross-sectional observation was performed using a scanning transmission electron microscope (STEM). The observation device used was an HD-2700 manufactured by Hitachi High-Technologies Corporation. The cross-sectional STEM observation results are shown in FIG. 20 and FIG. 21.

[0477] As shown in Fig. 20A, the length in the L direction of the channel portion of Sample 1A was 72 nm. As shown in Fig. 20B, the length in the W direction of the channel portion of Sample 1A was 51 nm. As shown in Fig. 21, the first transistor and the second transistor were fabricated by stacking them.

[0478] Next, the transistor characteristics of Sample 1A were evaluated.

[0479] First, it was confirmed that the threshold voltage changes by changing the voltage (Vbg) applied to the conductor 205 in the transistors 200 in the first layer and the transistors 200 in the second layer. Specifically, the conditions of the voltage (Vbg) applied to the conductor 205 of each transistor 200 were changed, and the I d -V g This was confirmed by carrying out measurements.

[0480] FIG. 22A shows the I d -V g The measurement results are shown in FIG. 22B. d -V g The measurement results are shown.

[0481] In addition, using the results shown in FIG. 22, the amount of change in threshold voltage with respect to the voltage (Vbg) applied to the conductor 205 of the transistor 200 provided in each layer was obtained. The results are shown in FIG. 23A. As shown in FIG. 23A, the transistor 200 has a threshold voltage with respect to the voltage (V bg It was found that by appropriately adjusting the threshold voltage, it is possible to control the threshold voltage depending on the circuit application.

[0482] Next, in the transistors 200 in the first and second layers, the fluctuation in the threshold of each transistor 200 affects the field effect mobility (μ FEs ) was investigated. The results are shown in FIG. 23B. As shown in FIG. 23B, the threshold shift amount −∂V th / ∂V bg is 0.13 V / V. The voltage (V bg ) is adjusted to vary the threshold of each transistor 200, while the field effect mobility (μ FEs ) was found to have a small effect.

[0483] Next, the temperature dependency of the transistor characteristics was evaluated for the transistors 200 provided in the first and second layers. The measurement conditions were -40°C, 27°C, and 85°C, and the semiconductor device was operated under the temperature conditions to measure the transistor characteristics. Note that FIG. 24A shows the I d -V g The measurement results are shown in FIG. 24B. d -V g The measurement results are shown.

[0484] As shown in FIG. 24, the off-leak current of the transistor 200 provided in the first and second layers is always below the detection limit (1×10 -13A) or less. The temperature dependence of the field effect mobility of each transistor 200 is also shown in the figure. It was confirmed that the field effect mobility hardly changes with temperature. This is a feature not found in Si transistors, whose field effect mobility decreases at high temperatures.

[0485] Next, in the transistor 200 in the first layer, the off-leakage current was measured between the conductor 240a and the conductor 240b, between the conductor 240a and the conductor 260, and between the conductor 240a and the conductor 205 at a high temperature of 85° C. The results are shown in FIG. 25. In FIG. 25, the vertical axis represents the leakage current, and the horizontal axis represents 1000 / T. The white circles represent the results for the drain, the squares represent the results for the D-TG, the triangles represent the results for the D-BG, and the diamonds represent the results for the Si FET[5]. As shown in FIG. 25, the off-leakage value between each conductor was 5.0×10 -20 Therefore, it was found that the off-leak current of the transistor 200 is extremely low, and therefore the refresh power can be significantly reduced.

[0486] Next, the write speed was calculated in a simulated manner assuming a DOSRAM or NOSRAM using the transistor 200. The results are shown in FIG. 26. In FIG. 26, the vertical axis represents write time and erase time, and the horizontal axis represents retention time. FIG. 26A shows the results assuming a DOSRAM, and FIG. 26B shows the results assuming a NOSRAM. Note that the retention time is calculated assuming only subthreshold leakage as the cause of leakage, and the I d -V g Calculated by extrapolating the curve.

[0487] The semiconductor device is designed for use at temperatures between -40°C and 85°C, and the conductor 205 is connected to a voltage (V bgThe data retention time at 85°C, where the off-leak current is at its maximum, was adjusted by applying a voltage of -0.8V / 2.5V. The power supply voltage used for retention and writing was set to -0.8V / 2.5V, the allowable voltage fluctuation was set to 0.2V, the write determination voltage was set to 0.52V, and the operating speed of the drive circuit was set to 2.5GHz.

[0488] As shown in Figure 26A, at -40°C where the write current is the smallest, the write speed was estimated to be about 1.0 to 3.0 nsec when the DOSRAM is operated (assuming a storage capacity of 3.5 fF and a data retention time of 1 hr at 85°C). This corresponds to an operating speed of the DOSRAM of 100 MHz or more.

[0489] As shown in Figure 26B, the write time assuming NOSRAM operation (retention capacity 1.2 fF, data retention time of 5 years at 85°C) was estimated to be 10.0 nsec or less. When used in NOSRAM, the stacked structure can be used to reduce the load on wiring such as bit lines, so the impact of the read speed is small and the write speed can determine the overall operating speed. Therefore, a write time of 10.0 nsec or less corresponds to an operating speed of 40 MHz or more.

[0490] Figure 26B also shows the estimated time required to erase written data. The data erase time was estimated using the same procedure as for calculating the write time, by determining the time required to reduce the voltage of the storage capacitor from Vd = 1.08V to 0.11V (10% of 1.08V) from the Id-Vd characteristics at Vs = 0V and Vg = 2.25V. The data erase time was estimated to be 2.0 nsec or less for the first layer.

[0491] As can be seen from Figure 26B, by adopting a semiconductor device in which transistors 200 are stacked as a memory cell, it is possible to achieve both long-term retention and high-speed operation regardless of whether DOSRAM operation or NOSRAM operation is assumed.

[0492] Next, in FIG. 27, in the transistor 200 of the first layer, data: 000 (V SN =0.00V) → data:111(V SN = 1.08V) and data:111(V SN =1.08V) → data:000(V SN 27 shows the estimated erase time required for a write voltage of 1.0 V (10% of 1.08 V). In Fig. 27, the vertical axis represents the write time and erase time, and the horizontal axis represents the retention time.

[0493] The retention capacitance is 3.5fF, and the allowable voltage fluctuation for multi-value (3bit / cell) retention is 0.02V. When assuming use in NOSRAM, analog voltage can be written directly to the retention node, so unlike flash memory, no verify operation is required. Therefore, it was confirmed that for retention times of one year or less, both the write time and data erase time are sufficiently shorter than the 100nsec write time of the drive circuit.

[0494] Next, we performed a write operation and retention test on Sample 1A when it functioned as a multilevel memory (multilevel operation). In Figure 28, the vertical axis represents the read voltage and the horizontal axis represents the retention time. Figure 28 shows the retention characteristics obtained from the evaluation results. Figure 28 shows that even when operated as a multilevel memory, it is possible to write the equivalent of 8 levels in 100 nsec, and data can be retained for more than 1 hr at 27°C.

[0495] Next, a write endurance test was performed on the sample 1A in a two-value operation when it functioned as a NOSRAM memory cell at an environmental temperature of 27° C. FIG. 29 shows the write endurance according to the evaluation results. In FIG. 29, the horizontal axis represents Write cycles. From FIG. 29, it can be seen that the write endurance of the sample 1A was 10 12 It was confirmed that the data was retained without any problems even after more than one rewrite operation.

[0496] Here, the cutoff frequency f of the transistor 200 is T The results are shown in FIG. 30. In FIG. 30, the horizontal axis represents the input frequency. In this evaluation, a sample in which only the first layer was fabricated was used. The evaluation was performed by applying a voltage (V g ), and the voltage applied to the conductor 240a (V d ) was set to 2.5 V and the evaluation was performed. As shown in Figure 30, T The result shows that the transistor 200 can be applied not only to memory but also to analog circuits such as high frequency circuits.

[0497] At least a part of this embodiment can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0498] 10: semiconductor device, 11: substrate, 12: adjustment layer, 14: layer, 16: adjustment layer, 18: layer, 20: semiconductor device, 21: substrate, 23: insulator, 24: layer, 26: adjustment layer, 27: insulator, 28: layer

Claims

[Claim 1] a first layer including a first transistor including an oxide semiconductor over a substrate; a second layer on the first layer; and a third layer including a second transistor including an oxide semiconductor provided over the second layer, a total internal stress in the first layer and a total internal stress in the third layer acting in a first direction; A semiconductor device in which the total internal stress of the second layer acts in a direction opposite to the first direction.

Images