Semiconductor device

Abstract

To reduce consumption power of a circuit that performs determination, improve accuracy of a system that performs the determination, increase safety of a target to be monitored by a sensor element, or provide a system to easily monitor the target.SOLUTION: A semiconductor device includes a detection circuit that has a function of performing first determination to select a first value or a second value by analyzing first data; a first determination circuit and a second determination circuit that have a function of extracting a characteristic of an image; a power source circuit; and a power source management device. If the first value is selected by the first determination, the power source management device has a function of supplying a voltage from the power source circuit to the first determination circuit. The first determination circuit has a function of performing a second determination by analyzing the first data. Upon the detection of occurrence of an event in the second determination, the second determination circuit has a function of performing a third determination by analyzing the first data.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Thus, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, electronic devices, and the like may include semiconductor elements and semiconductor circuits. Thus, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] Portable information terminals such as smartphones and tablet devices are becoming more and more popular. As information terminals become more popular, various communication standards have been established. For example, the LTE-Advanced standard, known as the fourth generation mobile communication system (4G), has begun operation.

[0005] In recent years, with the development of information technology such as the Internet of Things (IoT), the amount of data handled by information terminals is increasing. In addition, there is a demand for improved communication speeds for electronic devices such as information terminals.

[0006] In order to support various information technologies such as IoT, a new communication standard called the fifth generation mobile communication system (5G) is being considered, which will achieve faster communication speeds, more simultaneous connections, and shorter latency than 4G. 5G will use communication frequencies in the 3.7 GHz, 4.5 GHz, and 28 GHz bands.

[0007] Semiconductor devices compatible with 5G will be manufactured using semiconductors that use one type of element such as Si as the main component, or compound semiconductors that use multiple types of elements such as Ga and As as the main components. In addition, oxide semiconductors, a type of metal oxide, are attracting attention.

[0008] In oxide semiconductors, c-axis aligned crystalline (CAAC) structures and nanocrystalline (nc) structures, which are neither single crystal nor amorphous, have been found (see Non-Patent Documents 1 and 2).

[0009] Non-Patent Documents 1 and 2 disclose techniques for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

[0010] Also, known techniques for reducing power consumption of semiconductor devices include, for example, power gating (PG), clock gating (CG), voltage scaling, etc. For example, Patent Document 1 describes the implementation of a method that is advantageous for reducing power consumption out of the DVFS (Dynamic Voltage and Frequency Scaling) method and the PG method. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] International Publication No. 2009 / 078081 [Non-patent literature]

[0012] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0013] An object of one embodiment of the present invention is to provide a novel semiconductor device or a method for operating the novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel determination system or a method for operating the novel determination system. Another object of one embodiment of the present invention is to reduce power consumption, for example, to reduce power in a hibernation state. Another object of one embodiment of the present invention is to shorten the time required for a process of returning from a hibernation state to a normal state or to reduce energy required for the process. Another object of one embodiment of the present invention is to reduce power consumption of a circuit that performs determination. Another object of one embodiment of the present invention is to improve the accuracy of a system that performs determination. Another object of one embodiment of the present invention is to increase the safety of an object monitored by a sensor element. Another object of one embodiment of the present invention is to provide a system that easily monitors an object.

[0014] The description of multiple problems does not preclude the existence of each problem. Note that one embodiment of the present invention does not need to solve all of these problems. In addition, problems other than those listed will become apparent from the description of the specification, drawings, claims, etc., and these problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0015] One embodiment of the present invention is a semiconductor device comprising a detection circuit, a first judgment circuit, a second judgment circuit, a power supply circuit, and a power management device, wherein the detection circuit has a function of analyzing first data and making a first judgment in which a first value or a second value is selected, the first judgment circuit and the second judgment circuit have a function of extracting image features, and when the first value is selected by the first judgment, the power management device has a function of supplying a voltage from the power supply circuit to the first judgment circuit, the first judgment circuit has a function of analyzing the first data and making a second judgment, and the second judgment circuit has a function of analyzing the first data and making a third judgment if the occurrence of an event is detected in the second judgment.

[0016] In the above configuration, the first decision circuit preferably has a function of extracting contours.

[0017] In the above configuration, it is preferable that the first judgment circuit has a function of performing contour extraction, and the second judgment circuit has a function of executing one or more methods selected from a deep neural network, a convolutional neural network, a recurrent neural network, an autoencoder, a deep Boltzmann machine, and a deep belief network.

[0018] In the above configuration, it is preferable that the device has an antenna and has a function of transmitting the result of the third determination by wireless communication.

[0019] In the above-mentioned configuration, the event is preferably detection of a human being using contour extraction.

[0020] In the above configuration, it is preferable that the first judgment circuit has a function of performing human face authentication using contour extraction.

[0021] Alternatively, one embodiment of the present invention includes an imaging device, a detection circuit, a processing device, a second judgment circuit, and a power supply circuit, wherein the processing device includes a first judgment circuit, a power management device, a processor core, and a memory circuit, wherein the processor core has a function of providing an instruction to the first judgment circuit, and the memory circuit has a function of holding data generated by the processor core, the imaging device has a function of acquiring first data, the detection circuit has a function of analyzing the first data and making a first judgment in which a first value or a second value is selected, and the first judgment circuit and the second judgment circuit have a function of extracting features of an image, and when the first value is selected by the first judgment, the power management device has a function of causing the power supply circuit to supply a voltage to the first judgment circuit, the first judgment circuit has a function of analyzing the first data and making a second judgment, and the second judgment circuit has a function of analyzing the first data and making a third judgment when an occurrence of an event is detected in the second judgment, and the imaging device is a judgment system having a plurality of pixel circuits arranged in a matrix.

[0022] In the above structure, it is preferable that the memory circuit includes a first transistor and a first capacitor, one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor, and the first transistor has an oxide semiconductor in a channel formation region.

[0023] In the above configuration, it is preferable that the memory circuit includes a first transistor and a first capacitor, one of a source and a drain of the first transistor being electrically connected to one electrode of the first capacitor, the first transistor having an oxide semiconductor in a channel formation region, each of the multiple pixel circuits includes a photoelectric conversion device, a second transistor, and a second capacitor, one electrode of the photoelectric conversion device being electrically connected to one of a source and a drain of the second transistor, the other of the source and drain of the second transistor being electrically connected to one electrode of the second capacitor, and the second transistor having an oxide semiconductor in a channel formation region.

[0024] In the above configuration, the first decision circuit preferably has a function of extracting contours.

[0025] In the above configuration, it is preferable that the first judgment circuit has a function of performing contour extraction, and the second judgment circuit has a function of executing one or more methods selected from a deep neural network, a convolutional neural network, a recurrent neural network, an autoencoder, a deep Boltzmann machine, and a deep belief network. Effect of the Invention

[0026] According to one embodiment of the present invention, a novel semiconductor device or an operating method of the novel semiconductor device can be provided. According to one embodiment of the present invention, a novel determination system or an operating method of the novel determination system can be provided. According to one embodiment of the present invention, power consumption can be reduced, for example, power in a hibernation state can be reduced. According to one embodiment of the present invention, time required for a process of returning from a hibernation state to a normal state can be shortened or energy required for the process can be reduced. According to one embodiment of the present invention, power consumption of a circuit that performs determination can be reduced. According to one embodiment of the present invention, accuracy of a system that performs determination can be improved. According to one embodiment of the present invention, safety of an object monitored by a sensor element can be improved. According to one embodiment of the present invention, a system that easily monitors an object can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. Also, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, for one embodiment of the present invention, problems, effects, and novel features other than those described above will become apparent from the description and drawings of this specification. [Brief description of the drawings]

[0028] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a determination system. [Diagram 2]FIG. 2 is a block diagram showing an example of the configuration of the determination system. [Diagram 3] FIG. 3 is a flow diagram showing an example of the operation of the semiconductor device. [Figure 4] 4A and 4B are block diagrams showing configuration examples of a semiconductor device. [Diagram 5] 5A to 5D are diagrams for explaining an example of the operation of power management of a semiconductor device. [Figure 6] FIG. 6 is a flowchart showing an example of an operation of power management of a semiconductor device. [Figure 7] 7A and 7B are block diagrams showing configuration examples of a semiconductor device. [Figure 8] FIG. 8 is a block diagram showing an example of the configuration of a processor core. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of the memory circuit. [Figure 10] FIG. 10 is a timing chart illustrating an example of the operation of the memory circuit. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a memory cell of a cache. [Figure 12] FIG. 12 is a timing chart illustrating an example of the operation of the memory cell. [Figure 13] Fig. 13A is a functional block diagram showing a configuration example of a NOSRAM, and Fig. 13B is a circuit diagram showing a configuration example of a memory cell. [Figure 14] Fig. 14A is a circuit diagram showing an example of the configuration of a memory cell array, Fig. 14B and Fig. 14C are circuit diagrams showing an example of the configuration of a memory cell. [Figure 15] Fig. 15A is a circuit diagram showing a configuration example of a memory cell of a DOSRAM, and Fig. 15B is a diagram showing an example of a stacked structure of the DOSRAM. [Figure 16] 16A and 16B are diagrams showing examples of the configuration of a neural network. [Figure 17] FIG. 17 is a diagram illustrating a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a diagram showing a configuration example of a memory cell. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of the offset circuit. [Figure 20] FIG. 20 is a timing chart. [Figure 21] Fig. 21A is a block diagram illustrating an imaging device, and Fig. 21B and Fig. 21C are circuit diagrams illustrating pixel circuits. [Figure 22] Fig. 22A is a diagram for explaining the operation of a rolling shutter, and Fig. 22B is a diagram for explaining the operation of a global shutter. [Figure 23] 23A and 23B are timing charts illustrating the operation of the pixel circuit. [Figure 24] 24A and 24B are circuit diagrams illustrating a pixel circuit. [Diagram 25] FIG. 25 is a circuit diagram and a block diagram illustrating a read circuit. [Figure 26] 26A and 26B are cross-sectional views illustrating a pixel. [Figure 27] 27A, 27B, and 27C are diagrams illustrating a Si transistor. [Figure 28] 28A and 28B are cross-sectional views illustrating a pixel. [Figure 29] 29A, 29B, 29C, and 29D illustrate OS transistors. [Diagram 30] 30A and 30B are cross-sectional views illustrating an example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated description will be omitted.

[0030] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0031] In addition, in top views (also called "plan views"), perspective views, and the like, illustration of some components may be omitted in order to make the drawings easier to understand.

[0032] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally.

[0033] In addition, in this specification and the like, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0034] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0035] In addition, the functions of the source and drain are interchangeable depending on the operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, so it is difficult to determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain can be used interchangeably.

[0036] In addition, in this specification, "electrically connected" includes a direct connection and a connection via "something having some electrical action." Here, the "something having some electrical action" is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in the actual circuit, there may be no physical connection and only wiring extending therethrough.

[0037] In this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. This therefore includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This therefore includes cases in which the angle is 85° or more and 95° or less.

[0038] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "same," "equal," "uniform," etc. are used, they are intended to include an error of plus or minus 20% unless otherwise expressly stated.

[0039] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0040] Even when written as "semiconductor", for example, if the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" instead of "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read as interchangeable.

[0041] Furthermore, even when written as "semiconductor", if the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use "semiconductor" in place of "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be interchangeable.

[0042] In addition, ordinal numbers such as "first" and "second" in this specification are used to avoid confusion of components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0043] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0044] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0045] In this specification and the like, a high power supply potential (hereinafter also referred to as "power supply potential VDD", "VDD", "H potential", or "H") refers to a power supply potential that is higher than a low power supply potential (hereinafter also referred to as "power supply potential VSS", "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential that is lower than VDD. Also, a ground potential (hereinafter also referred to simply as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0046] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0047] In this specification and the like, the source refers to a source region, a source electrode, and a part or all of a source wiring. The source region refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The source electrode refers to a conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0048] In this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The drain electrode refers to a conductive layer that is connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0049] In addition, in drawings, etc., to make the potential of wiring and electrodes easier to understand, "H" indicating H potential or "L" indicating L potential may be written next to the wiring and electrode. Wiring and electrodes where a potential change has occurred may be written with "H" or "L" enclosed in a box. When a transistor is in the off state, an "x" symbol may be written over the transistor.

[0050] A terminal may refer to a group of multiple terminals. For example, an independent signal is applied to each terminal of the group of multiple terminals, and one or more wires are electrically connected to each terminal.

[0051] A transistor has three terminals (nodes) called a gate, a source, and a drain. The gate is a terminal that functions as a control terminal that controls the conductive state of a transistor. A pair of input / output terminals (nodes) that function as a source or a drain becomes a source and the other a drain depending on the type of transistor and the level of the potential applied to each terminal (node). Generally, in an n-type transistor, the node to which a low potential is applied is called a source, and the node to which a high potential is applied is called a drain. Conversely, in a p-type transistor, the node to which a low potential is applied is called a drain, and the node to which a high potential is applied is called a source. In this specification, the two terminals (nodes) other than the gate may be called a first terminal (node) and a second terminal (node).

[0052] In this specification, in order to facilitate understanding of the circuit configuration and its operation, one of the two input / output terminals (nodes) of a transistor may be limited to a source and the other to a drain. Of course, depending on the driving method, the magnitude relationship of the potentials applied to the three terminals of the transistor may change, and the source and drain may be interchanged. Therefore, in one embodiment of the present invention, the distinction between the source and drain of a transistor is not limited to the description in the specification and drawings.

[0053] In this specification, etc., even if the connection destinations of all terminals of active elements (e.g., transistors, diodes, etc.), passive elements (e.g., capacitance elements, resistance elements, etc.), etc. are not specified, a person skilled in the art may be able to configure one aspect of the invention. In other words, it can be said that one aspect of the invention is clear even if the connection destinations are not specified. And, when an aspect in which the connection destinations are specified is described in this specification, etc., it may be possible to determine that an aspect of the invention in which the connection destinations are not specified is described in this specification, etc. In particular, when there are multiple possible cases in which the connection destinations of a terminal are to be multiple, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, it may be possible to configure one aspect of the invention by specifying the connection destinations of only some of the terminals of active elements (transistors, diodes, etc.), passive elements (capacitance elements, resistance elements, etc.).

[0054] In this specification, etc., if at least the connection destination of a certain circuit is specified, a person skilled in the art may be able to specify the invention. Alternatively, if at least the function of a certain circuit is specified, a person skilled in the art may be able to specify the invention. In other words, if the function can be specified, it can be said that the aspect of the invention is clear. Then, it may be possible to determine that one aspect of the invention in which the function is specified is described in this specification, etc. Therefore, if the connection destination of a certain circuit is specified even if the function is not specified, one aspect of the invention is disclosed and one aspect of the invention can be configured. Alternatively, if the connection destination of a certain circuit is specified even if the connection destination is not specified, one aspect of the invention is disclosed and one aspect of the invention can be configured.

[0055] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention and an application example of the semiconductor device will be described.

[0056] <Example of semiconductor device configuration> An example of a determination system according to one embodiment of the present invention is described below. The determination system according to one embodiment of the present invention includes a semiconductor device. The determination system according to one embodiment of the present invention preferably includes an imaging device in addition to the semiconductor device. The semiconductor device according to one embodiment of the present invention includes a processing device. The processing device according to one embodiment of the present invention has a function of turning the power supply of some of its circuits into an off mode by a power gating operation. The power supply of the circuit in the off mode can return to an on mode in response to an interrupt request.

[0057] Fig. 1 shows an example of the configuration of a judgment system having a semiconductor device and a device such as an imaging device. The semiconductor device 700 shown in Fig. 1 is electrically connected to an imaging device 601. The semiconductor device 700 has a detection circuit 92, a processing unit (PU) 20, and a judgment circuit 91. The PU 20 has a preliminary judgment circuit 80. The judgment circuit 91 has a function of performing calculations using a neural network. The preliminary judgment circuit 80 may be called a first judgment circuit, and the judgment circuit 91 may be called a second judgment circuit.

[0058] The imaging device 601 has a function of capturing an image using visible light, and preferably has a function of capturing an image using infrared light.

[0059] When the imaging device 601 captures an image, a light source may be prepared and the light source may be irradiated onto the subject.

[0060] 1 also includes a display device 602. The display device 602 is electrically connected to the imaging device 601. The display device 602 has a function of displaying an image captured by the imaging device 601. The display device 602 includes, for example, a display unit and a driver circuit that controls the display unit.

[0061] 1 also includes a terminal 603. The semiconductor device 700 preferably has a function of performing wireless communication with the terminal 603. The semiconductor device 700 includes, for example, an antenna for wireless communication.

[0062] The semiconductor device 700 can perform analysis in stages in the order of the detection circuit 92, the preliminary judgment circuit 80, and the judgment circuit 91. The more stages, the more accurate the analysis. The more stages of analysis, the more accurate the judgment can be.

[0063] On the other hand, the more accurate the analysis, the larger the scale of the arithmetic circuit becomes, and the greater the power consumption of the semiconductor device 700 may become. Therefore, if the detection circuit 92 or the preliminary judgment circuit 80 judges that the analysis is sufficient, it is not necessary to proceed to the next stage. The fewer the stages, the greater the power consumption of the semiconductor device 700 can be reduced.

[0064] The semiconductor device of one embodiment of the present invention has a function of determining whether an abnormal event has occurred. In the semiconductor device of one embodiment of the present invention, the determination is preferably performed in stages. In this case, in an initial stage, it is necessary to determine only whether an event has occurred, and not to determine whether the event that has occurred is abnormal.

[0065] The detection circuit 92 is provided with the imaging data of the imaging device 601. The detection circuit 92 has a function of performing binary classification. More specifically, the detection circuit 92 has a function of analyzing the provided data and judging whether an event has occurred. The detection circuit 92 does not judge whether the event that has occurred is abnormal, for example. The detection circuit 92 analyzes the imaging data, for example, and performs a first judgment. The first judgment is a binary classification. If a predetermined standard is exceeded, a first value is selected, and if not, a second value is selected. Here, exceeding a predetermined standard refers to, for example, analyzing the imaging data, quantifying the result, and the obtained numerical value exceeding the standard. Alternatively, for example, the imaging data is analyzed, and it is judged that an event has occurred. If the first value is selected by the first judgment performed by the detection circuit 92, a signal INT is provided to the PU 20, and as a next step, the imaging data is analyzed in the preliminary judgment circuit 80.

[0066] As an example, consider a case where the imaging device 601 is used to identify a suspicious person. In such a case, for example, if an image presumably of a person is detected in the captured image, it may be determined that "an event has occurred." In this case, even if an event has occurred in the detection circuit 92, the captured person is not necessarily a suspicious person. The event may be a simple phenomenon. For example, the event may be "detection of movement of a subject." Or, for example, the event may be "detection of a subject." Or, for example, the event may be "a significant change in luminance."

[0067] The detection circuit 92 performs calculations simpler than those performed by the preliminary determination circuit 80 and the determination circuit 91, which will be described later. For example, the detection circuit 92 analyzes the spatial luminance distribution of the imaging data to detect the subject. Alternatively, for example, the detection circuit 92 sets a threshold value and determines that an event has occurred when the obtained data exceeds the threshold value.

[0068] The detection circuit 92 has a function of providing a signal INT to the PU 20 when an event occurs. The signal INT is a signal that requests interrupt processing. The power supply of a circuit in the PU 20 that has been put into the off mode, such as a processor core, can be restored to the on mode in response to the interrupt request. After that, the PU 20 executes a desired command, and the preliminary judgment circuit 80 of the PU 20 judges whether or not an abnormal event has occurred. Specifically, for example, the preliminary judgment circuit 80 analyzes the captured image data and judges whether or not a suspicious person is captured on the screen.

[0069] When the PU 20 does not perform analysis in the preliminary decision circuit 80, the power consumption can be significantly reduced by the power gating operation.

[0070] The PU 20 is a circuit that has the function of executing instructions. The detailed configuration of the PU 20 will be described later.

[0071] The preliminary judgment circuit 80 may only judge whether the subject is a "human" or not, without judging whether the subject is a suspicious person or not. In such a case, the judgment circuit 91 may judge whether the subject is a suspicious person or not.

[0072] The preliminary determination circuit 80, for example, extracts the contour of the subject and detects a human. For example, a spatial brightness comparison can be used as a method for extracting the contour. Specifically, for example, an analysis using HoG (Histogram of Oriented Gradient) and SVM (Support Vector Machine) can be performed.

[0073] The preliminary judgment circuit 80 may also analyze, for example, a change in the subject over time, more specifically, a change in the subject from frame to frame. By analyzing the change in the subject over time, it may be possible to infer whether the human movement is suspicious or not.

[0074] It is preferable that the preliminary judgment circuit 80 performs analysis with lower power consumption than the judgment circuit 91. It is preferable that the preliminary judgment circuit 80 performs calculations on a smaller scale than the judgment circuit 91. It is preferable that the preliminary judgment circuit 80 performs calculations in a shorter time than the judgment circuit 91.

[0075] When the preliminary judgment circuit 80 uses a neural network, it is preferable that the preliminary judgment circuit 80 performs calculations on a smaller scale than the judgment circuit 91. For example, when the preliminary judgment circuit 80 and the judgment circuit 91 both perform a convolutional neural network (CNN), the number of intermediate layers used in the preliminary judgment circuit 80 is smaller than the number of intermediate layers used in the judgment circuit 91.

[0076] In the preliminary judgment circuit 80, the imaging data or the data converted from the imaging data is analyzed, and a second judgment is performed. If a predetermined criterion is exceeded in the second judgment, it is preferable that, as a next step, the imaging data or the data converted from the imaging data is analyzed in the judgment circuit 91. More specifically, for example, if it is judged in the second judgment that an abnormal event has occurred, it is preferable that further analysis is performed in the judgment circuit 91 to judge whether or not an abnormal event has occurred in order to improve the accuracy of the judgment. The judgment circuit 91 has a function of performing calculations using, for example, a neural network.

[0077] After the preliminary judgment circuit 80 makes a judgment, the judgment accuracy can be improved by performing a more detailed analysis in the judgment circuit 91. Furthermore, if the preliminary judgment circuit 80 makes a judgment in advance and judges that no abnormal event has occurred, it is not necessary to perform calculations in the judgment circuit 91, and therefore the power consumption of the semiconductor device 700 can be reduced.

[0078] The judgment circuit 91 can perform calculations with higher accuracy than the preliminary judgment circuit 80. It is preferable that the judgment circuit 91 performs analysis using artificial intelligence (AI).

[0079] The determination circuit 91 preferably executes one method selected from a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network (DBN), etc., or a combination of two or more methods, to analyze the imaging data. More specifically, the determination circuit 91 can use a CNN to extract image features.

[0080] Furthermore, in the determination circuit 91, before extracting image features using CNN or the like, a process for increasing the image resolution or a process for colorizing a black-and-white image may be performed. For example, a method called a generative adversarial network (GAN) may be used as a colorization method.

[0081] When the determination circuit 91 determines that an abnormal event has occurred, the semiconductor device 700 transmits a signal notifying the terminal 603 of the abnormality by wireless communication. In addition, image data in which it has been determined that an abnormal event has occurred may be transmitted together with the signal notifying the abnormality. At this time, image data that has been subjected to processing to increase the resolution or colorization may be transmitted.

[0082] An example of the configuration of the semiconductor device will be described with reference to Fig. 2. The semiconductor device 700 shown in Fig. 1 includes a power supply circuit 10, a PU 20, a determination circuit 91, and a detection circuit 92. The semiconductor device 700 is electrically connected to the imaging device 601.

[0083] The PU 20 is a circuit having a function of executing instructions. The PU 20 has a plurality of functional circuits integrated on one chip. The PU 20 has a processor core 30, a power management unit (PMU) 60, a clock control circuit 65, a power switch (PSW) 70, a preliminary determination circuit 80, a memory 81, a circuit 82, an interface 88, and a bus line 89.

[0084] The PU 20 may also have a cache 40 and a power switch (PSW) 71. The cache 40 and the PSW 71 will be described in detail later.

[0085] The processor core 30, PMU 60, cache 40, PSW 70, PSW 71, preliminary determination circuit 80, memory 81, circuit 82, and interface 88 are electrically connected via a bus line 89. Each circuit can exchange signals via the bus line 89. The processor core 30 has a function of giving instructions to the preliminary determination circuit 80, for example.

[0086] The memory 81 has a function of holding imaging data provided from the imaging device 601 to the PU 20. As the memory 81, a memory formed using an OS transistor, which will be described later, may be used.

[0087] The interface 88 has a function of exchanging signals with devices external to the PU 20 .

[0088] The interface 88 has a function of providing an interrupt signal INT provided from the detection circuit 92 to the processor core 30 and the PMU 60 via a bus line 89 .

[0089] The interface 88 also has a function of receiving signals from the processor core 30 etc. via a bus line 89, and based on the received signals, providing a signal OU1 as a control signal to a determination circuit 91. The determination circuit 91 also has a function of providing a signal IN1 as a determination result to the interface 88.

[0090] The circuit 82 includes, for example, an analog-to-digital conversion circuit (hereinafter, referred to as an AD conversion circuit). The circuit 82 may also include a circuit for performing wireless communication. Examples of the circuit for performing wireless communication include a modulation circuit and a demodulation circuit.

[0091] 2 shows an example in which the power supply circuit 10 is provided on a chip different from the PU 20. The power supply circuit 10 has a function of inputting a power supply potential MVDD to the PU 20. A reference clock signal CLK is provided to the clock control circuit 65 from the outside. The clock control circuit 65 has a function of providing clock signals to each circuit of the PU 20. In addition, a return sequence can be executed by inputting a signal INT, which is an interrupt signal requesting interrupt processing, from the outside to the interface 88. The PMU 60 has a function of generating a control signal and providing it to the power supply circuit 10.

[0092] In a semiconductor device according to one embodiment of the present invention, the number of bits that a processing device can handle in an arithmetic circuit or the like can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0093] The clock control circuit 65 has a function of receiving the reference clock signal CLK, generating and outputting a gated clock signal.

[0094] The imaging data captured by the imaging device 601 is, for example, analog data. When the imaging device 601 has an AD conversion circuit, it is preferable that the analog data captured by the imaging device 601 is converted by the AD conversion circuit and then provided to the semiconductor device 700.

[0095] Furthermore, analog data captured by the imaging device 601 may be provided to the semiconductor device 700 without being converted into digital data. In that case, for example, the semiconductor device 700 may perform data conversion using an AD conversion circuit included in the circuit 82.

[0096] Digital data converted by, for example, an AD conversion circuit is provided to the detection circuit 92. Alternatively, the detection circuit 92 may have a function of analyzing analog data.

[0097] Further, digital data converted by, for example, an AD conversion circuit is provided to the preliminary determination circuit 80. Alternatively, the preliminary determination circuit 80 may have a function of analyzing analog data.

[0098] Also, digital data converted by, for example, an AD conversion circuit is provided to the decision circuit 91. Alternatively, the decision circuit 91 may have a function of analyzing analog data.

[0099] <Example of operation of semiconductor device> An operation example of the semiconductor device of one embodiment of the present invention will be described with reference to the flowchart in FIG.

[0100] The process starts in step S000.

[0101] In step S001, imaging data of the imaging device 601 is provided to the detection circuit 92. The imaging data is, for example, a still image or a moving image of the place to be monitored.

[0102] In step S002, the detection circuit 92 analyzes the imaging data. If the detection circuit 92 determines as a result of the analysis that "an event has occurred," the process proceeds to step S003. If the detection circuit 92 determines that "no event has occurred," the process returns to step S001. Here, the occurrence of an event refers to, for example, the detection of a "person," or the occurrence of an even simpler event. Examples of simple events include the aforementioned "detection of subject movement," "detection of a subject," and "significant change in brightness."

[0103] In step S003, a signal INT is sent from the detection circuit 92 to the PU 20, and the PU 20 executes a recovery sequence. After the PU 20 recovers, the imaging data of the imaging device 601, or data obtained by subjecting the imaging data of the imaging device 601 to processing, is sent to the PU 20. The processing applied to the imaging data refers to one or a combination of processes selected from, for example, signal amplification, analog-to-digital conversion of signals, digital-to-analog conversion, signal compression, signal restoration, and the like.

[0104] In step S004, the preliminary determination circuit 80 of the PU 20 analyzes the imaging data. One example of the imaging data analysis is the detection of a "human" by contour extraction using HoG and SVM.

[0105] In step S005, if the preliminary judgment circuit 80 judges that "an event has occurred" as a result of the analysis in step S004, the process proceeds to step S006. If the preliminary judgment circuit 80 judges that "an event has not occurred", the process proceeds to step S009.

[0106] Here, the preliminary determination circuit 80 may determine not only whether an event has occurred but also whether the event that has occurred is abnormal. For example, after detecting a "person" by contour extraction, face recognition of the detected "person" may be performed.

[0107] In step S009, the PU 20 transitions to a sleep state, and then the process returns to step S001.

[0108] In step S006, the imaging data of the imaging device 601 or the data obtained by processing the imaging data of the imaging device 601 is provided to the judgment circuit 91, which analyzes the imaging data. Specifically, for example, feature extraction is performed using CNN to recognize the face of a "human". The recognized face is then compared with a database to determine whether or not the person is a dangerous person. The database is, for example, included in the PU 20 or the judgment circuit 91. Alternatively, the database may be included in an external server. It is preferable that the external server and the PU 20 communicate with each other wirelessly, for example, and data is transferred between the server and the PU 20.

[0109] In step S007, if the determination circuit 91 determines that an abnormal event has occurred as a result of the analysis in step S006, the process proceeds to step S008. If it determines that no abnormal event has occurred, the process proceeds to step S009. The occurrence of an abnormal event here refers to, for example, the detection of an unexpected subject. Alternatively, the occurrence of an abnormal event refers to, for example, the detection of an object, subject, person, etc. that matches or is highly likely to match a pre-registered database. Alternatively, the occurrence of an abnormal event refers to, for example, the detection of an object, subject, person, etc. that is determined to be dangerous. Alternatively, the occurrence of an abnormal event refers to, for example, the determination circuit 91 determining that the face of a recognized "human" is highly likely to match a dangerous person as a result of the analysis of the imaging data.

[0110] In step S008, the semiconductor device 700 provides a signal notifying the terminal 603 of an abnormality. Here, the semiconductor device 700 may provide the terminal 603 with an image of the face of the “human” determined to be highly likely to match a dangerous person, in addition to the signal notifying the abnormality.

[0111] The processor core, memory circuitry and cache are described in more detail below.

[0112] <Processor core 30, memory circuit 31> 4A shows an example of the configuration of the processor core 30. The processor core 30 is a circuit having a function capable of processing instructions, and can be called an arithmetic processing circuit. It has a memory circuit 31 and a plurality of combinational circuits 32, which constitute various functional circuits. For example, the memory circuit 31 is included in a register. In FIG. 4A etc., the input signal of the memory circuit 31 is indicated as signal D, and the output signal of the memory circuit 31 is indicated as signal Q.

[0113] As shown in FIG. 4B, the memory circuit 31 has a circuit MemC1 and a circuit BKC1. The circuit MemC1 has a function of holding data generated by the processor core 30, and can be configured with, for example, a flip-flop circuit (FF), a latch circuit, etc. The circuit BKC1 can function as a backup circuit for the circuit MemC1, and is a circuit capable of holding data for a long period of time even if the power supply is cut off or the clock signal is cut off. By having such a memory circuit 31, it becomes possible to perform power gating of the processor core 30. This is because, by saving the data of the circuit MemC1 to the circuit BKC1 in the memory circuit 31 before cutting off the power supply, the state of the processor core 30 at the time of power cut off can be held. When the power supply is resumed, the data held in the circuit BKC1 is written to the circuit MemC1, so that the processor core 30 can be restored to the state at the time of power cut off. Therefore, after the power supply is resumed, the PU 20 can immediately perform normal processing operations.

[0114] The circuit BKC1 has at least a retention circuit having one transistor (MW1) and one capacitance element (CB1). The retention circuit shown in FIG. 4B has a circuit configuration similar to that of a 1T1C (one transistor, one capacitance element) type memory cell of a standard DRAM (dynamic random access memory), and can perform write and read operations in the same way. The charge and discharge of the capacitance element CB1 are controlled by controlling the conductive state of the transistor MW1. By turning off the transistor MW1, the node FN1 is electrically floating. By making the drain current (off current) of the transistor MW1 in the off state extremely small, the fluctuation of the potential of the node FN1 can be suppressed, and therefore the data retention time of the circuit BKC1 can be extended. The data retention time of the circuit BKC1 is determined by the leakage current of the transistor MW1, the capacitance of the capacitance element CB1, and the like. By making the transistor MW1 a transistor with an extremely small off current, it is not necessary to refresh the circuit BKC1 while the PU20 is operating. Therefore, the circuit BKC1 can be used as a non-volatile memory circuit.

[0115] It is preferable to use a transistor (also referred to as an "OS transistor" or "OS-FET") that contains an oxide semiconductor (OS), which is a type of metal oxide, in a semiconductor layer in which a channel is formed as the transistor MW1. Since an oxide semiconductor has a band gap of 2 eV or more, its off-state current is extremely small. In an OS transistor, the normalized off-state current per 1 μm of channel width when the source-drain voltage is 10 V is 10×10 -21 A (10 zeptoA) or less. By using an OS transistor for the transistor MW1, the circuit BKC1 can be made to function substantially as a nonvolatile memory circuit while the PU20 is in operation.

[0116] The oxide semiconductor film used in the semiconductor layer in which the channel is formed may be formed of a single-layer oxide semiconductor film or a laminated oxide semiconductor film. The oxide semiconductor constituting the semiconductor layer in which the channel is formed is preferably an oxide containing at least one element selected from In, Ga, Sn, and Zn. Examples of such oxides include In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, indium oxide, tin oxide, and zinc oxide.

[0117] In addition, as the oxide semiconductor, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) can be used.

[0118] The circuit BKC1 writes data using voltage, so it can reduce the write power compared to MRAM (Magnetoresistive RAM), which writes data using current. Also, because data is held by the load capacitance of node FN1, there is no limit to the number of times data can be rewritten, as there is with flash memory.

[0119] In the circuit BKC1, the energy required to write data corresponds to the energy associated with charging and discharging electric charge to the capacitive element CB1. On the other hand, in a storage circuit using a two-terminal storage element such as an MRAM, the energy required to write data corresponds to the energy consumed when a current flows through the storage element. In the MRAM, a current continues to flow during the data writing period, so the energy required to write data is high. Compared to such an MRAM, the circuit BKC1 can reduce the energy consumed in writing data. Therefore, compared to a storage circuit in which the backup circuit is configured with an MRAM, the storage circuit 31 has more opportunities to perform voltage scaling and power gating that can reduce the energy consumed, and therefore can reduce the power consumption of the PU 20.

[0120] <Power management> The PMU 60 has a function of controlling a power gating operation, a clock gating operation, a voltage scaling operation, and the like. More specifically, the PMU 60 has a function of controlling the power supply circuit 10, a function of controlling the memory circuit 31, a function of controlling the clock control circuit 65, and a function of controlling the PSW 70. Therefore, the PMU 60 has a function of generating control signals for controlling these circuits (the power supply circuit 10, the memory circuit 31, the clock control circuit 65, and the PSW 70). The PMU 60 has a circuit 61. The circuit 61 has a function of measuring time. The PMU 60 has a function of managing the power supply based on data related to time obtained by the circuit 61.

[0121] The PSW70 has a function of controlling the supply of a power supply potential MVDD to the PU20 in accordance with a control signal from the PMU60. Here, the power supply potential supplied to the PU20 via the PSW70 is referred to as the power supply potential VDD. The processor core 30 may have a plurality of power supply domains. In this case, it is sufficient if the PSW70 can independently control the power supply to the plurality of power supply domains. The processor core 30 may also have a power supply domain for which power gating is not required. In this case, the power supply potential may be supplied to this power supply domain without going through the PSW70.

[0122] The clock control circuit 65 has a function of being able to cut off the clock signal to the processor core 30 in accordance with a control signal from the PMU 60. The power supply circuit 10 has a function of being able to change the magnitude of the power supply potential VDD in accordance with a control signal from the PMU 60.

[0123] The signal SLP output from the processor core 30 to the PMU 60 is a signal that triggers the transition of the processor core 30 to a sleep state. When the signal SLP is input, the PMU 60 generates a control signal for transitioning to a sleep state and outputs it to the functional circuit to be controlled. The power supply circuit 10 lowers the power supply potential MVDD to a level lower than that during normal operation based on the control signal from the PMU 60. When the sleep state has continued for a certain period of time, the PMU 60 controls the PSW 70 to cut off the power supply to the processor core 30. When the processor core 30 transitions from the normal state to the sleep state, the PMU 60 performs a voltage scaling operation to lower the power supply potential VDD of the processor core 30. When the period of the sleep state exceeds a set time, the PMU 60 performs a power gating operation to stop the supply of the power supply potential VDD to the processor core 30 in order to further reduce the power consumption of the processor core 30. Hereinafter, the power management of the semiconductor device shown in FIG. 2 will be described with reference to FIGS. 5 and 6.

[0124] FIG. 5 shows a schematic diagram of a change in the potential of the power line 35. The power line 35 is a wiring to which a power supply potential VDD is supplied via a PSW 70. The horizontal axis of the diagram shows the elapsed time (time) from the normal state to the hibernation state, and t0, t1, etc. show time. The vertical axis of the diagram shows the potential of the power line. FIG. 5A shows an example in which only power gating is performed in the hibernation state, and FIG. 5B shows an example in which only voltage scaling is performed in the hibernation state. FIGS. 5C and 5D show examples in which voltage scaling and power gating are performed. In the normal state, the magnitude of the power supply potential MVDD supplied from the power supply circuit 10 is VH1.

[0125] In the following, the power supply modes of the PU 20 are classified into three modes: a power on mode, a power off mode, and a low power mode. The power on mode is a mode in which a power supply potential VDD that enables normal processing is supplied to the PU 20. The power off mode is a mode in which the supply of the power supply potential VDD is stopped by the PSW 70. The low power mode is a mode in which a power supply potential VDD lower than that of the power on mode is supplied.

[0126] An example of FIG. 5A will be described. At time t0, the processor core 30 starts a process of transitioning to a hibernation state. For example, the memory circuit 31 is backed up. The PMU 60 controls the PSW 70 to cut off the power supply to the processor core 30 at time t1. The power line 35 naturally discharges, and its potential drops to 0V. This allows the leakage current of the processor core 30 in the hibernation state to be significantly reduced, and the power consumption in the hibernation state (hereinafter, sometimes referred to as standby power) can be reduced. When returning to the normal state due to an external interrupt request or the like, the PMU 60 controls the PSW 70 to resume the supply of the power supply potential VDD. Here, the supply of the power supply potential VDD is resumed at time t4. The potential of the power line 35 rises and becomes VH1 at time t6.

[0127] 5B, in order to perform voltage scaling, at time t1, PMU 60 controls power supply circuit 10 and the power supply potential MVDD drops to VH2. The potential of power supply line 35 eventually becomes VH2. At time t4, when power supply potential MVDD returns from VH2 to VH1, the potential of power supply line 35 rises and becomes VH1 at time t5.

[0128] In the example of Fig. 5A, the time required to return from the hibernation state to the normal state (overhead time) is the time required for the potential of the power line 35 to rise from 0V to VH1, and the energy overhead required for return is the energy required to charge the load capacitance of the power line 35 from 0V to VH1. If the period (t1-t4) of the power-off mode is sufficiently long, power gating is effective in reducing the standby power of the PU 20. On the other hand, if the period (t1-t4) is short, the power required to return to the normal state becomes greater than the power that can be reduced by cutting off the power supply, and the effect of power gating cannot be obtained.

[0129] In the voltage scaling example shown in FIG. 5B, the potential of the power line 35 is VH2 in the hibernation state, so the reduction in standby power is smaller than that of the power gating example shown in FIG. 5A. On the other hand, in the example shown in FIG. 5B, the fluctuation in the potential of the power line 35 is small, so the time required to return to the normal state is shorter than that of the example shown in FIG. 5A, and the energy required for the return is smaller. Therefore, in the semiconductor device shown in FIG. 2, in order to reduce the standby power of the PU 20 more efficiently, power management that combines power gating and voltage scaling is possible. Examples of power management are shown in FIG. 5C and FIG. 5D.

[0130] As shown in FIG. 5C, first, in the hibernation state, a voltage scaling operation is performed, and the mode transitions from the power-on mode to the low power mode. As in FIG. 5B, at time t1, the PMU 60 controls the power supply circuit 10 to lower the potential of the power supply potential MVDD to VH2, so that the potential of the power line 35 eventually becomes VH2. After a certain period (t1-t3) has elapsed since the transition to the low power mode, the PMU 60 controls the PSW 70 to switch to the power-off mode. The period (t3-t4) is a period during which it is possible to reduce power by cutting off the power supply to the PU 20 by power gating, even if it includes the power consumed to return to the normal state, rather than supplying VH2 to the PU 20.

[0131] For example, the potential VH2 is a power supply potential having a magnitude capable of holding data in the circuit MemC1 of the memory circuit 31, and the potential VH3 is a potential at which the data in the circuit MemC1 is lost. In the PU20 of FIG. 2, the circuit BKC1 is a circuit capable of holding data even during a period when the supply of power is stopped. By saving the data in the memory circuit 31 to the circuit BKC1 during the period (t0-t1), it is possible to lower the VDD to the potential VH3 at which the data in the circuit MemC1 is lost in the low power mode. This allows the standby power of the PU20 to be further reduced.

[0132] The PMU 60 has a function that can return the PU 20 to the normal state based on an interrupt request or the like. The PMU 60 controls the power supply circuit 10 to boost the magnitude of MVDD to VH1, and also controls the PSW 70 to resume the supply of VDD to the PU 20. The power-on mode is in effect from time t4 onwards. At time t6, the potential of the power supply line 35 becomes stable, and the PU 20 becomes able to operate normally from time t6 onwards.

[0133] 5D shows an example in which an interrupt request to return to normal operation occurs before time t3. From time t2 onwards, the power-on mode is active. At time t2, the PMU 60 controls the power supply circuit 10 to change the magnitude of MVDD to the potential VH1 of the power-on mode. At time t3, the potential of the power line 35 rises to VH1.

[0134] 5C and 5D, in the hibernation state, the time required to return the potential of the power line 35 to VH1 is longer when returning from the power off mode to the power on mode than when returning from the low power mode to the power on mode. Therefore, the PMU 60 has a function that can adjust the timing of the operation of returning the processor core 30 from the hibernation state to the normal state according to the power mode. This makes it possible to return the processor core 30 from the hibernation state to the normal state in the shortest time.

[0135] In addition, in the hibernation state, the transition from the low power mode to the power off mode can be made by measuring time with a circuit 61 provided in the PMU 60. When a signal SLP is input from the PU 20, the PMU 60 starts measuring time with the circuit 61. When a predetermined time has elapsed since the low power mode was entered, the PMU 60 transitions to the power off mode. The PSW 70 is turned off by a control signal from the PMU 60, and the supply of VDD is cut off. In this way, it is possible to transition from the low power mode to the power off mode by an interrupt request based on the measurement data of the circuit 61. An example of the power management operation of the PMU 60 will be described below with reference to FIG. 6.

[0136] The PU 20 is performing a normal operation. The power supply mode is the power-on mode, and the PMU 60 is in an idle state (step S10). The PMU 60 is in the idle state until the signal SLP is input, and executes a save sequence triggered by the input of the signal SLP (step S11). In the example of the save sequence in FIG. 6, first, the PMU 60 outputs a control signal to the clock control circuit 65 to stop the output of the clock signal (step S12). Next, the PMU 60 outputs a control signal for saving data to the memory circuit 31 (step S13). In the memory circuit 31, the data held in the circuit MemC1 is saved to the circuit BKC1 according to the control signal of the PMU 60. Finally, the PMU 60 controls the power supply circuit 10 to reduce MVDD. These operations cause the power supply mode to transition to a low power supply mode (step S14). When the signal SLP is input, the PMU 60 controls the built-in circuit 61 to measure the time Ta of the low power supply mode (step S15). The timing for operating the circuit 61 can be any timing while the save sequence is being executed, such as when the signal SLP is input, when a control signal is output to the clock control circuit 65, when data save is started, when data save is completed, when a control signal is output to the power supply circuit 10, etc.

[0137] After the execution of the save sequence, the PMU 60 goes into an idle state (step S16) and monitors the input of the signal INT and the time Ta, which is the measurement time of the clock control circuit 65. When the signal INT is input, the process proceeds to a restore sequence (step S17). VS The PMU 60 determines whether the time Ta exceeds the time T VS If the time T exceeds the time T, the power supply mode is switched to the power off mode (step S19), and if the time T does not exceed the time T, the idle state is maintained (step S16). VS The time may be set so that the standby power consumption of the processor core 30 can be reduced more by putting the processor core 30 in the power off mode than by putting the processor core 30 in the low power mode.

[0138] In step S19, the PMU 60 outputs a control signal to the PSW 70 to cut off the power supply to the processor core 30. After entering the power-off mode, the PMU 60 again enters the idle state (step S20) and monitors the input of the signal INT (step S21). When the signal INT is input, the PMU 60 executes a recovery sequence.

[0139] In the recovery sequence, first, the PMU 60 transitions from the power off mode to the power on mode (step S22). The PMU 60 controls the power supply circuit 10 to output a power supply potential for normal operation. The PMU 60 also controls the PSW 70 to resume the supply of VDD to the processor core 30. Next, a control signal is output to the memory circuit 31 to restore the data in the memory circuit 31 (step S23). In response to the control signal from the PMU 60, the memory circuit 31 writes back the data held in the circuit BKC1 to the circuit MemC1. The PMU 60 outputs a control signal to the clock control circuit 65 to output a clock signal (step S24). In response to the control signal from the PMU 60, the clock control circuit 65 resumes outputting the clock signal.

[0140] When the return sequence is executed from the determination process of step S17, the mode is returned from the low power mode to the power on mode, and the potential of the power line 35 can be stabilized more quickly than when the return sequence is executed from the determination process of step S21. Therefore, in the PMU 60, when transitioning from step S17 to the return sequence, the timing of executing step S23 is made earlier than when transitioning from step S21 to the return sequence. This makes it possible to shorten the time required for the processor core 30 to return from the sleep state to the normal state.

[0141] 2, when the PU 20 enters a hibernation state, first, a voltage scaling operation is performed to lower the power supply potential supplied to the processor core 30, thereby reducing leakage current and suppressing the time and energy overhead of the process of returning from the hibernation state to the normal state. If the hibernation state continues for a certain period of time, a power gating operation is performed to suppress the leakage current of the processor core 30 as much as possible. This makes it possible to reduce the power consumption of the PU 20 in the hibernation state without reducing the processing capacity of the PU 20.

[0142] The processing unit (PU) 20 may also have a cache 40 and a power switch (PSW) 71. The cache 40 is capable of power gating and voltage scaling, and the power mode of the cache 40 changes in conjunction with the power mode of the PU 20. The PSW 71 is a circuit that controls the supply of a power supply potential MVDD to the cache 40, and is controlled by the PMU 60. Here, the power supply potential input to the cache 40 via the PSW 71 is set to VDD_M. Similar to the processor core 30, a control signal from the PMU 60 and a gated clock signal from the clock control circuit 65 are input to the cache 40.

[0143] <Cache 40> The cache 40 is a storage device having a function of temporarily storing frequently used data. The cache 40 shown in FIG. 7A has a memory array 41, a peripheral circuit 42, and a control circuit 43. The memory array 41 has a plurality of memory cells 45. The control circuit 43 controls the operation of the cache 40 according to a request from the processor core 30. For example, it controls the write operation and read operation of the memory array 41. The peripheral circuit 42 has a function of generating a signal to drive the memory array 41 according to a control signal from the control circuit 43. The memory array 41 has memory cells 45 that hold data.

[0144] As shown in FIG. 7B, the memory cell 45 has a circuit MemC2 and a circuit BKC2. The circuit MemC2 is a memory cell that is accessed in normal operation. For example, a memory cell of an SRAM (static random access memory) may be applied. The circuit BKC2 can function as a backup circuit for the circuit MemC2, and is a circuit that can hold data for a long period of time even if the power supply is cut off or the clock signal is cut off. By providing such a memory cell 45, it is possible to perform power gating of the cache 40. Before cutting off the power supply, the memory cell 45 saves data of the circuit MemC2 to BKC2. After the power supply is resumed, the data held in the circuit BKC2 is written back to the circuit MemC2, so that the PU 20 can be quickly restored to the state before the power supply was cut off.

[0145] Like the circuit BKC1, the circuit BKC2 of the memory cell 45 also has at least a retention circuit having one transistor (MW2) and one capacitance element (CB2). That is, the circuit BKC2 also has a retention circuit with a configuration similar to that of a 1T1C memory cell of a standard DRAM. The transistor MW2 has an extremely small off-state current. An OS transistor may be used for the transistor MW2, like the transistor MW1. With this configuration, the circuit BKC2 can also suppress the fluctuation of the potential of the node FN2, which is in an electrically floating state, so that the circuit BKC2 can retain data for a long period of time. The data retention time of the circuit BKC2 is determined by the leakage current of the transistor MW2, the capacitance of the capacitance element CB2, and the like. By making the transistor MW2 a transistor with an extremely small off-state current, the circuit BKC2 can be used as a nonvolatile memory circuit that does not require a refresh operation.

[0146] 6, data is saved from the memory circuit 31 and the cache 40. In step S19, the PSW70 and PSW71 are controlled to stop the power supply to the processor core 30 and the cache 40. In step S22, the PSW70 and PSW71 are controlled to resume the power supply to the processor core 30 and the cache 40. In step S23, data is restored from the memory circuit 31 and the cache 40.

[0147] <<Processor core configuration example>> An example of the configuration of a processor core is shown in Fig. 8. The processor core 130 shown in Fig. 8 has a control device 131, a program counter 132, a pipeline register 133, a pipeline register 134, a register file 135, an arithmetic logic unit (ALU) 136, and a data bus 137. Data is exchanged between the processor core 130 and peripheral circuits such as a PMU and a cache via the data bus 137.

[0148] The control device 131 has a function of decoding and executing instructions included in a program such as an input application by comprehensively controlling the operations of the program counter 132, pipeline register 133, pipeline register 134, register file 135, ALU 136, and data bus 137. The ALU 136 has a function of performing various arithmetic processing such as arithmetic operations and logical operations. The program counter 132 is a register that has a function of storing the address of the next instruction to be executed.

[0149] The pipeline register 133 is a register having a function of temporarily storing instruction data. The register file 135 has a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of the arithmetic processing of the ALU 136, etc. The pipeline register 134 is a register having a function of temporarily storing data used in the arithmetic processing of the ALU 136, data obtained by the arithmetic processing of the ALU 136, etc.

[0150] The storage circuit 31 in FIG. 4B is used for a register included in the processor core 130.

[0151] <Example of memory circuit configuration> A more specific configuration example of the memory circuit 31 shown in Fig. 4B will be described. Fig. 9 is a circuit diagram showing an example of the configuration of the memory circuit. The memory circuit 100 shown in Fig. 9 functions as a flip-flop circuit. In Fig. 9, an input signal of the memory circuit 100 is denoted as a signal D, and an output signal of the memory circuit 100 is denoted as a signal Q.

[0152] A standard flip-flop circuit (FF) can be applied to the circuit MemC1, for example, a master-slave type FF can be applied. An example of such a configuration is shown in FIG. 9. The FF 110 has transmission gates (TG1, TG2, TG3, TG4, TG5), inverter circuits (INV1, INV2, INV3, INV4), and NAND circuits (NAND1, NAND2). The signal RESET and the signal OSR are control signals output from the PMU 60. The signal OSR and its inverted signal are input to TG5. The clock signal CLK and its inverted signal are input to TG1-TG4. A clocked inverter circuit may be provided instead of TG1 and INV1. A clocked NAND circuit may be provided instead of TG2 and NAND2. A clocked inverter circuit may be provided instead of TG3 and INV3. TG5 functions as a switch that controls the conduction state between the output node of NAND1 and the node NR1. The node NB1 is electrically connected to an input node of the circuit BKC10, and the node NR1 is electrically connected to an output node of the circuit BKC10.

[0153] 9 functions as a backup circuit for FF110. The circuit BKC10 includes a circuit RTC10 and a circuit PCC10. Signals (OSG, OSC, OSR) input to the circuit BKC10 are control signals output from the PMU60. The power supply potential VSS is a low power supply potential, and may be, for example, a ground potential (GND) or 0V. The power supply potential VSS and the power supply potential VDD are input to the FF110 as in the case of BKC10. In the memory circuit 100, the supply of VDD is managed by the PMU60.

[0154] The circuit RTC10 includes a transistor MW1, a transistor MA1, a transistor MR1, a capacitance element CB1, a node FN1, and a node NK1. The circuit RTC10 has a function of retaining data, and is configured here as a memory circuit with a 3T-type gain cell structure. The transistor MW1 is a write transistor and an OS transistor. The transistor MR1 is a read transistor, and the transistor MA1 is an amplifying transistor and a read transistor. The data is retained at the node FN1. The node NK1 is a data input node. The node NR1 is a data output node of the circuit RTC10.

[0155] FIG. 9 shows an example of a configuration in which the circuit BKC10 reads data from the slave latch circuit of FF110 in a save operation, and writes the held data back to the master latch circuit in a restore operation. The data to be saved may be data from the master latch circuit. The data may also be restored to the slave latch circuit. In this case, TG5 may be provided in the slave latch circuit.

[0156] In addition, the transistors MR1 ​​and MA1 of the circuit RTC10 may be either n-type or p-type, and the potential of the signal OSR and the level of the power supply potential supplied to the transistor MA1 may be changed depending on the conductivity type of the transistors MR1 ​​and MA1. In addition, the logic circuit of the FF110 may be set appropriately. For example, if the transistors MR1 ​​and MA1 are p-type transistors, NAND1 and INV3 may be swapped in the master latch circuit, and INV2 and NAND2 may be swapped in the slave latch circuit. In addition, VDD may be input to the transistor MA1 instead of VSS.

[0157] The circuit BKC10 writes data using voltage, so it can reduce the write power compared to MRAM, which writes data using current. Also, since data is held by the load capacitance of the node FN1, there is no limit to the number of times data can be rewritten, as there is in flash memory.

[0158] In the circuit RTC10, the energy required to write data corresponds to the energy associated with charging and discharging electric charge to the capacitive element CB1. On the other hand, in a memory circuit using a two-terminal memory element such as MRAM, the energy required to write data corresponds to the energy consumed when a current flows through the memory element. Therefore, the circuit BKC10 can reduce the energy consumed by saving data compared to the case of using MRAM or the like in which a current continues to flow during the data writing period. Therefore, by providing the circuit BKC10 in the backup circuit, it is possible to shorten the BET (Break Even Time) compared to the case of providing MRAM. As a result, the opportunities for power gating that can reduce the consumed energy increase, and the power consumption of the semiconductor device can be reduced.

[0159] The circuit PCC10 includes a transistor MC1 and a transistor MC2. The circuit PCC10 has a function of precharging the node FN1. The circuit PCC10 does not necessarily have to be provided. As will be described later, by providing the circuit PCC10, the data save time of the circuit BKC10 can be shortened.

[0160] <Memory circuit operation example> FIG. 10 is a timing chart showing an example of the operation of the memory circuit 100, and shows the waveforms of the control signals (signal SLP, signal RESET, clock signal CLK, signal OSG, signal OSC, and signal OSR) and changes in the power supply potential VDD and the potentials of node FN1 and node NR1.

[0161] [Normal operation] A normal operation period will be described. A power supply potential VDD and a signal CLK are supplied to the memory circuit 100. The FF110 functions as a sequential circuit. Since the signal RESET is maintained at a high level, the NAND1 and NAND2 function as inverter circuits. In the circuit BKC1, the transistor MC1 is in an off state, and the transistors MC2 and MW1 are in an on state, so that the potential of the node FN1 is precharged to a high level.

[0162] [Data evacuation] Next, the backup period will be described. First, the clock signal CLK is stopped. This stops rewriting the data at the node NB1. In the example of FIG. 10, the potential level of the node NB1 is low ("0") when the potential of the node NR1 is high ("1"), and is high ("1") when the potential is low ("0"). During the period when the signal OSC is high, the data at the node NB1 is saved to the node FN1. Specifically, since the transistors MC1 and MW1 are on, the nodes FN1 and NB1 are electrically connected. By setting the signal OSG to low and turning the transistor MW1 off, the node FN1 is electrically floating, and the circuit BKC10 is in a data holding state. The potential of the node FN1 is high when the node NR1 is low ("0"), and is low when the node NR1 is high ("1").

[0163] The data evacuation ends when the signal OSG is set to low level, so the voltage scaling operation of the PU20 can be performed immediately after the signal OSG is set to low level. Also, because the node FN1 is precharged to high level by the transistor MC2 during normal operation, the data evacuation operation that sets the node FN1 to high level does not involve the movement of charge at the node FN1. This allows the circuit BKC10 to complete the evacuation operation in a short time.

[0164] In the data save operation, it is sufficient that the clock signal CLK is inactive. In the example of FIG. 10, the potential of the clock signal CLK is set to a low level, but it may also be set to a high level.

[0165] [Voltage scaling, low power mode] Next, the low power period will be described. In conjunction with the falling edge of the signal OSC, the PMU 60 performs a voltage scaling operation. This causes the memory circuit 100 to transition to a low power mode.

[0166] [Power gating, power off mode] Next, the power off period will be described. When a certain period of time has elapsed since the transition to the low power mode, the PMU 60 performs a power gating operation to put the memory circuit 100 into the power off mode.

[0167] [Power on mode] Next, the power-on period will be described. In response to an interrupt request, the PMU 60 returns the memory circuit 100 to the power-on mode. In the example of Fig. 10, when the potential of the power line supplying VDD becomes stable, the clock signal CLK becomes high level.

[0168] [Data recovery] A data recovery operation is performed while the signal OSR is at a high level. By setting the signal RESET to a high level, the potential of the node NR1 is precharged to a high level ("1"). By setting the signal OSR to a high level, TG5 is set to a high impedance state and the transistor MR1 is set to a conductive state. The conductive state of the transistor MA1 is determined by the potential of the node FN1. If the node FN1 is at a high level, the transistor MA1 is in a conductive state, so that the potential of the node NR1 drops to a low level ("0"). If the node FN1 is at a low level, the potential of the node NR1 is maintained at a high level. In other words, the state of FF110 is restored to the state before the transition to the hibernation state.

[0169] As described above, the rising edges of the signals RESET and OSR allow high-level data to be written back (Restored) to the node NR1, thereby enabling the storage circuit 100 to shorten the restoration operation period.

[0170] FIG. 10 shows an example of returning from power off mode to power on mode. When returning from low power mode to power on mode, the period Ton until the potential of the power line supplying VDD becomes stable is shorter. In this case, it is better to make the signal OSR rise earlier than when returning from power off mode. In FIG. 10, the period from after the start of the backup period to before the start of the next normal operation period is described as the sleep period.

[0171] [Normal operation] Next, the normal operation period will be described. By resuming the supply of the clock signal CLK, the normal operation is resumed. By setting the signal OSG to high level, the node FN1 is precharged by the circuit PCC10 and becomes high level.

[0172] <<Cache>> An example in which the cache 40 is configured using an SRAM will be described below.

[0173] <Memory cell configuration example> An example of the configuration of a cache memory cell is shown in FIG. 11. The memory cell 120 shown in FIG. 11 has a circuit SMC20 and a circuit BKC20. The circuit SMC20 may have a circuit configuration similar to that of a standard SRAM memory cell. The circuit SMC20 shown in FIG. 11 has an inverter circuit INV11, an inverter circuit INV12, a transistor M11, and a transistor M12.

[0174] The circuit BKC20 functions as a backup circuit for the circuit SMC20. The circuit BKC20 has a transistor MW11, a transistor MW12, a capacitance element CB11, and a capacitance element CB12. The transistors MW11 and MW12 are OS transistors. The circuit BKC20 has two 1T1C type holding circuits, and data is held at nodes SN1 and SN2, respectively. The holding circuit made up of the transistor MW11 and the capacitance element CB11 has a function of backing up data at node NET1. The holding circuit made up of the transistor MW12 and the capacitance element CB12 has a function of backing up data at node NET2.

[0175] The memory cell 120 is supplied with power supply potentials VDDMC and VSS. The memory cell 120 is electrically connected to wirings (WL, BL, BLB, BRL). A signal SLC is input to the wiring WL. When writing data, a data signal D and a data signal DB are input to the wiring BL and wiring BLB, respectively. Data is read by detecting the potentials of the wirings BL and BLB. A signal OSS is input to the wiring BRL. The signal OSS is a signal input from the PMU 60.

[0176] <Memory cell operation example> A description will now be given of an example of the operation of the memory cell 120. FIG.

[0177] [Normal operation] An access request is made to the circuit MemC2, and data is written to or read from the circuit. In the circuit BKC2, the signal OSS is at a low level, so that the nodes SN1 and SN2 are in an electrically floating state and are in a data holding state. In the example of FIG. 12, the potential of the node SN1 is at a low level ("0"), and the potential of the other node, the node SN2, is at a high level ("1").

[0178] [Data evacuation] When the signal OSS goes high, the transistors MW11 and MW12 are turned on, and the nodes SN1 and SN2 are at the same potential levels as the nodes NET1 and NET2, respectively. In the example of Fig. 12, the potentials of the nodes SN1 and SN2 are high and low, respectively. The signal OSS goes low, the circuit BKC20 goes into a data holding state, and the data save operation ends.

[0179] [Voltage scaling, low power mode] In conjunction with the falling edge of the signal OSS, the PMU 60 performs a voltage scaling operation, which causes the cache 40 to transition to a low power mode.

[0180] [Power gating, power off mode] When a certain period of time has elapsed since the transition to the low power mode, the PMU 60 performs a power gating operation and puts the cache 40 into the power off mode.

[0181] [Data recovery, power on mode] In response to the interrupt request, the PMU 60 restores the cache 40 to the normal state. The signal OSS is set to high level, and the data held in the circuit BKC 20 is written back to the circuit SMC 20. During the period when the signal OSS is at high level, the PMU 60 performs a voltage scaling operation and a power gating operation, and restores the memory circuit 100 to the power-on mode. In the example of FIG. 10, when the potential of the power line supplying VDD becomes stable, the clock signal CLK becomes high level. When the potential of the power line supplying VDDMC becomes stable, the signal OSS is returned to low level, and the data restoration operation is terminated. The states of the nodes SN1 and SN2 are restored to the state immediately before the hibernation state. In FIG. 12, the period from the start of the backup period to the start of the next normal operation period is described as the sleep period.

[0182] [Normal operation] When the supply of VDDMC is resumed, the circuit SMC20 returns to the normal mode in which normal operation is possible.

[0183] As described above, by using OS transistors, a backup circuit capable of retaining data for a long period of time even when the power supply is cut off can be configured. Providing this backup circuit enables power gating of the processor core and cache. In addition, by performing power management in hibernation that combines voltage scaling and power gating, it is possible to reduce the energy and time overhead required for the process of returning from the hibernation state to the normal state. Therefore, it is possible to efficiently reduce power without reducing the processing capacity of the processing device.

[0184] <Example of memory> Below, a memory including an OS transistor of one embodiment of the present invention will be described.

[0185] The power storage device of one embodiment of the present invention preferably includes a memory. A memory device including an OS transistor can be used as the memory. For example, NOSRAM (registered trademark), DOSRAM (registered trademark), or the like described below can be used.

[0186] NOSRAM is a gain cell type DRAM in which the write transistor of the memory cell is composed of an OS transistor. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. An example of the configuration of NOSRAM is shown below.

[0187] 13A is a block diagram showing an example of the configuration of a NOSRAM. The NOSRAM 220 is provided with power domains 212 and 213, and power switches 215 to 217. The power domain 212 is provided with a memory cell array 230, and the power domain 213 is provided with peripheral circuits for the NOSRAM 220. The peripheral circuits include a control circuit 231, a row circuit 232, and a column circuit 233.

[0188] A voltage VDDD, a voltage VSSS, a voltage VDHW, a voltage VDHR, a voltage VBG2, a clock signal GCLK2, an address signal Address, and signals CE, WE, and PSE5 are input to the NOSRAM 220 from the outside. The signals CE and WE are a chip enable signal and a write enable signal. The signal PSE5 controls the on / off of the power switches 215 to 217. The power switches 215 to 217 control the input of the voltages VDDD, VDHW, and VDHR to the power domain 213, respectively.

[0189] The voltages, signals, and the like input to the NOSRAM 220 are appropriately selected according to the circuit configuration and operation method of the NOSRAM 220. For example, a power domain that is not power-gated may be provided in the NOSRAM 220, and a power gating control circuit that generates the signal PSE5 may be provided.

[0190] The memory cell array 230 includes memory cells 11, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and a source line SL.

[0191] As shown in FIG. 13B, the memory cell 11 is a 2T1C (two transistors, one capacitor) type gain cell, and includes a node SN1, transistors M1 and M2, and a capacitor C1. The transistor M1 is a write transistor and is an OS transistor having a backgate. The backgate of the transistor M1 is electrically connected to a wiring BGL2 that supplies a voltage VBG2. The transistor M2 is a read transistor and is a p-channel type Si transistor. The capacitor C1 is a storage capacitor that holds the voltage of the node SN1.

[0192] The voltages VDDD and VSSS are voltages that represent data "1" and "0." The high-level voltages of the write word line WWL and the read word line RWL are voltages VDHW and VHDR.

[0193] Fig. 14A shows a configuration example of a memory cell array 230. In the memory cell array 230 shown in Fig. 14A, one source line is supplied to two adjacent rows.

[0194] In principle, the memory cell 11 has no limit to the number of times it can be rewritten, data can be rewritten with low energy, and no power is consumed to retain data. Since the transistor M1 is an OS transistor with an extremely small off-state current, the memory cell 11 can retain data for a long time.

[0195] The circuit configuration of the memory cell 11 is not limited to the circuit configuration of FIG. 13B. For example, the read transistor M2 may be an OS transistor having a back gate or an n-channel type Si transistor. Alternatively, the memory cell 11 may be a 3T type gain cell. For example, an example of a 3T type gain cell is shown in FIG. 14B and FIG. 14C. The memory cell 15 shown in FIG. 14B has transistors M3 to M5, a capacitance element C3, and a node SN3. The transistors M3 to M5 are a write transistor, a read transistor, and a selection transistor. The transistor M3 is an OS transistor having a back gate, and the transistors M4 and M5 are p-channel type Si transistors. The transistors M4 and M5 may be configured as n-channel type Si transistors or OS transistors having a back gate. In the memory cell 16 shown in FIG. 14C, the three transistors are configured as OS transistors having a back gate.

[0196] The node SN3 is a holding node. The capacitance element C3 is a holding capacitance for holding the voltage of the node SN3. The capacitance element C3 may not be provided intentionally, and the holding capacitance may be formed by the gate capacitance of the transistor M4 or the like. The wiring PDL is a wiring in place of the source line SL, and a fixed voltage, for example, the voltage VDDD, is input to the wiring PDL.

[0197] The control circuit 231 has a function of controlling the overall operation of the NOSRAM 220. For example, the control circuit 231 performs a logical operation on the signals CE and WE to determine whether an external access is a write access or a read access.

[0198] The row circuit 232 has a function of selecting a write word line WWL and a read word line RWL of a selected row specified by an address signal, and the column circuit 233 has a function of writing data to a write bit line WBL of a column specified by an address signal, and a function of reading data from a read bit line RBL of the column.

[0199] DOSRAM is a RAM having 1T1C type memory cells, and is an abbreviation for Dynamic Oxide Semiconductor RAM. DOSRAM will be described below with reference to FIG.

[0200] As shown in FIG. 15A, the memory cell 16 of the DOSRAM 341 is electrically connected to a bit line BL1 (or BLB1), a word line WL1, and wirings BGL6 and PL. The bit line BLB1 is an inverted bit line. For example, voltages VBG6 and VSSS are input to the wirings BGL6 and PL. The memory cell 16 includes a transistor M6 and a capacitance element C6. The transistor M6 is an OS transistor having a back gate.

[0201] Since data is rewritten by charging and discharging the capacitive element C6, the DOSRAM 341 has no restriction on the number of rewrites in principle, and data can be written and read with low energy. In addition, since the circuit configuration of the memory cell 16 is simple, it is easy to increase the capacity. Since the write transistor of the memory cell 16 is an OS transistor, the retention time of the DOSRAM 341 is much longer than that of a DRAM. Therefore, the frequency of refresh can be reduced, or the refresh operation can be made unnecessary, thereby reducing the power required for the refresh operation.

[0202] 15B, in the DOSRAM 341, the memory cell array 361 can be stacked on the peripheral circuit 365. This is because the transistor M6 of the memory cell 16 is an OS transistor.

[0203] In the memory cell array 361, a plurality of memory cells 16 are arranged in a matrix, and bit lines BL1, BLB1, word line WL1, wirings BGL6, and PL are provided according to the arrangement of the memory cells 16. In the peripheral circuit 365, a control circuit, a row circuit, and a column circuit are provided. The row circuit performs operations such as selecting a word line WL to be accessed. The column circuit performs operations such as writing and reading data to and from a bit line pair consisting of BL and BLB.

[0204] Power switches 371 and 373 are provided to power gate the peripheral circuit 365. The power switches 371 and 373 respectively control the input of voltages VDDD and VDHW6 to the peripheral circuit 365. The voltage VDHW6 is a high-level voltage of the word line WL1. The on / off of the power switches 371 and 373 is controlled by a signal PSE6.

[0205] <An example of an arithmetic circuit> Next, a configuration example of a semiconductor device that can be used for the calculation of a neural network will be described.

[0206] As shown in FIG. 16A, the neural network NN can be configured with an input layer ILy, an output layer OLy, and an intermediate layer (hidden layer) HLy. The input layer ILy, the output layer OLy, and the intermediate layer HLy each have one or more neurons (units). The intermediate layer HLy may be one layer or two or more layers. A neural network having two or more intermediate layers HLy can be called a DNN (deep neural network), and learning using a deep neural network can be called deep learning.

[0207] Input data is input to each neuron in the input layer ILy, an output signal of a neuron in the previous or next layer is input to each neuron in the hidden layer HLy, and an output signal of a neuron in the previous layer is input to each neuron in the output layer OLy. Each neuron may be connected to all neurons in the previous or next layer (full connection), or may be connected to only a part of the neurons.

[0208] FIG. 16B shows an example of a computation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N receives output x1 from a neuron in the previous layer and output x2 from a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of output x1 and weight w1 and the multiplication result (x2w2) of output x2 and weight w2, and then adds bias b as necessary to obtain value a=x1w1+x2w2+b. Value a is then transformed by activation function h, and output signal y=h(a) is output from neuron N.

[0209] In this way, the calculations performed by neurons include an operation of adding up the product of the output of a neuron in the previous layer and the weight, that is, a product-sum calculation (x1w1+x2w2 above). This product-sum calculation may be performed on software using a program, or it may be performed by hardware. When the product-sum calculation is performed by hardware, a product-sum calculation circuit can be used. As this product-sum calculation circuit, a digital circuit or an analog circuit may be used. When an analog circuit is used for the product-sum calculation circuit, it is possible to reduce the circuit scale of the product-sum calculation circuit, or to reduce the number of memory accesses, thereby improving the processing speed and reducing power consumption.

[0210] The product-sum operation circuit may be formed using transistors including silicon (such as single crystal silicon) in a channel formation region (hereinafter also referred to as Si transistors) or transistors including an oxide semiconductor in a channel formation region (hereinafter also referred to as OS transistors). In particular, OS transistors have an extremely small off-state current and are therefore suitable as transistors that constitute the memory of the product-sum operation circuit. Note that the product-sum operation circuit may be formed using both Si transistors and OS transistors. Hereinafter, a configuration example of a semiconductor device having the function of a product-sum operation circuit will be described.

[0211] 17 shows a configuration example of a semiconductor device MAC having a function of performing neural network calculations. The semiconductor device MAC has a function of performing a product-sum calculation of first data corresponding to the connection strength (weight) between neurons and second data corresponding to input data. The first data and the second data can be analog data or multi-valued digital data (discrete data). The semiconductor device MAC also has a function of converting the data obtained by the product-sum calculation using an activation function.

[0212] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.

[0213] The cell array CA has a plurality of memory cells MC and a plurality of memory cells MCref. FIG. 17 shows a configuration example in which the cell array CA has memory cells MC (MC[1,1] to [m,n]) arranged in m rows and n columns (m and n are integers equal to or greater than 1) and m memory cells MCref (MCref[1] to [m]). The memory cells MC have a function of storing first data. The memory cells MCref also have a function of storing reference data used in a product-sum operation. The reference data can be analog data or multi-valued digital data.

[0214] Memory cell MC[i,j] (i is an integer between 1 and m, and j is an integer between 1 and n) is connected to wiring WL[i], wiring RW[i], wiring WD[j], and wiring BL[j]. Memory cell MCref[i] is connected to wiring WL[i], wiring RW[i], wiring WDref, and wiring BLref. Here, the current flowing between memory cell MC[i,j] and wiring BL[j] is defined as I MC[i,j] and the current flowing between the memory cell MCref[i] and the line BLref is I MCref[i] It is written as follows.

[0215] A specific configuration example of the memory cell MC and the memory cell MCref is shown in Fig. 18. Although Fig. 18 shows memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] as representative examples, similar configurations can be used for other memory cells MC and memory cells MCref. The memory cell MC and the memory cell MCref each have transistors Tr11, Tr12, and a capacitance element C11. Here, a case where the transistors Tr11 and Tr12 are n-channel transistors will be described.

[0216] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and a first electrode of the capacitance element C11, and the other of the source or drain is connected to the wiring WD. One of the source or drain of the transistor Tr12 is connected to the wiring BL, and the other of the source or drain is connected to the wiring VR. The second electrode of the capacitance element C11 is connected to the wiring RW. The wiring VR is a wiring having a function of supplying a predetermined potential. Here, as an example, a case where a low power supply potential (such as a ground potential) is supplied from the wiring VR will be described.

[0217] A node connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is referred to as a node NM. The nodes NM of the memory cells MC[1,1] and MC[2,1] are respectively referred to as nodes NM[1,1] and NM[2,1].

[0218] The memory cell MCref has a similar configuration to the memory cell MC. However, the memory cell MCref is connected to a wiring WDref instead of the wiring WD, and is connected to a wiring BLref instead of the wiring BL. In addition, in the memory cells MCref[1] and [2], the nodes connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitance element C11 are denoted as nodes NMref[1] and [2], respectively.

[0219] The node NM and the node NMref function as the storage nodes of the memory cell MC and the memory cell MCref, respectively. The node NM stores first data, and the node NMref stores reference data. In addition, a current I MC[1,1] , I MC[2,1] In addition, a current I MCref[1] , I MCref[2] flows.

[0220] Since the transistor Tr11 has a function of holding the potential of the node NM or the node NMref, it is preferable that the off-state current of the transistor Tr11 is small. Therefore, it is preferable to use an OS transistor with an extremely small off-state current as the transistor Tr11. This can suppress fluctuations in the potential of the node NM or the node NMref, thereby improving the accuracy of the calculation. In addition, it is possible to reduce the frequency of operations for refreshing the potential of the node NM or the node NMref, thereby reducing power consumption.

[0221] The transistor Tr12 is not particularly limited, and may be, for example, a Si transistor or an OS transistor. When an OS transistor is used as the transistor Tr12, the transistor Tr12 can be manufactured using the same manufacturing equipment as that of the transistor Tr11, thereby reducing manufacturing costs. The transistor Tr12 may be an n-channel type or a p-channel type.

[0222] The current source circuit CS is connected to the wirings BL[1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL[1] to [n] and the wiring BLref. Note that the value of the current supplied to the wirings BL[1] to [n] may be different from the value of the current supplied to the wiring BLref. Here, the current supplied from the current source circuit CS to the wirings BL[1] to [n] is defined as I CThe current supplied from the current source circuit CS to the wiring BLref is I Cref It is written as follows.

[0223] The current mirror circuit CM has wiring IL[1] to [n] and wiring ILref. The wiring IL[1] to [n] are connected to wiring BL[1] to [n], respectively, and the wiring ILref is connected to wiring BLref. Here, the connection points of the wiring IL[1] to [n] and the wiring BL[1] to [n] are represented as nodes NP[1] to [n]. Also, the connection point of the wiring ILref and the wiring BLref is represented as node NPref.

[0224] The current mirror circuit CM generates a current I CM The function of passing this current I CM In FIG. 17, the current I flows from the wiring BLref to the wiring ILref. CM is discharged, and a current I flows from the wirings BL[1] to [n] to the wirings IL[1] to [n]. CM In addition, the current flowing from the current mirror circuit CM to the cell array CA via the wirings BL[1] to [n] is represented as I B The current flowing from the current mirror circuit CM to the cell array CA via the wiring BLref is represented as I Bref It is written as follows.

[0225] The circuit WDD is connected to the wirings WD[1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to the first data stored in the memory cell MC to the wirings WD[1] to [n]. The circuit WDD also has a function of supplying a potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL[1] to [m]. The circuit WLD has a function of supplying a signal for selecting the memory cell MC or the memory cell MCref to which data is written to the wirings WL[1] to [m]. The circuit CLD is connected to the wirings RW[1] to [m]. The circuit CLD has a function of supplying a potential corresponding to the second data to the wirings RW[1] to [m].

[0226] The offset circuit OFST is connected to the wirings BL[1] to [n] and the wirings OL[1] to [n]. The offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL[1] to [n] to the offset circuit OFST and / or the amount of change in the current flowing from the wirings BL[1] to [n] to the offset circuit OFST. The offset circuit OFST also has a function of outputting the detection result to the wirings OL[1] to [n]. Note that the offset circuit OFST may output a current corresponding to the detection result to the wiring OL, or may convert the current corresponding to the detection result into a voltage and output it to the wiring OL. The current flowing between the cell array CA and the offset circuit OFST is expressed as I α These are written as [1] through [n].

[0227] A configuration example of the offset circuit OFST is shown in FIG. 19. The offset circuit OFST shown in FIG. 19 has circuits OC[1] to [n]. Also, the circuits OC[1] to [n] each have a transistor Tr21, a transistor Tr22, a transistor Tr23, a capacitance element C21, and a resistance element R1. The connection relationship of each element is as shown in FIG. 19. Note that a node connected to a first electrode of the capacitance element C21 and a first terminal of the resistance element R1 is a node Na. Also, a node connected to a second electrode of the capacitance element C21, one of the source or drain of the transistor Tr21, and a gate of the transistor Tr22 is a node Nb.

[0228] The wiring VrefL has a function of supplying a potential Vref, the wiring VaL has a function of supplying a potential Va, and the wiring VbL has a function of supplying a potential Vb. The wiring VDDL has a function of supplying a potential VDD, and the wiring VSSL has a function of supplying a potential VSS. Here, a case will be described in which the potential VDD is a high power supply potential and the potential VSS is a low power supply potential. The wiring RST has a function of supplying a potential for controlling the conduction state of the transistor Tr21. A source follower circuit is formed by the transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL.

[0229] Next, an operation example of the circuits OC[1] to [n] will be described. Note that, although an operation example of the circuit OC[1] will be described here as a representative example, the circuits OC[2] to [n] can be operated in the same manner. First, when a first current flows through the wiring BL[1], the potential of the node Na becomes a potential according to the first current and the resistance value of the resistor element R1. At this time, the transistor Tr21 is in an on state, and a potential Va is supplied to the node Nb. After that, the transistor Tr21 is turned off.

[0230] Next, when a second current flows through the wiring BL[1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistor element R1. At this time, the transistor Tr21 is in an off state and the node Nb is in a floating state, so that the potential of the node Nb changes due to capacitive coupling as the potential of the node Na changes. Here, the change in the potential of the node Na is defined as ΔV Na If the capacitance coupling coefficient is 1, the potential of node Nb is Va+ΔV Na Then, the threshold voltage of the transistor Tr22 is V th Then, the potential from the wiring OL[1] is Va+ΔV Na -V th is output, where Va=V th By doing so, the potential ΔV Na can be output.

[0231] Potential ΔV Na is determined according to the change from the first current to the second current, the resistance value of the resistor R1, and the potential Vref. Here, since the resistance value of the resistor R1 and the potential Vref are known, the potential ΔV Na From this, the amount of change in the current flowing through the wiring BL can be obtained.

[0232] A signal corresponding to the amount of current and / or the amount of change in current detected by the offset circuit OFST as described above is input to the activation function circuit ACTV via lines OL[1] to [n].

[0233] The activation function circuit ACTV is connected to the wirings OL[1] to [n] and NIL[1] to [n]. The activation function circuit ACTV has a function of performing calculations to convert the signal input from the offset circuit OFST according to a predefined activation function. For example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used as the activation function. The signal converted by the activation function circuit ACTV is output to the wirings NIL[1] to [n] as output data.

[0234] Using the above semiconductor device MAC, it is possible to perform a multiply-and-accumulate operation on the first data and the second data. An example of the operation of the semiconductor device MAC when performing the multiply-and-accumulate operation will be described below.

[0235] 20 shows a timing chart of an operation example of the semiconductor device MAC. FIG. 20 shows the transition of the potentials of the wiring WL[1], the wiring WL[2], the wiring WD[1], the wiring WDref, the node NM[1,1], the node NM[2,1], the node NMref[1], the node NMref[2], the wiring RW[1], and the wiring RW[2] in FIG. 18, and the current I B [1]-I α [1], and the current I Bref The graph shows the transition of the current I B [1]-I α [1] corresponds to the sum of currents flowing from the wiring BL[1] to the memory cells MC[1,1] and [2,1].

[0236] Note that, here, the operation will be explained focusing on memory cells MC[1,1], [2,1] and memory cells MCref[1], [2] shown in FIG. 18 as representative examples, but other memory cells MC and memory cells MCref can be operated in the same manner.

[0237] First, at time T01-T02, the potential of the wiring WL[1] becomes high level (High), and the potential of the wiring WD[1] becomes V higher than the ground potential (GND). PR -V W[1,1] The potential of the wiring WDref becomes V higher than the ground potential. PR The potential of the wiring RW[1] and the wiring RW[2] becomes the reference potential (REFP). W[1,1] is a potential corresponding to the first data stored in the memory cell MC[1,1]. PR is a potential corresponding to the reference data. As a result, the transistors Tr11 in the memory cells MC[1,1] and MCref[1] are turned on, and the potential of the node NM[2,1] becomes V PR -V W[1,1] , the potential of node NMref[2] is V PR It becomes.

[0238] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],0 can be expressed by the following formula, where k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. th is the threshold voltage of transistor Tr12.

[0239] I MC[1,1],0 =k(V PR -V W[1,1] -V th ) 2 (E1)

[0240] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],0 can be expressed by the following formula:

[0241] I MCref[1],0 =k(V PR -V th ) 2 (E2)

[0242] Next, at time T02-T03, the potential of the line WL[1] becomes low level (Low), which turns off the transistors Tr11 of the memory cells MC[1,1] and MCref[1], and maintains the potentials of the nodes NM[1,1] and NMref[1].

[0243] As described above, it is preferable to use an OS transistor as the transistor Tr11, which can suppress leakage current of the transistor Tr11 and accurately hold the potentials of the nodes NM[1,1] and NMref[1].

[0244] Next, at time T03-T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring WD[1] becomes V higher than the ground potential. PR -V W[2,1]The potential of the wiring WDref becomes V higher than the ground potential. PR The potential V W[2,1] is a potential corresponding to the first data stored in the memory cell MC[2,1]. As a result, the transistors Tr11 in the memory cells MC[2,1] and MCref[2] are turned on, and the potential of the node NM[2,1] becomes V PR -V W[2,1] , the potential of node NMref[2] is V PR It becomes.

[0245] At this time, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],0 can be expressed by the following formula:

[0246] I MC[2,1],0 =k(V PR -V W[2,1] -V th ) 2 (E3)

[0247] In addition, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],0 can be expressed by the following formula:

[0248] I MCref[2],0 =k(V PR -V th ) 2 (E4)

[0249] Next, at time T04-T05, the potential of the line WL[2] becomes low, which turns off the transistors Tr11 of the memory cells MC[2,1] and MCref[2], and maintains the potentials of the nodes NM[2,1] and NMref[2].

[0250] Through the above operations, the first data is stored in the memory cells MC[1,1] and MC[2,1], and the reference data is stored in the memory cells MCref[1] and MCref[2].

[0251] Here, consider the current flowing through the wiring BL[1] and the wiring BLref at time T04-T05. A current is supplied to the wiring BLref from the current source circuit CS. The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current supplied from the current source circuit CS to the wiring BLref is defined as I Cref The current flowing from the wiring BLref to the current mirror circuit CM is I CM,0 Then, the following equation holds:

[0252] I Cref -I CM,0 =I MCref[1],0 +I MCref[2],0 (E5)

[0253] A current is supplied to the wiring BL[1] from the current source circuit CS. The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. A current also flows from the wiring BL[1] to the offset circuit OFST. The current supplied from the current source circuit CS to the wiring BL[1] is referred to as I C,0 , the current flowing from the wiring BL[1] to the offset circuit OFST is I α,0 Then, the following equation holds:

[0254] I C -I CM,0 =I MC[1,1],0 +I MC[2,1],0 +I α,0 (E6)

[0255] Next, at time T05-T06, the potential of the wiring RW[1] becomes V X[1] At this time, the capacitance elements C11 of the memory cells MC[1,1] and MCref[1] are supplied with a potential V X[1] is supplied, and the potential of the gate of the transistor Tr12 rises due to capacitive coupling. X[1] is a potential corresponding to the second data supplied to the memory cell MC[1,1] and the memory cell MCref[1].

[0256] The change in the potential of the gate of transistor Tr12 is calculated by multiplying the change in the potential of the wiring RW by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated from the capacitance of the capacitance element C11, the gate capacitance of transistor Tr12, and the parasitic capacitance. For the sake of convenience, the following description will be given assuming that the change in the potential of the wiring RW and the change in the potential of the gate of transistor Tr12 are the same, that is, the capacitance coupling coefficient is 1. In practice, the potential V X It is sufficient to determine the following.

[0257] A potential V X[1] When the voltages of the nodes NM[1,1] and NMref[1] are V X[1] to rise.

[0258] Here, during the period from time T05 to time T06, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1]. MC[1,1],1 can be expressed by the following formula:

[0259] I MC[1,1],1 =k(V PR -V W[1,1] +V X[1] -V th ) 2 (E7)

[0260] That is, the potential V X[1] By supplying the current ΔI MC[1,1] =I MC[1,1],1 -I MC[1,1],0 Increase.

[0261] In addition, at time T05-T06, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1],1 can be expressed by the following formula:

[0262] I MCref[1],1 =k(V PR +VX[1] -V th ) 2 (E8)

[0263] That is, the potential V X[1] By supplying the current from the wiring BLref to the transistor Tr12 of the memory cell MCref[1], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] is ΔI MCref[1] =I MCref[1],1 -I MCref[1],0 Increase.

[0264] Next, consider the current flowing through the wiring BL[1] and wiring BLref. The wiring BLref is supplied with a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,1 Then, the following equation holds:

[0265] I Cref -I CM,1 =I MCref[1],1 +I MCref[2],1 (E9)

[0266] The wire BL[1] carries the current I C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is defined as I α,1 Then, the following equation holds:

[0267] I C -I CM,1 =I MC[1,1],1 +I MC[2,1],1 +I α,1 (E10)

[0268] Then, from equations (E1) to (E10), the current I α,0 and current I α,1 Difference between the current (ΔI α) can be expressed by the following formula:

[0269] ΔI α =I α,1 -I α,0 =2kV W[1,1] V X[1] (E11)

[0270] Thus, the differential current ΔI α is the potential V W[1,1] and V X[1] The value depends on the product of these.

[0271] After that, during the period from time T06 to time T07, the potential of the wiring RW[1] becomes the reference potential, and the potentials of the nodes NM[1,1] and NMref[1] become the same as those during the period from time T04 to time T05.

[0272] Next, at time T07-T08, the potential of the wiring RW[1] becomes V X[1] The potential of the wiring RW[2] becomes V higher than the reference potential. X[2] As a result, a potential V X[1] is supplied, and the potentials of the nodes NM[1,1] and NMref[1] are V X[1] In addition, a potential V X[2] is supplied, and the potentials of the nodes NM[2,1] and NMref[2] are V X[2] to rise.

[0273] Here, at time T07-T08, a current I flows from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1]. MC[2,1],1 can be expressed by the following formula:

[0274] I MC[2,1],1 =k(V PR -V W[2,1] +V X[2] -V th )2 (E12)

[0275] That is, the potential V X[2] By supplying the current from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1], the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] is ΔI MC[2,1] =I MC[2,1],1 -I MC[2,1],0 Increase.

[0276] In addition, at time T07-T08, a current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2],1 can be expressed by the following formula:

[0277] I MCref[2],1 =k(V PR +V X[2] -V th ) 2 (E13)

[0278] That is, the potential V X[2] By supplying the current from the wiring BLref to the transistor Tr12 of the memory cell MCref[2], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] is ΔI MCref[2] =I MCref[2],1 -I MCref[2],0 Increase.

[0279] Next, consider the current flowing through the wiring BL[1] and wiring BLref. The wiring BLref is supplied with a current I Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and [2]. The current discharged from the wiring BLref to the current mirror circuit CM is I CM,2 Then, the following equation holds:

[0280] I Cref -I CM,2 =I MCref[1],1 +I MCref[2],1 (E14)

[0281] The wire BL[1] carries the current I CThe current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and [2,1]. Furthermore, a current also flows from the wiring BL[1] to the offset circuit OFST. The current flowing from the wiring BL[1] to the offset circuit OFST is defined as I α,2 Then, the following equation holds:

[0282] I C -I CM,2 =I MC[1,1],1 +I MC[2,1],1 +I α,2 (E15)

[0283] From the formulas (E1) to (E8) and the formulas (E12) to (E15), the current I α,0 and current I α,2 Difference between the current (ΔI α ) can be expressed by the following formula:

[0284] ΔI α =I α,2 -I α,0 =2k(V W[1,1] V X[1] +V W[2,1] V X[2] )(E16)

[0285] Thus, the differential current ΔI α is the potential V W[1,1] and potential V X[1] and the potential V W[2,1] and potential V X[2] The value is determined by adding the product of and .

[0286] After that, at times T08-T09, the potentials of the wirings RW[1] and [2] become the reference potential, and the potentials of the nodes NM[1,1] and [2,1] and the nodes NMref[1] and [2] become the same as at times T04-T05.

[0287] As shown in equations (E11) and (E16), the differential current ΔI α is the potential V corresponding to the first data (weight) Wand the potential V corresponding to the second data (input data) X That is, the differential current ΔI α By measuring this with the offset circuit OFST, the result of the multiplication and accumulation operation of the first data and the second data can be obtained.

[0288] In the above, we have focused on memory cells MC[1,1], [2,1] and memory cells MCref[1], [2], but the number of memory cells MC and memory cells MCref can be set arbitrarily. When the number of rows m of memory cells MC and memory cells MCref is set to an arbitrary number i, the differential current ΔIα can be expressed by the following formula.

[0289] ΔI α =2kΣ i V W[i,1] V X[i] (E17)

[0290] Moreover, by increasing the number n of columns of memory cells MC and memory cells MCref, the number of product-sum operations executed in parallel can be increased.

[0291] As described above, by using the semiconductor device MAC, it is possible to perform a product-sum operation on the first data and the second data. Note that by using the configuration shown in FIG. 18 for the memory cells MC and the memory cells MCref, it is possible to configure a product-sum operation circuit with a small number of transistors. Therefore, it is possible to reduce the circuit scale of the semiconductor device MAC.

[0292] When the semiconductor device MAC is used for calculations in a neural network, the number of rows m of the memory cells MC can be made to correspond to the number of input data supplied to one neuron, and the number of columns n of the memory cells MC can be made to correspond to the number of neurons. For example, consider a case where a multiply-and-accumulate operation is performed using the semiconductor device MAC in the hidden layer HLy shown in Fig. 16A. In this case, the number of rows m of the memory cells MC can be set to the number of input data supplied from the input layer ILy (the number of neurons in the input layer ILy), and the number of columns n of the memory cells MC can be set to the number of neurons in the hidden layer HL.

[0293] The structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can be used for a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), etc.

[0294] As described above, by using the semiconductor device MAC, it is possible to perform the product-sum operation of a neural network. Furthermore, by using the memory cell MC and the memory cell MCref shown in FIG. 18 in the cell array CA, it is possible to provide an integrated circuit capable of improving the operation accuracy, reducing the power consumption, or reducing the circuit scale.

[0295] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0296] (Embodiment 2) In this embodiment, an imaging device that can be used in a determination system of one embodiment of the present invention will be described.

[0297] 21A shows a configuration example of an imaging device. Pixel circuits 331 are arranged in a matrix and electrically connected to a driver circuit 332 (Driver) via wiring 351. The driver circuit 332 can control data acquisition and selection operations of the pixel circuits 331. For example, a shift register can be used as the driver circuit 332.

[0298] In addition, the pixel circuit 331 is electrically connected to a readout circuit 311 (RC) via a wiring 352. The readout circuit 311 has a correlated double sampling circuit (CDS circuit) that reduces noise and an A / D converter that converts analog data into digital data.

[0299] The read circuit 311 is electrically connected to, for example, a memory. The memory can hold the digital data output from the read circuit 311.

[0300] The A / D converter in the read circuit 311 outputs binary data of a predetermined number of bits in parallel. Therefore, the A / D converter is connected to memory cells of the number of bits. For example, if the output of the A / D converter is 8 bits, the A / D converter is connected to 8 memory cells.

[0301] <Pixel circuit> 21B is a circuit diagram illustrating an example of a pixel circuit 331. The pixel circuit 331 can include a photoelectric conversion device 240, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitor 108. Note that a structure in which the capacitor 108 is not provided is also possible.

[0302] One electrode (cathode) of the photoelectric conversion device 240 is electrically connected to one of the source or drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one electrode of the capacitor 108. One electrode of the capacitor 108 is electrically connected to the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.

[0303] Here, a wiring that connects the other of the source and the drain of the transistor 103, the other of the source and the drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105 is a node FD. The node FD can function as a charge detection portion.

[0304] The other electrode (anode) of the photoelectric conversion device 240 is electrically connected to a wiring 121. The gate of the transistor 103 is electrically connected to a wiring 127. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 123. The gate of the transistor 104 is electrically connected to a wiring 126. The gate of the transistor 106 is electrically connected to a wiring 128. The other electrode of the capacitor 108 is electrically connected to a reference potential line such as a GND wiring. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 352.

[0305] The wirings 127, 126, and 128 can function as signal lines for controlling the conduction of each transistor. The wiring 352 can function as an output line.

[0306] 21B, the cathode side of the photoelectric conversion device 240 is electrically connected to the transistor 103 and the node FD is reset to a high potential for operation, so the wiring 122 has a high potential (a higher potential than the wiring 121).

[0307] FIG. 21B shows a configuration in which the cathode of the photoelectric conversion device 240 is electrically connected to the node FD, but the anode side of the photoelectric conversion device 240 may be electrically connected to either the source or drain of the transistor 103, as shown in FIG. 21C.

[0308] In this configuration, the node FD is reset to a low potential for operation, so the wiring 122 is set to a low potential (a lower potential than the wiring 121).

[0309] The transistor 103 has a function of controlling the potential of the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as a source follower circuit and can output the potential of the node FD as image data to the wiring 352. The transistor 106 has a function of selecting a pixel to which image data is output.

[0310] It is preferable to use OS transistors as the transistors 103 to 106 in the pixel circuit 331. OS transistors have characteristics of extremely low off-state current. In particular, by using transistors with low off-state current as the transistors 103 and 104, the period during which charge can be held at the node FD can be made extremely long. Therefore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration or operation method.

[0311] <Operation method of imaging device> Fig. 22A is a schematic diagram of the operation method of the rolling shutter method, and Fig. 22B is a schematic diagram of the global shutter method. En represents the exposure (accumulation operation) of the nth column (n is a natural number), and Rn represents the readout operation of the nth column. Figs. 22A and 22B show the operations from the 1st row to the Mth row (M is a natural number).

[0312] The rolling shutter method is an operation method in which exposure and data readout are performed sequentially, overlapping the readout period of one row with the exposure period of another row. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration in which the data retention period is relatively short. However, since one frame of image is composed of data that is not captured simultaneously, distortion occurs in the image when capturing a moving object.

[0313] On the other hand, the global shutter method is a method of operation in which all pixels are exposed simultaneously, data is stored in each pixel, and the data is read out row by row, making it possible to obtain images without distortion even when capturing a moving object.

[0314] When a transistor with a relatively large off-state current, such as a Si transistor, is used in a pixel circuit, a rolling shutter system is often used because charge tends to flow out from a charge detection unit. To realize the global shutter system using a Si transistor, a complex operation must be performed at high speed, such as storing data in a separate memory circuit. On the other hand, when an OS transistor is used in a pixel circuit, the global shutter system can be easily realized because there is almost no flow of data potential from the charge detection unit. Note that the imaging device of one embodiment of the present invention can also be operated using the rolling shutter system.

[0315] Note that the pixel circuit 331 may be configured by combining OS transistors and Si transistors in any desired manner, or all the transistors may be Si transistors.

[0316] <Pixel circuit operation>

[0317] Next, an example of the operation of the pixel circuit shown in Fig. 21B will be described with reference to the timing chart in Fig. 23A. In the description of the timing chart in this specification, a high potential is represented by "H" and a low potential is represented by "L." It is assumed that "L" is constantly supplied to the wiring 121, and "H" is constantly supplied to the wirings 122 and 123.

[0318] In a period T1, when the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistors 103 and 104 are turned on, and the potential of the wiring 122 is supplied to the node FD at "H" (reset operation).

[0319] In period T2, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistor 104 becomes non-conductive and the supply of the reset potential is cut off. Also, the potential of the node FD decreases in response to the operation of the photoelectric conversion device 240 (accumulation operation).

[0320] In the period T3, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "L", the transistor 103 is turned off, and the potential of the node FD is determined and held (holding operation). At this time, by using OS transistors with low off-state current as the transistors 103 and 104 connected to the node FD, unnecessary outflow of charge from the node FD can be suppressed, and the data retention time can be extended.

[0321] In a period T4, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "H", the transistor 106 is turned on, and the potential of the node FD is read to the wiring 352 by the source follower operation of the transistor 105 (read operation).

[0322] The above is an example of the operation of the pixel circuit shown in FIG. 21B.

[0323] The pixel circuit shown in Fig. 21C can be operated according to the timing chart of Fig. 23B. Note that "H" is constantly supplied to the wirings 121 and 123, and "L" is constantly supplied to the wiring 122. The basic operation is the same as that described above with reference to the timing chart of Fig. 23A.

[0324] In one embodiment of the present invention, a transistor may have a back gate as illustrated in Fig. 24A and Fig. 24B. Fig. 24A shows a structure in which the back gate is electrically connected to the front gate, which has the effect of increasing the on-state current. Fig. 24B shows a structure in which the back gate is electrically connected to a wiring that can supply a constant potential, which allows the threshold voltage of the transistor to be controlled.

[0325] 24A and 24B may be combined so that each transistor can operate appropriately. Also, the pixel circuit may have a transistor that is not provided with a back gate.

[0326] <Readout circuit> 25 is a diagram for explaining an example of a readout circuit 311 connected to a pixel circuit 331, and shows a circuit diagram of a CDS circuit 400 and a block diagram of an A / D converter 410 electrically connected to the CDS circuit 400. Note that the CDS circuit and the A / D converter shown in FIG. 25 are merely examples, and other configurations may be used.

[0327] The CDS circuit 400 can have a configuration including a resistor 401 for voltage conversion, a capacitive element 402 for capacitive coupling, a transistor 403 for supplying a potential V0, a ​​transistor 404 for holding a potential to be supplied to an A / D converter 410, and a capacitive element 405 for holding a potential. The CDS circuit 400 has an input electrically connected to the pixel circuit 331 and an output electrically connected to a comparator circuit (COMP) of the A / D converter 410.

[0328] The potential of the wiring 352 is V resWhen the pixel circuit 331 is in a reset state, the potential of the node N (the connection point of the transistors 403 and 404 and the capacitor 402) is set to V0. Then, the node N is set to a floating state, and the potential of the wiring 352 is set to V data When the pixel circuit 331 outputs image data, the potential of the node N becomes V0+V data -V res Therefore, in the CDS circuit 400, it is possible to subtract the potential in the reset state from the potential of the imaging data output by the pixel circuit 331, and it is possible to reduce noise components.

[0329] The A / D converter 410 can be configured to include a comparator circuit (COMP) and a counter circuit (COUNTER). In the A / D converter 410, a signal potential input from the CDS circuit 400 to the comparator circuit (COMP) is compared with a swept reference potential (RAMP). Then, the counter circuit (COUNTER) operates according to the output of the comparator circuit (COMP), and digital signals are output to a plurality of wirings 353.

[0330] [Laminated structure 1] Next, the layered structure of the imaging device will be described with reference to a cross-sectional view.

[0331] FIG. 26A is an example of a cross-sectional view of a stack having layers 502 and 503.

[0332] <layer 502> The layer 502 includes a pixel circuit 331 formed on a silicon substrate. Here, the transistor 103, the transistor 104, the capacitor 108, and the photoelectric conversion device 240 are shown as parts of the pixel circuit 331.

[0333] The photoelectric conversion device 240 is a pn junction type photodiode formed on a silicon substrate, and has a p-type region 243 and an n-type region 244. The photoelectric conversion device 240 is a buried type photodiode, and the p-type region 241 provided on the surface side of the n-type region 244 can suppress dark current and reduce noise. The p-type region 243 may be used as the p-type region 241. It is preferable that the p-type region 241 has a lower resistance than the p-type region 243. It is also preferable that the n-type region 244 has a lower resistance than the p-type region 243. It is also possible to replace the p-type region and the n-type region in the p-type region 243, the p-type region 241, and the n-type region 244.

[0334] The transistor 103 and the transistor 104 are transistors formed on a silicon substrate. The transistor 103 and the transistor 104 each have a conductive layer functioning as a gate, a source and a drain formed on the silicon substrate, a channel formation region located between the source and the drain, and a gate insulating layer provided between the conductive layer functioning as a gate and the channel formation region. Note that in the example shown in FIG. 26A, the source region and the drain region of the transistor 103 and the transistor 104 are formed of n-type regions.

[0335] The layer 502 includes an insulating layer 242 and an insulating layer 245. The insulating layer 242 functions as an element isolation layer. The insulating layer 245 functions to suppress the outflow of carriers.

[0336] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 245 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 245, it is possible to prevent carriers generated in the photoelectric conversion device 240 from flowing out to adjacent pixels. The insulating layer 245 also has a function of suppressing the intrusion of stray light. For example, the insulating layer 245 may have grooves to suppress the intrusion of stray light from adjacent pixels. Therefore, the insulating layer 245 can suppress color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 245.

[0337] The element isolation layer can be formed by using a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like. For example, an inorganic insulating film such as a silicon oxide film or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used as the insulating layer 245. The insulating layer 245 may have a multi-layer structure.

[0338] In the example shown in FIG. 26A, the n-type region 244 (corresponding to the cathode) of the photoelectric conversion device 240 can also function as one of the source or drain of the transistor 103.

[0339] Further, the layer 502 is provided with insulating layers 222, 223, 226, 227, the wiring 121, the electrode 129a, and the electrode 129b. The insulating layer 222 functions as a protective film. The insulating layers 223 and 227 function as an interlayer insulating film and a planarizing film. The electrodes 129a and 129b each function as an electrode of the capacitance element 108. The insulating layer 226 is sandwiched between the electrodes 129a and 129b, and functions as a dielectric layer of the capacitance element 108. The electrode 129a is electrically connected to the other of the source and drain of the transistor 103 through a plug provided in the insulating layer 223. The wiring 121 functions as a power supply line. The p-type region 243 (anode) is electrically connected to the wiring 121.

[0340] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitive element may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film.

[0341] The Si transistor shown in Fig. 26A is a planar type having a channel formation region in a silicon substrate. The Si transistor may be a fin type as shown in Fig. 27A. Fig. 27B shows a cross section (cross section in the channel width direction) taken along line A1-A2 shown in Fig. 27A.

[0342] 27C, it may be a transistor having a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 210.

[0343] The conductor that can be used as wiring, electrodes, and plugs for electrical connection between devices may be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be multiple layers composed of different materials. It may have trontium or the like.

[0344] <layer 503> The layer 503 is formed on the layer 502. The layer 503 includes a light-shielding layer 251, an optical conversion layer 250, and a microlens array 255.

[0345] The light-shielding layer 251 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 251. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0346] A color filter can be used for the optical conversion layer 250. A color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.

[0347] Furthermore, if a wavelength cut filter is used in the optical conversion layer 250, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0348] For example, if a filter that blocks light with wavelengths equal to or shorter than visible light is used in the optical conversion layer 250, it can be used as an infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or shorter than near-infrared light is used in the optical conversion layer 250, it can be used as a far-infrared imaging device. Also, if a filter that blocks light with wavelengths equal to or longer than visible light is used in the optical conversion layer 250, it can be used as an ultraviolet imaging device.

[0349] Furthermore, if a scintillator is used for the optical conversion layer 250, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 240. An imaging device having such a configuration may also be used for a radiation detector or the like.

[0350] Scintillators contain a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., dispersed in resin or ceramics can be used.

[0351] A microlens array 255 is provided on the optical conversion layer 250. Light passing through each lens of the microlens array 255 passes through the optical conversion layer 250 directly below, and is irradiated onto the photoelectric conversion device 240. By providing the microlens array 255, concentrated light can be incident on the photoelectric conversion device 240, so that photoelectric conversion can be performed efficiently. The microlens array 255 is preferably formed of a resin or glass that is highly translucent to visible light.

[0352] Alternatively, OS transistors may be used as the transistors 103 and 104. The stacked structure shown in FIG. 26B includes layers 502 and 503, and the layer 502 includes a layer 562 including an element provided on a Si substrate, and a layer 563 including an OS transistor. The layer 562 shown in FIG. 26B includes a photoelectric conversion device 240 provided on a Si substrate. Although no Si transistor is shown in the layer 562 in FIG. 26B, the layer 562 may include the transistor 105 as shown in FIG. 28A. Although not shown, the layer 562 may include the transistor 106. Alternatively, the transistors 105, 106, and the like may be OS transistors provided in the layer 563.

[0353] Since the off-state current of the OS transistor is extremely small, the charge stored in the capacitor 108 can be held for a long time.

[0354] The OS transistor can be stacked with a Si transistor or a photoelectric conversion device 240 provided on a Si substrate. This allows for circuit integration. Also, the area of ​​the photoelectric conversion device 240 can be increased. The OS transistor will be described in detail with reference to FIG. 29.

[0355] In the configuration shown in FIG. 28B, the layer 502 has a layer 561 in addition to layers 562 and 563. The layer 561 is a configuration example in which a pn junction type photodiode with a selenium-based material as a photoelectric conversion layer is used as the photoelectric conversion device 240. The layer 561 has a layer 566a as one electrode, layers 566b and 566c as photoelectric conversion layers, and a layer 566d as the other electrode. The layer 561 can be formed directly on the layer 563. Note that the connection with the transistor is similar even when an organic photoconductive film is used as the photoelectric conversion device 240 of the layer 561.

[0356] The insulating layer 541 is provided over the transistor 102 and the transistor 103 included in the layer 563. The layer 566a has a region buried in the insulating layer 541.

[0357] 28B shows an example in which a fin-type transistor is used as a Si transistor in a layer 562. In the example shown in FIG.

[0358] The stacked structure of the Si transistor and the OS transistor shown in FIG. 28A and FIG. 28B can also be applied to the configuration of the Si transistor and the OS transistor included in the processing device (PU). For example, a pixel circuit of an imaging device and a semiconductor device including the above-mentioned processing device can be manufactured on the same silicon substrate. Therefore, for example, a pixel circuit and a driving circuit of an imaging device and a semiconductor device included in the determination system of one embodiment of the present invention can be provided on the same chip. For example, by providing the configuration of the determination system of one embodiment of the present invention on one chip, the area of ​​the chip can be reduced. Alternatively, for example, the pixel circuit and the driving circuit of the imaging device and the semiconductor device including the processing device (PU) and the like can be manufactured using the same process, so that the cost required for manufacturing the chip can be reduced. In addition, by providing the configuration of the determination system of one embodiment of the present invention on one chip, for example, the energy required for transferring an image to a memory circuit or a determination circuit included in the semiconductor device can be reduced, and the calculation efficiency can be improved in some cases.

[0359] Fig. 29A shows details of an OS transistor. The OS transistor shown in Fig. 29A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing grooves that reach the semiconductor layer.

[0360] The OS transistor can have a channel formation region, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the groove. An oxide semiconductor layer 707 may be further provided in the groove.

[0361] As shown in FIG. 29B, the OS transistor may have a self-aligned structure in which a source region and a drain region are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0362] Alternatively, as shown in FIG. 29C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0363] Although the transistors 102 and 103 are shown to have a structure having a back gate 535, they may have a structure not having a back gate. The back gate 535 may be electrically connected to the front gate of the transistor provided opposite to it, as shown in the cross-sectional view of the transistor in the channel width direction shown in Fig. 29D. Note that Fig. 29D shows the transistor in Fig. 21A as an example, but the same applies to transistors of other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 535.

[0364] An insulating layer 543 having a function of preventing diffusion of hydrogen is provided between a region where an OS transistor is formed and a region where a Si transistor is formed. Hydrogen in the insulating layer provided near the channel formation regions of the transistors 105 and 106 terminates dangling bonds of silicon. Meanwhile, hydrogen in the insulating layer provided near the channel formation regions of the transistors 102 and 103 is one of factors that generate carriers in the oxide semiconductor layer.

[0365] The insulating layer 543 confines hydrogen in one layer, which can improve the reliability of the transistors 105 and 106. In addition, the insulating layer 543 suppresses diffusion of hydrogen from one layer to the other layer, which can improve the reliability of the transistors 102 and 103.

[0366] The insulating layer 543 can be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0367] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0368] (Embodiment 3) In this embodiment, examples of electronic devices to which a semiconductor device of one embodiment of the present invention is applied will be described.

[0369] FIG. 30A shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on a ceiling to enable imaging of the entire periphery. The camera unit 952 can be used as an imaging device included in the determination system of one embodiment of the present invention. When the camera unit 952 is electrically connected to the semiconductor device of one embodiment of the present invention, a suspicious person can be identified from imaged information. Note that the term "surveillance camera" is a common name and is not intended to limit the use of the camera. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0370] Fig. 30B shows an example of an aircraft. The aircraft 6500 shown in Fig. 30B has a propeller 6501, a camera 6502, a battery 6503, and the like, and has a function of flying autonomously.

[0371] For example, image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of an obstacle when moving. As the camera 6502, imaging devices of multiple types may be used. The camera 6502 can be used as an imaging device included in the determination system of one embodiment of the present invention. Furthermore, when the camera 6502 is electrically connected to the semiconductor device of one embodiment of the present invention, a suspicious person can be identified from captured information.

[0372] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments. [Explanation of symbols]

[0373] :ACTV: activation function circuit, BGL2: wiring, BGL6: wiring, BKC1: circuit, BKC2: circuit, BKC10: circuit, BKC20: circuit, BL: wiring, BLref: wiring, BL1: bit line, BLB: wiring, BLB1: bit line, C1: capacitance element, C3: capacitance element, C6: capacitance element, C11: capacitance element, C21: capacitance element, CA: cell array, CB1: capacitance element, CB2: capacitance element, CB11: capacitance element, CB12: capacitance element, CLD: circuit, CM: current mirror circuit, CS: current source circuit, HLy: hidden layer, IL: wiring, ILref: wiring, ILy: Input layer, INV11: inverter circuit, INV12: inverter circuit, INV2: inverter circuit, INV3: inverter circuit, INV4: inverter circuit, M1: transistor, M11: transistor, M12: transistor, M2: transistor, M3: transistor, M4: transistor, M5: transistor, M6: transistor, MA1: transistor, MAC: semiconductor device, MC: memory cell, MCref: memory cell, MC1: transistor, MC2: transistor, MemC1: circuit, MemC2: circuit, MemC20: circuit, MR1: transistor transistor, MW1: transistor, MW2: transistor, MW11: transistor, MW12: transistor, OFST: offset circuit, OLy: output layer, PCC10: circuit, PDL: wiring, R1: resistive element, RBL: bit line, RTC10: circuit, RWL: word line, SMC20: circuit, Tr11: transistor, Tr12: transistor, WBL: bit line, WD: wiring, WDref: wiring, WL: wiring, WL1: word line, WLD: circuit, WWL: word line, 10: power supply circuit, 11: memory cell, 15: memory cell, 16: memory cell, 20: PU, 30: processor core, 31: memory circuit, 32: circuit, 35: power line, 40: cache, 41: memory array, 42: peripheral circuit, 43: control circuit, 45: memory cell, 60: PMU, 61: circuit, 65: clock control circuit, 70: PSW, 71: PSW, 80: preliminary judgment circuit, 81: memory, 82: circuit, 88: interface, 89: bus line, 91: judgment circuit, 92: detection circuit, 100: memory circuit, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 108: capacitance element,110: FF, 120: memory cell, 121: wiring, 122: wiring, 123: wiring, 126: wiring, 127: wiring, 128: wiring, 129a: electrode, 129b: electrode, 130: processor core, 131: control device, 132: program counter, 133: pipeline register, 134: pipeline register, 135: register file, 136: ALU, 137: data bus, 210: silicon substrate, 212: power domain, 213: power domain, 215: power switch switch, 217: power switch, 220: NOSRAM, 222: insulating layer, 223: insulating layer, 226: insulating layer, 227: insulating layer, 230: memory cell array, 231: control circuit, 232: row circuit, 233: column circuit, 240: photoelectric conversion device, 241: p-type region, 242: insulating layer, 243: p-type region, 244: n-type region, 245: insulating layer, 250: optical conversion layer, 251: light shielding layer, 255: microlens array, 311: circuit, 331: pixel circuit, 332: drive circuit, 341: DO SRAM, 351: wiring, 352: wiring, 353: wiring, 361: memory cell array, 365: peripheral circuit, 371: power switch, 373: power switch, 400: CDS circuit, 401: resistor, 402: capacitance element, 403: transistor, 404: transistor, 405: capacitance element, 410: A / D converter, 502: layer, 503: layer, 535: backgate, 541: insulating layer, 543: insulating layer, 545: semiconductor layer, 546: insulating layer, 561: layer, 562: layer, 563: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 601: imaging device, 602: display device, 603: terminal, 700: semiconductor device, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 951: support, 952: camera unit, 953: protective cover, 6500: flying object, 6501: propeller, 6502: camera, 6503: battery, 6504: electronic component,

Claims

[Claim 1] The power supply control device includes a detection circuit, a first determination circuit, a second determination circuit, a power supply circuit, and a power supply management device. the detection circuit has a function of analyzing first data and making a first determination in which a first value or a second value is selected; the first determination circuit and the second determination circuit have a function of extracting image features; when the first value is selected by the first determination, the power management device has a function of supplying a voltage from the power supply circuit to the first determination circuit; the first determination circuit has a function of analyzing the first data and making a second determination; The second determination circuit has a function of analyzing the first data and making a third determination when an occurrence of an event is detected in the second determination.

Images