Semiconductor device and manufacturing method of the same

Abstract

To provide an advantageous technology that achieves at least one of miniaturization of wiring and high-speed signal transmission in a semiconductor device.SOLUTION: A semiconductor device includes a plurality of interconnections on a semiconductor layer, each having a damascene structure. The plurality of interconnections includes first and second interconnections that are adjacent to each other. The first interconnection has, along a direction in which the first interconnection extends, a first portion, a second portion, and a third portion between the first portion and the second portion. The width of the third portion is greater than the width of the first portion and the width of the second portion.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices, damascene wiring is used to miniaturize wiring. Patent Document 1 discloses that the damascene wiring is formed by connecting and exposing the wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-229749 A Summary of the Invention [Problem to be solved by the invention]

[0004] The technology of Patent Document 1 has a problem that a connection error at a connection part easily causes a break in the wiring or a short circuit with an inappropriate wiring. This problem may become apparent as the wiring is miniaturized, and these problems may become an obstacle to miniaturization. In addition, no consideration has been given to increasing the speed of signal transmission through the wiring. Therefore, the present invention aims to provide a technology for wiring in a semiconductor device that is advantageous for at least one of miniaturization and high-speed signal transmission. [Means for solving the problem]

[0005] A first aspect for the above purpose is a semiconductor device having a plurality of wirings each having a damascene structure on a semiconductor layer, the plurality of wirings including a first wiring and a second wiring adjacent to each other, a distance between one end and the other end of the first wiring being greater than 33 mm, the first wiring having a first portion, a second portion, and a third portion between the first portion and the second portion along a direction in which the first wiring extends, the width of the first portion and the width of the second portion being smaller than 180 nm, and the width of the third portion being greater than the width of the first portion and the width of the second portion.

[0006] Another aspect of the above object is a semiconductor device including a plurality of wirings each having a damascene structure on a semiconductor layer, the wirings comprising: the plurality of wirings include a first wiring and a second wiring adjacent to each other, the first wiring has, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion between the first portion and the second portion; the distance between the first portion and the second portion of the first wiring is greater than 33 mm; In the semiconductor device, the width of the third portion is the maximum width of the first wiring in the range from the first portion to the second portion, and is smaller than 180 nm.

[0007] Another aspect of the above object is a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a wafer including a semiconductor layer and an insulator film provided on the semiconductor layer; exposing a positive photoresist film provided on the insulator film to light; developing the photoresist film to form a resist pattern from the photoresist film; processing the insulator film using the resist pattern to form a trench in the insulator film; and forming a wiring in the trench, wherein the wafer has a first region, a second region, and a third region between the first region and the second region, and the trench is formed by a front the wiring extends from the first region through the third region to the second region, the exposure process includes a first exposure shot for exposing the photoresist film over the first region and the third region, and a second exposure shot for exposing the photoresist film over the second region and the third region after the first exposure shot, the wiring has, along the direction in which the wiring extends, a first portion located over the first region, a second portion located over the second region, and a third portion located over the third region, and a width of the third portion is larger than the width of the first portion and the width of the second portion.

[0008] Another aspect for achieving the above object is a semiconductor device having a plurality of unit pixels arranged across a plurality of rows and a plurality of columns, each having a photoelectric conversion portion, and a plurality of output lines connected to the unit pixels in one column and transmitting outputs of the unit pixels, the plurality of output lines including at least a first output line, a second output line including a portion adjacent to the first output line, and a third output line including a portion adjacent to the second output line, the first output line, the second output line, and the third output line all including portions extending along a first direction, the first output line, the second output line, and the third output line each passing through a first position and a second position different from the first position, and at least two distances among a distance between the first output line and the second output line, a distance between the second output line and the third output line, and a distance between the first output line and the third output line are each longer at the second position than at the first position.

[0009] Another aspect of the above object is a method for manufacturing a semiconductor device, the method comprising: a step of preparing a wafer including a semiconductor layer and an insulator film provided on the semiconductor layer; an exposure step of exposing a positive photoresist film provided on the insulator film; a development step of developing the photoresist film to form a resist pattern from the photoresist film; a processing step of processing the insulator film using the resist pattern to form a trench in the insulator film; and a wiring step of forming wiring in the trench, wherein the wafer has a first region, a second region, and a third region between the first region and the second region, and the trench extends from the first region to the second region via the third region, the exposure step includes a first exposure shot of exposing the photoresist film on the first region and the third region, and a second exposure shot of exposing the photoresist film on the second region and the third region after the first exposure shot, and The photoresist film between the first exposure shot and the second exposure shot has a first exposure section located on the first region and exposed by the first exposure shot, a second exposure section located on the third region and exposed by the first exposure shot, and a third exposure section located between the first exposure section and the second exposure section and exposed by the first exposure shot; the photoresist film after the second exposure shot of the exposure process has a fourth exposure section located on the second region and exposed by the second exposure shot, a fifth exposure section located on the third region and exposed by the second exposure shot, and a sixth exposure section located between the fourth exposure section and the fifth exposure section and exposed by the second exposure shot, wherein at least a part of the fifth exposure section includes the second exposure section; and in the developing process, the first exposure section, the second exposure section, the third exposure section, the fourth exposure section, the fifth exposure section, and the sixth exposure section are removed, and the width of the second exposure section is smaller than the width of the third exposure section. Effect of the Invention

[0010] According to the present invention, it is possible to provide a technique that is advantageous in at least one of miniaturization and high-speed signal transmission with respect to wiring in a semiconductor device. [Brief description of the drawings]

[0011] [Figure 1] 1A to 1C are schematic diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C are schematic diagrams illustrating a semiconductor device. [Diagram 3] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 6] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 7] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 8] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 9] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 10] 1A to 1C are schematic views illustrating a semiconductor device and a manufacturing method thereof; [Figure 11] 1A to 1C are schematic diagrams illustrating a semiconductor device. [Figure 12] FIG. [Figure 13] 1A to 1C are schematic diagrams illustrating a semiconductor device. [Figure 14] 1A to 1C are schematic diagrams illustrating a semiconductor device. [Figure 15] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 16] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 17] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 18] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 19] 1A to 1C are schematic diagrams illustrating a method for manufacturing a semiconductor device. [Figure 20]1A to 1C are schematic diagrams illustrating a semiconductor device and an apparatus. [Figure 21] Schematic diagram showing the configuration of a semiconductor device [Figure 22] Schematic diagram showing the configuration of a semiconductor device [Diagram 23] FIG. 1 is a diagram showing an operation of a semiconductor device. [Figure 24] Schematic diagram showing the configuration of a semiconductor device [Diagram 25] Schematic diagram showing the configuration of a semiconductor device [Figure 26] Schematic diagram showing the configuration of a semiconductor device [Figure 27] Schematic diagram showing the configuration of a semiconductor device [Figure 28] Schematic diagram showing the configuration of a semiconductor device DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description and the drawings, common reference numerals are used to designate common components across multiple drawings. Therefore, common configurations will be described by mutually referring to multiple drawings, and descriptions of configurations with common reference numerals will be omitted as appropriate.

[0013] FIG. 1 shows a photoelectric conversion device as an example of the semiconductor device APR. The photoelectric conversion device is, for example, a CMOS image sensor, and can be used in an imaging device, a distance measuring device, a photometer, and the like. The semiconductor device APR as a photoelectric conversion device is a semiconductor device having a plurality of wirings 110 each having a damascene structure on a semiconductor layer 100. The semiconductor device APR has a pixel section 11 in which unit pixels including photoelectric conversion elements are arranged two-dimensionally in m rows and n columns, and a signal processing circuit 12 formed around the pixel section. The semiconductor device APR has a size equal to or larger than the maximum exposure area of ​​an exposure device (exposure machine), and cannot be manufactured by one-shot exposure with such an exposure device. Therefore, the device area is divided into adjacent left and right areas, and is manufactured using a divided exposure technique in which each area is exposed separately. For example, the wiring layer may be formed by divided exposure. Hereinafter, the direction toward the center of the semiconductor device APR on a plane is called the inner periphery side, and the opposite direction is called the outer periphery side.

[0014] The semiconductor device APR is not limited to a front-illuminated photoelectric conversion device, but may be a back-illuminated photoelectric conversion device. In either photoelectric conversion device, the performance can be improved by miniaturizing the wiring. However, the front-illuminated photoelectric conversion device is particularly suitable because it can achieve an improvement in sensitivity by miniaturizing the wiring. The semiconductor device APR may also be a semiconductor device having a semiconductor layer having a photoelectric conversion unit and another semiconductor layer stacked on the semiconductor layer. The other semiconductor layer may be provided with a control circuit for controlling a pixel circuit including the photoelectric conversion unit, or a processing circuit for processing a signal from the pixel circuit. The semiconductor device APR is not limited to a photoelectric conversion device, but may be a display device using an organic EL element or a liquid crystal element, or may be a liquid ejection device such as a piezo-type or thermal-type inkjet head. The semiconductor device APR may be a storage device having a memory cell array in which a plurality of memory cells are arranged, or may be a calculation device such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit).

[0015] FIG. 1(b) is a plan view showing a plurality of device regions DR formed on the wafer WF. The dimensions of each device region DR are larger than the maximum exposure area of ​​the exposure tool. Each device region DR is divided into regions having dimensions equal to or smaller than the maximum exposure area of ​​the exposure tool, and is formed by dividing the regions into regions and exposing them individually.

[0016] FIG. 1(c) shows a conceptual diagram of one device region DR. The device region DR is divided into at least a left region SL and a right region SR with respect to the line A-A', and each of the left region SL and the right region SR is exposed with a different photomask. Hereinafter, the line A-A' may be referred to as the division center line. The left region SL is defined as the region from the left end to the line C-C', and the right region SR is defined as the region from the right end to the line B-B'. Hereinafter, the line C-C' may be referred to as the right end of the left region, and the line B-B' may be referred to as the left end of the right region. The intermediate region SC between the line B-B' and the line C-C' is exposed when the left region SL is exposed, and may also be exposed when the right region SR is exposed. In this way, the exposure overlaps in the intermediate region SC, so the intermediate region SC can also be referred to as an overlap region. In this embodiment, the device region DR is divided into two regions for explanation, but the number of divisions may be three or more. Although the following example shows a case where the image is divided into left and right portions for convenience, the direction of division is arbitrary, and the image may be divided into top and bottom portions.

[0017] The semiconductor device APR shown in Fig. 1(a) is formed on a wafer WF with a plurality of device regions DR arranged two-dimensionally as shown in Fig. 1(b), and after additional manufacturing steps, is divided into individual semiconductor devices (chips) by dicing. The semiconductor device APR includes at least these semiconductor devices (chips). As described later, the semiconductor device APR may include a package that houses the semiconductor device in addition to the semiconductor device.

[0018] 1(c) shows the dimensions of the device region DR of the semiconductor device APR manufactured by the manufacturing method of this embodiment. The vertical length W1 of the semiconductor device APR is 33 mm or less, and the horizontal length W2 is greater than 33 mm. For example, the vertical length W1 of the device region DR is 32 mm, and the horizontal length W2 is 42 mm. Therefore, an exposure tool with a maximum exposure area of ​​26 mm×33 mm cannot expose the device region DR in one go.

[0019] Therefore, the distance W2L between the reference line A-A' dividing the device region DR into the left region SL and the right region SR and the left end of the device region DR is set to 26 mm or less, for example, 21 mm. The distance W2R between the line A-A' and the right end of the device region DR is set to 26 mm or less, for example, 21 mm. The distance W3 from the line A-A' to the line B-B' is set to 10 to 1000 nm, preferably 50 to 500 nm, for example, 100 nm. The distance W4 from the line A-A' to the line C-C' is set to 10 to 1000 nm, preferably 50 to 500 nm, for example, 100 nm.

[0020] Since the length W1 is 33 mm or less and the sum of the distances W2L and W3 is 26 mm or less, the left area SL and the middle area SC can be exposed with an exposure device having a maximum exposure area of ​​26 mm×33 mm.

[0021] Furthermore, since the length W1 is 33 mm or less and the sum of the distances W2R and W4 is 26 mm or less, the right side region SR and the middle region SC can be exposed with an exposure device having a maximum exposure area of ​​26 mm×33 mm.

[0022] Therefore, a semiconductor device APR having a length W1 of 33 mm or less and a length W2 of more than 33 mm can be exposed using an exposure tool with a maximum exposure area of ​​26 mm×33 mm, with the division number of the device area DR being set to two.

[0023] In this example, the distances W2L and W2R are equal, but they do not have to be equal. Also, the lines A-A', B-B', and C-C' are straight lines, but they may be appropriately meandering depending on the pattern in the device area as long as the sum of the distances W2L and W3 does not exceed the maximum exposure area.

[0024] In an exposure device with a maximum exposure area of ​​26 mm×33 mm, the peripheral portion of the maximum exposure area may have a lower resolution than the central portion, so even if the exposure device has a maximum exposure area of ​​26 mm×33 mm, exposure may be performed using only a portion of the maximum exposure area. In such a case, divided exposure can be applied even to a semiconductor device APR with a size smaller than 26 mm×33 mm. In other words, there is no particular limit to the size of the semiconductor device APR to which divided exposure in this embodiment is applied.

[0025] The dimensions of the pixel section 11 in FIG. 1(a) are 36±1 mm×24±1 mm for a so-called 35 mm full-size image sensor. FIG. 1(c) shows row wiring of the pixel section 11 among a plurality of wirings 110 in the semiconductor device APR. The row wiring is a global wiring commonly connected to a pixel group included in one pixel row. The row wiring is, for example, a signal line that transmits an input signal (control signal) to a pixel group included in one pixel row. The row wiring is, for example, a power supply line that supplies a power supply (power supply potential or ground potential) to a pixel group included in one pixel row. The column wiring is, for example, a global wiring that crosses the row wiring and is commonly connected to a pixel group included in one pixel column. The row wiring and the column wiring must extend at least from one end to the other end of the pixel section 11. Therefore, the distance from one end to the other end of the row wiring must be longer than the horizontal width of the pixel section (36±1 mm), and the distance from one end to the other end of the column wiring may be longer than the horizontal width of the pixel section (24±1 mm). The column wiring is, for example, a signal line that transmits an output signal (pixel signal) from a group of pixels included in one pixel column. The column wiring is, for example, a power supply line that supplies a power supply (power supply potential or ground potential) to a group of pixels included in one pixel column. These row wirings and column wirings can be assigned to any of the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer arranged in order from the side closer to the semiconductor layer 100. The first wiring layer may have a single damascene structure, and the second wiring layer, the third wiring layer, and the fourth wiring layer may have a dual damascene structure. The power supply lines as global wirings (column wirings) can be arranged, for example, in the first wiring layer and / or the second wiring layer. The signal lines as global wirings (row wirings) can be arranged, for example, in one of the third wiring layer and the fourth wiring layer (typically, the third wiring layer). The signal lines as global wirings (column wirings) can be arranged, for example, in the other of the third wiring layer and the fourth wiring layer (typically, the fourth wiring layer). In addition, local wiring is arranged in each wiring layer, and particularly many local wirings can be arranged in the first wiring layer. Here, an example having four wiring layers has been described, but for example, the second wiring layer can be omitted, and local wirings and power lines can be arranged in the first wiring layer.Although the allocation of global wiring to wiring layers is not limited to these, taking these relationships into consideration, wiring having a length exceeding 33 mm can be a power supply line (row wiring) having a single damascene structure or a signal line (row wiring) having a dual damascene structure.

[0026] FIG. 2 shows a plan view of a plurality of wirings 110 in the semiconductor device APR. Each of the wirings Q1, Q2, and Q3 has a damascene structure. The wirings Q1 and Q2 are adjacent to each other, and the wirings Q2 and Q3 are adjacent to each other. The distance between one end Ea and the other end Eb of the wiring Q2 is greater than 33 mm. As described above, the distance between one end Ea and the other end Eb of the wiring Q2 may be 36±1 mm or more. FIG. 2(b) is an enlarged view of the range AA in FIG. 2(a). Each of the wirings Q1, Q2, and Q3 has a left portion 110a, a right portion 110b, and an intermediate portion 110c between the left portion 110a and the right portion 110b along the direction in which the wirings Q1, Q2, and Q3 extend. The left portion 110a is located in the left region SL, the right portion 110b is located in the right region SR, and the intermediate portion 110c is located in the intermediate region SC. FIG. 2(b) shows the width Wa of the left portion 110a, the width Wb of the right portion 110b, and the width Wc of the middle portion 110c. It is characteristic that the width Wc of the middle portion 110c is larger than the width Wa of the left portion 110a and the width Wb of the right portion 110b (Wc>Wa, Wc>Wb). The width Wa of the left portion 110a and the width Wb of the right portion 110b may be smaller than 230 nm. The advantageous effect in realizing the miniaturization obtained by making the width Wc larger than the width Wa and the width Wb can be significantly obtained when the width Wa of the left portion 110a and the width Wb of the right portion 110b are less than 230 nm. When the width Wa of the left portion 110a and the width Wb of the right portion 110b are 230 nm or more, the width Wc of the middle portion 110c may be the same as or different from the width Wa of the left portion 110a and the width Wb of the right portion 110b. When the widths Wa and Wb are 230 nm or more, making the width Wc of the intermediate portion 110c larger than the widths Wa and Wb may be disadvantageous in achieving miniaturization. The width Wa of the left portion 110a and the width Wb of the right portion 110b may be smaller than 180 nm. The advantageous effect in realizing miniaturization obtained by making the width Wc larger than the width Wa and the width Wb can be particularly significantly obtained when the width Wa of the left portion 110a and the width Wb of the right portion 110b are less than 180 nm. It is preferable that the difference (Wc - Wa) between the width Wc of the intermediate portion 110c and the width Wa of the left portion 110a is larger than 50 nm, which is preferable for making the width Wa of the left portion 110a smaller than 180 nm. It is preferable that the difference (Wc - Wb) between the width Wc of the intermediate portion 110c and the width Wb of the right portion 110b is larger than 50 nm, which is preferable for making the width Wb of the right portion 110b smaller than 180 nm. It is preferable that the difference (Wc - Wa) between the width Wc of the intermediate portion 110c and the width Wa of the left portion 110a is smaller than the width Wa of the left portion 110a (Wc - Wa < Wa). It is also preferable that the difference (Wc - Wb) between the width Wc of the intermediate portion 110c and the width Wb of the right portion 110b is smaller than the width Wb of the right portion 110b (Wc - Wb < Wb). It is also preferable that the width Wc of the intermediate portion 110c is larger than 110 nm. It is also preferable that the width Wc of the intermediate portion 110c is larger than 180 nm. The width Wc of the intermediate portion 110c may be smaller than 300 nm. In this example, the width Wb is equal to the width Wa, but the width Wb may be different from the width Wa.

[0027] Figure 2(b) shows the distance Da between the left portion 110a of wiring Q2 and wirings Q1 and Q3, the distance Db between the right portion 110b of wiring Q2 and wirings Q1 and Q3, and the distance Dc between the middle portion 110c of wiring Q2 and wirings Q1 and Q3. It is preferable that the distance Dc between the middle portion 110c of wiring Q2 and wirings Q1 and Q3 is larger than the width Wa of the left portion 110a (Dc > Wa). It is preferable that the distance Dc between the middle portion 110c of wiring Q2 and wirings Q1 and Q3 is larger than the width Wb of the right portion 110b (Dc > Wb). It is preferable that the distance Da between the left portion 110a of wiring Q2 and wirings Q1 and Q3 is smaller than the width Wc of the middle portion 110c (Da < Wc). It is preferable that the distance Db between the right portion 110b of wiring Q2 and wirings Q1 and Q3 is smaller than the width Wc of the middle portion 110c (Db < Wc). In this example, the distance Db is equal to the distance Da, but the distance Db may be different from the distance Da.

[0028] Figure 2(b) shows the length La of the left portion 110a, the length Lb of the right portion 110b, and the length Lc of the middle portion 110c along the direction in which wirings Q1, Q2, and Q3 extend. The length Lc of the middle portion 110c may be larger than the width Wa of the left portion 110a. The length Lc of the middle portion 110c may be larger than the width Wb of the right portion 110b. The length Lc of the middle portion 110c may be smaller than the length La of the left portion 110a. The length Lc of the middle portion 110c may be smaller than the length Lb of the right portion 110b.

[0029] Typically, the width Wa, the width Wb, the distance Da, and the distance Db are smaller than the width Wc and the distance Dc.

[0030] An example of the case where the semiconductor device APR is applied to a photoelectric conversion device will be described. The wirings Q1, Q2, and Q3 are, for example, row wirings having a dual damascene structure. The wirings Q1, Q2, and Q3 are signal lines that transmit control signals to a pixel circuit having four transistors (transfer transistor, reset transistor, amplification transistor, and selection transistor) per pixel P. For example, the wiring Q1 is a transfer signal line that controls the transfer transistor, the wiring Q2 is a reset signal line that controls the reset transistor, and the wiring Q3 is a selection signal line that controls the selection transistor. The functions of the multiple wirings 110 and the wirings Q1, Q2, and Q3 in this embodiment are not limited to the above example.

[0031] FIG. 2(a) shows the range of a plurality of pixels P. A thick portion (thick line portion) and a thin portion (thin line portion) of the wiring are repeatedly provided for each pixel P. The left portion 110a is located between one end Ea and the middle portion 110c of the range AA along the direction in which the wirings Q1, Q2, and Q3 extend. The right portion 110b is located between the other end Eb and the middle portion 110c of the range AA along the direction in which the wirings Q1, Q2, and Q3 extend. The wirings Q1, Q2, and Q3 have a thin line portion L4 between one end Ea and the left portion 110a and a thick line portion L5 between the thin line portion L4 and the left portion 110a along the direction in which the wirings Q1, Q2, and Q3 extend. In addition, the wirings Q1, Q2, and Q3 have a thin line portion R6 between the other end Eb and the right part 110b, and a thick line portion R7 between the thin line portion R6 and the right part 110b along the direction in which the wirings Q1, Q2, and Q3 extend. The width of the thick line portion L5 is larger than the width Wa of the left part 110a, the width Wb of the right part 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion R7 is larger than the width Wa of the left part 110a, the width Wb of the right part 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion L5 and the width of the thick line portion R7 are preferably equal to the width Wc, but may be different from the width Wc. The width of the thin line portion L4 and the width of the thin line portion R6 are preferably equal to the widths Wa and Wb, but may be different from the widths Wa and Wb.

[0032] In this way, by providing the thick line portion (thick line portion L5, R7) at the position corresponding to the range AA in the pixel away from the A-A' line not including the intermediate region SC, the uniformity of the wiring layout in each pixel can be improved, and the uniformity of the characteristics of each pixel can be improved. That is, the signal output difference between the pixel near the A-A' line including the intermediate region SC and the pixel away from the A-A' line not including the intermediate region can be reduced, and the occurrence of line noise along the A-A' line in the image can be suppressed. Of course, since the thick line portion L5 is on the left region SL and the thick line portion R7 is on the right region SR, the thick line portions L5, R7 have almost no function of mitigating the influence of the misalignment between the photomask at the time of exposure of the left region SL and the photomask at the time of exposure of the right region SR.

[0033] Each of the wirings Q1, Q2, and Q3 has a left portion 110d between the left portion 110a and the middle portion 110c and a right portion 110e between the right portion 110b and the middle portion 110c along the direction in which the wirings Q1, Q2, and Q3 extend. In FIG. 2(b), the width Wd of the left portion 110d and the width We of the right portion 110e are described. The width Wd of the left portion 110d is larger than the width Wa of the left portion 110a (Wd>Wa), and the width We of the right portion 110e is larger than the width Wb of the right portion 110b (We>Wb). In this example, the width Wd of the left portion 110d is equal to the width Wc of the middle portion (Wd = Wc). When the width Wd of the left portion 110d is different from the width Wc of the middle portion, the width Wd of the left portion 110d may be larger than the width Wc of the middle portion (Wd>Wc), but the width Wd of the left portion 110d is preferably smaller than the width Wc of the middle portion (Wd<Wc). Similarly, the width We of the right portion 110e is equal to the width Wc of the middle portion (We = Wc). When the width We of the right portion 110e is different from the width Wc of the middle portion, the width We of the right portion 110e may be larger than the width Wc of the middle portion (We>Wc), but the width We of the right portion 110e is preferably smaller than the width Wc of the middle portion (We<Wc). The difference (|Wc - Wd|) between the width Wc of the middle portion 110c and the width Wd of the left portion 110d is preferably smaller than the difference (|Wd - Wa|) between the width Wa of the left portion 110a and the width Wd of the left portion 110d (|Wc - Wd|<|Wd - Wa|). Similarly, the difference (|Wc - We|) between the width Wc of the middle portion 110c and the width We of the right portion 110e is preferably smaller than the difference (|We - Wb|) between the width Wb of the right portion 110b and the width We of the right portion 110e (|Wc - We|<|We - Wb|). As described above, since Wc = Wd = We can be satisfied, the relationship between the widths Wd and We and the widths Wa and Wb can apply the relationship between the width Wc and the widths Wa and Wb. Note that the left portion 110d and the right portion 110e can be omitted, which is equivalent to making the width Wd of the left portion 110d equal to the width Wa and making the width We of the right portion 110e equal to the width Wb.

[0034] As shown in Fig. 2(b), between the left part 110a and the left part 110d, the wirings Q1 and Q3 are arranged obliquely. Thereby, the coexistence of Wa < Wc and Da < Dc is realized. Similarly, between the right part 110b and the right part 110e, the wirings Q1 and Q3 are arranged obliquely. Thereby, the coexistence of Wb < Wc and Db < Dc is realized.

[0035] Also, by making the width Wc larger than the widths Wa and Wb (Wc > Wa & Wb), even when the photomasks of the left region SL and the right region SR are misaligned, it is possible to suppress the disconnection of the pattern in the intermediate part 110c. And in the left part 110a and the right part 110b, finer patterns can be formed. Also, by making the distance Dc larger than the distances Da and Db (Dc > Da & Db), even when the photomasks of the left region SL and the right region SR are misaligned, it is possible to suppress the short - circuit of the pattern in the intermediate part 110c.

[0036] As shown in Fig. 2(a), the wiring pitch Y2 in the Y direction can be made wider than the wiring pitch Y1 in the Y direction. Thereby, a wider wiring opening in the Y direction can be obtained, and the sensitivity of the photoelectric conversion device can be improved.

[0037] Hereinafter, a method for manufacturing a semiconductor device will be described with reference to Figs. 3 and 4. In Figs. 3 and 4, the drawings labeled with the number (x - 1) are cross - sectional views, and the drawings labeled with the number (x - 2) are plan views. Here, x is an alphabet from a to h. The cross - sectional view of the number (x - 1) represents the cross - section when the plan view of the number (x - 2) is cut along D - D'.

[0038] As shown in the plan view of the number (x - 2) in each figure, the wafer WF has, in each of the plurality of device regions DR, a left region SL on the left side of the line C - C', a right region SR on the right side of the line B - B', and an intermediate region SC between the left region SL and the right region SR.

[0039] 3(a-1) and (a-2) show step A of preparing a wafer WF including a semiconductor layer 100 and a second insulator film 104 provided on the semiconductor layer 100. The wafer WF used in manufacturing the semiconductor device APR of this embodiment includes a semiconductor layer 100 as an element functional layer. A silicon layer or a compound semiconductor layer can be used as the semiconductor layer 100. In the element functional layer, a plurality of photoelectric conversion units (not shown), a plurality of transistors (not shown), and an isolation structure (not shown) that isolates the plurality of photoelectric conversion units and the plurality of transistors at locations where they should be electrically isolated from each other are formed. The element functional layer can be formed by a known method using a known material.

[0040] An interlayer insulating film 101 is formed on the semiconductor layer 100 as an element functional layer. The interlayer insulating film 101 is formed to electrically insulate the structure in the semiconductor layer 100 as an element functional layer from layers above the interlayer insulating film 101. The interlayer insulating film 101 may be made of, for example, silicon oxide, and may be formed by a known method.

[0041] In the interlayer insulating film 101, contact plugs 102 are formed at locations where electrical conduction is desired between the structure in the semiconductor layer 100 as the element functional layer and the wiring above the interlayer insulating film 101. A first insulator film 103 functioning as an etching stop layer and a second insulator film 104 serving as an interlayer insulating film are formed on the contact plugs 102. For example, the contact plugs 102 may be tungsten, the first insulator film 103 may be a silicon carbide film or a silicon nitride film, and the second insulator film 104 may be a silicon oxide film. Note that these configurations do not limit this embodiment, but are merely shown as examples.

[0042] 3(b-1) and (b-2) show step B of forming mask material films 105 and 106 on the wafer WF. A first mask material film 105 and a second mask material film 106 are formed on a second insulator film 104 that serves as an interlayer insulating film. The first mask material film 105 is composed of an inorganic material film 1051 and an organic material film 1052. For example, the inorganic material film 1051 may be a silicon nitride film, and the organic material film 1052 may be a novolac-based resin. In this embodiment, the first mask material film 105 has the above-mentioned configuration, but may have another configuration. For example, a silicon oxide film is used as the second mask material film 106.

[0043] 3(c-1) and (c-2) show an exposure process C in which the positive photoresist film 111 provided on the upper layer side of the insulator films 103 and 104 is exposed by a left exposure shot L. The left exposure shot L exposes the photoresist film 111 on the left region SL and the middle region SC. After the positive photoresist film 111 is formed on the second mask material film 106, a left exposure pattern 111L is exposed on the photoresist film 111 on the left region SL and the middle region SC using a photomask PML. As shown in FIG. 3(c-2), the left exposure pattern 111L is exposed across line A-A' up to line B-B'.

[0044] 3(d-1) and (d-2) show an exposure process D in which the positive photoresist film 111 provided on the upper layer side of the insulator films 103 and 104 is exposed by a right exposure shot R. The right exposure shot R exposes the photoresist film 111 on the right region SR and middle region SC after the left exposure shot L. After the left region SL is exposed, the middle region SC and right region SR are exposed using a photomask PMR on the right region SR and middle region SC, exposing the right exposure pattern 111R on the photoresist film 111. The right exposure pattern 111R is exposed across line A-A' up to line C-C'.

[0045] In this way, the exposure process combining the exposure process C and the exposure process D includes a left exposure shot L and a right exposure shot R after the left exposure shot L. Here, an example is shown in which the right exposure shot R is performed after the left exposure shot L, but the left exposure shot L may be performed after the right exposure shot R. Details of the left exposure pattern 111L and the right exposure pattern 111R will be described later. The wavelength of the exposure light is, for example, 175 to 275 nm, and exposure light with a wavelength of 225 to 275 nm (for example, a KrF excimer laser with a wavelength of 248 nm) or exposure light with a wavelength of 175 to 225 nm (for example, an ArF excimer laser with a wavelength of 193 nm) is preferable. Using an ArF excimer laser as the exposure light is more preferable for fine wiring.

[0046] 4(e-1) and (e-2) show a developing step E in which the photoresist film 111 is developed to form a resist pattern 111D from the photoresist film 111. The photoresist film 111 on which a latent image pattern has been formed via the left exposure shot L and the right exposure shot R is subjected to a developing process to form a resist pattern 111D. Since the photoresist film 111 is a positive type, the portion of the photoresist film 111 that has been exposed in the exposure step is removed in the developing step.

[0047] 4(f-1) and (f-2) show processing step F in which the mask material film 106 is processed using the resist pattern 111D as a mask to transfer the resist pattern to the mask material film 106. The second mask material film 106 is etched using the resist pattern 111D as a mask to form a mask pattern 1061.

[0048] 4(g-1) and (g-2) show processing step G in which the insulator films 104, 103 are processed using the mask pattern 1061 as a mask to form trenches 109 in the insulator films 104, 103. Using the mask pattern 1061 as a mask, the first mask material film 105, the second insulator film 104 that serves as an interlayer insulating film, and the first insulator film 103 are etched to form the trench 109. The trench 109 extends from the left region SL through the middle region SC to the right region SR.

[0049] The processing steps F and G can be collectively referred to as a processing step in which the insulator films 104, 103 are processed using the resist pattern 111D to form trenches in the insulator films 104, 103. Here, the processing step F is performed, but it is not essential to perform the processing step F or to use the first mask material film 105. The resist pattern itself formed from a photoresist film formed directly on the insulator film 104 may be used as a mask to process the insulator films 104, 103 to form trenches in the insulator films 104, 103.

[0050] 4(h-1) and (h-2) show a wiring process H for forming a wiring 110 in the trench. A conductive material is filled into the trench 109 by, for example, plating. The conductive material may be, for example, copper or an alloy containing copper. After filling the conductive material, unnecessary conductive material formed on the second insulator film 104 is removed by, for example, chemical mechanical polishing (CMP). Thus, the wiring 110 is formed in the trench 109. The wiring 110 extends from the left region SL through the middle region SC to the right region SR. The wiring 110 has, along the direction in which the wiring 110 extends, a left portion 110L located on the left region SL, a right portion 110R located on the right region SL, and a middle portion 110C located on the middle region SC. The wiring formed by filling the insulator film with a conductive material and removing the unnecessary conductive material in this way is called a damascene wiring, and such a process is called a damascene process.

[0051] Thereafter, at least one upper wiring layer (typically, a plurality of upper wiring layers) is formed. The upper wiring layer may be formed by applying the same damascene process as described above to the interlayer insulating film formed on the second insulator film 104 and the wiring 110. When the semiconductor device APR is a front-illuminated photoelectric conversion device, an opening may be provided in the plurality of interlayer insulating films including the second insulator film 104 after the upper wiring layer is formed. This opening forms an optical path for light to the photoelectric conversion unit. This opening can be filled with a light-transmitting material different from the insulator film 103 and / or the second insulator film 104. For example, if the insulator film 103 is silicon carbide or silicon nitride and the second insulator film 104 is silicon oxide, the light-transmitting material may be silicon nitride, silicon oxide, or resin.

[0052] The above describes the case where the manufacturing method of the semiconductor device is applied to the formation of wiring. The wiring layer includes wiring that transmits a power supply and a signal common to each column of the pixel section, and these wirings are arranged across the left region SL and the right region SR. By applying the divided exposure in this embodiment, the wiring in each region can be finely processed, and the portion extending between the regions can also be finely processed. The wiring connected by divided exposure can be, for example, a power supply line that supplies power to operate the pixel section or the column circuit. Alternatively, the wiring connected by divided exposure can be, for example, a signal line that supplies a control signal for controlling the operation of the pixel section or the column circuit, or a signal line that transmits an output signal from the column circuit based on the amount of light received by each pixel. However, other wirings may be connected by divided exposure. The wiring for which the manufacturing method has been described in this embodiment is a single damascene wiring by a single damascene process, but a similar method may be applied to a dual damascene wiring by a dual damascene process. Although a trench first method can be adopted for the dual damascene process, it is more advantageous to adopt a via first method in terms of fine processing.

[0053] Although the manufacturing method is described for one wiring layer, the above-mentioned embodiment may be applied to wiring layers of two or more layers. Also, the exposure apparatus used for exposure during formation may be different between the first-layer wiring and the second-layer wiring. For example, when forming the first-layer wiring, an exposure apparatus with a wavelength of 193 nm and a maximum exposure area of ​​26 mm×33 mm using an ArF light source may be used, and when forming the second-layer and subsequent wirings, an exposure apparatus with a wavelength of 248 nm and a maximum exposure area of ​​26 mm×33 mm using a KrF light source may be used. The first-layer wiring may be a single damascene wiring, and the second-layer wiring may be a dual damascene wiring. Then, a joint exposure (split exposure) using an ArF light source may be applied to the first-layer single damascene wiring, and a joint exposure (split exposure) using a KrF light source may be applied to the second-layer dual damascene wiring.

[0054] Hereinafter, the left exposure pattern 111L and the right exposure pattern 111R in the exposure step of FIG. 3 in the manufacturing method of the semiconductor device APR will be described in detail with reference to FIGS.

[0055] In each of Figures 5 to 9, the drawing (a) numbered (a) shows a pattern on the photomask PML used in the left exposure shot L for exposing the left region SL. In each of Figures 5 to 9, the drawing (c) numbered (c) shows a pattern on the photomask PMR used in the right exposure shot R for exposing the right region SR. The photomasks PML and PMR include light-shielding regions LS and light-transmitting regions LT. The exposure light transmitted through the light-transmitting regions LT exposes the photoresist film 111.

[0056] In each of the figures of Figures 5 to 9, the drawing (b) with the number (b) shows the left exposure pattern 111L of the photoresist film 111 between the left exposure shot L and the right exposure shot R in the exposure process C. In the drawing (b), the left exposure pattern 111L is hatched with diagonal lines slanting upward to the left. As shown in the drawing (b), the photoresist film 111 has an exposed portion 111La located on the left region 111 and exposed by the left exposure shot L, and an exposed portion 111Lc located on the middle region SC and exposed by the left exposure shot L. Furthermore, the photoresist film 111 has an exposed portion 111Ld located between the exposed portion 111La and the exposed portion 111Lc and exposed by the left exposure shot L.

[0057] In each of Figures 5 to 9, drawing (d) with the number (d) shows a right-side exposed pattern 111R of the photoresist film 111 after the right-side exposure shot R of the exposure process. In drawing (d), the right-side exposed pattern 111R is hatched with diagonal lines slanting upward to the right. As shown in drawing (d), the photoresist film 111 has an exposed portion 111Rb located on the right side region SR and exposed by the right-side exposure shot R, and an exposed portion 111Rc located on the middle region SC and exposed by the right-side exposure shot R. The photoresist film 111 further has an exposed portion 111Re located between the exposed portions 111Rb and 111Rc and exposed by the right-side exposure shot R.

[0058] In each of Figures 5 to 9, drawing (e) labeled with the number (e) shows by hatching the latent image pattern of the left exposure pattern 111L and the right exposure pattern 111R of the photoresist film 111 after the left exposure shot L and the right exposure shot R of the exposure process. In drawing (e), the parts without hatching are the parts that are not removed by development. In drawing (d), the left exposure pattern 111R is hatched with diagonal lines slanting upwards to the left. In drawing (e), the right exposure pattern 111R is hatched with diagonal lines slanting upwards to the right.

[0059] In the region located above the left region SL and the right region SR in (e) of each of Figures 5 to 9, the left exposure pattern 111L and the right exposure pattern 111R in (b) and (d) of each of Figures 5 to 9 become latent image patterns. In the region located above the middle region SC in (e) of each of Figures 5 to 9, the latent image pattern can change from the left exposure pattern 111Lc and the right exposure pattern 111Rc in (b) and (d) of each of Figures 5 to 9 by double exposure with the left exposure shot L and the right exposure shot R.

[0060] As shown in FIG. 1(e), the latent image pattern of the photoresist film 111 has an exposed portion 111Rb located on the right region SR and exposed by the right exposure shot R, and an exposed portion 111LR located on the middle region SC and exposed by the right exposure shot R. The photoresist film 111 further has an exposed portion 111Re located between the exposed portions 111Rb and 111LR and exposed by the right exposure shot R.

[0061] Here, the exposed portion of the photoresist film 111 located above the intermediate region SC includes a double exposed portion 111LR exposed by both the left exposure shot L and the right exposure shot R. In each of the drawings (e) of Figs. 5 to 9, the double exposed portion 111LR is hatched with diagonal lines slanting left and right. That is, at least the exposed portion 111LR exposed by the right exposure shot R includes an exposed portion 111Lc. In Figs. 8 and 9, the exposed portion located above the intermediate region SC includes an exposed portion 111Lc exposed by the left exposure shot L and not exposed by the right exposure shot R, and an exposed portion 111Rc not exposed by the left exposure shot L but exposed by the right exposure shot R.

[0062] Since the photoresist film 111 is a positive type, the exposed portions 111La, 111Lc, 111Ld, 111Rb, 111Rc, 111LR, and 111Re are removed.

[0063] Drawing (b) of each of FIGS. 5 to 9 shows the width Ma of the exposed portion 111La, the width Md of the exposed portion 111Ld, and the width Mc' of the exposed portion 111Lc.

[0064] In addition, drawing (d) of each of Figures 5 to 9 shows the width Mb of exposed portion 111Rb, the width Me of exposed portion 111Re, and the width Mc" of exposed portion 111Rc. Note that in drawing (d) of each of Figures 5 to 9, the width Mc" of the exposed portion of the intermediate region SC by the right-side exposure shot R may be the same as the width Mc'.

[0065] Also, drawing (e) of each of Figures 5 to 9 shows width Ma of the latent image in exposed portion 111La, width Md of the latent image in exposed portion 111Ld, width Mb of the latent image in exposed portion 111Rb, width Me of the latent image in exposed portion 111Re, and width Mc of the latent image in intermediate region SC. Widths Ma and Md are equal between drawings (b) and (e) of each of Figures 5 to 9. Also, widths Mb and Me are equal between drawings (d) and (e) of each of Figures 5 to 9.

[0066] It should be noted here that the width Mc' may be different from the width Mc. In the intermediate region SC, the width Mc may be larger than the width Mc' or Mc" due to the double exposure by the left exposure shot L and the right exposure shot R, as the cumulative exposure amount increases. This is because the increase in the cumulative exposure amount increases the amount of acid generated in the exposed area, and the acid-catalyzed protective group elimination reaction occurs more frequently, expanding the area that can be dissolved in the developer. In addition, light diffraction may occur during exposure, and the width Mc may be larger than the width Mc' due to the double exposure by both the diffracted light by the left exposure shot L and the diffracted light by the right exposure shot R. In addition, the width Mc may be different from the width Mc' or Mc" due to the misalignment between the left exposure shot L and the right exposure shot R. In the drawing (e) of each of Figures 5 to 9, the areas in which a latent image is not formed by only the left exposure shot L or only the right exposure shot R among the left exposure shot L and the right exposure shot R are hatched without diagonal lines. The area with non-diagonal hatching is an area where a latent image is formed by the influence of acid or double exposure of diffracted light as described above. In each of the drawings of Figs. 5 to 9, the drawing (f) with the number (f) shows the pattern of the wiring 110 after the wiring process. As shown in the drawing (f) of each of the drawings of Figs. 5 to 9, the wiring 110 has a left part 110a, a right part 110b, and a middle part 110c between the left part 110a and the right part 110b. The wiring 110 also has a left part 110d between the left part 110a and the middle part 110c, and a right part 110e between the right part 110b and the middle part 110c. The middle part 110c is located between the left part 110d and the right part 110e.

[0067] Drawing (f) of each of Figures 5 to 9 shows the width Wa of left portion 110a, the width Wb of right portion 110b, the width Wc of middle portion 110c, the width Wd of left portion 110d, and the width We of right portion 110e. Note that FIG. 7(f) also shows a portion having width Wc' and a portion having width Wc".

[0068] Hereinafter, for the widths Ma, Mb, Mc, Mc’, Mc”, Md, Me of each exposure portion and the widths Wa, Wb, Wc, Wc’, Wc”, Wd, We of the wiring portions, a plurality of embodiments (Embodiments 1 to 5) will be described with examples.

[0069] One thing common to the embodiments of Embodiments 1 to 5 is that the width Wc of the intermediate portion 110c is greater than the width Wa of the left portion 100a and the width Wb of the right portion 100b (Wc > Wa & Wb). Here, “Wa & Wb” means “Wa and Wb”, and “Wc ≧ Wa & Wb” is synonymous with “Wc ≧ Wa and Wc ≧ Wb”. In Wc ≧ Wa & Wb, Wa and Wb may be the same or different. The same applies hereinafter. Note that when using an inequality with an equal sign, it means that it may be an equal sign or an inequality sign even when it is an equal sign. That is, “Wc ≧ Wa & Wb” is synonymous with “Wc = Wa & Wb” or “Wc > Wa & Wb”.

[0070] In this way, by making the width Wc of the wiring 110 in the intermediate region SC larger than the widths Wa and Wb, even if the photomasks PML and PMR are misaligned, disconnection of the wiring 110 in the intermediate region SC can be suppressed.

[0071] One thing common to the embodiments of Embodiments 1 to 5 is that the width Ma of the exposure portion 111La is smaller than the width Mc’ of the exposure portion 111Lc (Ma < Mc’). One thing common to the embodiments of Embodiments 1 to 5 is that the width Mb of the exposure portion 111Rb is smaller than the width Mc” of the exposure portion 111Rc (Mb < Mc”). Thereby, the resolution of the exposure portions 111Lc and 111Rc can be improved compared to the exposure portions 111La and 111Rb. Thereby, it is possible to suppress non - resolution of the exposure portions 111Lc and 111Rc under the conditions for exposing the exposure portions 111La and 111Rb.

[0072] Another common feature among the first to fifth embodiments is that the width Md of the exposure portion 111Ld is greater than the width of the exposure portion 111La (Md > Ma). Another common feature among the first to fifth embodiments is that the width Me of the exposure portion 111Re is greater than the width of the exposure portion 111Rb (Me > Mb).

[0073] One thing common to the second to fifth embodiments is that the width Mc’ of the exposure portion 111Lc is smaller than the width Md of the exposure portion 111Ld (Mc’ < Md). One thing common to the second to fifth embodiments is that the width Mc” of the exposure portion 111Rc is smaller than the width Me of the exposure portion 111Le (Mc” < Me).

[0074] One thing common to the first to fifth embodiments is that the difference between the width Ma of the exposure portion 111La and the width Md of the exposure portion 111Ld (|Md - Ma|) is greater than the difference between the width Mc’ of the exposure portion 111Lc and the width Md of the exposure portion 111Ld (|Md - Mc’|) (|Md - Ma| > |Md - Mc’|). One thing common to the first to fifth embodiments is that the difference between the width Mb of the exposure portion 111Rb and the width Me of the exposure portion 111RLe (|Me - Mb|) is greater than the difference between the width Mc” of the exposure portion 111Rc and the width Me of the exposure portion 111Re (|Me - Mc”|) (|Me - Mb| > |Me - Mc”|).

[0075] <First Embodiment> The manufacturing method of the semiconductor device APR of the first embodiment is shown in FIG. 5. FIG. 5(a) shows the pattern on the photomask PML used when exposing the left region SL. FIG. 5(b) shows the left exposure pattern 111L exposed on the photoresist film 111. FIG. 5(c) shows the pattern on the photomask PMR used when exposing the right region SR. FIG. 5(d) shows the right exposure pattern 111R exposed on the photoresist film 111.

[0076] In the first embodiment, the relationship Ma & Mb < Md & Me ≦ Mc’ & Mc” ≦ Mc is satisfied. Also, in the first embodiment, the relationship Wa & Wb < Wd & We < Wc is satisfied.

[0077] As shown in FIGS. 5(b) and 5(d), the width Mc' of the exposure portion 111Lc is the same as the width Md of the exposure portion 111Ld, and the width Mc'' of the exposure portion 111Rc is the same as the width Me of the exposure portion 111Le. However, since exposure is performed repeatedly in the intermediate region SC, as shown in FIG. 5(e), the width Mc in the intermediate region SC of the latent image pattern including the exposure portion 111LR formed on the photoresist film 111 can be thicker than the width Mc' and the width Mc'' (Mc'&Mc''<Mc). Therefore, the width Mc of the latent image pattern in the intermediate region SC is thicker than the widths Md and Me of the latent image pattern in the regions other than the intermediate region SC. Therefore, the opening of the resist pattern after development in the intermediate region SC is thicker than the openings of the resist patterns after development in the left region SL and the right region SR other than the intermediate region SC. Therefore, an increase in the resistance of the wiring due to the intermediate region SC can be suppressed. If there is no influence of the diffracted light, acid, or misalignment described above, Mc'&Mc'' = Mc can hold. Even if Mc'&Mc'' = Mc, if Md&Me ≦ Mc'&Mc'', Wd&We < Wc can hold.

[0078] In order to suppress a short circuit between adjacent wiring patterns in the intermediate region SC, it is preferable to increase the space from the adjacent pattern. In FIG. 2(b), it is sufficient that the distance Dc, which is the interval between wirings in the intermediate region SC, is larger than the distance Da and the distance Db. In performing miniaturization, the distance Dc may be equal to or less than the width Wc.

[0079] <Second Embodiment> FIG. 6 shows a method of manufacturing the semiconductor device APR of the second embodiment. The semiconductor device APR of the second embodiment has different regions exposed on the photoresist film 111.

[0080] Fig. 6(a) shows the pattern on the photomask used when exposing the left region SL. Fig. 6(b) shows the left exposure pattern 111L exposed on the photoresist film 111. Fig. 6(c) shows the pattern on the photomask used when exposing the right region SR. Fig. 6(d) shows the right exposure pattern 111R exposed on the photoresist film 111. The photomasks PML and PMR include a light-shielding region LS and a light-transmitting region LT. The exposure light transmitted through the light-transmitting region LT exposes the photoresist film 111.

[0081] In the first embodiment, the relationship of Mc’&Mc”≧Md&Me is satisfied, while in the second embodiment, the relationship of Mc’&Mc”<Md&Me is satisfied. In the second embodiment, the relationship of Ma&Mb<Mc’&Mc”≦Mc≦Md&Me is satisfied. Also, in the second embodiment, the relationship of Wa&Wb<Wc≦Wd&We is satisfied.

[0082] In the second embodiment, as shown in Fig. 6(a), the pattern width on the photomask PML corresponding to the intermediate region SC is partially narrowed. As a result, as shown in Fig. 6(b), the left exposure pattern 111L exposed on the photoresist film 111 has a width Mc’ in the intermediate region SC that is narrower than the width Md in the left region SL outside the intermediate region SC. Also, in the second embodiment, as shown in Fig. 6(c), the pattern width on the photomask PMR corresponding to the intermediate region SC is partially narrowed. As a result, as shown in Fig. 6(d), the right exposure pattern 111R exposed on the photoresist film 111 has a width Mc” in the intermediate region SC that is narrower than the width Me in the right region SR outside the intermediate region SC. In this way, the exposed portion 111LR on the intermediate region SC of the photoresist film 111 is double-exposed, and the exposed portion 111Ld of the left region SL continuously extending from the intermediate region SC is single-exposed.

[0083] In the intermediate region SC, since exposure is performed repeatedly, the width Mc of the latent image pattern in the intermediate region SC including the exposed portion 111LR formed on the photoresist film 111 can be thicker than the widths Mc' and Mc" (Mc' & Mc" < Mc). If there is no influence of the above-described diffracted light, acid, or misalignment, Mc' & Mc" = Mc can be achieved.

[0084] By setting the widths Mc' and Mc" to suitable values, it is possible to adjust the integrated exposure amount in the intermediate region SC and make the width Mc of the latent image pattern in the intermediate region SC closer to the widths Md and Me of the latent image patterns in the regions other than the intermediate region SC. In this example, Mc = Mc = Md & Me, but Mc < Md & Me may also be acceptable.

[0085] By performing a development process on the photoresist in which the latent image is formed in this way, a resist pattern 111D is formed. The pattern dimensions on the photoresist after development in the intermediate region SC are formed close to the pattern dimensions on the photoresist after development in the regions other than the intermediate region SC. This means that the difference between the width Mc and the width Md is smaller than the difference between the width Mc" and the width Md (|Mc - Md| < |Mc" - Md|).

[0086] In the manufacturing method of the second embodiment, the widths Mc' and Mc" of the exposed portions 111Lc and 111Rc in the intermediate region SC, which is a double-exposure region, are made smaller than the width Md of the left region SL and the width Me of the right region SR, which are single-exposure regions. Therefore, in the second embodiment compared to the first embodiment, short circuits with adjacent patterns can be more appropriately suppressed. Also, in the second embodiment, since it is possible to make the width of the latent image pattern in the intermediate region SC including the exposed portion 111LR smaller than that in the first embodiment, it is advantageous in terms of miniaturization compared to the first embodiment.

[0087] <Third Embodiment> FIG. 7 shows a method for manufacturing a semiconductor device APR according to the third embodiment. In the semiconductor device APR of the third embodiment, the regions exposed on the photoresist film 111 are different. In the semiconductor device APR of the third embodiment, the same photomasks PML and PMR as those in the second embodiment can be used.

[0088] FIG. 7(a) shows the pattern on the photomask used when exposing the left region SL. FIG. 7(b) shows the left exposure pattern 111L exposed on the photoresist film 111. FIG. 7(c) shows the pattern on the photomask used when exposing the right region SR. FIG. 7(d) shows the right exposure pattern 111R exposed on the photoresist film 111.

[0089] In the third embodiment, the relationship of Mc’&Mc” < Md&Me is satisfied. In the third embodiment, the relationship of Ma&Mb < Mc’&Mc” ≤ Mc ≤ Md&Me is satisfied. Also, in the third embodiment, the relationship of Wa&Wb < Wc’&Wc” < Wc ≤ Wd&We is satisfied.

[0090] In the third embodiment, as shown in FIG. 7(a), in the region corresponding to the intermediate region SC and a part of the region corresponding to the left region SL, the pattern width on the photomask PML is partially narrowed. As a result, as shown in FIG. 7(b), the left exposure pattern 111L exposed on the photoresist film 111 has a width Mc’ in the intermediate region SC that is exposed thinner than the width Md in the left region SL outside the intermediate region SC. Also, the end of the left region SL on the side of the intermediate region SC is exposed with a width Mc’. Also, in the third embodiment, as shown in FIG. 7(c), in the region corresponding to the intermediate region SC and a part of the region corresponding to the right region SR, the pattern width on the photomask PMR is partially narrowed. As a result, as shown in FIG. 7(d), the right exposure pattern 111R exposed on the photoresist film 111 has a width Mc” in the intermediate region SC that is exposed thinner than the width Me in the right region SR outside the intermediate region SC. Also, the end of the right region SR on the side of the intermediate region SC is exposed with a width Mc”. Similar to the second embodiment, due to the effect of double exposure in the intermediate region SC, Mc’&Mc” < Mc may occur.

[0091] Also, in the third embodiment, the distance between the B-B' line and the C-C' line is different from that in the second embodiment. Under such a relationship, by setting the widths Mc' and Mc" of the exposure pattern in the intermediate region SC to suitable values, as shown in FIG. 7(e), it is possible to make the dimensions of the latent image pattern in the intermediate region SC closer to the dimensions of the latent image pattern in the regions other than the intermediate region SC.

[0092] <Fourth Embodiment> FIG. 8 shows a method for manufacturing the semiconductor device APR of the fourth embodiment. The semiconductor device APR of the fourth embodiment has a different region exposed on the photoresist film 111. In the semiconductor device APR of the fourth embodiment, the same photomasks PML and PMR as those in the second embodiment can be used.

[0093] FIG. 8(a) shows the pattern on the photomask used when exposing the left region SL. FIG. 8(b) shows the left exposure pattern 111L exposed on the photoresist film 111. FIG. 8(c) shows the pattern on the photomask used when exposing the right region SR. FIG. 8(d) shows the right exposure pattern 111R exposed on the photoresist film 111.

[0094] In the fourth embodiment, the relationship of Mc'&Mc" < Md&Me is satisfied. In the fourth embodiment, the relationship of Ma&Mb < Mc'&Mc" ≦ Mc ≦ Md&Me is satisfied. Also, in the fourth embodiment, the relationship of Wa&Wb < Wc ≦ Wd&We is satisfied.

[0095] In the fourth embodiment, as shown in Fig. 8(a), in the region corresponding to the end portion on the right region SR side of the intermediate region SC, the pattern width on the photomask PML is partially narrowed. As a result, as shown in Fig. 8(b), the left exposure pattern 111L exposed on the photoresist film 111 is exposed with a width Mc' on the right region SR side of the intermediate region SC being narrower than the width Md on the left region SL outside the intermediate region SC. Also, in the fourth embodiment, as shown in Fig. 8(c), in the region corresponding to the end portion on the left region SL side of the intermediate region SC, the pattern width on the photomask PMR is partially narrowed. As a result, as shown in Fig. 8(d), the right exposure pattern 111R exposed on the photoresist film 111 is exposed with a width Mc'' on the left region SL side of the intermediate region SC being narrower than the width Me on the right region SR outside the intermediate region SC.

[0096] Also, in the fourth embodiment, the distance between the B - B' line and the C - C' line is different from that in the second embodiment. Under such a relationship, by setting the widths Mc', Mc'' of the exposure patterns in the intermediate region SC to suitable values, as shown in Fig. 8(e), it is possible to make the dimensions of the latent image patterns in the intermediate region SC approach the dimensions of the latent image patterns in the regions outside the intermediate region SC. Note that in Fig. 8(e), the illustration of the regions where no latent image is formed by only the left exposure shot L or only the right exposure shot R as described above, and where latent images are formed due to the influence of acid or double exposure of diffracted light, is omitted. Also, in Fig. 8(e), the case of Ma & Mb < Mc' & Mc'' < Mc < Md & Me is illustrated, but the width Mc may be formed equal to the width Md or the width Me, i.e., Wc = Wd & We. In this case, in the vicinity of the B - B' line and the C - C' line which are the ends of the intermediate region SC, portions thicker than the width Md or the width Me may be formed.

[0097] <Fifth Embodiment> Fig. 9 shows the manufacturing method of the semiconductor device APR of the fifth embodiment. The semiconductor device APR of the fifth embodiment has different regions exposed on the photoresist film 111. In the semiconductor device APR of the fifth embodiment, the same photomasks PML and PMR as those in the second embodiment can be used.

[0098] In the fifth embodiment, the relationship of Mc’&Mc”<Md&Me is satisfied. In the fifth embodiment, the relationship of Ma&Mb<Mc’&Mc”<Mc<Md&Me, or Ma&Mb<Mc’&Mc”<Md&Me<Mc is satisfied. Also, in the fifth embodiment, the relationship of Wa&Wb<Wc<Wd&We, or Wa&Wb<Wd&We<Wc is satisfied.

[0099] In the fifth embodiment, in the second embodiment, a case where there is a misalignment in the photomasks of the left region SL and the right region SR is shown. Fig. 9(e) shows a state in which the right exposure shot R is misaligned in the vertical direction on the drawing and exposed with respect to the left exposure shot L.

[0100] In this embodiment, by making the width Md thicker than the width Ma, it is possible to suppress the disconnection of the wiring 110 in the intermediate region SC even when the photomask is misaligned in this way. Further, in the left region SL and the right region SR where there is no influence of the photomask misalignment, fine patterns with widths Ma and Mb can be formed.

[0101] Note that in Fig. 9(e), the illustration of the region where a latent image cannot be formed by only the left exposure shot L or only the right exposure shot R as described above, and where a latent image can be formed due to the influence of acid or double exposure of diffracted light is omitted. In this embodiment, the region where a latent image can be formed due to the influence of acid generated within the double exposure region is outside the exposure portions 111Lc and 111Rc. Also, in this embodiment, since the photomasks of the left region SL and the right region SR are misaligned in the vertical direction on the drawing, there is almost no effect of forming a latent image due to double exposure of diffracted light.

[0102] Also, in the fifth embodiment, due to the misalignment of the photomasks in the left region SL and the right region SR, in the intermediate region SC, the area of the double-exposed region is reduced compared to the case where there is no misalignment of the photomask, so the integrated exposure amount in the double-exposed region decreases. For this reason, the amount of acid generated in the double-exposed region decreases. Also, the region double-exposed by the diffracted light from the left exposure shot L and the diffracted light from the right exposure shot R decreases. Due to these effects, the width of the latent image pattern in the intermediate region SC can become narrower compared to the case where there is no misalignment of the photomasks in the left region SL and the right region SR.

[0103] Also, in the fifth embodiment, due to the misalignment of the photomasks in the left region SL and the right region SR, in the intermediate region SC, the width of the region exposed by the amount of misalignment can become wider. Due to this effect, the width of the latent image pattern in the intermediate region SC can become wider compared to the case where there is no misalignment of the photomasks in the left region SL and the right region SR. In the fifth embodiment, whether the relationship is Ma&Mb<Mc’&Mc”<Mc<Md&Me, or Ma&Mb<Mc’&Mc”<Md&Me<Mc depends on which of the effects of the width of the latent image pattern in the intermediate region SC becoming narrower and the width becoming wider appears stronger as described above.

[0104] <Sixth Embodiment> The sixth embodiment is applicable to any of the first to fifth embodiments. Fig. 11(a) shows the relationship between the enlarged views of the A-A' line, B-B' line, and C-C' lines in a certain range S within the product region DR in Fig. 1(c) and the wiring 110. Thus, depending on the pattern, for example, to avoid the pattern, the A-A' line, B-B' line, and C-C' lines may be meandered.

[0105] FIG. 11(b) shows a case where the A-A' line, the B-B' line, and the C-C' line are straight lines for the same wiring 110 as in FIG. 11(a). In the situation shown in this figure, a pattern P1 occurs that crosses the A-A' line but does not reach the B-B' line. In this case, the integrated exposure amount in the double exposure area is compared with a pattern P2 that crosses the A-A' line and extends to the right side of the B-B' line. The line width of the pattern P1 is LP1, the double exposure area is E1, the line width of the pattern P2 is LP2, and the double exposure area is E2. Even if LP1 and LP2 are equal, the areas of the areas E1 and E2 are different. Therefore, the integrated exposure amount in the double exposure area differs between the patterns P1 and P2, and the line width of the double exposure part differs between the patterns P1 and P2. Therefore, by avoiding such pattern P1 by meandering along lines A-A', B-B', and C-C' as shown in Figure 11(a), it is possible to avoid dividing pattern P1 into a photomask used for exposing the left region SL and a photomask used for exposing the right region SR.

[0106] Seventh embodiment Fig. 11 shows a cross-sectional view of the semiconductor device APR manufactured by the manufacturing method of this embodiment. Fig. 2 shows a plan view of the semiconductor device APR manufactured by the manufacturing method of this embodiment. Figs. 11(c) and (d) are diagrams showing cross-sectional views of the semiconductor device APR of this embodiment. Fig. 11(c) shows a cross-sectional view on the division center line A-A' in Figs. 2(a) and (b). Fig. 11(d) shows a cross-sectional view of a region away from the division center line A-A'.

[0107] The semiconductor device APR uses a silicon layer as the semiconductor layer 100, and on the semiconductor layer 100, an element function layer (not shown) in which a photoelectric conversion section, a transistor, an isolation structure, and the like are formed is formed.

[0108] The element functional layer may be formed by divided exposure, or may be formed by one-shot exposure in an exposure apparatus with a lower resolution and a wider maximum exposure area. In addition, among the multiple photolithography steps required for forming the element functional layer, these may be used according to the degree of fineness.

[0109] An interlayer insulating film 101 made of silicon oxide is formed on the element functional layer, and a contact plug made of tungsten is formed in the interlayer insulating film 101. A first insulator film 103 made of silicon carbide and a second insulator film 104 made of silicon oxide and serving as an interlayer insulating film are formed on the interlayer insulating film 101. Wiring 110 made of copper is formed on the first insulator film 103 and the second insulator film 104 serving as an interlayer insulating film.

[0110] As shown in Fig. 11(c), the wiring 110 includes a portion on the dividing center line A-A' where the wiring 110 is formed with width Wc and interval Dc. Also, as shown in Fig. 11(d), the wiring 110 includes a portion in a region away from the dividing center line A-A' where the wiring 110 is formed with width Wb and interval Db. Here, width Wc is larger than width Wa, and interval Dc is larger than interval Db.

[0111] Eighth embodiment FIG. 12 illustrates an apparatus 9191 including a semiconductor device 930. The eighth embodiment 9 can be applied to any of the first to seventh embodiments. FIG. 12(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 of this embodiment. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 has the structural and / or manufacturing method features described for the semiconductor device APR. The semiconductor device 930 has a central portion 901 in which the circuit units 900 are arranged, and a peripheral portion 902 located around the central portion 901. The pixel portion 11 described in FIG. 1 corresponds to the central portion 901, and the signal processing circuit 12 described in FIG. 1 is provided in the peripheral portion 902. The semiconductor device 930 includes a semiconductor device 910, and the semiconductor device 910 has a semiconductor layer 100 included in the semiconductor device APR. The semiconductor device 930 can include a package 920 that accommodates the semiconductor device 910 in addition to the semiconductor device 910 having the semiconductor layer 100. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910.

[0112] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, an image device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, a mirror, or a filter. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0113] The processing device 960 processes a signal output from the semiconductor device 930 or a signal input to the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for configuring an AFE (analog front end) or a DFE (digital front end).

[0114] The imaging device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930 when the semiconductor device 930 is a photoelectric conversion device (imaging device). When the semiconductor device 930 is a display device, the imaging device 970 can be a photoelectric conversion device (imaging device) that captures an image to be displayed on the semiconductor device 930.

[0115] The storage device 980 is a magnetic device or a semiconductor device that stores information (images) handled by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0116] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0117] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0118] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or office equipment such as a copier or printer.

[0119] According to the above-described embodiment, it is possible to form good wiring. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0120] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment 9191 can also be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device. EXAMPLES

[0121] [Example 1] Example 1 will be described in which the wiring 110 is formed using an exposure apparatus with an ArF light source having a wavelength of 193 nm and a maximum exposure area of ​​26 mm×33 mm. In Example 1, in the form of FIG. 5 shown as the first embodiment, the width Ma and width Mb are set to 120 nm, the width Mc' and width Mc" are set to 230 nm, and the width Md and width Me are set to 230 nm. Also, the length of the portion exposed with the width Mc' and width Mc", that is, the length from the line B-B' to the line C-C', is set to 200 nm. Also, the length of the portion exposed with the width Md and width Me is set to 200 nm. This corresponds to i) in FIGS. 10(a) and (b). As a result, the wiring 110 can be formed with the width Wa and width Wb of 120 nm, the width Wc of 290 nm, and the width Wd and width We of 230 nm. This corresponds to i) in FIG. 10(c).

[0122] Here, the distance Da and the distance Db shown in Fig. 2 are 120 nm, and the distance Dc is 170 nm. As in the embodiment shown in Fig. 9 as the fifth embodiment, the photomask PML and the photomask PMR may be misaligned in the y direction. The photomask PML and the photomask PMR may also be misaligned in the x direction in Fig. 2. The amount of misalignment between the photomask PML and the photomask PMR is up to 60 nm, and is highly likely to cause no breaks or shorts in the wiring Q1, the wiring Q2, and the wiring Q3 when the photomask PML and the photomask PMR are misaligned in the y direction in Fig. 2.

[0123] When the photomasks PML and PMR are misaligned by 60 nm in the y direction in Fig. 2, the distance Dc shown in Fig. 2 becomes 120 nm. If the misalignment amount is greater than this, the distance Dc shown in Fig. 2 becomes smaller than the distances Da and Db shown in Fig. 2, and there is a high possibility that a short circuit will occur at the distance Dc shown in Fig. 2.

[0124] In this embodiment, the length of the portions exposed to widths Md and Me is set to 200 nm. Therefore, even if the photomask PML and photomask PMR are misaligned in the x direction in FIG. 2, changing the area of ​​the double exposure region and changing the integrated exposure amount within the double exposure region, the influence of this change can be reduced from reaching the regions exposed to widths Ma and Mb.

[0125] [Example 2] Example 2 will be described in which the wiring 110 is formed using an exposure apparatus with an ArF light source having a wavelength of 193 nm and a maximum exposure area of ​​26 mm×33 mm. In Example 2, in the form of FIG. 6 shown as the second embodiment, the width Ma and width Mb are set to 120 nm, the width Mc' and width Mc" are set to 180 nm, and the width Md and width Me are set to 230 nm. Also, the length of the portion exposed with the width Mc' and width Mc", that is, the length from the line B-B' to the line C-C', is set to 200 nm. Also, the length of the portion exposed with the width Md and width Me is set to 200 nm. This corresponds to ii) in FIG. 10(a) and (b). As a result, the wiring 110 having the width Wa and width Wb of 120 nm and the width Wc, width Wd, and width We of 230 nm can be formed. This corresponds to ii) in FIG. 10(c). Here, the distance Da and the distance Db shown in Fig. 2 are 120 nm, and the distance Dc is 230 nm. As in the embodiment shown in Fig. 9 as the fifth embodiment, the photomask PML and the photomask PMR may be misaligned in the y direction. The photomask PML and the photomask PMR may also be misaligned in the x direction in Fig. 2. The amount of misalignment between the photomask PML and the photomask PMR is up to 95 nm, and is highly likely to cause no breaks or shorts in the wiring Q1, the wiring Q2, and the wiring Q3 when the photomask PML and the photomask PMR are misaligned in the y direction in Fig. 2.

[0126] When the photomasks PML and PMR are misaligned by 95 nm in the y direction in Fig. 2, the distance Dc shown in Fig. 2 becomes 120 nm. If the misalignment amount is greater than this, the distance Dc shown in Fig. 2 becomes smaller than the distances Da and Db shown in Fig. 2, and there is a high possibility that a short circuit will occur at the distance Dc shown in Fig. 2.

[0127] In this embodiment, the length of the portions exposed to widths Md and Me is set to 200 nm. Therefore, even if the photomask PML and photomask PMR are misaligned in the x direction in FIG. 2, changing the area of ​​the double exposure region and changing the integrated exposure amount within the double exposure region, the influence of this change can be reduced from reaching the regions exposed to widths Ma and Mb.

[0128] [Example 3] Example 3 will be described in which the wiring 110 is formed using an exposure device using a KrF light source with a wavelength of 248 nm and a maximum exposure area of ​​26 mm×33 mm. In Example 3, in the form shown in FIG. 6 as the second embodiment, the width Ma and width Mb are set to 140 nm, the width Mc' and width Mc" are set to 180 nm, and the width Md and width Me are set to 240 nm. Also, the length of the portion exposed with the width Mc' and width Mc", that is, the length from the line B-B' to the line C-C', is set to 300 nm. Also, the length of the portion exposed with the width Md and width Me is set to 150 nm. This corresponds to ii) in FIGS. 10(a) and (b). As a result, the wiring 110 having the width Wa and width Wb of 140 nm and the width Wc, width Wd, and width We of 240 nm can be formed. This corresponds to ii) in FIG. 10(c). Here, the distance Da and the distance Db shown in Fig. 2 are 140 nm, and the distance Dc is 240 nm. As in the embodiment shown in Fig. 9 as the fifth embodiment, the photomask PML and the photomask PMR may be misaligned in the y direction. The photomask PML and the photomask PMR may also be misaligned in the x direction in Fig. 2. The amount of misalignment between the photomask PML and the photomask PMR is up to 80 nm, and is highly likely to cause no breaks or shorts in the wiring Q1, the wiring Q2, and the wiring Q3 when the photomask PML and the photomask PMR are misaligned in the y direction in Fig. 2.

[0129] When the photomasks PML and PMR are misaligned by 80 nm in the y direction in Fig. 2, the distance Dc shown in Fig. 2 becomes 140 nm. If the misalignment amount is greater than this, the distance Dc shown in Fig. 2 becomes smaller than the distances Da and Db shown in Fig. 2, and there is a high possibility that a short circuit will occur at the distance Dc shown in Fig. 2.

[0130] In this embodiment, the length of the portions exposed to widths Md and Me is set to 150 nm. Therefore, even if the photomask PML and photomask PMR are misaligned in the x direction in FIG. 2, changing the area of ​​the double exposure region and changing the integrated exposure amount within the double exposure region, the influence of this change can be reduced from reaching the regions exposed to widths Ma and Mb.

[0131] [Example 4] Example 4 will be described in which the wiring 110 is formed using an exposure apparatus with an ArF light source having a wavelength of 193 nm and a maximum exposure area of ​​26 mm×33 mm. In Example 4, in the form of FIG. 6 shown as the second embodiment, the width Ma and width Mb are set to 120 nm, the width Mc' and width Mc" are set to 120 nm, and the width Md and width Me are set to 230 nm. Also, the length of the portion exposed with the width Mc' and width Mc", that is, the length from the line B-B' to the line C-C', is set to 200 nm. Also, the length of the portion exposed with the width Md and width Me is set to 200 nm. This corresponds to iii) in FIG. 10(a) and (b). As a result, the wiring 110 having the width Wa and width Wb of 120 nm, the width Wc of 160 nm, and the width Wd and width We of 230 nm can be formed. This corresponds to iii) in FIG. 10(c). Here, the distance Da and the distance Db shown in Fig. 2 are 120 nm, and the distance Dc is 300 nm. Also, as in the embodiment of Fig. 9 shown as the fifth embodiment, the photomask PML and the photomask PMR may be misaligned in the y direction. Also, the photomask PML and the photomask PMR may be misaligned in the x direction of Fig. 2. The amount of misalignment of the photomask PML and the photomask PMR in the y direction of Fig. 2 is the maximum amount of misalignment that is likely to result in no breaks or shorts in the wiring Q1, the wiring Q2, and the wiring Q3.

[0132] When the photomasks PML and PMR are misaligned by 120 nm or more in the y direction in FIG. 2, the exposed portions 111Lc and 111Rc will no longer overlap, increasing the possibility of breaks in the wiring Q1, wiring Q2, and wiring Q3.

[0133] <Ninth embodiment> Hereinafter, the present embodiment will be described with reference to the drawings. In the following description and drawings, common reference numerals are used to designate components common to multiple drawings. Therefore, the common components will be described with mutual reference to multiple drawings, and descriptions of the components with common reference numerals will be omitted as appropriate.

[0134] FIG. 13 shows a photoelectric conversion device as an example of the semiconductor device APR. The photoelectric conversion device is, for example, a CMOS image sensor, and can be used in an imaging device, a distance measuring device, a photometer, and the like. The semiconductor device APR as a photoelectric conversion device is a semiconductor device having a plurality of wirings 110 each having a damascene structure on a semiconductor layer 100. The semiconductor device APR has a pixel section 11 in which unit pixels including photoelectric conversion elements are arranged two-dimensionally in m rows and n columns, and a signal processing circuit 12 formed around the pixel section. The semiconductor device APR has a size equal to or larger than the maximum exposure area of ​​an exposure device (exposure machine), and cannot be manufactured by one-shot exposure with such an exposure device. Therefore, the device area is divided into adjacent left and right areas, and is manufactured using a divided exposure technique in which each area is exposed separately. For example, the wiring layer may be formed by divided exposure. Hereinafter, the direction toward the center of the semiconductor device APR on a plane is called the inner periphery side, and the opposite direction is called the outer periphery side.

[0135] 13(b) is a plan view showing a plurality of device regions DR formed on the wafer WF. The dimensions of each device region DR are larger than the maximum exposure area of ​​the exposure tool. Each device region DR is divided into regions having dimensions equal to or smaller than the maximum exposure area of ​​the exposure tool, and is formed by dividing the regions into regions and exposing them individually.

[0136] FIG. 13(c) shows a conceptual diagram of one device region DR. The device region DR is divided into at least a left region SL and a right region SR with respect to the line A-A', and each of the left region SL and the right region SR is exposed with a different photomask. Hereinafter, the line A-A' may be referred to as the division center line. The left region SL is defined as the region from the left end to the line C-C', and the right region SR is defined as the region from the right end to the line B-B'. Hereinafter, the line C-C' may be referred to as the right end of the left region, and the line B-B' may be referred to as the left end of the right region. The intermediate region SC sandwiched between the line B-B' and the line C-C' is exposed when the left region SL is exposed, and may also be exposed when the right region SR is exposed. In this way, the exposure overlaps in the intermediate region SC, so the intermediate region SC can also be referred to as an overlap region. In this embodiment, the device region DR is divided into two regions for explanation, but the number of divisions may be three or more. Although the following example shows a case where the image is divided into left and right portions for convenience, the direction of division is arbitrary, and the image may be divided into top and bottom portions.

[0137] The semiconductor device APR shown in Fig. 13(a) is formed on a wafer WF with a plurality of device regions DR arranged two-dimensionally as shown in Fig. 13(b), and after additional manufacturing steps, is divided into individual semiconductor devices (chips) by dicing. The semiconductor device APR includes at least this semiconductor device (chip). As described later, the semiconductor device APR may include a package that houses the semiconductor device in addition to the semiconductor device.

[0138] 13(c) shows the dimensions of the device region DR of the semiconductor device APR manufactured by the manufacturing method of this embodiment. The vertical length W1 of the semiconductor device APR is 33 mm or less, and the horizontal length W2 is greater than 33 mm. For example, the vertical length W1 of the device region DR is 32 mm, and the horizontal length W2 is 42 mm. Therefore, an exposure tool with a maximum exposure area of ​​26 mm×33 mm cannot expose the device region DR in one go.

[0139] Therefore, the distance W2L between the reference line A-A' dividing the device region DR into the left region SL and the right region SR and the left end of the device region DR is set to 26 mm or less, for example, 21 mm. The distance W2R between the line A-A' and the right end of the device region DR is set to 26 mm or less, for example, 21 mm. The distance W3 from the line A-A' to the line B-B' is set to 10 to 1000 nm, preferably 50 to 500 nm, for example, 100 nm. The distance W4 from the line A-A' to the line C-C' is set to 10 to 1000 nm, preferably 50 to 500 nm, for example, 100 nm.

[0140] Since the length W1 is 33 mm or less and the sum of the distances W2L and W3 is 26 mm or less, the left area SL and the middle area SC can be exposed with an exposure device having a maximum exposure area of ​​26 mm×33 mm.

[0141] Furthermore, since the length W1 is 33 mm or less and the sum of the distances W2R and W4 is 26 mm or less, the right side region SR and the middle region SC can be exposed with an exposure device having a maximum exposure area of ​​26 mm×33 mm.

[0142] Therefore, a semiconductor device APR having a length W1 of 33 mm or less and a length W2 of more than 33 mm can be exposed using an exposure tool with a maximum exposure area of ​​26 mm×33 mm, with the number of divisions of the device area DR set to two.

[0143] In this example, the distances W2L and W2R are equal, but they do not have to be equal. Also, the lines A-A', B-B', and C-C' are straight lines, but they may be appropriately meandering depending on the pattern in the device area as long as the sum of the distances W2L and W3 does not exceed the maximum exposure area.

[0144] In an exposure device with a maximum exposure area of ​​26 mm×33 mm, the peripheral portion of the maximum exposure area may have a lower resolution than the central portion, so even if the exposure device has a maximum exposure area of ​​26 mm×33 mm, exposure may be performed using only a portion of the maximum exposure area. In such a case, divided exposure can be applied even to a semiconductor device APR with a size smaller than 26 mm×33 mm. In other words, there is no particular limit to the size of the semiconductor device APR to which divided exposure in this embodiment is applied.

[0145] The dimensions of the pixel section 11 in Fig. 13(a) are 36±1 mm × 24±1 mm for a so-called 35 mm full-size image sensor. Fig. 13(c) shows row wiring of the pixel section 11 among a plurality of wirings 110 in the semiconductor device APR. The row wiring is a global wiring commonly connected to a group of pixels included in one pixel row. The row wiring is, for example, a signal line that transmits an input signal (control signal) to a group of pixels included in one pixel row. The row wiring is a power line that supplies power (power supply potential or ground potential) to a group of pixels included in, for example, one pixel row. The column wiring is a global wiring that crosses the row wiring and is commonly connected to a group of pixels included in one pixel column. The row wiring and the column wiring must extend at least from one end to the other end of the pixel section 11. Therefore, the distance from one end to the other end of the row wiring must be longer than the horizontal width of the pixel section (36±1 mm), and the distance from one end to the other end of the column wiring may be longer than the horizontal width of the pixel section (24±1 mm). The column wiring is a signal line that transmits an output signal (pixel signal) from a group of pixels included in, for example, one pixel column. The column wiring is a power line that supplies power (power supply potential or ground potential) to a group of pixels included in, for example, one pixel column. These row wirings and column wirings can be assigned to any of the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer arranged in order from the side closest to the semiconductor layer 100. The first wiring layer may have a single damascene structure, and the second wiring layer, the third wiring layer, and the fourth wiring layer may have a dual damascene structure. The power supply line as the global wiring (column wiring) may be arranged, for example, in the first wiring layer and / or the second wiring layer. The signal line as the global wiring (row wiring) may be arranged, for example, in one of the third wiring layer and the fourth wiring layer (typically the third wiring layer). The signal line as the global wiring (column wiring) may be arranged, for example, in the other of the third wiring layer and the fourth wiring layer (typically the fourth wiring layer). In addition, local wiring may be arranged in each wiring layer, and particularly many local wirings may be arranged in the first wiring layer. Here, an example having four wiring layers has been described, but for example, the second wiring layer may be omitted, and local wiring and power supply lines may be arranged in the first wiring layer. The allocation of global wiring to wiring layers is not limited to these, but considering these relationships, wiring having a length exceeding 33 mm may be a power supply line (row wiring) having a single damascene structure or a signal line (row wiring) having a dual damascene structure.

[0146] 19(a) and (b) show cross-sectional views of the semiconductor device APR of this embodiment. FIG. 19(a) and (b) are diagrams showing cross-sectional views of the semiconductor device APR of this embodiment. FIG. 19(a) shows a cross-sectional view on the division center line A-A' of FIG. 14(a) and (b). FIG. 19(b) shows a cross-sectional view of a region away from the division center line A-A'. The semiconductor device APR uses a silicon layer as the semiconductor layer 100, and an element functional layer (not shown) in which a photoelectric conversion section, a transistor, an isolation structure, and the like are formed is formed on the semiconductor layer 100. The element functional layer may be formed by division exposure, or may be formed by one-shot exposure in an exposure device with a lower resolution and a wider maximum exposure area. In addition, among the multiple photolithography processes required for forming the element functional layer, they may be used according to the degree of fineness. An interlayer insulating film 101 made of silicon oxide is formed on the element functional layer, and a contact plug made of tungsten is formed in the interlayer insulating film 101. Then, on the interlayer insulating film 101, an insulating film 103 made of silicon carbide and an insulating film 104 made of silicon oxide that will become an interlayer insulating film are formed. Wiring 110 made of copper is formed on the insulating film 103 and the insulating film 104 that will become an interlayer insulating film. As shown in FIG. 19(a), the wiring 110 includes a portion on the middle region SC where the wiring 110 is formed with a width Wc and a distance Dc. Also, as shown in FIG. 19(b), the wiring 110 includes a portion on the left region SL and the right region SR where the wiring 110 is formed with a width Wh and a distance Dh. Here, the width Wc is larger than the width Wh, and the distance Dc is larger than the distance Dh, but is not limited to this.

[0147] FIG. 14 shows a plan view of a plurality of wirings 110 in the semiconductor device APR. Each of the wirings Q1, Q2, and Q3 has a damascene structure. The wirings Q1 and Q2 are adjacent to each other, and the wirings Q2 and Q3 are adjacent to each other. The distance between one end Ea and the other end Eb of the wiring Q2 is greater than 33 mm. As described above, the distance between one end Ea and the other end Eb of the wiring Q2 can be 36±1 mm or more. Here, the one end Ea and the other end Eb of the wiring Q2 have been described, but the same applies to the one ends Ea and the other ends Eb of the wirings Q1 and Q3.

[0148] Each of the wirings Q1, Q2, and Q3 has a portion Ph, a portion Pm, and a portion Pc between the portion Ph and the portion Pm in the direction in which the wirings Q1, Q2, and Q3 extend. Here, the portion Ph and the portion Pm are set so that the distance between the portion Ph and the portion Pm is greater than 33 mm. In each of the wirings Q1, Q2, and Q3, the width Wmax of the portion Pc is the maximum width of the wirings Q1, Q2, and Q3 in the range from the portion Ph to the portion Pm. The wirings Q1, Q2, and Q3 may include a portion (not shown) having a width Wmax' that exceeds the width Wmax of the portion Pc outside the range from the portion Ph to the portion Pm. In other words, the maximum width Wmax' of the wirings Q1, Q2, and Q3 in the entire wirings Q1, Q2, and Q3 may be greater than the width Wmax of the portion Pc (Wmax'>Wmax) or may be equal to the width Wmax of the portion Pc (Wmax'=Wmax). In other words, the wirings Q1, Q2, and Q3 should not exceed the width Wmax of the portion Pc over a length of at least 33 mm. In this example, the portion Pc is located within the range AA, but the portion Pc may be located anywhere between the portions Ph and Pm. Typically, the portion Ph is located in the left region SL, the portion Pm is located in the right region SR, and the portion Pc is located in the middle region SC.

[0149] FIG. 19(a) shows a cross section (cross section along line E-E' in FIG. 14(a)) of a portion having a structure equivalent to portion Pc in FIG. 14(a). FIG. 19(a) shows the maximum width Wmax of wirings Q1, Q2, and Q3 as width Wc (Wmax=Wc). The thickness of the portion having the maximum width Wmax of wirings Q1, Q2, and Q3 as thickness Tc. FIG. 19(b) shows a cross section (cross section along line F-F' in FIG. 14(a)) of a portion having a structure equivalent to portion Ph in FIG. 14(a). The width of portion Ph of wirings Q1, Q2, and Q3 is shown as width Wh. Note that width Wm of portion Pm of wirings Q1, Q2, and Q3 may be the same as width Wh or may be different. Since width Wc of portion Pc is the maximum width Wmax from portion Ph to portion Pm, width Wc does not exceed width Wh and Wm. The width Wc may be larger than the width Wh and the width Wm (Wc>Wh&Wm), but the width Wc may be the same as the width Wh and the width Wm (Wc=Wh&Wm). Here, the maximum width Wmax is preferably smaller than 230 nm. It is more preferable that the maximum width Wmax is smaller than 180 nm. In order to suppress an increase in the resistance of the wirings Q1, Q2, and Q3, it is more preferable that the maximum width Wmax is larger than 65 nm. The maximum width Wmax may be 90 nm or more, and may be 120 nm or more. By making the width of the wirings Q1, Q2, and Q3 less than 230 nm in the range from the portion Ph to the portion Pm, it is possible to miniaturize the wirings Q1, Q2, and Q3. As shown in FIG. 19(a), it is preferable that the thickness Tc of the portion Pc is larger than the width Wh of the portion Ph and the width Wm of the portion Pm (Tc>Wh&Wm). By making the thickness Tc of the portion Pc larger than the width Wh or width Wm, even if the wirings Q1, Q2, Q3 are miniaturized (reduced in width), an increase in the resistance of the wirings Q1, Q2, Q3 can be suppressed. FIG. 19(a) shows the thickness Th of the portion Ph. In this example, the thickness Th is equal to the thickness Tc (Tc=Th), but the thickness Th may be larger than the thickness Tc, or the thickness Th may be smaller than the thickness Tc. Similarly, the thickness Tm of the portion Pm may be larger than the thickness Tc, or the thickness Th may be smaller than the thickness Tc. It is preferable that the thickness Th is larger than the width Wh.By making the thickness Th of the partial Ph larger than the width Wh, even if the wirings Q1, Q2, and Q3 are miniaturized (the width is made smaller), an increase in the resistance of the wirings Q1, Q2, and Q3 can be suppressed. Similarly, it is preferable that the thickness Tm is larger than the width Wm. In this example, the thickness Tm is equal to the thickness Th (Tm = Th), but the thickness Tm may be larger than the thickness Th, or the thickness Tm may be smaller than the thickness Th. In miniaturizing the wirings Q1, Q2, and Q3, the width Wh of the partial Ph and the width Wm of the partial Pm are preferably smaller than 230 nm, more preferably smaller than 180 nm, and even more preferably smaller than 140 nm. In suppressing an increase in the resistance of the wirings Q1, Q2, and Q3 having a length of 33 mm or more, the width Wh of the partial Ph and the width Wm of the partial Pm are preferably larger than 65 nm. The width Wh of the partial Ph and the width Wm of the partial Pm may be 90 nm or more, and the width Wh of the partial Ph and the width Wm of the partial Pm may be 120 nm or more. In suppressing an increase in the resistance of the wirings Q1, Q2, and Q3 having a length of 33 mm or more, the thickness Tc (the same applies to the thickness Th and / or the thickness Tm) is preferably larger than 130 nm. At least any one of the thickness Tc, the thickness Th, and the thickness Tm may be 150 nm or more, or may be 180 nm or more. The distance Dc between the wiring Q2 and the wiring Q3 in the partial Pc and the distance between the wiring Q2 and the wiring Q1 in the partial Pc are preferably smaller than the thickness Tc (Dc < Tc). The distance Dh between the wiring Q2 and the wiring Q3 in the partial Ph and the distance between the wiring Q2 and the wiring Q1 in the partial Ph are preferably smaller than the thickness Tc (Dh < Th). Similarly, the distance between the wiring Q2 and the wiring Q3 in the partial Pm and the distance between the wiring Q2 and the wiring Q1 in the partial Ph are preferably smaller than the thickness Tm.

[0150] Fig. 14(b) is an enlarged view of the range AA in Fig. 14(a). Each of the wirings Q1, Q2, and Q3 has a left portion 110a, a right portion 110b, and a middle portion 110c between the left portion 110a and the right portion 110b along the direction in which the wirings Q1, Q2, and Q3 extend. The left portion 110a is located in the left region SL, the right portion 110b is located in the right region SR, and the middle portion 110c is located in the middle region SC.

[0151] FIG. 14(b) shows the width Wa of the left portion 110a, the width Wb of the right portion 110b, and the width Wc of the middle portion 110c. Here, the width Wa and the width Wh may be equal (Wa=Wh), so the description of the width Wa in the following description is also applicable to the width Wh. Similarly, the width Wa and the width Wh may be equal (Wb=Wm), so the description of the width Wb in the following description is also applicable to the width Wm. It is also preferable that the width Wc of the middle portion 110c is larger than the width Wa of the left portion 110a and the width Wb of the right portion 110b (Wc>Wa, Wc>Wb), but the widths of the wirings Q1, Q2, and Q3 may be uniform between the portions Ph and Pm. The width Wa of the left portion 110a and the width Wb of the right portion 110b may be smaller than 230 nm. The advantageous effect in achieving miniaturization obtained by making the width Wc larger than the widths Wa and Wb can be significantly obtained when the width Wa of the left portion 110a and the width Wb of the right portion 110b are less than 230 nm. The maximum width Wmax of any of the wirings Q1, Q2, and Q3 may be 230 nm or more. When the width Wa of the left portion 110a and the width Wb of the right portion 110b are 230 nm or more, the width Wc of the middle portion 110c may be the same as or different from the width Wa of the left portion 110a and the width Wb of the right portion 110b. When the widths Wa and Wb are 230 nm or more, making the width Wc of the middle portion 110c larger than the widths Wa and Wb may be disadvantageous in achieving miniaturization. The width Wa of the left portion 110a and the width Wb of the right portion 110b may be smaller than 180 nm. The advantageous effect of making the width Wc larger than the widths Wa and Wb in realizing miniaturization can be particularly noticeable when the width Wa of the left portion 110a and the width Wb of the right portion 110b are less than 180 nm. The difference (Wc-Wa) between the width Wc of the middle portion 110c and the width Wa of the left portion 110a is preferably greater than 50 nm, which is preferable for making the width Wa of the left portion 110a smaller than 180 nm. The difference (Wc-Wb) between the width Wc of the middle portion 110c and the width Wb of the right portion 110b is preferably greater than 50 nm, which is preferable for making the width Wb of the right portion 110b smaller than 180 nm.It is preferable that the difference (Wc - Wa) between the width Wc of the middle portion 110c and the width Wa of the left portion 110a is smaller than the width Wa of the left portion 110a (Wc - Wa < Wa). It is also preferable that the difference (Wc - Wb) between the width Wc of the middle portion 110c and the width Wb of the right portion 110b is smaller than the width Wb of the right portion 110b (Wc - Wb < Wb). It is also preferable that the width Wc of the middle portion 110c is larger than 110 nm. It is also preferable that the width Wc of the middle portion 110c is larger than 180 nm. The width Wc of the middle portion 110c may be smaller than 300 nm. In this example, the width Wb is equal to the width Wa, but the width Wb may be different from the width Wa.

[0152] FIG. 14(b) shows the distance Da between the left portion 110a of the wiring Q2 and the wirings Q1, Q3, the distance Db between the right portion 110b of the wiring Q2 and the wirings Q1, Q3, and the distance Dc between the middle portion 110c of the wiring Q2 and the wirings Q1, Q3. It is preferable that the distance Dc between the middle portion 110c of the wiring Q2 and the wirings Q1, Q3 is larger than the width Wa of the left portion 110a (Dc > Wa). It is preferable that the distance Dc between the middle portion 110c of the wiring Q2 and the wirings Q1, Q3 is larger than the width Wb of the right portion 110b (Dc > Wb). It is preferable that the distance Da between the left portion 110a of the wiring Q2 and the wirings Q1, Q3 is smaller than the width Wc of the middle portion 110c (Da < Wc). It is preferable that the distance Db between the right portion 110b of the wiring Q2 and the wirings Q1, Q3 is smaller than the width Wc of the middle portion 110c (Db < Wc). In this example, the distance Db is equal to the distance Da, but the distance Db may be different from the distance Da.

[0153] FIG. 14(b) shows the length La of the left portion 110a, the length Lb of the right portion 110b, and the length Lc of the middle portion 110c along the direction in which the wirings Q1, Q2, Q3 extend. The length Lc of the middle portion 110c may be larger than the width Wa of the left portion 110a. The length Lc of the middle portion 110c may be larger than the width Wb of the right portion 110b. The length Lc of the middle portion 110c may be smaller than the length La of the left portion 110a. The length Lc of the middle portion 110c may be smaller than the length Lb of the right portion 110b.

[0154] Typically, the width Wa, the width Wb, the distance Da and the distance Db are smaller than the width Wc and the distance Dc.

[0155] An example of the case where the semiconductor device APR is applied to a photoelectric conversion device will be described. The wirings Q1, Q2, and Q3 are, for example, row wirings having a dual damascene structure. The wirings Q1, Q2, and Q3 are signal lines that transmit control signals to a pixel circuit having four transistors (transfer transistor, reset transistor, amplification transistor, and selection transistor) per pixel P. For example, the wiring Q1 is a transfer signal line that controls the transfer transistor, the wiring Q2 is a reset signal line that controls the reset transistor, and the wiring Q3 is a selection signal line that controls the selection transistor. The functions of the multiple wirings 110 and the wirings Q1, Q2, and Q3 in this embodiment are not limited to the above example.

[0156] FIG. 14(a) shows the range of a plurality of pixels P. A thick portion (thick line portion) and a thin portion (thin line portion) of the wiring are repeatedly provided for each pixel P. The left portion 110a is located between one end Ea and the middle portion 110c of the range AA along the direction in which the wirings Q1, Q2, and Q3 extend. The right portion 110b is located between the other end Eb and the middle portion 110c of the range AA along the direction in which the wirings Q1, Q2, and Q3 extend. The wirings Q1, Q2, and Q3 have a thin line portion L4 between one end Ea and the left portion 110a and a thick line portion L5 between the thin line portion L4 and the left portion 110a along the direction in which the wirings Q1, Q2, and Q3 extend. In addition, the wirings Q1, Q2, and Q3 have a thin line portion R6 between the other end Eb and the right part 110b, and a thick line portion R7 between the thin line portion R6 and the right part 110b along the direction in which the wirings Q1, Q2, and Q3 extend. The width of the thick line portion L5 is larger than the width Wa of the left part 110a, the width Wb of the right part 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion R7 is larger than the width Wa of the left part 110a, the width Wb of the right part 110b, the width of the thin line portion L4, and the width of the thin line portion R6. The width of the thick line portion L5 and the width of the thick line portion R7 are preferably equal to the width Wc, but may be different from the width Wc. The width of the thin line portion L4 and the width of the thin line portion R6 are preferably equal to the widths Wa and Wb, but may be different from the widths Wa and Wb.

[0157] In this way, by providing the thick line portion (thick line portion L5, R7) at the position corresponding to the range AA in the pixel away from the A-A' line not including the intermediate region SC, the uniformity of the wiring layout in each pixel can be improved, and the uniformity of the characteristics of each pixel can be improved. That is, the signal output difference between the pixel near the A-A' line including the intermediate region SC and the pixel away from the A-A' line not including the intermediate region can be reduced, and the occurrence of line noise along the A-A' line in the image can be suppressed. Of course, since the thick line portion L5 is on the left region SL and the thick line portion R7 is on the right region SR, the thick line portions L5, R7 have almost no function of mitigating the influence of the misalignment between the photomask at the time of exposure of the left region SL and the photomask at the time of exposure of the right region SR.

[0158] Each of the wirings Q1, Q2, and Q3 has a left-side portion 110d between the left-side portion 110a and the middle portion 110c and a right-side portion 110e between the right-side portion 110b and the middle portion 110c along the direction in which the wirings Q1, Q2, and Q3 extend. In FIG. 14(b), the width Wd of the left-side portion 110d and the width We of the right-side portion 110e are described. The width Wd of the left-side portion 110d is larger than the width Wa of the left-side portion 110a (Wd > Wa), and the width We of the right-side portion 110e is larger than the width Wb of the right-side portion 110b (We > Wb). In this example, the width Wd of the left-side portion 110d is equal to the width Wc of the middle portion (Wd = Wc). When the width Wd of the left-side portion 110d is different from the width Wc of the middle portion, the width Wd of the left-side portion 110d may be larger than the width Wc of the middle portion (Wd > Wc), but the width Wd of the left-side portion 110d is preferably smaller than the width Wc of the middle portion (Wd < Wc). Similarly, the width We of the right-side portion 110e is equal to the width Wc of the middle portion (We = Wc). When the width We of the right-side portion 110e is different from the width Wc of the middle portion, the width We of the right-side portion 110e may be larger than the width Wc of the middle portion (We > Wc), but the width We of the right-side portion 110e is preferably smaller than the width Wc of the middle portion (We < Wc). The difference (|Wc - Wd|) between the width Wc of the middle portion 110c and the width Wd of the left-side portion 110d is preferably smaller than the difference (|Wd - Wa|) between the width Wa of the left-side portion 110a and the width Wd of the left-side portion 110d (|Wc - Wd| < |Wd - Wa|). Similarly, the difference (|Wc - We|) between the width Wc of the middle portion 110c and the width We of the right-side portion 110e is preferably smaller than the difference (|We - Wb|) between the width Wb of the right-side portion 110b and the width We of the right-side portion 110e (|Wc - We| < |We - Wb|). As described above, since Wc = Wd = We can be satisfied, the relationship between the widths Wd and We and the widths Wa and Wb is applicable to the relationship between the width Wc and the widths Wa and Wb. Note that the left-side portion 110d and the right-side portion 110e can also be omitted, which is equivalent to making the width Wd of the left-side portion 110d equal to the width Wa and making the width We of the right-side portion 110e equal to the width Wb.

[0159] As shown in FIG. 14(b), wiring Q1 and wiring Q3 are arranged obliquely between the left portion 110a and the left portion 110d. This realizes the coexistence of Wa < Wc and Da < Dc. Similarly, between the right portion 110b and the right portion 110e, wiring Q1 and wiring Q3 are arranged obliquely. This realizes the coexistence of Wb < Wc and Db < Dc.

[0160] Also, by making the width Wc larger than the width Wa and the width Wb (Wc > Wa & Wb), even when the photomasks of the left region SL and the right region SR are misaligned, it is possible to suppress the disconnection of the pattern in the intermediate portion 110c. And in the left portion 110a and the right portion 110b, finer patterns can be formed. Also, by making the distance Dc larger than the distance Da and the distance Db (Dc > Da & Db), even when the photomasks of the left region SL and the right region SR are misaligned, it is possible to suppress the short - circuit of the pattern in the intermediate portion 110c.

[0161] As shown in FIG. 14(a), the wiring interval Y2 in the Y direction can be made wider than the wiring interval Y1 in the Y direction. Thereby, the wiring opening in the Y direction can be made wider, and the sensitivity of the photoelectric conversion device can be improved.

[0162] Hereinafter, a method for manufacturing a semiconductor device will be described with reference to FIGS. 15, 16, and 17. In FIGS. 15, 16, and 17, the drawing with the number (x - 1) is a cross - sectional view, and the drawing with the number (x - 2) is a plan view when the semiconductor device is viewed in plan. Here, x is an alphabet from a to j. The cross - sectional view of the number (x - 1) represents the cross - section when the plan view of the number (x - 2) is cut along the line D - D'. The line corresponding to the line D - D' is also shown in FIG. 14(b). The same hatching is given to the members common to the number (x - 1) and the number (x - 2).

[0163] As shown in the plan view of number (x-2) in each figure, the wafer WF has, in each of a plurality of device regions DR, a left region SL to the left of line C-C', a right region SR to the right of line B-B', and an intermediate region SC between the left region SL and the right region SR.

[0164] 15(a-1) and (a-2) show a step A of preparing a wafer WF including a semiconductor layer 100 and an insulator film 104 provided on the semiconductor layer 100. The wafer WF used in the manufacture of the semiconductor device APR of this embodiment includes the semiconductor layer 100 as an element functional layer. A silicon layer or a compound semiconductor layer can be used as the semiconductor layer 100. In the element functional layer, a plurality of photoelectric conversion units (not shown), a plurality of transistors (not shown), and an isolation structure (not shown) that isolates the plurality of photoelectric conversion units and the plurality of transistors at locations where they should be electrically isolated from each other are formed. The element functional layer can be formed by a known method using a known material.

[0165] An interlayer insulating film 101 is formed on the semiconductor layer 100 as an element functional layer. The interlayer insulating film 101 is formed to electrically insulate the structure in the semiconductor layer 100 as an element functional layer from layers above the interlayer insulating film 101. The interlayer insulating film 101 may be made of, for example, silicon oxide, and may be formed by a known method.

[0166] In the interlayer insulating film 101, contact plugs 102 are formed at locations where electrical conduction is required between the structure in the semiconductor layer 100 as the element functional layer and the wiring above the interlayer insulating film 101. An insulator film 103 functioning as an etching stop layer and an insulator film 104 serving as an interlayer insulating film are formed on the contact plug 102. For example, the contact plug 102 may be tungsten, the insulator film 103 may be a silicon carbide film or a silicon nitride film, and the insulator film 104 may be a silicon oxide film. Note that the silicon oxide film is a film whose main constituent elements are oxygen and silicon, and may contain impurities such as carbon, nitrogen, fluorine, and chlorine at a lower rate than oxygen and silicon. Similarly, the silicon nitride film is a film whose main constituent elements are nitrogen and silicon, and may contain impurities such as carbon, oxygen, fluorine, and chlorine at a lower rate than nitrogen and silicon. Similarly, the silicon carbide film is a film whose main constituent elements are carbon and silicon, and may contain impurities such as nitrogen, oxygen, fluorine, and chlorine at a lower rate than carbon and silicon. Here, regarding the composition of silicon compounds such as silicon oxide film, silicon nitride film, and silicon carbide film, light elements such as hydrogen and helium are not regarded as main constituent elements. Therefore, silicon oxide film, silicon nitride film, silicon carbide film, etc. may contain light elements such as hydrogen at a higher ratio than nitrogen and / or silicon. The insulator film 104 serving as an interlayer insulating film may be a silicon oxide film containing carbon, an organic material film, a silicon nitride film, or a silicon carbide film. The insulator film 104 may be a porous film or a low-k film. Note that these configurations do not limit this embodiment and are merely shown as examples.

[0167] 15(b-1) and (b-2) show step B of forming a mask material film 105 and a mask material film 106 on the wafer WF. The mask material film 105 and the mask material film 106 are formed on the insulator film 104 that serves as an interlayer insulating film. The mask material film 105 is composed of an inorganic material film 1051 and an organic material film 1052. For example, the inorganic material film 1051 may be a silicon nitride film, and the organic material film 1052 may be a novolac-based resin. The mask material film 105 may include an inorganic material film 1053 (not shown) provided on the organic material film 1052, and may have a laminated structure in which the organic material film 1052 is sandwiched between the inorganic material film 1053 and the inorganic material film 1051 (not shown). The inorganic material film 1053 on the organic material film 1052 may be a silicon oxide film. In this embodiment, the mask material film 105 has the above configuration, but may have another configuration. The material of the mask material film 106 may be any material different from the material of the top layer of the mask material film 105. If the material of the top layer of the mask material film 105 is the organic material film 1052, an inorganic material film may be used as the mask material film 106, for example, a silicon oxide film or a silicon nitride film. If the top layer (for example, the inorganic material film 1053) of the mask material film 105 is a silicon oxide film, an inorganic material film different from the inorganic material film 1053, for example, a silicon nitride film or a titanium nitride film, may be used as the mask material film 106. Note that the formation of the mask material film 105 may be omitted, and in that case, the mask material film 106 may be formed so as to be in contact with the insulator film 104.

[0168] 15(c-1) and (c-2) show an exposure process C in which the positive photoresist film 107 provided on the upper layer side of the insulating film 103, 104 is exposed by a left exposure shot L. The left exposure shot L exposes the photoresist film 107 on the left region SL and the middle region SC. After the positive photoresist film 107 is formed on the mask material film 106, the left exposure pattern 107H is exposed on the photoresist film 107 on the left region SL and the middle region SC using a photomask PML. The photomask PML and the wafer can be aligned using an alignment mark (not shown) formed in a layer below the mask material film 106. As shown in FIG. 15(c-2), the left exposure pattern 107H is exposed across the line A-A' up to the line B-B'. In this exposure process C, in addition to the left exposure pattern 107H, an alignment exposure pattern 107A can be formed on the photoresist film 107.

[0169] 15(d-1) and (d-2) show a developing step D in which the photoresist film 107 is developed to form a resist pattern 107L from the photoresist film 107. Since the photoresist film 107 is a positive type, the portion of the photoresist film 107 exposed in the exposure step D (left-side exposed pattern 107H) is removed in the developing step. Similarly, the exposed pattern 107A for alignment is removed to form a resist pattern 107A for alignment.

[0170] 16(e-1) and (e-2) show processing step E in which the mask material film 106 is processed using the resist pattern 107L as a mask to transfer the resist pattern to the mask material film 106. The mask material film 106 is etched using the resist pattern 107L as a mask to form a mask pattern 106L. After the mask pattern 106L is formed, the resist pattern 107L is removed. Note that an alignment mark 106A is formed in the mask material film 106 using the alignment resist pattern 107A.

[0171] 16(f-1) and (f-2) show an exposure process F in which the positive photoresist film 108 provided on the upper layer side of the insulating film 103, 104 is exposed by the right exposure shot R. The right exposure shot R exposes the photoresist film 108 on the right region SR and the middle region SC. After the positive photoresist film 108 is formed on the mask material film 106, the right exposure pattern 108M is exposed on the photoresist film 108 on the right region SR and the middle region SC using the photomask PMR. As shown in FIG. 16(f-2), the right exposure pattern 108M is exposed to the C-C' line across the A-A' line. In the exposure process F, the photomask PMR and the wafer can be aligned using the alignment mark 106A. Furthermore, the alignment between the photomask PMR and the wafer may be performed using both the alignment mark 106A and an alignment mark (not shown) formed in a layer below the mask material film 106. In this way, the positional deviation during exposure of the right region SR can be controlled with high precision for both the lower layer and the left region SL.

[0172] 16(g-1) and (g-2) show a developing step G in which the photoresist film 108 is developed to form a resist pattern 108R from the photoresist film 108. Since the photoresist film 108 is a positive type, the portion of the photoresist film 108 that is exposed in the exposure step F (right-side exposed pattern 108M) is removed by the developing step.

[0173] 17(h-1) and (h-2) show processing step H in which the mask material film 106 is processed using the resist pattern 108R as a mask to transfer the resist pattern to the mask material film 106. The mask material film 106 is etched using the resist pattern 108R as a mask to form a mask pattern 106R. A mask pattern 106LR is formed by combining the mask patterns 106L and 106R. Once the mask pattern 106R (mask pattern 106LR) is formed, the resist pattern 108R may be removed.

[0174] In this example, the right exposure shot R is performed after the left exposure shot L, but the left exposure shot L may be performed after the right exposure shot R. Details of the left exposure pattern 107L and the right exposure pattern 108R will be described later. The wavelength of the exposure light is, for example, 175 to 275 nm, and exposure light with a wavelength of 225 to 275 nm (for example, a KrF excimer laser with a wavelength of 248 nm) or exposure light with a wavelength of 175 to 225 nm (for example, an ArF excimer laser with a wavelength of 193 nm) is preferable. Using an ArF excimer laser as the exposure light is more preferable for miniaturizing the wiring. When forming wiring with a width smaller than 230 nm, the wavelength of the exposure light (exposure wavelength) used in the exposure steps C and F is preferably smaller than 230 nm.

[0175] 17(i-1) and (i-2) show a processing step I in which the insulating films 104 and 103 are processed using the mask pattern 106LR as a mask to form trenches 109 in the insulating films 104 and 103. Using the mask pattern 106LR as a mask, the mask material film 105, the insulating film 104 that serves as an interlayer insulating film, and the insulating film 103 are etched to form the trench 109. The trench 109 extends from the left region SL through the middle region SC to the right region SR. It is preferable that the depth of the trench 109 in the middle region SC is greater than the width of the trench 109. In the entire trench 109, the maximum depth of the trench 109 may be greater than the maximum width of the trench.

[0176] 17(j-1) and (j-2) show a wiring process J for forming a wiring 110 in a trench. A conductive material is filled into the trench 109 by, for example, plating. The conductive material may be, for example, copper or an alloy containing copper. After filling the conductive material, unnecessary conductive material formed on the insulator film 104 is removed by, for example, chemical mechanical polishing (CMP). Thus, a wiring 110 is formed in the trench 109. The wiring 110 extends from the left region SL through the middle region SC to the right region SR. The wiring 110 has, along the direction in which the wiring 110 extends, a left portion 110L located on the left region SL, a right portion 110R located on the right region SL, and a middle portion 110C located on the middle region SC. The wiring formed by filling the insulator film with a conductive material and removing the unnecessary conductive material in this way is called a damascene wiring, and such a process is called a damascene process. Although the application to a single damascene process has been described here, a similar technique may be applied to a dual damascene process.

[0177] Thereafter, at least one upper wiring layer (typically, a plurality of upper wiring layers) is formed. The upper wiring layer may be formed by applying the same damascene process as described above to the interlayer insulating film formed on the insulator film 104 and the wiring 110. When the semiconductor device APR is a front-illuminated photoelectric conversion device, an opening may be provided in the plurality of interlayer insulating films including the insulator film 104 after the upper wiring layer is formed. This opening forms an optical path for light to the photoelectric conversion unit. This opening can be filled with a light-transmitting material different from the insulator film 103 and / or the insulator film 104. For example, if the insulator film 103 is silicon carbide or silicon nitride and the insulator film 104 is silicon oxide, the light-transmitting material may be silicon nitride, silicon oxide, or resin.

[0178] The above describes the case where the manufacturing method of the semiconductor device is applied to the formation of wiring. The wiring layer includes wiring that transmits a power supply and a signal common to each column of the pixel section, and these wirings are arranged across the left region SL and the right region SR. By applying the divided exposure in this embodiment, the wiring in each region can be finely processed, and the portion extending between the regions can also be finely processed. The wiring connected by divided exposure can be, for example, a power supply line that supplies power to operate the pixel section or the column circuit. Alternatively, the wiring connected by divided exposure can be, for example, a signal line that supplies a control signal for controlling the operation of the pixel section or the column circuit, or a signal line that transmits an output signal from the column circuit based on the amount of light received by each pixel. However, other wirings may be connected by divided exposure. The wiring for which the manufacturing method has been described in this embodiment is a single damascene wiring by a single damascene process, but a similar method may be applied to a dual damascene wiring by a dual damascene process. Although a trench first method can be adopted for the dual damascene process, it is more advantageous to adopt a via first method in terms of fine processing.

[0179] Although the manufacturing method is described for one wiring layer, the above-mentioned embodiment may be applied to wiring layers of two or more layers. Also, the exposure apparatus used for exposure during formation may be different between the first-layer wiring and the second-layer wiring. For example, when forming the first-layer wiring, an exposure apparatus with a wavelength of 193 nm and a maximum exposure area of ​​26 mm×33 mm using an ArF light source may be used, and when forming the second-layer and subsequent wirings, an exposure apparatus with a wavelength of 248 nm and a maximum exposure area of ​​26 mm×33 mm using a KrF light source may be used. The first-layer wiring may be a single damascene wiring, and the second-layer wiring may be a dual damascene wiring. Then, a joint exposure (split exposure) using an ArF light source may be applied to the first-layer single damascene wiring, and a joint exposure (split exposure) using a KrF light source may be applied to the second-layer dual damascene wiring.

[0180] In the above embodiment, the photoresist films 107 and 108 are positive type, but the photoresist films 107 and / or 108 may be negative type. In that case, photomasks PML and PMR are used to expose the portions of the negative photoresist film corresponding to the portions where wiring is not to be formed, and the unexposed portions of the negative photoresist film are removed by a development process.

[0181] Hereinafter, the left exposure pattern 107H and the right exposure pattern 108M in the exposure step of FIG. 15 in the manufacturing method of the semiconductor device APR will be described in detail with reference to FIG.

[0182] The drawing numbered (y-1) in Fig. 18 is a plan view showing the positional relationship between the exposure pattern 107H in the left region SL and the exposure pattern 108R in the right region SR. The drawing numbered (y-2) in Fig. 18 shows a plan view when a mask pattern 106LR consisting of mask patterns 106L and 106R is formed. Here, y is an alphabet from a to c.

[0183] 18(a-1) shows a configuration in which the left exposure pattern 107H and the right exposure pattern 108M overlap in the middle region SC. At the position where the left exposure pattern 107H and the right exposure pattern 108R overlap, hatching in which the left exposure pattern 107H and the right exposure pattern 108R are overlapped is shown. As described above, this embodiment is characterized in that the left exposure pattern 107H is formed in the photoresist film 107, and the right exposure pattern 108R is formed in the photoresist film 108.

[0184] On the other hand, when the same photoresist film is exposed in the left region SL with the left exposure pattern 107H and in the right region SR with the right exposure pattern 108R, the exposure pattern is double-exposed in the middle region SC, resulting in double exposure. Line width variations caused by this double exposure may become a problem. In the middle region SC, the width of the latent image pattern may be larger than the width of the exposure pattern due to the increase in the cumulative exposure amount caused by the double exposure with the left exposure shot L and the right exposure shot R. This is because the increase in the cumulative exposure amount increases the amount of acid generated in the exposed area, and more protective group elimination reactions occur with the acid as a catalyst, expanding the area that can be dissolved in the developer. In addition, light diffraction may occur during exposure, but it may also occur due to double exposure with both the diffracted light from the left exposure shot L and the diffracted light from the right exposure shot R. Line width variations caused by double exposure can be suppressed by devising a layout such as providing an auxiliary pattern in the middle region SC. In the method of providing such an auxiliary pattern, for example, in the case of a line pattern (wiring formed with a remaining pattern), the auxiliary pattern can be arranged so that the line width becomes thicker in order to suppress line width variations caused by double exposure. At this time, in order to suppress poor resolution between the auxiliary patterns, it is desirable to secure a sufficient distance between the auxiliary patterns. In addition, in the case of a trench pattern (wiring formed by a cutout pattern), in order to suppress line width fluctuation due to double exposure, the auxiliary pattern is arranged so as to narrow the trench width. At that time, if the dimension of the auxiliary pattern is too large compared to the trench width, the trench may break, so the trench width needs to be set to a certain dimension or more. For the above reasons, there is a limit in terms of miniaturization of the pattern only by the method of arranging the auxiliary pattern. On the other hand, in this embodiment, the left region SL and the right region SR are exposed to different photoresist films to form the mask pattern 106LR. Therefore, double exposure does not occur in the intermediate region SC, and dimensional fluctuations of the pattern in the intermediate region SC can be suppressed as shown in FIG. 18(a-2), which is advantageous for miniaturizing the pattern.

[0185] FIG. 18(b-1) shows a plan view showing the positional relationship of the exposure patterns in the left region SL and the right region SR when the left region SL and the right region SR are misaligned in the X direction. FIG. 18(b-2) shows a plan view of the mask pattern 106L and the mask pattern 106R formed on the mask material film 106 in this case. In the conventional division exposure technique, the left region SL and the right region SR are exposed to the same photoresist, so that when misalignment in the X direction occurs, as shown in FIG. 18(b-1), the area of ​​the middle region SC changes. In that case, the integrated exposure amount changes in the middle region SC, so that the line width of the pattern varies, and there is a possibility that the breakage of the pattern or a short circuit between the patterns may become a problem. In order to prevent the pattern from being broken even when the line width of the pattern varies due to misalignment, an auxiliary pattern is provided in the middle region SC. However, in this method, the dimension of the pattern width becomes large in the overlapping region, which is contrary to miniaturization. On the other hand, in this embodiment, the left region SL and the right region SR are exposed to different photoresist films to form patterns. Therefore, even if the area of ​​the middle region SC changes due to misalignment in the X direction, the dimensional fluctuation of the pattern can be suppressed, which is suitable for miniaturizing the pattern (FIG. 18(b-2)).

[0186] FIG. 18(c-1) is a plan view showing the positional relationship between the exposure patterns in the left region SL and the right region SR when the left region SL and the right region SR are misaligned with each other in the Y direction. Also, in that case, a plan view of the mask patterns 106L and 106R formed on the mask material film 106 is shown in FIG. 18(c-2). Let the width of the exposure pattern 107H be Mh, the width of the exposure pattern 108M be Mm, and the alignment deviation amount in the Y direction be My. Then, the width of the wiring in the intermediate region SC is My+(Mh+Mm) / 2. The condition for no short circuit of the wiring is My<Mh&Mm. Typically, My+(Mh+Mm) / 2≒Wmax. For example, when Mh&Mm<180 nm and My<50 nm, Wmax<230 nm. When Mh&Mm<130 nm and My<100 nm, Wmax<230 nm. When Mh&Mm<130 nm and My<50 nm, Wmax<180 nm. When Mh&Mm<90 nm and My<80 nm, Wmax<170 nm. When Mh&Mm<90 nm and My<40 nm, Wmax<130 nm.

[0187] In a typical split exposure technique, the left region SL and the right region SR are exposed to the same photoresist film. Therefore, as shown in FIG. 18(c-2), when an alignment deviation in the Y direction occurs, in the intermediate region SC, the space SS between the pattern of the left region SL and the pattern of the right region becomes smaller. As a result, sufficient optical contrast required for resolution cannot be obtained in the space portion, and pattern short circuit may become a problem. On the other hand, in the present embodiment, since the left region SL and the right region SR are transferred to different photoresists, even when the distance SS between the patterns becomes smaller, the width of the portion Ps between the adjacent mask patterns 106LR is less likely to decrease. Therefore, short circuit of the wiring can be suppressed as compared with the case of transferring to the same photoresist.

[0188] As described above, in the method according to the present embodiment, since the left region SL and the right region SR are exposed to different resists, dimensional variations, pattern breakage, and short circuit between adjacent patterns can be suppressed, which is advantageous for pattern miniaturization.

[0189] The relationship between the mask pattern 106L and the resist pattern 108R will be described with reference to Figures 19(c), (d), and (e). The left diagram of Figure 19(c) is a plan view of the semiconductor device in step G, and the right diagram of Figure 19(c) is a plan view of the semiconductor device in step H. Figures 19(d) and (e) are cross-sectional views taken along line A-A' (not shown) between line C-C' and line B-B' in Figure 19(c). Line A-A' in Figures 19(d) and (e) corresponds to line A-A' shown in Figures 16(g-2) and 17(h-2). Members common to Figures 19(c) and 19(d) and (e) are marked with the same hatching. In FIG. 19(c), the hatching (diagonal lines) of the photoresist film 108 and the hatching (dots) of the mask material film 106 are overlapped to show the relationship between the resist pattern 108R and the mask pattern 106L. If the side of the mask pattern 106L formed by etching in the step E is exposed by the resist pattern 108R in the step G, the side of the mask pattern 106L may be exposed to etching in the step H. Therefore, in the intermediate region SC where the resist pattern 108R and the mask pattern 106L overlap, the side of the mask pattern 106L may be side-etched. In that case, the shape of the mask pattern 106LR may differ from the simple overlap of the exposure pattern 107H and the exposure pattern 108M. The left side of FIG. 19(c) shows the positional relationship between the mask pattern 106L and the resist pattern 108R, and the right side of FIG. 19(c) shows the shape of the mask pattern 106LR. FIG. 19(c) shows six examples (i) to (vi). Examples (i), (iii), and (v) show changes according to the amount of misalignment in the x direction as shown in FIG. 18. As in example (i), even if the misalignment in the y direction is zero, the width of the wiring may become thicker in the intermediate region SC due to the side etching of the mask pattern 106L described above. As described above, this portion may be the portion Pc having the maximum width Wmax. As shown in examples (i), (iii), and (v), the greater the amount of misalignment, the more the portion of the mask pattern 106L exposed to etching in step H. Therefore, the range in which the wiring is thicker increases.This is advantageous in terms of suppressing an increase in the resistance of the wiring, but is disadvantageous in terms of reducing the distance between adjacent wirings.

[0190] Therefore, as shown in FIG. 19(d) and (e), it is effective to arrange a side protection member SWP for protecting the side of the mask pattern 106L in the step H. The side protection member SWP exists between the opening of the resist pattern 108R and the side of the mask pattern 106L. For example, as shown in FIG. 19(d), it is preferable that the resist pattern 108R covers the side of the mask pattern 106L. Here, the side protection member SWP can be a part of the resist pattern 108R. Such a form can be formed by making the size of the opening of the resist pattern 108R smaller than the size of the opening of the mask pattern 106L. This can suppress the deformation of the mask pattern 106L in the step H. Alternatively, as shown in FIG. 19(e), the side protection member SWP may be arranged on the side of the mask pattern 106L. The side protection member SWP may be a part of the photoresist film 108 and may be a member separated from the resist pattern 108R. Alternatively, the side protection member SWP may be made of a material different from the photoresist film 108.

[0191] In examples (ii), (iv), and (vi) of FIG. 19(c), the resist pattern 108R covers the side surface of the mask pattern 106L. The resist pattern 108R is thinner in the middle region SC than other portions (portions on the right region SR). The amount of misalignment in the x direction is the same in examples (iii) and (iv), but the increase in the wiring width in the middle region SC is suppressed more in example (iv) than in example (iii). The amount of misalignment in the x direction is the same in examples (v) and (vi), but the increase in the wiring width in the middle region SC is suppressed more in example (vi) than in example (v).

[0192] This embodiment may be applied to a stacked semiconductor device APR shown in Fig. 20(a). The stacked semiconductor device APR has a structure in which a photoelectric conversion chip 21 and a peripheral circuit chip 22 are stacked. The photoelectric conversion chip 21 is a semiconductor component including a pixel array in which unit pixels including photoelectric conversion elements are arranged two-dimensionally. The peripheral circuit chip 22 is a semiconductor component having a structure in which a signal processing circuit 22L and a signal processing circuit 22R are arranged on the same substrate.

[0193] The circuits included in the signal processing circuits 22L and 22R are, for example, a Timing Generator (TG) circuit, an Analog-to-Digital Converter (ADC) circuit, and a Digital-to-Analog Converter (DAC) circuit.

[0194] The circuits included in the signal processing circuits 22L and 22R are, for example, a DFE (Digital Front End) circuit, a DSP (Digital Signal Processor) circuit, a vertical scanning circuit, and a horizontal scanning circuit. The circuits included in the signal processing circuits 22L and 22R are, for example, a SRAM (Static Random Access Memory) circuit and a DRAM (Dynamic Random Access Memory) circuit. The signal processing circuits 22L and 22R may be connected by an inter-circuit wiring layer (not shown). The dimensions of the photoelectric conversion chip 21 and the peripheral circuit chip 22 are larger than the maximum exposure area of ​​the exposure device, and the dimensions of the signal processing circuits 22L and 22R formed on the peripheral circuit chip 22 are each smaller than the maximum exposure area of ​​the exposure device. The method according to this embodiment can be applied to the pattern formation of the photoelectric conversion chip 21 and the peripheral circuit chip 22.

[0195] FIG. 20(b) illustrates an apparatus 9191 including the semiconductor device 930. FIG. 20(b) is a schematic diagram illustrating an apparatus 9191 including the semiconductor device 930 of this embodiment. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 has the structural and / or manufacturing method features described for the semiconductor device APR. The semiconductor device 930 has a central portion 901 in which the circuit units 900 are arranged, and a peripheral portion 902 located around the central portion 901. The pixel portion 11 described in FIG. 1 corresponds to the central portion 901, and the signal processing circuit 12 described in FIG. 1 is provided in the peripheral portion 902. The semiconductor device 930 includes a semiconductor device 910, and the semiconductor device 910 has a semiconductor layer 100 included in the semiconductor device APR. The semiconductor device 930 can include a package 920 that accommodates the semiconductor device 910 in addition to the semiconductor device 910 having the semiconductor layer 100. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device 910.

[0196] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, an image device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, a mirror, or a filter. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0197] The processing device 960 processes a signal output from the semiconductor device 930 or a signal input to the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or an ASIC for configuring an AFE (analog front end) or a DFE (digital front end).

[0198] The imaging device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930 when the semiconductor device 930 is a photoelectric conversion device (imaging device). When the semiconductor device 930 is a display device, the imaging device 970 can be a photoelectric conversion device (imaging device) that captures an image to be displayed on the semiconductor device 930.

[0199] The storage device 980 is a magnetic device or a semiconductor device that stores information (images) handled by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0200] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) included in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit included in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0201] The device 9191 is also suitable for electronic devices such as information terminals (e.g., smartphones and wearable devices) with a photographing function and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operation.

[0202] The device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as a transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) by using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or office equipment such as a copier or printer.

[0203] According to the above-described embodiment, it is possible to form good wiring. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental load, reducing costs, reducing size, and reducing weight.

[0204] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment 9191 can also be improved. For example, by mounting the semiconductor device 930 on a transport equipment, excellent performance can be obtained when photographing the outside of the transport equipment or measuring the external environment. Therefore, in manufacturing and selling the transport equipment, it is advantageous to decide to mount the semiconductor device according to this embodiment on the transport equipment in order to improve the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0205] Tenth embodiment FIG. 21 is a schematic block diagram of a photoelectric conversion device according to this embodiment. The photoelectric conversion device 1101 includes an imaging region 1102 in which a plurality of pixels are arranged in a matrix, a vertical scanning circuit 1103 for driving each unit included in the pixel, a horizontal scanning circuit 1105 for reading out an electrical signal of the pixel, and an output unit 1106 to which the electrical signal of the pixel is output. The output unit 1106 outputs an electrical signal to the outside of the photoelectric conversion device. The photoelectric conversion device outputs an electrical signal corresponding to the amount of light incident on the imaging region 1102. The photoelectric conversion device also includes a control unit 1104 for controlling the operations of the vertical scanning circuit 1103, the horizontal scanning circuit 1105, and the output unit 1106. The control unit 1104 may also be called a timing generator.

[0206] Fig. 22 is an equivalent circuit diagram of a pixel included in the imaging region 1102. In Fig. 22, a configuration of 3 rows and 2 columns is shown for simplification, but the number of pixels is not limited to this. Typically, tens of millions of pixels are arranged in the imaging region 1102. Also, three output lines 1018-1, 1018-2, and 1018-3 are arranged for one column, but the number of output lines is not limited to this and may be greater.

[0207] The unit pixel 1201 includes a photoelectric conversion unit 1001, a floating diffusion unit 1002, and a transfer unit 1011 provided between the photoelectric conversion unit 1001 and the floating diffusion unit 1002. The unit pixel 1201 also includes a capacitance switching unit 1012 for switching the capacitance of the floating diffusion unit 1002 as necessary. The unit pixel 1201 further includes a reset unit 1013 for resetting the floating diffusion unit 1002, an amplifier unit 1014 for outputting a signal from the floating diffusion unit 1002, and a row selection unit 1015 that is provided as necessary.

[0208] The photoelectric conversion unit 1001 receives light incident on the unit pixel 1201 and generates an electric charge according to the amount of light received. The floating diffusion unit 1002 temporarily holds the electric charge transferred from the photoelectric conversion unit 1001, and at the same time functions as a charge-voltage converter that converts the held electric charge into a voltage signal.

[0209] The transfer unit 1011 is driven by a signal pTX output from a vertical scanning circuit 1103 , and transfers the charge generated in the photoelectric conversion unit 1001 to the floating diffusion unit 1002 .

[0210] The capacitance switching unit 1012 is driven by a signal pFDinc and switches the capacitance of the floating diffusion unit 1002. By turning on the capacitance switching unit 1012, the gate capacitance of the capacitance switching unit can be added to the floating diffusion unit 1002. The signal pFDinc may be output from the vertical scanning circuit 1103 or may be output from the control unit 1104. When the vertical scanning circuit 1103 outputs the signal pFDinc, the capacitance of the floating diffusion unit 1002 can be switched for each row of pixels. When the control unit 1104 outputs the signal pFDinc, the capacitance of the floating diffusion unit 1002 can be switched collectively for the entire imaging region 1102.

[0211] The reset unit 1013 is driven by a signal pRES output from the vertical scanning circuit 1103. At that time, the floating diffusion unit 1002 can be reset by simultaneously turning on the reset unit 1013 and the capacitance switching unit 1012.

[0212] The amplifier 1014 amplifies the voltage signal converted by the floating diffusion unit 1002 and outputs it as a pixel signal. The row selection unit 1015 is driven by a row selection drive pulse pSEL and outputs the pixel signal amplified by the amplifier 1014 to one of output lines 1018-1, 1018-2, and 1018-3.

[0213] 23 shows an example of a timing chart for outputting pixel signals at low luminance, where the horizontal axis indicates time and the vertical axis indicates voltage, which correspond to the drive pulses shown in FIG.

[0214] At time t1, the vertical scanning circuit 1103 turns on the capacitance switching unit 1012, the reset unit 1013, and the row selection unit 1015 of the pixels in a predetermined row, thereby selecting the pixels and resetting the floating diffusion unit 1002. The control of the selected pixels in the predetermined row will be described below.

[0215] Next, at time t2, the capacitance switching unit 1012 is turned off. This reduces the capacitance of the floating diffusion unit 1002 during readout, and reduces noise. At this time, the signal output to the output line 1018-m (m is any of 1 to 3) through the amplifier unit 1014 is output to the output unit 1106 as a reset level signal. Note that the output line 1018-m may be referred to as the output line 1018 in the column when referring to output lines in general.

[0216] Next, at time t3, the vertical scanning circuit 1103 turns on the transfer unit 1011. This causes the charge stored in the photoelectric conversion unit 1001 to be transferred to the floating diffusion unit 1002.

[0217] Then, the vertical scanning circuit 1103 turns off the transfer unit 1011 at time t4. The amplifier 1014 outputs a signal (pixel signal) corresponding to the potential of the floating diffusion unit 1002 to the corresponding output line 1018-m. The pixel signal output to the output line 1018-n is subjected to processing such as amplification, noise reduction, and AD conversion by the corresponding column circuit. After that, the processed pixel signal is output to the output unit 1106 from the column circuit of each column by horizontal scanning by the horizontal scanning circuit 1105.

[0218] FIG. 24(a) is a plan view of a unit pixel 1201 in this embodiment. Elements that are the same as or correspond to those shown in FIG. 22 are given the same numbers. In addition, in the plan view, each region is shown as a rectangle for simplification, but this does not represent the shape of each part, but indicates that at least each part is arranged in this region. A reset unit 1013, an amplifier unit 1014, a row selection unit 1015, etc. are arranged in the pixel transistor region 1401. FIG. 24 shows unit pixels 1201 with two rows and two columns. Output lines 1018-1 to 1018-3 extend along a first direction. Of the multiple unit pixels, the photoelectric conversion unit of the first pixel is shown as 1001-1. The photoelectric conversion unit of the second pixel adjacent to the first pixel along a second direction, which is a direction different from the first direction, is shown as 1001-2. In FIG. 24, the first direction and the second direction are orthogonal to each other in a plan view seen from the top surface of the semiconductor substrate. The photoelectric conversion unit of a third pixel adjacent to the second pixel along the first direction is indicated as 1001-3. The photoelectric conversion unit of a fourth pixel adjacent to the first pixel along the first direction is indicated as 1001-4. The photoelectric conversion unit 1001-3 is adjacent to the photoelectric conversion unit 1001-4 along the second direction.

[0219] FIG. 24(b) shows a cross-sectional view of GG' which is the second position in FIG. 24(a). FIG. 24(c) shows a cross-sectional view of HH' which is the first position in FIG. 24(a). The first position is located in the region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-3 of the third pixel. The second position is located in the region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-2 of the second pixel. For the sake of simplicity, wiring other than the output line 1018 is omitted. The first output line 1018-1, the second output line 1018-2, and the third output line 1018-3 are configured in the same wiring layer. Here, the space between the first output line 1018-1 and the second output line 1018-2 when viewed from the GG' cross section is shown as S1A, and the space between the second output line 1018-2 and the third output line 1018-3 is shown as S2A. The space between the first output line 1018-1 and the third output line 1018-3 is shown as S3A. The space between the first output line 1018-1 and the second output line 1018-2 when viewed from the HH' cross section is shown as S1B, the space between the second output line 1018-2 and the third output line 1018-3 is shown as S2B, and the space between the first output line 1018-1 and the third output line 1018-3 is shown as S3B.

[0220] In this embodiment, the wiring capacitance of the second output line 1018-2, which is disposed in the center among the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3, is reduced. In this embodiment, with respect to the distance between the first output line and the second output line and the distance between the second output line and the third output line, the distance at the second position is made larger than the distance at the first position. Specifically, the space S1A is made larger than the space S1B, the space S2A is made larger than the space S2B, and the space S3A is made larger than the space S3B. This reduces the parasitic capacitance of the second output line 1018-2. This reduction in parasitic capacitance can speed up the stabilization of the potential of the output line 1018-2 for each of the reset level signal and the pixel signal. Therefore, the readout speed of the pixel signal can be increased. In addition, in this embodiment, four control lines are provided for transmitting the signals pRES, pFDinc, pTX, and pSEL for each row of pixels. The distance from one end (control line for signal pRES) of the four control lines to the other end (control line for signal pSEL) of the control lines is D1 as shown in FIG. 24. On the other hand, three output lines 1018-1 to 1018-3 are provided as output lines for outputting pixel signals to pixels in one column. The distance from one end (output line 1018-1) to the other end (output line 1018-3) of the output line group, which is the output lines 1018-1 to 1018-3, is D2 between a plurality of transistor regions of adjacent unit pixels 1201. Also, the distance from one end (output line 1018-1) to the other end (output line 1018-3) of the output line group is D3, which is smaller than D2, between a plurality of photoelectric conversion units 1001 of adjacent unit pixels 1201. Focusing on row 1, there are more control lines than output lines. Therefore, if the distance from one end to the other end of the output line group is D2 even between multiple photoelectric conversion units 1001, the distance between unit pixels in multiple rows tends to be greater than the distance between unit pixels in multiple columns. Therefore, the length of the aperture of the photoelectric conversion unit 1001 of one unit pixel 1201 along the direction in which the unit pixels in multiple rows are arranged tends to be longer than the length along the direction in which the unit pixels in multiple columns are arranged.On the other hand, in this embodiment, the portions where the spaces from the output lines 1018-1 and 1018-3 to the output line 1018-2 are expanded are provided in the regions between the photoelectric conversion units 1001. This makes it easier to align the length of the aperture of the photoelectric conversion unit 1001 of one unit pixel 1201 along the direction in which the unit pixels of multiple rows are arranged and the length along the direction in which the unit pixels of multiple columns are arranged. This makes it easier to align the ease of crosstalk between the unit pixels 1201 of multiple rows and the ease of crosstalk between the unit pixels 1201 of multiple columns. Here, consider a case where the unit pixels 1201 are provided with color filters in a Bayer array. The unit pixel 1201 located in the adjacent row and the unit pixel 1201 located in the adjacent column relative to the unit pixel 1201 provided with a color filter that transmits light corresponding to a green wavelength are provided with color filters that transmit light corresponding to wavelengths of different colors. Typically, a unit pixel 1201 having a color filter that transmits light of a red wavelength and a unit pixel 1201 having a color filter that transmits light of a blue wavelength are arranged in adjacent rows and adjacent columns. In this case, if the ease of crosstalk between multiple rows of unit pixels 1201 differs from the ease of crosstalk between multiple columns, one signal of the red and blue unit pixels 1201 is likely to crosstalk to the green unit pixel 1201. As a result, an image generated by a pixel signal output from a photoelectric conversion device is likely to be generated that is closer to a color different from the original color. This causes a decrease in image quality. On the other hand, in this embodiment, since the crosstalk between multiple rows and multiple columns is easily made uniform, the crosstalk from each of the red and blue unit pixels 1201 is also easily made uniform. This makes it easier to obtain an image that expresses the original color of the subject.

[0221] <Eleventh embodiment> FIG. 25(a) is a plan view of a unit pixel 1201 in this embodiment. Elements that are the same as or correspond to those shown in FIG. 22 are given the same numbers. In addition, in the plan view, each region is shown as a rectangle for simplification, but this does not represent the shape of each part, but indicates that at least each part is arranged in this region. In the pixel transistor region 1501, a reset section 1013, an amplifier section 1014, a row selection section 1015, etc. are arranged. In addition, in a front-illuminated photoelectric conversion device, the waveguide structure 1502 can improve pixel sensitivity by focusing light on the photoelectric conversion section 1001. However, the waveguide structure 1502 needs to be arranged so as not to overlap with wiring.

[0222] FIG. 25(b) shows a cross-sectional view of GG' (first position) in FIG. 25(a). FIG. 25(c) shows a cross-sectional view of HH' (second position) in FIG. 25(a). The distance from one end of the first output line 1018-1 to one end of the third output line 1018-3 at the first position is shown as D4. The distance from one end of the first output line 1018-1 to one end of the third output line 1018-3 at the second position is shown as D5. D5 is longer than D4. For the sake of simplicity, wiring other than the output line 1018 is omitted. The first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 are configured in the same wiring layer. Here, the space between the first output line 1018-1 and the second output line 1018-2 when viewed from the GG' cross section is shown as S1A, and the space between the second output line 1018-2 and the third output line 1018-3 is shown as S2A. Furthermore, the space between the first output line 1018-1 and the third output line 1018-3 is shown as S3A. Moreover, the space between the first output line 1018-1 and the second output line 1018-2 when viewed from the HH' cross section is shown as S1B, the space between the second output line 1018-2 and the third output line 1018-3 is shown as S2B, and the space between the first output line 1018-1 and the third output line 1018-3 is shown as S3B.

[0223] In this embodiment, the wiring capacitance of the second output line 1018-2 among the first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 is reduced. Specifically, the space S1B is made larger than the space S1A, and the space S3B is made larger than the space S3A. The wiring capacitance of the third output line 1018-3 can also be reduced in the same manner as the second output line 1018-2. This reduces the parasitic capacitance of the second output line 1018-2 and the third output line 1018-3 arranged in the center. This makes it possible to hasten the settling of the reset level signal and the pixel signal. This makes it possible to increase the readout speed of pixel signals. Also, it is possible to suppress a reduction in the diameter of the waveguide structure 1502 due to the output lines 1018-1 to 1018-3. As a result, it is possible to suppress a reduction in the sensitivity of the photoelectric conversion unit 1001.

[0224] <Twelfth embodiment> FIG. 26(a) is a plan view of a unit pixel 1201 in this embodiment. Elements that are the same as or correspond to those shown in FIG. 22 are given the same numbers. In addition, in the plan view, each region is shown as a rectangle for simplification, but this does not represent the shape of each part, but indicates that at least each part is arranged in this region. In the pixel transistor region 1601, a reset unit 1013, an amplifier unit 1014, a row selection unit 1015, etc. are arranged. In addition, in a back-illuminated photoelectric conversion device, the shield wiring 1602 can improve pixel sensitivity by reflecting light that has passed through the silicon substrate to the photoelectric conversion unit 1001. That is, a microlens is provided on the upper part of the first surface, which is the light incident surface of the semiconductor substrate on which the photoelectric conversion unit 1001 is provided, and a wiring layer including the shield wiring 1602 is provided on the upper part of the second surface opposite to the first surface. The shield wiring 1602 is a metal film made of metal (including alloy).

[0225] FIG. 26(b) shows a cross-sectional view of GG' which is the first position in FIG. 26(a). FIG. 26(c) shows a cross-sectional view of HH' which is the second position in FIG. 26(a). In this embodiment, the first position is located in a region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-2 of the second pixel. The second position is located in a region between the photoelectric conversion unit 1001-1 of the first pixel and the photoelectric conversion unit 1001-3 of the third pixel. For the sake of simplicity, wiring other than the output line 1018 and the shield wiring 1602 is omitted. The first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 are configured in the same wiring layer. Here, when viewed from the GG' cross section, the space between the first output line 1018-1 and the second output line 1018-2 is indicated as S1A, the space between the second output line 1018-2 and the third output line 1018-3 is indicated as S2A, and the space between the first output line 1018-1 and the third output line 1018-3 is indicated as S3A. Also, when viewed from the HH' cross section, the space between the first output line 1018-1 and the second output line 1018-2 is indicated as S1B, the space between the second output line 1018-2 and the third output line 1018-3 is indicated as S2B, and the space between the first output line 1018-1 and the third output line 1018-3 is indicated as S3B.

[0226] In this embodiment, the wiring capacitance of the second output line 1018-2 among the first output line 1018-1, the second output line 1018-2, the third output line 1018-3, and the fourth output line 1018-4 is reduced. In this embodiment, the distance between the first output line and the second output line and the distance between the second output line and the third output line are made larger at the second position than at the first position. Specifically, the space S1B is made larger than the space S1A, and the space S3B is made larger than the space S3A. Also, the wiring capacitance of the third output line 1018-3 can be reduced in the same manner as the second output line 1018-2. This reduces the parasitic capacitance of the second output line 1018-2 and the third output line 1018-3 arranged in the center. Therefore, the reset level signal and the pixel signal can be settled earlier, and the readout speed of the pixel signal can be increased.

[0227] <Thirteenth embodiment> Fig. 27(a) is a plan view of a unit pixel 1201 in this embodiment. Elements that are the same as or correspond to those shown in Fig. 22 are given the same numbers. In addition, in the plan view, each region is shown as a rectangle for simplification, but this does not represent the shape of each part, but indicates that at least each part is arranged in this region. In the pixel transistor region 1701, a reset section 1013, an amplifier section 1014, a row selection section 1015, etc. are arranged.

[0228] Fig. 27(b) shows a cross-sectional view of GG' in Fig. 27(a). Fig. 27(c) shows a cross-sectional view of HH' in Fig. 27(a). For simplicity of explanation, wiring other than the output line 1018 is omitted. In the GG' cross-section, the first output line 1018-1 and the third output line 1018-3 are configured in the same wiring layer, but the second output line 1018-2 is configured in a different wiring layer. In the HH' cross-section, the first output line 1018-1 and the third output line 1018-3 are switched to the same wiring layer as the second output line 1018-2 via the connection part 1702.

[0229] In this embodiment, the wiring capacitance of the second output line 1018-2, which is disposed in the center among the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3, is reduced. Specifically, the wiring layers of the first output line 1018-1 and the third output line 1018-3, which are disposed on the outside, are switched. This reduces the parasitic capacitance of the output line 1018-2, and can hasten the settling of the reset level signal and the pixel signal. This can increase the readout speed of the pixel signal.

[0230] <Fourteenth embodiment> Fig. 28(a) is a plan view of a unit pixel 1201 in this embodiment. Elements that are the same as or correspond to those shown in Fig. 22 are given the same numbers. In addition, in the plan view, each region is shown as a rectangle for simplification, but this does not represent the shape of each part, but indicates that at least each part is arranged in this region. In the pixel transistor region 1801, a reset unit 1013, an amplifier unit 1014, a row selection unit 1015, etc. are arranged.

[0231] Fig. 28(b) shows a cross-sectional view of GG' in Fig. 28(a). Fig. 28(c) shows a cross-sectional view of HH' in Fig. 28(a). For simplicity of explanation, wiring other than the output line 1018 is omitted. In the GG' cross-section, the first output line 1018-1 and the third output line 1018-3 are arranged in the same wiring layer, but the second output line 1018-2 is arranged in a different wiring layer. In the HH' cross-section, the second output line 1018-2 is switched to the same wiring layer as the first output line 1018-1 and the third output line 1018-3 via the connection part 1802.

[0232] In this embodiment, in order to reduce the wiring capacitance of the second output line 1018-2, which is disposed in the center among the first output line 1018-1, the second output line 1018-2, and the third output line 1018-3, the wiring layer of the second output line 1018-2, which is disposed in the center, is switched. This reduces the parasitic capacitance of the output line 1018-2, and can speed up the settling of the reset level signal and the pixel signal. This can increase the readout speed of the pixel signal.

[0233] Each of the semiconductor devices according to the tenth to fourteenth embodiments described above can be applied to the semiconductor device APR shown in Fig. 20(a) and also to the semiconductor device 930 shown in Fig. 20(b).

[0234] The present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached to this specification. Furthermore, the disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification contains a statement that "A is B," even if the statement that "A is not B" is omitted, this specification can be said to disclose that "A is not B." This is because when a statement that "A is B" is made, it is assumed that the case in which "A is not B" is taken into consideration. [Explanation of symbols]

[0235] 100 Semiconductor layer 110 Wiring 110a Left side part 110b Right side part 110c middle part APR Semiconductor Device Q1, Q2, Q3 wiring Wa,Wb,Wc Width Ph,Pc,Pm part Wh, Wc, Wm Width

Claims

1. A semiconductor device comprising a plurality of wirings, each of which has a damascene structure, on a semiconductor layer, the plurality of wirings include a first wiring and a second wiring adjacent to each other, The distance between one end and the other end of the first wiring is greater than 33 mm, the first wiring has, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion between the first portion and the second portion; the width of the first portion and the width of the second portion are less than 180 nm; A semiconductor device, comprising: a third portion having a width greater than the width of the first portion and the width of the second portion.

2. A semiconductor device comprising a plurality of wirings, each of which has a damascene structure, on a semiconductor layer, the plurality of wirings include a first wiring and a second wiring adjacent to each other, the first wiring has, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion between the first portion and the second portion; the distance between the first portion and the second portion of the first wiring is greater than 33 mm; The semiconductor device, wherein the width of the third portion is the maximum width of the first wiring in the range from the first portion to the second portion, and is smaller than 180 nm.

3. 3 . The semiconductor device according to claim 1 , wherein a difference between the width of the third portion and the width of the first portion and a difference between the width of the third portion and the width of the second portion are greater than 50 nm.

4. 4. The semiconductor device according to claim 1, wherein a difference between the width of the third portion and the width of the first portion is smaller than the width of the first portion, and a difference between the width of the third portion and the width of the second portion is smaller than the width of the second portion.

5. The semiconductor device according to claim 1 , wherein the width of the third portion is greater than 110 nm.

6. The semiconductor device according to claim 1 , wherein a distance between said third portion and said second wiring is larger than said width of said first portion and said width of said second portion.

7. 7. The semiconductor device according to claim 1, wherein a distance between the first portion and the second wiring and a distance between the second portion and the second wiring are smaller than the width of the third portion.

8. The semiconductor device according to claim 1 , wherein a length of the second portion along the direction is greater than the width of the first portion and the width of the second portion.

9. the first portion is located between the one end and the third portion along the direction, the second portion is located between the other end and the third portion along the direction, the first wiring has, along the direction, a fourth portion between the one end and the first portion, a fifth portion between the fourth portion and the first portion, a sixth portion between the other end and the second portion, and a seventh portion between the sixth portion and the second portion; 9. The semiconductor device according to claim 1, wherein a width of the fifth portion and a width of the seventh portion are greater than the width of the first portion, the width of the second portion, the width of the fourth portion, and the width of the sixth portion.

10. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises a plurality of photoelectric conversion portions.

11. A plurality of unit pixels arranged across a plurality of rows and a plurality of columns, each of which includes a photoelectric conversion unit; a plurality of output lines connected to the unit pixels in one column and transmitting outputs of the unit pixels, the plurality of output lines include at least a first output line, a second output line having a portion adjacent to the first output line, and a third output line having a portion adjacent to the second output line; the first output line, the second output line, and the third output line all include a portion extending along a first direction, the first output line, the second output line, and the third output line pass through a first position and a second position different from the first position; a distance between the first output line and the second output line, a distance between the second output line and the third output line, and a distance between the first output line and the third output line, each of at least two of these distances being longer at the second position than at the first position.

12. the plurality of unit pixels include a first pixel and a second pixel adjacent to each other in a direction different from the first direction, and a third pixel adjacent to the second pixel in the first direction; the first position is a position between the photoelectric conversion units of the first pixel and the second pixel, The semiconductor device according to claim 11 , wherein the second position is a position between the photoelectric conversion units of the first pixel and the third pixel.

13. the plurality of unit pixels include a first pixel and a second pixel adjacent to each other in a direction different from the first direction, and a third pixel adjacent to the second pixel in the first direction; the first position is a position between the photoelectric conversion units of the first pixel and the third pixel, The semiconductor device according to claim 11 , wherein the second position is a position between the photoelectric conversion units of the first pixel and the second pixel.

14. The plurality of unit pixels are provided on a semiconductor substrate, and a wiring layer is provided on an upper portion of a second surface of the semiconductor substrate opposite to a first surface through which light is incident; 14. The semiconductor device according to claim 11, wherein the wiring layer includes a metal film at a position overlapping the photoelectric conversion portion in a plan view.

15. 15. The semiconductor device according to claim 11, wherein the number of wiring layers through which the first output lines extend is greater than the number of wiring layers through which the second output lines extend.

16. 15. The semiconductor device according to claim 11, wherein the number of wiring layers through which the second output lines extend is greater than the number of wiring layers through which the first output lines extend.

17. providing a wafer including a semiconductor layer and an insulator film disposed on the semiconductor layer; an exposure step of exposing a positive photoresist film provided on the insulating film; a developing step of developing the photoresist film to form a resist pattern from the photoresist film; a processing step of processing the insulating film using the resist pattern to form a trench in the insulating film; forming an interconnect in the trench; A method for manufacturing a semiconductor device comprising the steps of: the wafer has a first region, a second region, and a third region between the first region and the second region, the trench extending from the first region through the third region to the second region; the exposure step includes a first exposure shot for exposing the photoresist film on the first region and the third region, and a second exposure shot for exposing the photoresist film on the second region and the third region after the first exposure shot, The wiring has a first portion located above the first region, a second portion located above the second region, and a third portion located above the third region along a direction in which the wiring extends. having A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on said first portion; forming a second insulating film on said second portion;

18. The photoresist film between the first exposure shot and the second exposure shot in the exposure step is a first exposure section located above the first region and exposed by the first exposure shot, a second exposure section located above the third region and exposed by the first exposure shot, and a third exposure section located between the first exposure section and the second exposure section and exposed by the first exposure shot, The photoresist film after the second exposure shot of the exposure step is a fourth exposure section located above the second region and exposed in the second exposure shot, a fifth exposure section located above the third region and exposed in the second exposure shot, and a sixth exposure section located between the fourth exposure section and the fifth exposure section and exposed in the second exposure shot, At least a portion of the fifth exposure section includes the second exposure section, 18. The method for manufacturing a semiconductor device according to claim 17, wherein in the developing step, the first exposed portion, the second exposed portion, the third exposed portion, the fourth exposed portion, the fifth exposed portion, and the sixth exposed portion are removed.

19. The method for manufacturing a semiconductor device according to claim 18 , wherein a width of the third exposed portion is greater than a width of the first exposed portion.

20. The method for manufacturing a semiconductor device according to claim 18 or 19, wherein a width of the second exposed portion is smaller than a width of the third exposed portion.

21. 21. The method of claim 18, wherein a difference between a width of the first exposed portion and a width of the third exposed portion is larger than a difference between a width of the second exposed portion and a width of the third exposed portion.

22. 21. The method for manufacturing a semiconductor device according to claim 18, wherein a width of the sixth exposed portion is larger than a width of the fourth exposed portion.

23. 22. The method for manufacturing a semiconductor device according to claim 18, wherein a width of the fifth exposed portion is smaller than a width of the sixth exposed portion.

24. 24. The method of claim 18, wherein a difference between a width of the fourth exposed portion and a width of the sixth exposed portion is larger than a difference between a width of the fifth exposed portion and a width of the sixth exposed portion.

25. providing a wafer including a semiconductor layer and an insulator film disposed on the semiconductor layer; an exposure step of exposing a positive photoresist film provided on the insulating film; a developing step of developing the photoresist film to form a resist pattern from the photoresist film; a processing step of processing the insulating film using the resist pattern to form a trench in the insulating film; a wiring step of forming wiring in the trench; A method for manufacturing a semiconductor device comprising the steps of: the wafer has a first region, a second region, and a third region between the first region and the second region, the trench extending from the first region through the third region to the second region; the exposure step includes a first exposure shot for exposing the photoresist film on the first region and the third region, and a second exposure shot for exposing the photoresist film on the second region and the third region after the first exposure shot, The photoresist film between the first exposure shot and the second exposure shot in the exposure step is a first exposure section located above the first region and exposed by the first exposure shot, a second exposure section located above the third region and exposed by the first exposure shot, and a third exposure section located between the first exposure section and the second exposure section and exposed by the first exposure shot, The photoresist film after the second exposure shot of the exposure step is a fourth exposure section located above the second region and exposed in the second exposure shot, a fifth exposure section located above the third region and exposed in the second exposure shot, and a sixth exposure section located between the fourth exposure section and the fifth exposure section and exposed in the second exposure shot, At least a portion of the fifth exposure section includes the second exposure section, In the developing step, the first exposed section, the second exposed section, the third exposed section, the fourth exposed section, the fifth exposed section, and the sixth exposed section are removed, A method for manufacturing a semiconductor device, wherein the width of the second exposed portion is smaller than the width of the third exposed portion.

26. The method for manufacturing a semiconductor device according to claim 25 , wherein a width of the fifth exposed portion is smaller than a width of the sixth exposed portion.

Images