Semiconductor device

Abstract

To provide a semiconductor device having a radio communication function, which can reduce power consumption or can prolong a life.SOLUTION: A semiconductor device can solve a problem by electrically connecting a battery serving as a power supply source to a specific circuit through a transistor in which a channel formation region is composed of an oxide semiconductor. Hydrogen concentration of the oxide semiconductor is 5×1019 (atoms / cm3) or less. Therefore, leak current of the transistor can be reduced. As a result, power consumption during stand-by of the semiconductor device can be reduced. In addition, this leads to a prolonged life of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wireless communication function.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] Semiconductor devices having a wireless communication function capable of wirelessly transmitting and receiving data are being used in various fields. Such semiconductor devices are being put to practical use as new types of communication and information terminals. The market is expected to expand further as a result of this. Semiconductors with wireless communication functions that are in practical use The device has an antenna and an integrated circuit formed using a semiconductor element formed on the same substrate. Semiconductor devices with wireless communication functions include wireless tags, RF (Radio Frequency) equency) tags, RFID (Radio Frequency Identification cation) tag, IC (Integrated Circuit) tag, or ID Also called an (Identification) tag.

[0004] The semiconductor devices are broadly divided into two types: active and passive. The latter is a semiconductor device that has a battery inside the device and operates using the battery as a power supply source. The semiconductor device does not have a power supply source such as a battery, and requires an external interrogator (reader, reader / writer, It is a semiconductor device that operates using a signal input from a power supply terminal (also called R / W) as a power supply source.

[0005] Active RF tags have a built-in power supply, so they are more reliable than passive RF tags. However, active wireless tags have a high response time. Regardless of the presence or absence of an interrogator, the device operates constantly or periodically (generating signals), so the power consumption is The power becomes greater.

[0006] A technology for reducing the power consumption of active wireless tags is disclosed in Patent Document 1. The active type wireless tag (active wireless tag) disclosed in the document 1 is different from the conventional active In addition to the configuration of the wireless tag, a second antenna for receiving a signal from the outside and a and a voltage detection circuit to which the output voltage of the generator is input. The intermittent operation is controlled by the detection circuit, which reduces power consumption. . [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2006-229558 Summary of the Invention [Problem to be solved by the invention]

[0008] However, the power consumed by a semiconductor device that performs intermittent operation is This includes not only the power consumption but also the power consumption during standby (hereinafter referred to as standby power). Here, standby power refers to the power generated by a small amount of discharge through an element or circuit to which a battery is electrically connected. In particular, the power consumption of the intermittent operation control disclosed in Patent Document 1 is In semiconductor devices, the proportion of standby power in the total power consumption is high. In order to reduce the power consumption of semiconductor devices, it is important to reduce standby power.

[0009] In view of the above, an object of one embodiment of the present invention is to reduce standby power of a semiconductor device.

[0010] Another object of one embodiment of the present invention is to extend the life of a semiconductor device. [Means for solving the problem]

[0011] The above problem is solved by a method in which a battery serving as a power supply source and a specific circuit are connected in a channel forming region made of an oxide semiconductor. The problem is solved by electrically connecting the semiconductor device via a transistor composed of a semiconductor body. Note that the oxide semiconductor can remove hydrogen, which serves as an electron donor. Thus, it is an intrinsic or substantially intrinsic semiconductor.

[0012] Specifically, the amount of hydrogen contained in the oxide semiconductor is 5×10 19 (atoms / cm 3 ) Less than or equal to 5×10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 1 7 (atoms / cm 3 By reducing the hydrogen concentration in this way, Carrier density is 1×10 14 cm -3 Less than 1 x 10 12 cm -3 Less than, more Preferably, it is 1×10 below the measurement limit. 11 cm -3 It becomes possible to make it less than that.

[0013] By using such a highly purified oxide semiconductor for a channel formation region of a transistor, Therefore, even if the channel width is 10 mm, the drain current in the off state of the transistor is The input current is 1×10 -13 [A] or less. That is, highly purified By applying an oxide semiconductor to the channel formation region of a transistor, leakage current can be reduced. It can be significantly reduced.

[0014] That is, one embodiment of the present invention is a receiver including an antenna, a battery, and a receiver for decoding a signal input from the antenna. A demodulation circuit that demodulates the signal and the power supply voltage supplied from the battery are used. A signal processing unit that operates in accordance with the demodulation circuit, and a power control circuit that is controlled by a signal input from the demodulation circuit. and a signal processing unit that performs switching in response to a signal input from the power control circuit. A transistor that controls the voltage of the battery and is electrically connected to the anode or cathode of the battery through the transistor. and a functional circuit having a hydrogen concentration of 5×10 1 9 (atoms / cm 3 ) A semiconductor device including the following oxide semiconductor.

[0015] Also, the demodulation circuit included in the above configuration can be replaced with a timer. An antenna, a battery, a timer that periodically outputs a signal, and a signal input from the timer and a signal processing unit that operates using a power supply voltage supplied from a battery. and a power control circuit controlled by a signal from the power control circuit. A transistor whose switching is controlled by a signal input from a and a functional circuit electrically connected to the anode or cathode of the battery, The hydrogen concentration in the cell formation region is 5×10 19(atoms / cm 3 ) for the following oxide semiconductors: A semiconductor device configured in this manner is also one embodiment of the present invention.

[0016] In addition, the battery in the above configuration is a secondary battery, and in addition to the above configuration, A rectifier circuit that rectifies the input signal and a secondary battery that uses the signal input from the rectifier circuit. The charging circuit includes a secondary battery and a stabilized power supply circuit that generates a power supply voltage using the secondary battery. A semiconductor device is also one embodiment of the present invention.

[0017] The functional circuit may be, for example, a logic gate. It can be constructed using complementary metal oxide semiconductor (CMOS) and N-type transistors. It is also possible to configure it using only transistors (NMOS). Effect of the Invention

[0018] A semiconductor device according to one embodiment of the present invention includes a functional circuit, a battery, and an electrical connection between the functional circuit and the battery. A channel formation region of the transistor has a hydrogen concentration Specifically, the hydrogen concentration of the oxide semiconductor is reduced. is 5 x 10 19 (atoms / cm 3 ) or less. Therefore, in the standby state, By turning off the transistor, it is possible to suppress discharge through the transistor. As a result, the standby power consumption of the semiconductor device can be reduced. By reducing the discharge of the battery in the semiconductor device, the life of the semiconductor device can be extended. [Brief description of the drawings]

[0019] [Figure 1]1 illustrates a configuration example of a semiconductor device described in Embodiment 1. [Diagram 2] 1 illustrates a configuration example of a semiconductor device described in Embodiment 2. [Diagram 3] 1 illustrates a configuration example of a semiconductor device described in Embodiment 3. [Figure 4] 1 illustrates a configuration example of a semiconductor device described in Embodiment 4. [Diagram 5] 1A to 1C illustrate configuration examples of a logic gate included in a semiconductor device described in Embodiment 4. [Figure 6] 1A to 1C illustrate configuration examples of a logic gate included in a semiconductor device described in Embodiment 4. [Figure 7] 11 is a cross-sectional view showing a configuration example of a P-type transistor and an N-type transistor described in Embodiment 5. FIG. [Figure 8] 1A to 1H are cross-sectional views illustrating an example of a manufacturing process of a P-type transistor described in Embodiment 5. [Figure 9] 1A to 1G are cross-sectional views illustrating an example of a manufacturing process of an N-type transistor described in Embodiment 5. [Figure 10] 1A to 1D are cross-sectional views illustrating an example of a manufacturing process of an N-type transistor described in Embodiment 5. [Figure 11] 11 is a cross-sectional view showing a configuration example of a P-type transistor and an N-type transistor described in Embodiment 5. FIG. [Figure 12] 13A and 13B are cross-sectional views illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 5. [Figure 13] 13A and 13B are cross-sectional views illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 5. [Figure 14] 13A and 13B are cross-sectional views illustrating configuration examples of a P-type transistor and an N-type transistor described in Embodiment 5. [Figure 15] 13A and 13B are a plan view and a cross-sectional view illustrating a configuration example of a transistor described in Embodiment 6. [Figure 16] 1A to 1E are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 6. [Figure 17] 1A to 1E are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 7. [Figure 18] 1A to 1D are cross-sectional views illustrating an example of a manufacturing process of a transistor described in Embodiment 8. [Figure 19] 13A to 13C are diagrams illustrating examples of use of a semiconductor device described in Embodiment 9. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0021] The source and drain terminals of a transistor depend on the structure and operating conditions of the transistor. It is difficult to identify which is the source terminal and which is the drain terminal. Therefore, in this document, one of the source terminal and the drain terminal is referred to as a first terminal. The other of the source terminal and the drain terminal is referred to as a second terminal for distinction.

[0022] In addition, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may differ from the actual size, layer thickness, or area shown in the drawings of each embodiment. In some cases, the figures are exaggerated for clarity. Therefore, the figures are not necessarily limited to the scale. In addition, ordinal numbers such as "first," "second," and "third" used in this specification are not limited to the structure. It is added to avoid confusion of the constituent elements, and is not a numerical limitation. do.

[0023] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. An example of a semiconductor device having a wireless communication function using a digital signal as a source will be described with reference to FIG.

[0024] The semiconductor device shown in FIG. 1 includes an antenna 10 capable of transmitting and receiving wireless signals, and a power supply voltage (VD D) a battery 11 that serves as a power supply source, and a demodulation circuit 1 that demodulates a signal input from an antenna 10. 2, a signal input from the demodulation circuit 12 and a power supply voltage (VDD) supplied from the battery 11 A signal processing unit 13 that operates using a demodulation circuit 12 and a signal processing unit 1 The power control circuit 14 is controlled by a signal input from the power supply 3. In the embodiment, the operation is performed by the signal processing unit 13 or a part of the signal processing unit 13. This refers to the generation of a signal.

[0025] Furthermore, the signal processing unit 13 is switched by a signal input from the power control circuit 14. Specifically, the transistor 15 is a transistor for controlling the demodulation circuit. The power control circuit 14 is switched from the OFF state to the ON state by a signal input from the line 12. The switching is controlled by a signal input from the signal processor 13 to the power control circuit 14. Switching from an on state to an off state is controlled.

[0026] The signal processor 13 also receives the signal input from the demodulator 12 and the power supply voltage (VDD). The transistor 15 is a functional circuit (not shown) that operates using the transistor 15. and the positive or negative electrode of the battery 11. That is, the functional circuit is The functional circuit is electrically connected to the positive or negative electrode of the battery 11 via the positive or negative electrode 15. can perform operations during the period when transistor 15 is in the on state.

[0027] The channel formation region of the transistor 15 has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) The following are more preferable is 5 x 10 17 (atoms / cm 3 ) It is composed of the following oxide semiconductors. That is, the transistor 15 has a very low concentration of hydrogen, which acts as a carrier donor. The transistor has a channel formation region made of a highly purified oxide semiconductor. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This was performed using secondary ion mass spectrometry. .

[0028] This makes it possible to significantly reduce the leakage current of the transistor 15. In the semiconductor device of this embodiment, the transistor 15 is maintained in an off state during standby. Therefore, the discharge of the battery 11 in the standby state can be suppressed. The standby power consumption of the semiconductor device can be reduced. By suppressing this, the life of the semiconductor device can be extended.

[0029] <Modification> The above-described semiconductor device is an example of the semiconductor device of the present embodiment. The present embodiment also includes semiconductor devices that have differences from the conventional semiconductor devices.

[0030] For example, in the above-mentioned semiconductor device, the transistor 15 is connected to the functional circuit and the battery 11. However, the semiconductor device of this embodiment has a structure in which the first electrode is provided between the anode and the cathode. In the semiconductor device of this embodiment, the transistor 15 is The transistor 15 may be a component of a functional circuit. It is not necessary to connect them directly. The order of the circuits or transistors connected in series can be changed. By doing so, it may be provided within the functional circuit while maintaining its functionality.

[0031] In the above-mentioned semiconductor device, the transistor 15 is turned from an on state to an off state. Although the switching is controlled by the output signal of the signal processing unit 13, The semiconductor device of this embodiment is not limited to this configuration. The switching of the transistor 15 from the on state to the off state is performed by the input from the demodulation circuit 12. The transistor 15 may be controlled by a signal input from the After a certain time has elapsed since the off-state was switched to the on-state, the It is also acceptable to have a configuration in which switching is performed from the ON state to the OFF state.

[0032] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0033] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. An example of a semiconductor device having a wireless communication function using a digital signal as a source will be described with reference to FIG.

[0034] The semiconductor device shown in FIG. 2 is an antenna 20 capable of transmitting and receiving wireless signals, and a power supply voltage (V D) and a battery 21 that periodically outputs a signal to the semiconductor device for intermittent operation. A timer 22 controls the operation of the timer 22 and a signal supplied from a battery 21. A signal processor 23 operates using a power supply voltage (VDD) input from a timer 22. and a power control circuit 24 controlled by a signal input from the signal processing unit 23. In the present embodiment, the operation refers to the operation of the signal processing unit 23 or the signal processing unit 23 This refers to the generation of signals that takes place in a part of the

[0035] Furthermore, the signal processing unit 23 is switched by a signal input from the power control circuit 24. Specifically, the transistor 25 is a timer. The power control circuit 24 switches from the OFF state to the ON state by a signal input from the power supply 22. The switching is controlled by a signal input from the signal processor 23 to the power control circuit 24. Switching from an on state to an off state is controlled.

[0036] The signal processor 23 operates using the output signal of the timer 22 and the power supply voltage (VDD). The transistor 25 has a function circuit (not shown) that operates the In other words, the functional circuit is connected via the transistor 25. The functional circuit is electrically connected to the positive or negative electrode of the battery 21. During the period that transistor 25 is in the on state, an operation can be performed.

[0037] The channel formation region of the transistor 25 has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) The following are more preferable is 5 x 10 17 (atoms / cm 3 ) It is composed of the following oxide semiconductors. That is, the transistor 25 has a very low concentration of hydrogen, which acts as a carrier donor. The transistor has a channel formation region made of a highly purified oxide semiconductor. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This was performed using secondary ion mass spectrometry. .

[0038] This makes it possible to significantly reduce the leakage current of the transistor 25. In the semiconductor device of this embodiment, the transistor 25 is maintained in an off state in the standby state. Therefore, the discharge of the battery 21 in the standby state can be suppressed. The standby power consumption of the semiconductor device can be reduced. By suppressing this, the life of the semiconductor device can be extended.

[0039] <Modification> The above-described semiconductor device is an example of the semiconductor device of the present embodiment. The present embodiment also includes semiconductor devices that have differences from the conventional semiconductor devices.

[0040] For example, in the above-mentioned semiconductor device, the output signal of the timer 22 is input to the signal processing unit 23 and and the power control circuit 24. In the semiconductor device according to the present embodiment, the output signal of the timer 22 The signal processing unit 23 may be configured so that the signal is input only to the power control circuit. The output signal may be input to the timer 22. For example, the signal processing unit 23 The reset signal for the timer 22 is output and input to the timer 22, thereby setting the next operation time. It is possible to control the

[0041] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0042] (Embodiment 3) In this embodiment, an example of a semiconductor device will be described. An example of a semiconductor device having a wireless communication function serving as a supply source will be described with reference to FIG.

[0043] The semiconductor device shown in FIG. 3 includes an antenna 30 capable of transmitting and receiving wireless signals and a power supply source. a secondary battery 31 for receiving a signal from the antenna 30; a rectifier circuit 32 for rectifying a signal input from the antenna 30; A charging circuit 33 that charges the secondary battery 31 using a signal input from a line 32; 31 to generate a power supply voltage (VDD) used in the semiconductor device. a demodulation circuit 35 for demodulating a signal input from the antenna 30; The power supply circuit 34 supplies a power supply voltage (VDD) to the power supply 35. A signal processing unit 36 ​​operates as a demodulator circuit 35 and a signal processing unit 36. The power control circuit 37 is controlled by a signal input from the power supply 31. In this case, the operation refers to the generation of a signal performed in the signal processing unit 36 ​​or a part of the signal processing unit 36. This refers to the following.

[0044] Furthermore, the signal processing unit 36 ​​is switched by a signal input from the power control circuit 37. Specifically, the transistor 38 is a transistor for controlling the demodulation circuit. The power control circuit 37 is switched from the OFF state to the ON state by a signal input from the line 35. The switching is controlled by a signal input from the signal processor 36 to the power control circuit 37. Switching from an on state to an off state is controlled.

[0045] The signal processor 36 also receives the signal input from the demodulator 35 and the power supply voltage (VDD). The transistor 38 is a functional circuit (not shown) that operates using the transistor 38. and the stabilized power supply circuit 34. That is, the functional circuit is provided between the transistor 38 and electrically connected to the anode or cathode of the secondary battery 31 via a stabilized power supply circuit 34. The functional circuit operates while the transistor 38 is in the on state. It is possible to do so.

[0046] The channel formation region of the transistor 38 has a hydrogen concentration of 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) The following are more preferable is 5 x 10 17 (atoms / cm 3 ) It is composed of the following oxide semiconductors. That is, the transistor 38 has a very low concentration of hydrogen, which acts as a carrier donor. The transistor has a channel formation region made of a highly purified oxide semiconductor. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This was performed using secondary ion mass spectrometry. .

[0047] This makes it possible to significantly reduce the leakage current of the transistor 38. In the semiconductor device of this embodiment, the transistor 38 is maintained in an off state during standby. Therefore, discharge of the secondary battery 31 in the standby state can be suppressed. This makes it possible to reduce the standby power consumption of the semiconductor device. By suppressing the discharge, the life of the semiconductor device can be extended.

[0048] Furthermore, the semiconductor device shown in FIG. 3 generates a secondary battery in response to a signal input from the antenna 30. The semiconductor device can charge the battery 31 in parallel during operation. In the standby state, it is possible to charge the battery by using a signal input from the antenna 30. It is also possible to do the following.

[0049] In addition, if the semiconductor device is constantly charged with power equivalent to the standby power, the battery will not run out. Furthermore, the semiconductor device includes the transistor 38 as described above. This reduces standby power consumption, thereby improving the charging distance of the semiconductor device. The semiconductor device according to the present embodiment having such characteristics can be used in particular for access. Effective in places where it is difficult to use (such as inside the body, in spaces where radioactivity or poisons are present, or in a vacuum) It is.

[0050] <Modification> The above-described semiconductor device is an example of the semiconductor device of the present embodiment. The present embodiment also includes semiconductor devices that have differences from the conventional semiconductor devices.

[0051] For example, the above-mentioned semiconductor device has one antenna 30. The configuration in which the secondary battery 31 is charged and wireless signals are transmitted and received using the wireless communication device 31 has been described. The semiconductor device of the present embodiment is not limited to the above configuration. The antenna for transmitting and receiving signals and the antenna for charging the secondary battery 31 are separately provided. That's fine.

[0052] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0053] (Embodiment 4) In this embodiment, an example of a semiconductor device will be described. An example of a semiconductor device having a wireless communication function serving as a supply source will be described with reference to FIG.

[0054] The semiconductor device shown in FIG. 4 includes an antenna 40 capable of transmitting and receiving wireless signals and a power supply source. A secondary battery 41 that receives a signal from an antenna 40, a rectifier circuit 42 that rectifies the signal, and A charging circuit 43 that charges the secondary battery 41 using the output signal of the circuit 42, and A stabilized power supply circuit 44 that generates a power supply voltage (VDD) used in the semiconductor device. A demodulation circuit 45 demodulates a signal input from the antenna 40, and The signal to be output and the signal to be operated using the power supply voltage (VDD) supplied from the stabilized power supply circuit 44 are A signal processing unit 46, a signal input from the demodulation circuit 45 and a signal input from the signal processing unit 46 In this embodiment, the power control circuit 47 is controlled by a driving signal. The operation refers to the generation of a signal performed in the signal processing unit 46 or a part of the signal processing unit 46. Let us assume that.

[0055] Furthermore, the signal processing unit 46 is a logic unit that performs processing using the signal input from the demodulation circuit 45. A clock generator 48 for generating a clock signal (CK) used in the semiconductor device. A synthesis circuit 49, a sensor 50 for converting specific external information into a signal, and a memory circuit for storing the information. The antenna 40 includes a logic circuit 51 and a modulation circuit 52 for applying load modulation to the antenna 40. 8, the clock generating circuit 49, the sensor 50, the memory circuit 51, and the modulation circuit 52. A standby signal (Stdby) output from the power control circuit 47 is input to the .

[0056] Various circuits included in the semiconductor device of this embodiment mode have transistors. The logic circuit 48 has logic gates (inverters (NOT gates), NOR gates, and A specific example of the circuit configuration of the AND gate will be described with reference to FIG.

[0057] FIG. 5(A) shows a specific example of the circuit configuration of an inverter. The inverter shown in FIG. 5(A) is , a P-type transistor 80, an N-type transistor 81, and an N-type transistor 82. .

[0058] The first terminal of the P-type transistor 80 is electrically connected to a line that supplies a power supply voltage (VDD). To be continued.

[0059] The first terminal of the N-type transistor 81 is electrically connected to the second terminal of the P-type transistor 80. will be done.

[0060] The gate terminal of the N-type transistor 82 is connected to a line that supplies a standby signal (Stdby). a first terminal electrically connected to the second terminal of the N-type transistor 81; The second terminal is grounded.

[0061] In the inverter shown in FIG. 5A, a P-type transistor 80 and an N-type transistor An input signal is input to the gate terminal of the P-type transistor 81, and a second terminal of the N-type The potential of the node to which the first terminal of the transistor 81 is electrically connected is the output signal of the inverter. and output.

[0062] FIG. 5(B) shows a specific example of the circuit configuration of a NOR gate. The gate includes a P-type transistor 83, a P-type transistor 84, an N-type transistor 85, and an N The MOS transistor 81 includes an N-type transistor 86 and an N-type transistor 87 .

[0063] The first terminal of the P-type transistor 83 is electrically connected to the wiring that supplies the power supply voltage (VDD). To be continued.

[0064] The first terminal of the P-type transistor 84 is electrically connected to the second terminal of the P-type transistor 83. will be done.

[0065] The first terminal of the N-type transistor 85 is electrically connected to the second terminal of the P-type transistor 84. will be done.

[0066] The first terminal of the N-type transistor 86 is connected to the second terminal of the P-type transistor 84 and the second terminal of the N-type transistor 86. It is electrically connected to the first terminal of resistor 85.

[0067] The gate terminal of the N-type transistor 87 is connected to the line that supplies the standby signal (Stdby). , and a first terminal is electrically connected to the second terminal of N-type transistor 85 and the second terminal of N-type transistor 86, and the second terminal is grounded.

[0068] In the NOR gate shown in FIG. 5B, a P-type transistor 83 and an N-type transistor A first input signal is input to the gate terminal of the P-type transistor 84 and the N-type transistor 85. A second input signal is input to the gate terminal of the P-type transistor 85, and a second terminal of the N-type transistor 84 A first terminal of the N-type transistor 85 and a first terminal of the N-type transistor 86 are electrically connected to each other. The potential of the node is output as an output signal of the NOR gate.

[0069] FIG. 5(C) shows a specific example of the circuit configuration of a NAND gate. The gates are P-type transistor 88, P-type transistor 89, and N-type transistor 90. , an N-type transistor 91 and an N-type transistor 92 .

[0070] The first terminal of the P-type transistor 88 is electrically connected to the wiring that supplies the power supply voltage (VDD). To be continued.

[0071] A first terminal of the P-type transistor 89 is electrically connected to the wiring that supplies the power supply voltage (VDD). To be continued.

[0072] An N-type transistor 90 has a first terminal connected to the second terminal of the P-type transistor 88 and It is electrically connected to the second terminal of resistor 89.

[0073] The first terminal of the N-type transistor 91 is electrically connected to the second terminal of the N-type transistor 90. will be done.

[0074] The gate terminal of the N-type transistor 92 is connected to a line that supplies a standby signal (Stdby). a first terminal electrically connected to the second terminal of the N-type transistor 91; The second terminal is grounded.

[0075] In the NAND gate shown in FIG. 5C, a P-type transistor 88 and an N-type transistor A first input signal is input to the gate terminal of the P-type transistor 89 and the N-type transistor 90. A second input signal is input to the gate terminal of the P-type transistor 88. The second terminal of the P-type transistor 89 and the first terminal of the N-type transistor 90 are electrically connected The potential of the node that corresponds to the NAND gate is output as an output signal of the NAND gate.

[0076] The logic gate described above is a transistor that controls the electrical connection to the wiring that supplies the ground potential. (N-type transistor 82, N-type transistor 87, or N-type transistor 92) In addition, in the logic gate, the channel formation region of the transistor is heated to a low temperature. Degree is 5×10 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 ) or less, more preferably 5 × 10 17 (atoms / cm 3 ) or less oxide semiconductor This significantly reduces the leakage current of the transistor. This makes it possible to reduce the shoot-through current that flows through the logic gate. As a result, the standby power consumption of the semiconductor device can be reduced.

[0077] In this embodiment, each logic gate has a transistor that controls the input of a ground potential. We have shown that a single transistor can provide a ground potential input to multiple logic gates. The force may be controlled.

[0078] In the above description, logic games are implemented using complementary metal oxide semiconductors (CMOS). However, the semiconductor device of the present embodiment is configured with only N-type transistors. Figure 6 shows a logic gate consisting of only N-type transistors. FIG. 6(A) shows an inverter, FIG. 6(B) shows a NOR gate, and FIG. C) A NAND gate. In short, the logic gate shown in Figure 6 is a NAND gate. The P-type transistor at the gate is replaced with a diode-connected N-type transistor. It is a completion.

[0079] As described above, the logic gates shown in FIGS. 6(A) to 6(C) are connected to the wiring that supplies the ground potential. The transistor that controls the electrical connection of the 19 (atoms / cm 3 ) or less, preferably 5 × 10 18 (atoms / cm 3 )below , and more preferably 5 × 10 17 (atoms / cm 3 ) Consists of the following oxide semiconductors: This significantly reduces the leakage current of the transistor. Therefore, the shoot-through current flowing through the logic gate can be reduced. As a result, the standby power consumption of the semiconductor device can be reduced.

[0080] In addition, in the clock generation circuit 49, the sensor 50, the memory circuit 51, and the modulation circuit 52, However, based on the conventional circuit configuration, the wiring that supplies the circuit with the ground potential or the wiring that supplies the circuit with the power supply The power control circuit 47 controls switching between the wiring that supplies the potential (VDD). In addition, it is possible to provide a transistor that is different from the conventional circuit configuration. The transistors controlled by the power control circuit 47 may be provided in blocks each of which is made up of a plurality of transistors. Alternatively, a transistor controlled by the power control circuit 47 may be provided for each functional circuit. stomach.

[0081] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0082] (Embodiment 5) In this embodiment, one of the transistors included in the semiconductor device described in any of Embodiments 1 to 4 will be described. Specifically, the semiconductor device has a P-type transistor, A transistor formed using a substrate containing a conductive material is applied as an N-type transistor. An example in which a transistor formed using an oxide semiconductor is used will be described.

[0083] <Configuration example> FIG. 7 shows a P-type transistor and an N-type transistor included in the semiconductor device of this embodiment. vinegar.

[0084] The P-type transistor 160 shown in FIG. 7 is a channel formed on a substrate 100 including a semiconductor material. A pair of impurity regions are provided so as to sandwich the channel forming region. The regions 114a and 114b and the pair of high concentration impurity regions 120a and 120b (collectively A gate insulating layer 115 is formed on the channel forming region 116. 108a, a gate electrode layer 110a provided on the gate insulating layer 108a, and an impurity region 1 A source electrode layer 130a electrically connected to the impurity region 114b is electrically connected to the impurity region 114b. and a drain electrode layer 130b.

[0085] Sidewall insulating layers 118 are provided on the sides of the gate electrode layer 110a. In addition, in the region of the substrate 100 including the semiconductor material that does not overlap with the sidewall insulating layer 118, has a pair of high concentration impurity regions 120a and 120b, A pair of metal compound regions 124a and 124b are present on the substrate 1. An element isolation insulating layer 106 is provided on the semiconductor device 100 so as to surround a P-type transistor 160. An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided to cover the P-type transistor 160. The source electrode layer 130a and the drain electrode layer 130b are formed by the interlayer insulating layer 126 and the A pair of metal compound regions 124a, 124b are formed through an opening formed in the interlayer insulating layer 128. That is, the source electrode layer 130a is electrically connected to one of the metal compound regions 4b. The high concentration impurity region 120a and the impurity region 114a are electrically connected to each other through the region 124a. The drain electrode layer 130b is connected to the high concentration impurity region 110b via the metal compound region 124b. 20b and the impurity region 114b.

[0086] In addition, the lower layer of the N-type transistor 164 described later is made of the same material as the gate insulating layer 108a. an insulating layer 108b made of the same material as the gate electrode layer 110a; The electrode layer 130 is made of the same material as the source electrode layer 130a and the drain electrode layer 130b. c is provided.

[0087] The N-type transistor 164 shown in FIG. 136d, a gate insulating layer 138 provided on the gate electrode layer 136d, and a gate insulating layer An oxide semiconductor layer 140 is provided on the oxide semiconductor layer 138. A source electrode layer 142a electrically connected to the nitride semiconductor layer 140 and a drain electrode layer 142b.

[0088] Here, the gate electrode layer 136d is formed on the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode layer 136d, the P-type transistor The electrode layer 136a in contact with the source electrode layer 130a and the drain electrode layer 136b in contact with the source electrode layer 130a are included in the transistor 160. An electrode layer 136b is formed in contact with the electrode layer 30b. 136c is formed.

[0089] In addition, a semiconductor layer 140 is formed on the N-type transistor 164 so as to be in contact with a part of the oxide semiconductor layer 140. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode layer 14 An opening is provided that reaches the drain electrode layer 142b and the drain electrode layer 142a. , an electrode layer 150d in contact with the source electrode layer 142a, an electrode layer 150b in contact with the drain electrode layer 142b, Similarly to the electrode layers 150d and 150e, the gate The electrode layer 138 is formed through the openings in the insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. Electrode layer 150a in contact with electrode layer 136a, electrode layer 150b in contact with electrode layer 136b, and electrode layer An electrode layer 150c is formed in contact with 136c.

[0090] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 (atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 18 (atoms / cm 3 ) or less, and 5×10 17 (atoms / cm 3 ) or less It is more preferable that the hydrogen concentration in the oxide semiconductor layer 140 is sufficiently reduced and the oxide semiconductor layer 140 is highly purified. By using the above, an N-type transistor 164 having extremely excellent off-current characteristics can be obtained. In this manner, the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and highly purified is appropriately prepared. By using the above, it is possible to reduce the leakage current of the N-type transistor 164. The hydrogen concentration in the oxide semiconductor layer 140 described above was measured by secondary ion mass spectrometry (SIMS). The measurements were performed using General Ion Mass Spectrometry.

[0091] An insulating layer 152 is provided on the interlayer insulating layer 146. Electrode layers 154a, 154b, 154c, and 154d are provided so as to include The electrode layer 154a is in contact with the electrode layer 150a, and the electrode layer 154b is in contact with the electrode layer 150a. The electrode layer 154c is in contact with the electrode layer 150c and the electrode layer 150d. electrode layer 154d contacts electrode layer 150e.

[0092] The source electrode layer 130a of the P-type transistor 160 shown in this embodiment is an upper layer region. The electrode layer 136a, the electrode layer 150a, and the electrode layer 154a are electrically connected to the electrode layer 136a, the electrode layer 150a, and the electrode layer 154a provided in the region. Therefore, the source electrode layer 130a of the P-type transistor 160 is formed by these conductive layers. By appropriately forming the electrodes of the N-type transistor 164 provided in the upper layer region, It is possible to electrically connect the P-type transistor to any of the layers. Similarly, the drain electrode layer 130b is also formed on the N-type transistor 16 provided in the upper layer region. It is possible to electrically connect the electrode layer of the semiconductor device 4 to any of the electrode layers of the semiconductor device 4. Although not shown, the gate electrode layer 110a of the P-type transistor 160 is formed in the upper layer region. Through the electrode layer, the N-type transistor 164 is electrically connected to one of the electrode layers of the N-type transistor 164. It is also possible to configure the device to be connected to the

[0093] Similarly, the source electrode layer 142a of the N-type transistor 164 shown in this embodiment is , and is electrically connected to the electrode layer 130c and the electrode layer 110b provided in the lower layer region. Therefore, the source electrode layer 130a of the N-type transistor 164 is formed by appropriately forming these conductive layers. By this, the gate electrode layer 142a of the P-type transistor 160 provided in the lower layer region , the source electrode layer 130a, or the drain electrode layer 130b. Although not shown in FIG. 7, the gate electrode of the N-type transistor 164 The layer 136d or the drain electrode layer 142b is connected to the P-type Alternatively, the transistor 160 may be electrically connected to any of the electrode layers. do.

[0094] By appropriately providing the above-mentioned P-type transistor 160 and N-type transistor 164, In addition, the N-type transistor 164 of the circuit can be It is not necessary that all of the transistors are formed using an oxide semiconductor. For example, when a semiconductor device is used, The N-type transistors that make up the logic gates are formed using a substrate containing semiconductor material. A transistor is applied to control the electrical connection between the logic gate and the cathode of the battery. A transistor formed using an oxide semiconductor is used as an N-type transistor. It is possible.

[0095] <Production process example> Next, an example of a method for manufacturing the P-type transistor 160 and the N-type transistor 164 will be described. First, a method for fabricating a P-type transistor 160 will be described with reference to FIG. Then, a method for fabricating the N-type transistor 164 will be described with reference to FIGS. 9 and 10. and explain.

[0096] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 8(A)). The substrate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. The substrates can be used for semiconductor devices such as silicon germanium, compound semiconductor substrates, and SOI substrates. In this embodiment, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has silicon on an insulating surface. The term "substrate" refers to a substrate having a semiconductor layer formed thereon. In this specification, however, the term "substrate" refers to a substrate having a silicon layer formed on an insulating surface. The concept is used to include substrates having a semiconductor layer made of a material other than silicon. Therefore, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The I substrate also has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This is to be included.

[0097] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. The protective layer 102 is made of, for example, silicon oxide or silicon nitride. For example, an insulating layer made of silicon oxynitride or the like can be used. Later, impurities that impart n-type conductivity are added to control the threshold voltage of the semiconductor device. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0098] Next, etching is performed using the protective layer 102 as a mask. The part of the substrate 100 in the area where the ion implantation is not performed (exposed area) is removed. The semiconductor region 104 is formed (see FIG. 8B). It is preferable to use a gas such as fluorine, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0099] Next, an insulating layer is formed so as to cover the semiconductor region 104, and an insulating layer is formed in a region overlapping the semiconductor region 104. The insulating layer in the region is selectively removed to form an element isolation insulating layer 106 (see FIG. 8(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. The insulating layer is removed by chemical mechanical polishing (CMP). There are processes such as polishing (polishing) and etching, but which one is used? After the semiconductor region 104 is formed or after the element isolation insulating layer 106 is formed, In this case, the protective layer 102 is removed.

[0100] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0101] The insulating layer will later become the gate insulating layer, and is deposited using CVD, sputtering, etc. Obtained silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or a multilayer structure of a film containing tungsten oxide, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more. 00 nm or less.

[0102] The layer containing the conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. The insulating layer can be formed of a semiconductor material such as polycrystalline silicon that contains a conductive material. The method for forming the layer containing the conductive material is not particularly limited, and examples thereof include a deposition method, Various film formation methods such as CVD, sputtering, and spin coating can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. This section shall show the following:

[0103] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 10. 8a, a gate electrode layer 110a is formed (see FIG. 8(C)).

[0104] Next, an insulating layer 112 is formed to cover the gate electrode layer 110a (see FIG. 8C). Then, boron (B) or aluminum (Al) is added to the semiconductor region 104 to form a shallow junction. A pair of impurity regions 114a and 114b having the same length are formed (see FIG. 8(C)). In order to form a P-type transistor, boron or aluminum is added, but in order to form an N-type transistor, To form a transistor, impurity elements such as phosphorus (P) or arsenic (As) can be added. By forming the pair of impurity regions 114a and 114b, the gate of the semiconductor region 104 is A channel formation region 116 is formed under the insulating layer 108a (see FIG. 8(C)). The concentration of the added impurities can be appropriately set. However, since the semiconductor element is highly finely divided, In this embodiment, the insulating layer 112 is preferably made of a high concentration of Zn. After forming the first impurity region, a pair of impurity regions 114a and 114b are formed. As a step of forming the insulating layer 112 after forming the pair of impurity regions 114a and 114b, is also good.

[0105] Next, the sidewall insulating layer 118 is formed (see FIG. 8(D)). The edge layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying anisotropic By applying a high-speed etching process, it can be formed in a self-aligned manner. At that time, the insulating layer 112 is partially etched to form a pair of gate electrode layers 110a and a top surface of the gate electrode layer 110b. It is preferable that the upper surfaces of the impurity regions 114a and 114b are exposed.

[0106] Next, the gate electrode layer 110a, the pair of impurity regions 114a and 114b, the sidewall An insulating layer is formed to cover the insulating layer 118 and the like. Boron (B) and aluminum (Al) are added to a part of 114b to form a pair of high-concentration In this case, the N-type transistor is also formed. To form a transistor, impurity elements such as phosphorus (P) or arsenic (As) can be added. Thereafter, the insulating layer is removed, and the gate electrode layer 110a and the sidewall insulating layer 118 are left. Then, a metal layer 122 is formed so as to cover the pair of high concentration impurity regions 120a, 120b, etc. ( See FIG. 8(E). The metal layer 122 is formed by a method such as vacuum deposition, sputtering, or spin coating. The metal layer 122 can be formed by using any of various deposition methods. Formed using a metal material that reacts with the constituent semiconductor material to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, Examples include nickel, cobalt, and platinum.

[0107] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A pair of metal compound regions 124a, 124b are in contact with the high concentration impurity regions 120a, 120b. b is formed (see FIG. 8(F)). Note that polycrystalline silicon is used as the gate electrode layer 110a. When using a metal layer 122, the metal layer 122 of the gate electrode layer 110a is also in contact with the metal layer 122. A compound region will be formed.

[0108] As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but chemical reactions involving the formation of metal compounds are preferred. In order to improve the controllability of the reaction, it is necessary to use a method that allows for very short heat treatment times. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region having a sufficiently high electrical conductivity. By doing so, the electrical resistance can be sufficiently reduced, and the element characteristics can be improved. After metal compound regions 124a, 124b are formed, metal layer 122 is removed.

[0109] Next, an interlayer insulating layer 126 and an interlayer insulating film 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, oxide The insulating layer 11 can be formed using a material containing an inorganic insulating material such as tantalum. Alternatively, the insulating layer 11 may be formed using an organic insulating material such as acrylic. Although the insulating layer 126 and the interlayer insulating layer 128 are of a two-layer structure, the configuration of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface of the interlayer insulating layer 128 may be treated by CMP, etching, or the like. It is preferable to flatten the surface of the substrate by a flattening agent.

[0110] Thereafter, openings are formed in the interlayer insulating layer, the openings reaching the pair of metal compound regions 124a and 124b. An opening is formed, and the source electrode layer 130a and the drain electrode layer 130b are formed in the opening. The source electrode layer 130a and the drain electrode layer 130b are, for example, formed with an opening. After forming a conductive layer in the area including the conductor by using a PVD method or a CVD method, etching and C The conductive layer can be formed by removing a portion of the conductive layer using a method such as MP. do.

[0111] When the source electrode layer 130a and the drain electrode layer 130b are formed, For example, a titanium film or a nitride film is applied to the area including the opening. When a thin titanium film is formed and then a tungsten film is formed to fill the opening, Then, unnecessary tungsten, titanium, titanium nitride, etc. are removed by CMP. In addition, the surface flatness of the source electrode layer 130a can be improved. By planarizing the surface including the drain electrode layer 130b, the following steps can be performed satisfactorily. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0112] In this case, the source electrode layer 1 in contact with the pair of metal compound regions 124a and 124b is Although only the drain electrode layer 30a and the drain electrode layer 130b are shown, in this step, A functional electrode layer (for example, electrode layer 130c in FIG. 7) can be formed at the same time. Materials that can be used for the source electrode layer 130a and the drain electrode layer 130b There is no particular limitation on the material, and various conductive materials can be used. For example, molybdenum, Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium The following conductive materials can be used.

[0113] As a result of the above, a P-type transistor 160 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. The multi-layer wiring structure is made of a laminated structure of an interlayer insulating layer and a conductive layer. In addition, a highly integrated circuit can be provided by the same process as the above. It is also possible to form an N-type transistor using a substrate 100 containing a semiconductor material. That is, in the above-mentioned process, the impurity element to be added to the semiconductor region is phosphorus (P) or arsenic (H). By changing the impurity element to something like As (As), an N-type transistor can be formed. can be done.

[0114] Next, an N-type transistor 164 is formed on the interlayer insulating layer 128 with reference to FIGS. 9 and 10 show various electrodes on the interlayer insulating layer 128. Since this shows the manufacturing process of the electrode layer and the N-type transistor 164, The P-type transistor 160 and other components present below the capacitor 164 are omitted.

[0115] First, the interlayer insulating layer 128, the source electrode layer 130a, the drain electrode layer 130b, and the electrode layer 1 An insulating layer 132 is formed on the substrate 30c (see FIG. 9(A)). The insulating layer 132 is formed by a PVD method or a CV method. It can be formed by using a method such as method D. Also, silicon oxide, silicon nitride oxide, and nitride Materials containing inorganic insulating materials such as silicon, hafnium oxide, aluminum oxide, and tantalum oxide It can be formed using materials.

[0116] Next, the source electrode layer 130a, the drain electrode layer 130b, and An opening is formed that reaches the electrode layer 130c. At this time, the gate electrode layer 136d is to be formed later. An opening is also formed in the area where the conductive layer 13 is to be formed. The opening is formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. Etching can be done by either wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 134 can be formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 134 include molybdenum, titanium, chromium, and the like. Conductive materials such as aluminum, tantalum, tungsten, aluminum, copper, neodymium, and scandium These include materials, their alloys, and compounds (e.g., nitrides).

[0117] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and C After forming a thin titanium nitride film by the VD method, a tungsten film is deposited to fill the opening. The titanium film formed by the PVD method is The oxide film at the interface is reduced, and the lower electrode layer (here, the source electrode layer 130a and the drain electrode layer The contact resistance between the insulating layer 130 and the electrode layer 130b, the electrode layer 130c, etc. is reduced. The titanium nitride film formed in the above has a barrier function to suppress the diffusion of conductive materials. After forming a barrier film using titanium or titanium nitride, a copper film is formed by plating. Good too.

[0118] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. 134 is removed to expose the insulating layer 132, and the electrode layers 136a, 136b, An electrode layer 136c and a gate electrode layer 136d are formed (see FIG. 9C). A portion of the layer 134 is removed to form the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode When forming the pole layer 136d, it is desirable to process it so that the surface is flat. Thus, the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, the gate electrode By planarizing the surface of the layer 136d, it is possible to form good electrodes, wiring, and insulation in the subsequent steps. It is possible to form a layer, a semiconductor layer, etc.

[0119] Next, the insulating layer 132, the electrode layer 136a, the electrode layer 136b, the electrode layer 136c, and the gate electrode A gate insulating layer 138 is formed to cover the layer 136d (see FIG. 9(D)). The insulating layer 138 can be formed by using a CVD method, a sputtering method, or the like. The insulating layer 138 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or aluminum oxide. It is preferable that the oxide layer is formed so as to contain tungsten oxide, hafnium oxide, tantalum oxide, or the like. The gate insulating layer 138 may have a single layer structure or a multilayer structure. Nitrogen oxide is produced by the plasma CVD method using silane (SiH4), oxygen, and nitrogen as gases. The gate insulating layer 138 can be formed of silicon carbide. The thickness of the gate insulating layer 138 can be Although not particularly limited, the thickness can be, for example, 10 nm or more and 500 nm or less. In the case of the structure, for example, a first gate insulating layer having a film thickness of 50 nm to 200 nm and a first It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the gate insulating layer. It is appropriate.

[0120] Note that an oxide semiconductor that has been made i-type or substantially i-type by removing impurities ( Since highly purified oxide semiconductors are extremely sensitive to interface states and interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is heavily That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is There will be a demand for quality improvement.

[0121] For example, the high-density plasma CVD method using microwaves (2.45 GHz) has a high dielectric strength and This is advantageous in that a high-quality gate insulating layer 138 with high purity can be formed. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made to be a good one.

[0122] Of course, if it can form a good insulating layer as a gate insulating layer, it is possible to use it with high purification. Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. The above method can be applied. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, a layer having good film quality as the gate insulating layer 138 may be used. The present invention provides a gate insulating film that can reduce the interface state density with an oxide semiconductor layer and form a good interface. Then, a gate insulating layer 138 may be formed.

[0123] Furthermore, at 85°C, 2 × 10 6 (V / cm), 12-hour gate bias-thermal stress test In a BT test, when impurities are added to an oxide semiconductor, the impurities and the oxide The bonds with the main component of the semiconductor are broken by a strong electric field (B: bias) and high temperature (T: temperature). The generated dangling bonds induce a drift in the threshold voltage (Vth).

[0124] In response to this, impurities in the oxide semiconductor, particularly hydrogen and water, are eliminated as much as possible, and the above-mentioned By improving the interface characteristics with the gate insulating layer, the transistor is stable even in BT tests. It is possible to obtain stars.

[0125] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by a method such as etching to form an island-shaped oxide semiconductor layer 140. (See FIG. 9(E)).

[0126] The oxide semiconductor layer may be In-Ga-Zn-O, In-Sn-Zn-O, or In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn It is preferable to use a Zn-O-based or Zn-O-based oxide semiconductor layer, and in particular an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O based metal oxide ter is used as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using the get. By adding silicon to an amorphous oxide semiconductor layer, crystallization of the layer can be suppressed. For example, a target containing 2% to 10% by weight of SiO2 is used to perform oxidation. A compound semiconductor layer may be formed.

[0127] As a target for forming an oxide semiconductor layer by a sputtering method, for example, A target made of a metal oxide mainly composed of zinc oxide can be used. Metal oxide target containing Ga and Zn (composition ratio: In2O3:Ga2O3 :ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom ratio] ) can also be used. Metal oxide targets containing In, Ga, and Zn can also be used. As a substrate, In:Ga:Zn=1:1:1 [atomic ratio] or In:Ga:Zn=1 A target having a composition ratio of 1:2 [atom ratio] may be used. The target filling rate is 90% or more and 100% or less, preferably 95% or more (e.g., 99.9%). By using a metal oxide target with a high filling rate, it is possible to form a dense oxide semiconductor. A layer is formed.

[0128] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are preferably present at a level of several ppm. It is preferable to use a high-purity gas in which the concentration of contaminants has been reduced to about a few ppb.

[0129] When the oxide semiconductor layer is formed, the substrate is held in a treatment chamber that is kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer Also, damage caused by sputtering is reduced. The residual moisture in the chamber is removed and a sputtering gas from which hydrogen and water have been removed is introduced to form a metal oxide. The oxide semiconductor layer is formed by using the target as a target. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump is used. A titanium sublimation pump or a titanium sublimation pump can be used as the exhaust means. A cryopump with a cold trap may be used. The process chamber is filled with, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably Since the oxide semiconductor formed in the processing chamber is exhausted, The concentration of impurities contained in the body layer can be reduced.

[0130] The formation conditions are, for example, a distance of 100 mm between the substrate and the target and a pressure of 0. 6 Pa, DC power 0.5 kW, oxygen atmosphere (oxygen flow rate 100%) In addition, if a pulsed direct current (DC) power supply is used, This reduces the amount of powdery material (also called particles or dust) that is generated during film formation, and the film thickness distribution is uniform. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less. The thickness is 5 nm to 30 nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0131] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced into the preheater. A reverse sputtering process is performed to generate plasma, and the dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtered material by removing the sputtered material. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The surface is then modified by bombarding it with ions. In the method, a high-frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. is also good.

[0132] The oxide semiconductor layer may be etched by either dry etching or wet etching. Of course, both can be used in combination. In order to etch the material, the etching conditions (etching gas, etching solution, etc.) are adjusted according to the material. Etching time, temperature, etc. are set appropriately.

[0133] The etching gas used in the dry etching is, for example, a gas containing chlorine (a chlorine-based gas). For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4, etc.). In addition, gases containing fluorine (fluorine-based gases, such as tetrafluoride Carbon (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane ( CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (He ), or a gas containing a rare gas such as argon (Ar), etc. may also be used.

[0134] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) Inductively coupled plasma etching can be used. It can be etched into the desired shape. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate side, etc. are set appropriately.

[0135] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. In addition, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0136] Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. The temperature of the first heat treatment can be set to 1000° C., so that the oxide semiconductor layer can be dehydrated or dehydrogenated. The temperature is set to 300° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. A heat treatment is performed at 450° C. for 1 hour in an atmosphere. During this time, the oxide semiconductor layer 140 is Ensure that there is no contact with the gas and that no water or hydrogen is re-mixed.

[0137] The heat treatment device is not limited to an electric furnace, and may be any device that utilizes heat conduction from a medium such as a heated gas, or The heating device may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0138] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is put in and heated for a few minutes, after which the GRTA process is carried out, in which the plate is removed from the inert gas. GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, it can be applied even under temperature conditions that exceed the distortion point of the substrate.

[0139] The first heat treatment is performed in a vacuum chamber mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.). It is preferable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. For example, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device may be , 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0140] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become crystalline. For example, the crystallinity is 90% or more, or 80% or more. In some cases, the oxide semiconductor layer may be a microcrystalline oxide semiconductor layer having a crystallinity of 0% or more. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be an amorphous oxide semiconductor layer that does not contain crystalline components. There are cases like this.

[0141] In addition, microcrystals (grain size 1 nm) are formed in the amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer). and 20 nm or less (typically 2 nm or more and 4 nm or less) are mixed. In some cases.

[0142] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, it is possible to use an In-Ga-Zn-O metal oxide target. When forming an oxide semiconductor layer, the crystal of In2Ga2ZnO7, which has electrical anisotropy, is used. By forming a microcrystal part in which grains are oriented, the electrical characteristics of an oxide semiconductor layer are changed. can be done.

[0143] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a specific direction, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. As a result, the insulating property in a direction perpendicular to the surface of the oxide semiconductor layer can be improved. Such a microcrystal portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. Possesses the ability.

[0144] Note that the oxide semiconductor layer having the above-described microcrystal portion is an oxide semiconductor layer formed by GRTA treatment. The Zn content can be reduced by heating the surface of the Zn alloy. By using a sputtering target smaller than the amount of .

[0145] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment may be performed on the oxide semiconductor layer before the first heat treatment. The substrate is then removed from the mold and a photolithography process is performed.

[0146] The heat treatment may have a dehydration or dehydrogenation effect on the oxide semiconductor layer 140. Such dehydration treatment, dehydrogenation treatment, etc. The oxidation treatment is carried out by forming a source electrode layer and a drain electrode layer on the oxide semiconductor layer 140 after the oxide semiconductor layer is formed. After laminating the source electrode layer, or forming a protective insulating layer on the source electrode layer and the drain electrode layer, In addition, such a dehydration treatment can be performed at any time, such as after the dehydration treatment. The dehydrogenation treatment may be carried out not only once but also multiple times.

[0147] Next, the source electrode layer 142a and the drain electrode The source electrode layer 142a and the drain electrode layer 142b are formed (see FIG. 9F). In the step 42b, a conductive layer is formed so as to cover the oxide semiconductor layer 140, and then the conductive layer is selectively The etched portion can be formed by etching.

[0148] The conductive layer is formed by using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed of a material such as aluminum, chromium, copper, or tin. An element selected from the group consisting of niobium, titanium, molybdenum, and tungsten, or a combination of the above elements. Manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, a material selected from one or more of aluminum, thorium, and aluminum may be used. Minium, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a single element selected from the group consisting of ruthenium and cadmium may be used. The insulating film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of an aluminum film with a titanium film laminated on top, Examples of such a thin film include a three-layer structure in which a silicon film, an aluminum film, and a titanium film are laminated.

[0149] Here, the exposure to light when forming the mask used for etching is performed using ultraviolet light, KrF laser light, or Ar It is preferable to use F laser light.

[0150] The channel length (L) of the transistor is determined by the distance between the bottom end of the source electrode layer 142a and the drain electrode It is determined by the distance between the bottom end of the layer 142b and the channel length (L) of less than 25 nm. When performing exposure to ultraviolet light, the wavelength is extremely short, ranging from a few nm to a few tens of nm. Exposure to form a mask is performed using ultra violet. The ion implantation method has high resolution and a large depth of focus. Therefore, the channel length of the transistor to be formed later can be reduced. It is also possible to set (L) to 10 nm or more and 1000 nm or less, thereby enabling high-speed circuit operation. It can be made.

[0151] In addition, when the conductive layer is etched, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted as appropriate. Therefore, in this step, a part of the oxide semiconductor layer 140 is etched, and a groove (a recess In some cases, the oxide semiconductor layer may have a gate insulating film.

[0152] In addition, between the oxide semiconductor layer 140 and the source electrode layer 142a or between the oxide semiconductor layer 140 and the source electrode layer 142b, An oxide conductive layer may be formed between the drain electrode layer 142b and the oxide conductive layer. The metal layers for forming the source electrode layer 142a and the drain electrode layer 142b are continuously formed. The oxide conductive layer can be formed in the source region or the drain region. By providing such an oxide conductive layer, the source region or the drain region can be formed. Since the resistance of the gate region can be reduced, high-speed operation of the transistor can be achieved.

[0153] In order to reduce the number of masks used and the number of processes, the exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone optical mask, and this is used for etching. The resist mask formed using the multi-tone mask has a plurality of thicknesses. The shape becomes stepped, and the shape can be further deformed by ashing. It can be used in multiple etching processes to process different patterns. By using the multi-tone mask, resist patterns corresponding to at least two different patterns can be produced. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, simplifying the process.

[0154] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the exposed surface of the oxide semiconductor layer is treated by the plasma treatment. Water and other substances adhering to the surface are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. may be carried out.

[0155] Next, the protective insulating layer 1 in contact with a part of the oxide semiconductor layer 140 is removed without exposing it to the air. 44 is formed (see FIG. 9(G)).

[0156] The protective insulating layer 144 is formed by mixing impurities such as water and hydrogen into the protective insulating layer 144 using a method such as sputtering. The thickness of the layer is at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide or silicon nitride. , silicon oxynitride, silicon nitride oxide, etc. Also, the structure may be a single layer structure. The substrate temperature when the protective insulating layer 144 is formed is set to room temperature or higher and 300 The temperature is preferably set to 0.4 ° C. or less, and the atmosphere is a rare gas (typically argon) atmosphere or an oxygen atmosphere. It is preferable to use an atmosphere of oxygen or a mixture of a rare gas (typically argon) and oxygen.

[0157] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140 or The hydrogen extracts oxygen from the oxide semiconductor layer 140, and the oxide semiconductor layer 14 The back channel side of MOSFET 0 becomes low-resistance, which may result in the formation of a parasitic channel. Therefore, in order to prevent the protective insulating layer 144 from containing hydrogen as much as possible, the formation method is It is important not to use

[0158] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The oxide semiconductor layer 140 and the protective insulating layer 144 are preferably formed so as not to contain hydrogen, a hydroxyl group, or moisture. This is to make it possible.

[0159] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may contain hydrogen atoms, water (H Since compounds containing hydrogen atoms such as 2O) have been removed, the protective insulating material formed in the treatment chamber The concentration of impurities contained in the edge layer 144 can be reduced.

[0160] The sputtering gas used in forming the protective insulating layer 144 may be hydrogen, water, a hydroxyl group, or Impurities such as hydrides are removed to a few ppm (preferably a few ppb). It is preferable to use a high purity gas.

[0161] Then, a second heat treatment (preferably 2 It is preferable to carry out the heating at a temperature between 00°C and 400°C, for example between 250°C and 350°C. For example, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The variation in the electrical characteristics of the transistors can be reduced.

[0162] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by holding the temperature constant or by heating from room temperature to 100°C. Repeat heating to a temperature of 200°C or more and cooling from the heating temperature to room temperature several times. This heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. If the heat treatment is performed under reduced pressure, the heating time can be shortened. This may be carried out instead of the second heat treatment, or may be carried out before or after the second heat treatment.

[0163] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 10(A)). The interlayer insulating layer 146 can be formed by using a PVD method, a CVD method, or the like. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as tantalum. After formation, the surface can be flattened by methods such as CMP or etching. desirable.

[0164] Next, electrodes are formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Layer 136a, electrode layer 136b, electrode layer 136c, source electrode layer 142a, drain electrode layer An opening is formed that reaches 142b, and a conductive layer 148 is formed so as to fill the opening. (See FIG. 10(B)). The opening is formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. It is possible. Either wet etching or dry etching can be used. However, from the viewpoint of fine processing, it is preferable to use dry etching. The layer 148 can be formed by a deposition method such as a PVD method or a CVD method. Materials that can be used to form 148 include molybdenum, titanium, chromium, tantalum, and the like. Conductive materials such as zinc, tungsten, aluminum, copper, neodymium, and scandium, Examples of such materials include alloys and compounds (eg, nitrides) of these materials.

[0165] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CVD After forming a thin titanium nitride film by the method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has an interface The oxide film of the lower electrode (here, electrode layer 136a, electrode layer 136b, electrode layer 136c) is reduced. 6c) a function of reducing contact resistance with the source electrode layer 142a and the drain electrode layer 142b) In addition, the titanium nitride film formed thereafter has a burr-like effect that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, etc., plating is performed. The copper film may be formed by a method.

[0166] After the conductive layer 148 is formed, the conductive layer 14 is removed by a method such as etching or CMP. 8 is removed to expose the interlayer insulating layer 146, and the electrode layers 150a, 150b, Electrode layers 150c, 150d, and 150e are formed (see FIG. 10(C)). A part of the conductive layer 148 is removed to form the electrode layer 150a, the electrode layer 150b, and the electrode layer 150 c) When forming the electrode layer 150d and the electrode layer 150e, the surfaces are processed to be flat. In this manner, the interlayer insulating layer 146, the electrode layer 150a, the electrode layer 150b, The surfaces of the electrode layers 150c, 150d, and 150e are flattened, so that the following In the process, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, and the like.

[0167] Further, an insulating layer 152 is formed, and the electrode layers 150a, 150b, Openings are formed so as to reach the electrode layers 150c, 150d, and 150e. After forming a conductive layer so as to embed the conductive layer in the A part of the insulating layer 152 is removed to expose the electrode layer 154a, the electrode layer 154b, and the electrode layer 1 54c, an electrode layer 154d is formed (see FIG. 10(D)). Since this is similar to the case of forming the above, details will be omitted.

[0168] When the N-type transistor 164 is fabricated by the above-described method, the oxide semiconductor layer 140 Hydrogen concentration is 5 x 10 19 (atoms / cm 3 ) or less, and the N-type transistor 164 It is possible to reduce the leakage current. 64 is applied to the semiconductor device shown in the first to fourth embodiments, This makes it possible to reduce standby power consumption.

[0169] <Modification> 11 to 14 show modified examples of the configuration of the N-type transistor 164. The configuration of the transistor 160 is the same as above.

[0170] FIG. 11 shows a gate electrode layer 136d under an oxide semiconductor layer 140, and a source electrode layer The drain electrode layer 142a and the drain electrode layer 142b are in contact with each other on the lower side of the oxide semiconductor layer 140. 1 shows an N-type transistor 164.

[0171] The major difference between the configuration shown in FIG. 11 and the configuration shown in FIG. 7 is that the source electrode layer 142a and One example is the position of connection between the drain electrode layer 142b and the oxide semiconductor layer 140. In the configuration shown in FIG. 7, the source electrode layer 142 is formed on the upper surface of the oxide semiconductor layer 140. a and the drain electrode layer 142b, whereas in the configuration shown in FIG. The source electrode layer 142a and the drain electrode layer 142b are in contact with the lower side of the semiconductor layer 140. Due to this difference in contact, the arrangement of other electrode layers, insulating layers, etc. may differ. The details of each component are the same as those in Figure 7.

[0172] Specifically, the N-type transistor 164 shown in FIG. 11 is provided on the interlayer insulating layer 128. a gate electrode layer 136d formed thereon, and a gate insulating layer 138 formed on the gate electrode layer 136d. A source electrode layer 142a and a drain electrode layer 142b are provided on the gate insulating layer 138. b, and an oxide semiconductor layer in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. The N-type transistor 164 has an oxide semiconductor layer 140 on it. A protective insulating layer 144 is provided to cover the insulating film 140.

[0173] FIG. 12 shows an N-type transistor having a gate electrode layer 136d on an oxide semiconductor layer 140. 12A shows the source electrode layer 142a and the drain electrode layer 164. 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140. FIG. 12B shows an example of a structure of a source electrode layer 142a and a drain electrode layer 14 2b is in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140. FIG.

[0174] 12. The major difference between the configuration shown in FIG. 7 or FIG. 11 and the configuration shown in FIG. 12 is that the oxide semiconductor layer 14 12A and 12B, the gate electrode layer 136d is provided on the gate electrode layer 136d. 2(B) is that the source electrode layer 142a and the drain electrode layer 142 b contacts the lower surface or the upper surface of the oxide semiconductor layer 140. Due to these differences, the arrangement of other electrode layers, insulating layers, etc. The details of each component are the same as those in FIG. 7.

[0175] Specifically, the N-type transistor 164 shown in FIG. 12A is provided on the interlayer insulating layer 128. The source electrode layer 142a and the drain electrode layer 142b are formed by the above-mentioned and an oxide semiconductor layer 140 in contact with the upper surface of the drain electrode layer 142b. A gate insulating layer 138 is provided on the gate insulating layer 140, and an oxide semiconductor layer 1 on the gate insulating layer 138. 40 and a gate electrode layer 136d in a region overlapping with the gate electrode 136a.

[0176] In addition, an N-type transistor 164 shown in FIG. 12(B) is provided on the interlayer insulating layer 128. The oxide semiconductor layer 140 is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The source electrode layer 142a and the drain electrode layer 142b, the oxide semiconductor layer 140, and the source A gate insulating layer 138 is provided on the gate electrode layer 142a and the drain electrode layer 142b. A gate electrode layer 13 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. 6d and.

[0177] In addition, in the configuration shown in FIG. 12, components are omitted compared to the configuration shown in FIG. In this case, the electrode layer 150a or the electrode layer 154a may be formed. Of course, even in the configuration shown in Figure 7, It goes without saying that components that are not

[0178] FIG. 13 shows a case where the size of the element is relatively large, and a The N-type transistor 164 is shown having a gate electrode layer 136d. Since the requirements for flatness and coverage are relatively low, wiring and electrodes can be easily insulated. It is not necessary to form the conductive layer so as to be embedded in the edge layer. For example, the conductive layer may be patterned after it is formed. By performing this process, the gate electrode layer 136d and the like can be formed.

[0179] The major difference between the configuration shown in FIG. 13(A) and the configuration shown in FIG. 13(B) is that the source electrode layer 1 42a and the drain electrode layer 142b are disposed on the lower or upper surface of the oxide semiconductor layer 140. And due to these differences, The arrangement of the electrode layers, insulating layers, etc. is different. 7 and so on.

[0180] Specifically, the N-type transistor 164 shown in FIG. 13A is provided on the interlayer insulating layer 128. A gate electrode layer 136d is formed on the gate electrode layer 136d. A gate insulating layer 1 is formed on the gate electrode layer 136d. 38, and a source electrode layer 142a and a drain electrode layer 142b provided on the gate insulating layer 138. 142b, and the oxide layer in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b. and a semiconductor layer 140.

[0181] In addition, an N-type transistor 164 shown in FIG. 13(B) is provided on the interlayer insulating layer 128. a gate electrode layer 136d formed thereon, and a gate insulating layer 138 formed on the gate electrode layer 136d. The oxide semiconductor layer 136d is formed on the gate insulating layer 138 in a region overlapping the gate electrode layer 136d. a source electrode layer provided in contact with the upper surface of the oxide semiconductor layer; The drain electrode layer 142a and the drain electrode layer 142b.

[0182] In addition, in the configuration shown in FIG. 13, the number of components is reduced compared to the configuration shown in FIG. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0183] FIG. 14 shows a case where the size of the element is relatively large, and a An N-type transistor 164 is shown having a gate electrode layer 136d. The requirements for surface flatness and coverage are relatively low, so wiring, electrodes, etc. It is not necessary to form the conductive layer so as to be embedded in the insulating layer. For example, the conductive layer may be patterned after the formation of the conductive layer. By performing etching, the gate electrode layer 136d and the like can be formed.

[0184] The major difference between the configuration shown in FIG. 14(A) and the configuration shown in FIG. 14(B) is that the source electrode layer 1 42a and the drain electrode layer 142b are disposed on the lower or upper surface of the oxide semiconductor layer 140. And due to these differences, The arrangement of the electrode layers, insulating layers, etc. is different. 7 and so on.

[0185] Specifically, the N-type transistor 164 shown in FIG. 14A is provided on the interlayer insulating layer 128. The source electrode layer 142a and the drain electrode layer 142b are formed by the above-mentioned The oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode layer 142b and the drain electrode layer 142b, 42a, the drain electrode layer 142b, and the gate insulating film provided on the oxide semiconductor layer 140. the oxide semiconductor layer 140 provided over the gate insulating layer 138 and a gate electrode layer 136d.

[0186] In addition, an N-type transistor 164 shown in FIG. 14(B) is provided on the interlayer insulating layer 128. The oxide semiconductor layer 140 is provided so as to be in contact with the upper surface of the oxide semiconductor layer 140. The source electrode layer 142a and the drain electrode layer 142b are The gate insulating layer 138 is provided on the electrode layer 142b and the oxide semiconductor layer 140. A gate electrode layer 13 is provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138. 6d and.

[0187] In addition, in the configuration shown in FIG. 14, the number of components is reduced compared to the configuration shown in FIG. In this case as well, the effect of simplifying the manufacturing process can be obtained.

[0188] In this embodiment, an N-type transistor 164 is stacked on a P-type transistor 160. The configuration of the P-type transistor 160 and the N-type transistor 164 has been described. For example, a P-type transistor and an N-type transistor may be arranged on the same plane. In addition, a P-type transistor 160 and an N-type transistor The sensor 162 may be provided so as to overlap the sensor 164.

[0189] The above-mentioned N-type transistor 164 is an N type transistor included in the semiconductor device shown in the first to fourth embodiments. By applying this to a MOSFET, it is possible to suppress the discharge of the battery during standby. In other words, the standby power consumption of the semiconductor device can be reduced. By suppressing the discharge of the battery, the life of the semiconductor device can be extended.

[0190] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0191] (Embodiment 6) In this embodiment, one of the transistors included in the semiconductor device described in any of Embodiments 1 to 4 will be described. Specifically, a semiconductor device in which a channel formation region is formed of an oxide semiconductor will be described. An example of a transistor will be described.

[0192] One mode of a transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS. explain.

[0193] 15A and 15B show an example of a planar structure and a cross-sectional structure of a transistor. A transistor 460 shown in FIG.

[0194] FIG. 15A is a plan view of a transistor 460 having a top-gate structure, and FIG. FIG. 15(A) is a cross-sectional view taken along line D1-D2 of FIG.

[0195] The transistor 460 includes an insulating layer 457, a source electrode 458, a gate insulating layer 459 ... the drain electrode layer 465a (465a1 and 465a2), the oxide semiconductor layer 462, a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, a gate The electrode layer 461 (461a, 461b) and the source or drain electrode layer 465a ( 465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also formed on the gate insulating layer 4 An opening provided in 52 electrically connects to the wiring layer.

[0196] Hereinafter, a transistor 460 is manufactured on a substrate 450 using FIGS. The process will be explained.

[0197] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0198] In this embodiment, a silicon oxide layer is formed by a sputtering method as the insulating layer 457. The substrate 450 is transferred to a processing chamber, and a spa containing high-purity oxygen from which hydrogen and moisture have been removed is used. A target gas is introduced, and a silicon target or quartz (preferably synthetic quartz) is used to heat the substrate 4. A silicon oxide layer is formed as an insulating layer 457 on the substrate 50. Note that oxygen is used as a sputtering gas. Alternatively, a mixed gas of oxygen and argon is used.

[0199] For example, the purity is 6N, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., The distance between the substrate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high frequency voltage was Power source 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = A silicon oxide film is formed by RF sputtering in a 1:1) atmosphere. The thickness of the silicon target is set to 0 nm. It can be used as a target for forming a silicon film.

[0200] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl, or moisture. The process chamber evacuated using an ion pump contains hydrogen atoms, water (H2O), and other hydrogen atoms. Since the compound containing the compound is exhausted, the compound containing the compound is not included in the insulating layer 457 formed in the processing chamber. This can reduce the concentration of impurities.

[0201] The insulating layer 457 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use high-purity gas in which impurities have been removed to the level of a few ppm or a few ppb. I wish.

[0202] The insulating layer 457 may have a laminated structure, for example, a silicon nitride layer from the substrate 450 side, Nitride insulating layers such as silicon oxynitride layers, aluminum nitride layers, and aluminum oxynitride layers The insulating layer may have a stacked structure of the oxide insulating layer and the oxide insulating layer.

[0203] For example, a silicon oxide layer and a substrate are provided with a space between them that contains high-purity nitrogen from which hydrogen and moisture have been removed. A putter gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to form a film.

[0204] Next, a conductive film is formed on the insulating layer 457, and a conductive film is formed by a first photolithography process. A resist mask is formed on the conductive film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After the electrode layers 465a1 and 465a2 are formed, the resist mask is removed (FIG. 16(A) The source and drain electrode layers 465a1 and 465a2 are divided in the cross-sectional view. Although the film is shown as a continuous film, the source electrode layer and the drain electrode The end of the layer is preferably tapered, since this improves the coverage of the gate insulating layer to be laminated thereon. It is.

[0205] The material of the source electrode layer or the drain electrode layer 465a1, 465a2 is Al, Cr , Cu, Ta, Ti, Mo, W, or an alloy containing the above elements or an alloy film made of a combination of the above elements. The material is selected from one or more of the following: zirconium, beryllium, and thorium. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a titanium film laminated on an aluminum film, A two-layer structure is formed by laminating a Ti film and an aluminum film on top of the Ti film. A three-layer structure in which a Ti film is formed is also available. In addition, titanium (Ti) and tantalum are added to Al. (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd ), scandium (Sc), or a film or alloy film made of a single or multiple combinations of elements selected from the group consisting of Alternatively, a nitride film may be used.

[0206] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are A titanium film having a thickness of 150 nm is formed by a tarpaulin deposition method.

[0207] Next, the insulating layer 457 and the source and drain electrode layers 465a1 and 465a2 are An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed on the insulating film.

[0208] Next, the oxide semiconductor layer 462 is processed into an island shape by a second photolithography process (FIG. In this embodiment, an In-Ga-Zn-O based metal oxide semiconductor film is used as the oxide semiconductor film. The film is formed by sputtering using a metal oxide target.

[0209] The oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state, and removing residual water in the treatment chamber. A sputtering gas from which hydrogen and moisture have been removed while removing the molybdenum is introduced, and a metal oxide is deposited on the target. As a starting material, an oxide semiconductor film is formed over a substrate 450. For this purpose, it is preferable to use an adsorption type vacuum pump. It is preferable to use a vacuum pump or a titanium sublimation pump. Alternatively, a turbo pump with a cold trap may be used. The exhausted processing chamber contains, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (more Preferably, the oxide film formed in the processing chamber is exhausted, since the oxide film is exhausted. The concentration of impurities in the semiconductor film can be reduced. May be heated.

[0210] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities such as these have been removed to the level of a few ppm or a few ppb. preferable.

[0211] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, Pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: argon flow rate 30sccm) atmosphere is applied. Note that pulse direct current (DC ) power supply reduces the amount of powdery material (also called particles or dust) that is generated during film formation. The oxide semiconductor film is preferably 5 nm or more and 30 nm or more in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0212] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 462 by a thermal etching method.

[0213] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the distortion point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is After heat treatment at 450°C for 1 hour in a nitrogen atmosphere, the specimen was placed in an oxygen-free environment without exposure to air. This first heat treatment prevents water and hydrogen from re-mixing into the oxide semiconductor layer, and obtains an oxide semiconductor layer. The oxide semiconductor layer 462 can be dehydrated or dehydrogenated by this.

[0214] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction from a heating element such as a resistance heating element or the like. The apparatus may be equipped with a device for heating the object to be treated by thermal radiation. For example, the GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment For example, the first heat treatment may be performed at a temperature of 650° C. to 7 The substrate is moved into an inert gas atmosphere heated to a high temperature of 00°C and heated for several minutes. Alternatively, GRTA can be performed by moving the container and releasing it from the inert gas heated to a high temperature. When used, high-temperature heat treatment can be performed in a short period of time.

[0215] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or more Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0216] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and may become fine. It may be a crystalline or polycrystalline film.

[0217] In addition, the first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is removed from the heating device. Then, the substrate is taken out and subjected to a photolithography process.

[0218] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed by After the film formation, a source electrode and a drain electrode are further laminated on the oxide semiconductor layer, and then a source This may be performed either after forming a gate insulating layer on the electrode and the drain electrode.

[0219] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask is The source or drain electrode layer 465b and the wiring layer 465c are removed (see FIG. 16C). 468 is a source electrode layer or a drain electrode layer 465a1, 465a2, which is formed using the same material and process. It may be formed as follows.

[0220] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are A titanium film having a thickness of 150 nm is formed by a photo-deposition method. The source or drain electrode layers 465a1 and 465a2 and the source or drain electrode layer 46 In the example where the same titanium film is used for the source electrode layer or the drain electrode layer 465a1, 4 The source or drain electrode layer 465b has a selectivity in etching. Therefore, the source electrode layer or the drain electrode layer 465a1 and 465a2 are not The oxide semiconductor layer 465b is preferably formed on the substrate 461 so as not to be etched during etching of the drain electrode layer 465b. The wiring layer 468 is provided on the source or drain electrode layer 465a2 that is not covered with the conductor layer 462. The source electrode layer or drain electrode layer 465a1 and the source electrode layer 465a2 are provided. Alternatively, the drain electrode layer 465b may be made of a different material having a high selectivity in an etching process. In the case of using a SiO 2 film, the source or drain electrode layer 465a2 needs to be protected during etching. The wiring layer 468 is not necessarily provided.

[0221] Note that the conductive film is etched such that the oxide semiconductor layer 462 is not removed. The materials and etching conditions are adjusted appropriately.

[0222] In this embodiment, a Ti film is used as the conductive film, and an In-G Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0223] Note that in the third photolithography step, the oxide semiconductor layer 462 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). Alternatively, a resist mask for forming the drain electrode layer 465b and the wiring layer 468 is formed by ink jet printing. If the resist mask is formed by the inkjet method, the photomask Since no wiring is used, manufacturing costs can be reduced.

[0224] Next, the insulating layer 457, the oxide semiconductor layer 462, and the source or drain electrode layer 46 5a1, 465a2, the source or drain electrode layer 465b, and the wiring layer 468. A gate insulating layer 452 is formed.

[0225] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The gate insulating layer 452 may be formed as a single layer or a stacked layer. In order to prevent a large amount of SiO2 from being contained, the gate insulating layer 452 is formed by sputtering. When the silicon oxide film is formed by sputtering, A silicon target or a quartz target is used as the target, and oxygen or is carried out using a mixed gas of oxygen and argon.

[0226] The gate insulating layer 452 is a source or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer are laminated from the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, and the high frequency power supply is 1.5 kW. , oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm=1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed by RF sputtering in air.

[0227] Next, a resist mask is formed by a fourth photolithography process, and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 that reaches the wiring layer 468. Although not shown, when the opening 423 is formed, the source electrode layer or An opening reaching the drain electrode layer 465b may be formed. An opening for the drain electrode layer 465b is formed after laminating an interlayer insulating layer. In this example, a wiring layer for connecting to a target is formed in an opening.

[0228] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a lithography process. The resist mask may be formed by an ink-jet method. When formed by the ink jet method, no photomask is used, which reduces manufacturing costs.

[0229] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium It is formed in a single layer or multilayer using metal materials such as aluminum or alloy materials that contain these as the main components. It is possible.

[0230] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are A titanium film having a thickness of 150 nm is formed by a sputtering method.

[0231] Then, a second heat treatment (preferably The temperature is 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. The second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the transistor 460 .

[0232] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature, or by heating from room temperature for 1 The temperature is raised to 00°C or higher and lowered to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0233] Through the above steps, the oxide semiconductor layer 4 is obtained, in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced. A transistor 460 having a gate insulating layer 62 can be formed (see FIG. 16(E)).

[0234] A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistor 460. Although not shown, a source electrode may be formed on the gate insulating layer 452, the protective insulating layer, and the planarizing insulating layer. An opening reaching the source electrode layer or drain electrode layer 465b is formed in the opening. A wiring layer is formed which is electrically connected to the drain electrode layer 465b.

[0235] When forming the oxide semiconductor film as described above, it is necessary to remove the residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0236] The above-described transistor may be included in the semiconductor device described in any one of the first to fourth embodiments. By applying the above, it is possible to suppress the discharge of the battery in the standby state. This makes it possible to reduce the standby power consumption of the semiconductor device. By suppressing this, the life of the semiconductor device can be extended.

[0237] Furthermore, all of the transistors included in the semiconductor device shown in any of the first to fourth embodiments may be used in the present embodiment. By using the transistors of the embodiment, the manufacturing process can be reduced and the yield can be improved. Furthermore, the manufacturing cost can be reduced.

[0238] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0239] (Embodiment 7) In this embodiment, one of the transistors included in the semiconductor device described in any of Embodiments 1 to 4 will be described. Specifically, a semiconductor device in which a channel formation region is formed of an oxide semiconductor will be described. An example of a transistor will be described.

[0240] One mode of a transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS.

[0241] 17A to 17E show examples of cross-sectional structures of transistors. The transistor 390 shown in FIG. 1E is a bottom-gate transistor. Also called ta.

[0242] Although the transistor 390 has been described as a single-gate transistor, If necessary, a transistor having a multi-gate structure having a plurality of channel formation regions may be formed. It is possible.

[0243] Hereinafter, a transistor 390 is fabricated on a substrate 394 using FIGS. The process will be explained.

[0244] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 391 is formed by a deposition process. The end of the gate electrode layer 391 is A perforated shape is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The resist mask may be formed by an inkjet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0245] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as a borosilicate glass or an aluminoborosilicate glass substrate can be used.

[0246] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. The above is recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. In general, the more barium oxide (BaO) is contained compared to boron oxide, the better the A practical heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to use

[0247] Instead of the above glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used. Alternatively, a crystallized glass substrate or the like may be used. Additionally, plastic substrates and the like can also be used as appropriate.

[0248] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. The function of the insulating layer 394 is to prevent the diffusion of impurity elements from the substrate 394. A silicon film, a silicon oxide nitride film, or a silicon oxynitride film is applied to one or more films. The laminated structure can be formed by the above.

[0249] The material of the gate electrode layer 391 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a laminated layer using an alloy material.

[0250] For example, the gate electrode layer 391 may have a two-layer laminate structure of molybdenum on an aluminum layer. A two-layer structure with a molybdenum layer on a copper layer, a two-layer structure with a molybdenum layer on a copper layer, A two-layer structure with a titanium nitride layer or a tantalum nitride layer laminated thereon, a titanium nitride layer and a molybdenum layer or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated. As the three-layer laminate structure, a tungsten layer or a tungsten nitride layer is preferably used. and an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride or It is preferable to use a laminate of a transparent conductive film and a titanium layer. The gate electrode layer can be formed using a light-transmitting conductive film. Examples of such films include conductive oxide films.

[0251] Then, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0252] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The gate insulating layer 397 may be formed as a single layer or a stacked layer. In order to prevent a large amount of isopropyl alcohol from being contained, the gate insulating layer 397 is formed by sputtering. When the silicon oxide film is formed by sputtering, A silicon target or a quartz target is used as the target, and oxygen or is carried out using a mixed gas of oxygen and argon.

[0253] The gate insulating layer 397 is a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, the first gate insulating layer may be formed by sputtering. The silicon nitride layer (SiN y (y>0) A second gate insulating layer having a thickness of 5 nm to 300 nm is formed on the first gate insulating layer. Silicon oxide layer (SiO x (x>0) is laminated to form the gate insulating layer.

[0254] In addition, hydrogen, a hydroxyl group, and moisture are preferably contained in the gate insulating layer 397 and the oxide semiconductor film 393. In order to prevent this from being included, the pre-heating chamber of the sputtering equipment is used as a pre-treatment for film formation. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which a gate insulating layer 397 is formed The substrate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100° C. or higher and 400° C. or lower. The temperature is usually between 150 and 300°C. It is preferable to use a preheating pump. However, this preheating process can be omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b are The same process may be carried out on the substrate 394 on which the above steps have been formed.

[0255] Next, an oxide semiconductor film 3 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 397. 93 is formed (see FIG. 17(A)).

[0256] Note that before the oxide semiconductor film 393 is formed by a sputtering method, argon gas is The reverse sputtering is performed by introducing the ions into the gate insulating layer 397 to generate plasma. It is preferable to remove the dust that is in the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power source to form plasma near the substrate. The surface is modified by forming an argon atmosphere. etc. may also be used.

[0257] The oxide semiconductor film 393 is formed by a sputtering method. In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxides In this embodiment, the oxide semiconductor film 393 is an In-Ga-Zn-O based The oxide semiconductor film is formed by a sputtering method using a metal oxide target. 393 is heated under a rare gas (typically argon) atmosphere, under oxygen atmosphere, or under a rare gas (typically It can be formed by sputtering in an atmosphere of argon and oxygen. In addition, when using the sputtering method, the SiO2 content is 2% by weight or more and 10% by weight or less. Alternatively, the film may be formed using a target.

[0258] The oxide semiconductor film 393 was formed by sputtering using a target of nitric oxide. A metal oxide target mainly composed of lead can be used. Another example of a target is a metal oxide target containing In, Ga, and Zn (composition ratio: As the molar ratio, In2O3:Ga2O3:ZnO=1:1:1, In:Ga:Zn =1:1:0.5 [atom ratio]) can be used. In, Ga, and Zn As a metal oxide target containing In:Ga:Zn=1:1:1 [atomic ratio], A target with a composition ratio of In:Ga:Zn=1:1:2 [atomic ratio] was used. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or less. % or more and 99.9% or less. By using a metal oxide target with a high filling rate, The formed oxide semiconductor film is a dense film.

[0259] The substrate is held in a processing chamber maintained at a reduced pressure, and the substrate is heated to a temperature above room temperature but below 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering process in which hydrogen and moisture are removed is completed. A gas is introduced, and an oxide semiconductor film 393 is formed on a substrate 394 using a metal oxide as a target. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump is used. As an exhaust means, a turbo pump with a cold trap is preferably used. The processing chamber evacuated using a cryopump may be contaminated with, for example, hydrogen atoms, water, etc. Compounds containing hydrogen atoms such as (H2O) (and more preferably compounds containing carbon atoms) are excluded. Therefore, the concentration of impurities in the oxide semiconductor film formed in the treatment chamber can be reduced. In addition, the sputtering process is performed while removing the moisture remaining in the processing chamber using a cryopump. By performing the above-mentioned process, the substrate temperature during the formation of the oxide semiconductor film 393 is set to be from room temperature to lower than 400° C. It is possible.

[0260] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 P. a. DC power supply 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere In addition, when a pulsed direct current (DC) power supply is used, the powdery material (particulate matter) generated during film formation is reduced. This is preferable because it can reduce the amount of dirt and dust that accumulates on the surface of the oxide semiconductor film and also makes the film thickness uniform. The thickness of the oxide film is preferably 5 nm to 30 nm. The appropriate thickness varies depending on the material, and an appropriate thickness may be selected depending on the material.

[0261] There are two types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, and There is a DC sputtering method, and there is also a pulsed DC sputtering method, which applies a bias in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is also used. The tarring method is mainly used when forming a metal film.

[0262] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The TA equipment can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0263] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. ECR using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0264] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering agent are interposed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting with gas components. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0265] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer. The oxide semiconductor layer 399 is then processed into an island-shaped oxide semiconductor layer 399 (see FIG. 17B). A resist mask for this purpose may be formed by an inkjet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0266] Also, when forming a contact hole in the gate insulating layer 397, the process is performed using an oxide semiconductor. This can be done when forming the coating layer 399 .

[0267] Note that the etching of the oxide semiconductor film 393 here can be performed by dry etching or wet etching. Etching may be used, or both may be used.

[0268] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C Cl4) etc.) are preferred.

[0269] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride ( SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide ( HBr), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas having a gas added thereto, etc. can be used.

[0270] As a dry etching method, parallel plate type RIE (Reactive Ion Etc. fing method and ICP (Inductively Coupled Plasma) The inductively coupled plasma etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0271] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0272] In addition, the etching solution after wet etching is washed away together with the etched material. The waste liquid of the etching solution containing the removed material is purified, and the material contained therein is The indium contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials such as these, we can make effective use of resources and reduce costs. do.

[0273] In order to etch the desired shape, the etching conditions are adjusted according to the material. Adjust the etching conditions (etching solution, etching time, temperature, etc.) as appropriate.

[0274] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate It is preferable to remove resist residues and the like adhering to the surface of the gate insulating layer 397.

[0275] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum deposition. Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The above-mentioned elements may be alloyed or alloyed in combination. Materials selected from one or more of the following: tungsten, zirconium, beryllium, and thorium The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film stacked on an aluminum film, A two-layer structure with a Ti film and an aluminum film layered on top of the Ti film. A three-layer structure is also available, in which a titanium film is formed on top of the aluminum. Ta (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium ( A film or alloy made of a single or multiple combinations of elements selected from Nd) and scandium (Sc) A film or a nitride film may be used.

[0276] A resist mask is formed on the conductive film by a third photolithography process, and selectively etched. After etching to form a source electrode layer 395a and a drain electrode layer 395b, The mask is then removed (see FIG. 17(C)).

[0277] The third photolithography process uses ultraviolet light and KrF for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 399 are irradiated with a laser beam or an ArF laser beam. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the drain electrode layer determines the channel width of the transistor to be formed later. In addition, when performing exposure with a channel length L of less than 25 nm, the number n Extreme ultraviolet rays have extremely short wavelengths of 10 nm to several tens of nm. ) is used to perform exposure when forming a resist mask in the third photolithography process. Exposure to ultraviolet light has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less, and the circuit operation This allows for faster speeds and, because the off-current value is extremely small, it also allows for lower power consumption. Cut.

[0278] Note that the conductive film is etched such that the oxide semiconductor layer 399 is not removed. The materials and etching conditions are adjusted appropriately.

[0279] In this embodiment, a Ti film is used as the conductive film, and an In-GaAs film is used as the oxide semiconductor layer 399. Using a-Zn-O oxide semiconductor, ammonia hydrogen peroxide (NH3H2O) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0280] Note that in the third photolithography step, the oxide semiconductor layer 399 is only partly etched. In some cases, the source electrode layer is formed by etching, resulting in an oxide semiconductor layer having a groove (a recess). A resist mask for forming the drain electrode layer 395a and the drain electrode layer 395b is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0281] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Resist formed using a multi-tone mask, an exposure mask that allows light to pass through in multiple intensities The etching process may be performed using a mask. The mask has a shape with multiple film thicknesses, and the shape is further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can be used to produce at least two different patterns. Therefore, the number of exposure masks can be reduced. This also eliminates the need for a corresponding photolithography process, making it possible to simplify the process.

[0282] Plasma treatment with gases such as N2O, N2, or Ar removes exposed oxide. Water adsorbed on the surface of the semiconductor layer may be removed. A plasma treatment may be performed using the gas.

[0283] When the plasma treatment is performed, the oxide semiconductor layer is protected from contact with the air. An oxide insulating layer 396 is formed as an oxide insulating layer serving as a protective insulating film (see FIG. 17(D)). In this embodiment, the oxide semiconductor layer 399 serves as the source electrode layer 395a and the drain electrode layer 395b. In a region not overlapping with the oxide insulating layer 396, the oxide semiconductor layer 399 is in contact with the oxide insulating layer 396. It is formed so that

[0284] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399, a source The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated to 100° C. A sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon target is used to deposit a defective silicon oxide layer.

[0285] For example, a silicon target with a purity of 6N and doped with boron (resistance value of 0.0 1 Ωcm), the distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0 .4Pa, DC power supply 6kW, oxygen (oxygen flow rate 100%) atmosphere, pulse D A silicon oxide layer is formed by C sputtering. The film thickness is 300 nm. Instead of a silicon target, quartz (preferably synthetic quartz) is used to form a silicon oxide layer. The sputtering gas can be oxygen or oxygen and The process is carried out using a mixture of argon and argon gas.

[0286] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 399 and the oxide insulating layer 396. This is to ensure that it is not included.

[0287] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the processing chamber The concentration of impurities contained in layer 396 can be reduced.

[0288] Note that as the oxide insulating layer 396, a silicon oxynitride layer or an oxide Alternatively, an aluminum nitride layer, an aluminum oxynitride layer, or the like can be used.

[0289] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 4 Heat treatment may be performed at 00° C. In this embodiment, the oxide insulating layer 396 has many defects. Therefore, hydrogen, moisture, and hydroxide contained in the oxide semiconductor layer 399 are removed by this heat treatment. Impurities such as bases or hydrides are diffused into the oxide insulating layer 396, and the oxide semiconductor layer 399 is The impurities contained in the above can be further reduced.

[0290] The oxide semiconductor layer 3 in which the concentration of hydrogen, moisture, hydroxyl groups, or hydrides is reduced by the above steps is obtained. A transistor 390 having 92 can be formed (see FIG. 17(E)).

[0291] When forming the oxide semiconductor film as described above, it is necessary to remove the residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. This can stabilize the oxide semiconductor film.

[0292] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is The protective insulating layer 398 is formed over the oxide insulating layer 396. The protective insulating layer 398 can be formed using a silicon nitride film, a nitride oxide film, or the like. A silicon nitride film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0293] The substrate 394 on which the oxide insulating layer 396 has been formed is heated to 100° C. The sputtering gas was heated to 400°C and contained high-purity nitrogen from which hydrogen and moisture had been removed. In this case, the silicon nitride film is formed by using a silicon target. As with the protective insulating layer 396, a protective insulating layer 398 is formed while removing residual moisture in the processing chamber. It is preferable.

[0294] When forming the protective insulating layer 398, the temperature is set to 100° C. to 400° C. during the film formation of the protective insulating layer 398. By heating the substrate 394, hydrogen or moisture contained in the oxide semiconductor layer is oxidized to an oxide insulating layer. In this case, a heat treatment is performed after the formation of the oxide insulating layer 396. This does not have to be done.

[0295] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and the silicon nitride layer are placed in the same processing chamber and a common A silicon target can be used for deposition. First, oxygen-containing sputtering gas is introduced. Then, a silicon oxide layer is formed using a silicon target mounted in the processing chamber, and then The sputtering gas was changed to one containing nitrogen, and the same silicon target was used. The silicon oxide layer and the silicon nitride layer are successively formed without exposure to the atmosphere. Therefore, impurities such as hydrogen and moisture are adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396. A silicon nitride layer is then laminated as a protective insulating layer 398, and then the oxide semiconductor layer is Heat treatment (temperature 100°C to 40°C) to diffuse hydrogen or moisture into the oxide insulating layer. 0℃).

[0296] After the protective insulation layer is formed, it is further left in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment may be performed at a constant temperature. Alternatively, the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less, and then decreased from the heating temperature to room temperature. This heat treatment may be repeated several times to lower the temperature to 100° C. Before the formation, the heating treatment may be performed under reduced pressure. By performing the heating treatment under reduced pressure, the heating time can be shortened. This heat treatment makes it possible to obtain a normally-off transistor. This makes it possible to improve the reliability of the semiconductor device.

[0297] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, By removing residual moisture in the reaction atmosphere, the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced. can be reduced.

[0298] The above process is applicable to LCD panels, electroluminescent display panels, and electronic ink displays. It is used in the manufacture of backplanes (substrates on which transistors are formed) for display devices and other devices. The above process is carried out at a temperature of 400℃ or less, so the thickness is 1mm or less, It can also be applied to manufacturing processes using glass substrates with sides exceeding 1 m. All processes can be carried out at temperatures below 0°C, making it ideal for manufacturing display panels. It doesn't consume a lot of energy.

[0299] The above-described transistor may be included in the semiconductor device described in any one of the first to fourth embodiments. By applying the above, it is possible to suppress the discharge of the battery in the standby state. This makes it possible to reduce the standby power consumption of the semiconductor device. By suppressing this, the life of the semiconductor device can be extended.

[0300] Furthermore, all of the transistors included in the semiconductor device shown in any of the first to fourth embodiments may be the same as those described above. By using transistors with the same structure, the manufacturing process can be reduced, and the yield can be improved. Manufacturing costs can be reduced.

[0301] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0302] (Embodiment 8) In this embodiment, one of the transistors included in the semiconductor device described in any of Embodiments 1 to 4 will be described. Specifically, a semiconductor device in which a channel formation region is formed of an oxide semiconductor will be described. An example of a transistor will be described.

[0303] One mode of a transistor and a manufacturing method thereof in this embodiment will be described with reference to FIGS.

[0304] 18A to 18D show examples of cross-sectional structures of transistors. The transistor 360 is a bottom transistor called a channel protection type (also called a channel stop type). It is one of the gate structures and is also called an inverted staggered transistor.

[0305] Although the transistor 360 has been described as a transistor having a single gate structure, If necessary, a transistor having a multi-gate structure having a plurality of channel formation regions may be formed. It is possible.

[0306] Hereinafter, a transistor 360 is fabricated on a substrate 320 using FIGS. The process will be explained.

[0307] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 361 is formed by a deposition process. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0308] The material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, tungsten, or the like. Metallic materials such as stainless steel, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a laminated layer using an alloy material.

[0309] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0310] In this embodiment, the gate insulating layer 322 is formed to a thickness of 100 nm by plasma CVD. The following silicon oxynitride layers are formed:

[0311] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. In this embodiment, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor film. The film is formed by sputtering.

[0312] In this case, the oxide semiconductor film can be formed while removing moisture remaining in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0313] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, The concentration of impurities contained in the body membrane can be reduced.

[0314] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities such as these have been removed to the level of a few ppm or a few ppb. preferable.

[0315] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. or more and 750° C. or less, preferably 400° C. or more so as to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor is The conductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 332 is obtained. (See Figure 18(A)).

[0316] Then, a plasma treatment is performed using gas such as N2O, N2, or Ar. The Zuma treatment removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0317] Next, an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332. Then, a resist mask is formed by a third photolithography process, and selective etching is performed. After etching is performed to form the oxide insulating layer 366, the resist mask is removed.

[0318] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 366. The substrate temperature during film formation should be between room temperature and 300° C. In the case of the above, the temperature is set at 100°C. The deposition of silicon oxide film by sputtering method is carried out using rare gas (typically Argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) and oxygen atmosphere. The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in an atmosphere.

[0319] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the treatment chamber. It is preferable that hydrogen, a hydroxyl group, or moisture be contained in the oxide semiconductor layer 332 and the oxide insulating layer 366. This is to ensure that it is not included.

[0320] To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. The exhaust means is preferably a turbo pump with a cold trap. The process chamber evacuated using a cryopump may contain hydrogen atoms, water (H 2O), etc., which contain hydrogen atoms, are exhausted, so the oxide insulating film formed in the processing chamber The concentration of impurities contained in layer 366 can be reduced.

[0321] The oxide insulating layer 366 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or hydrogen. By using high-purity gas in which impurities such as chlorine and chlorides have been removed to the level of a few ppm or a few ppb, is preferred.

[0322] Then, a second heat treatment (preferably The heating may be performed at 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer is heated while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366. can be.

[0323] In this embodiment, an oxide insulating layer 366 is further provided, and a part of the oxide semiconductor is exposed. The oxide insulating layer 332 is subjected to a heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by 366 are filled with nitrogen, an inert Heat treatment in a gas atmosphere or under reduced pressure can reduce the resistance. Heat treatment is carried out at 250° C. for 1 hour in a nitrogen atmosphere.

[0324] The oxide semiconductor layer 332 provided with the oxide insulating layer 366 is subjected to heat treatment in a nitrogen atmosphere. Due to this phenomenon, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 18 In FIG. 1B, the oxide semiconductor layer 362 has a portion (indicated by a hatched area and a white area).

[0325] Next, a semiconductor layer 362, a gate insulating layer 322, and an oxide insulating layer 366 are formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After the conductive film is formed, a resist mask is formed by a fourth photolithography process. After selective etching to form the source electrode layer 365a and the drain electrode layer 365b, Then, the resist mask is removed (see FIG. 18(C)).

[0326] The source electrode layer 365a and the drain electrode layer 365b are made of materials such as Al, Cr, Cu, An element selected from Ta, Ti, Mo, and W, or an alloy containing the above elements; Examples of the metal conductive film include an alloy film made by combining the above elements. Alternatively, it may have a laminated structure of two or more layers.

[0327] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor film is reduced by heat treatment for oxidation, a part of the oxide semiconductor film is selectively treated with excess oxygen. As a result, the channel formation region 363 overlapping with the gate electrode layer 361 has an I-type The high resistance source region 364a overlapping the source electrode layer 365a and the drain electrode layer 3 The high resistance drain region 364b overlapping the gate insulating layer 65b is formed in a self-aligned manner. A transistor 360 is formed.

[0328] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained at 100° C. or 200° C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By performing the heat treatment, the heating time can be shortened. Hydrogen is taken into the oxide insulating layer, and a normally-off transistor can be obtained. This makes it possible to improve the reliability of the semiconductor device.

[0329] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) By forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the As a result, the reliability of the transistor can be improved. By forming the drain region 364b, the high resistance drain region 364b and the It is possible to provide a structure in which the conductivity can be changed stepwise over the channel forming region 363. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated in this manner, a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if the transistor is damaged, the high-resistance drain region acts as a buffer to prevent localized electric field concentration. This improves the breakdown voltage of the stator.

[0330] A protective insulating layer is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See FIG. 18(D)).

[0331] Note that a thin film is further provided on the source electrode layer 365 a, the drain electrode layer 365 b, and the oxide insulating layer 366. An oxide insulating layer may be formed over the insulating film 324 and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0332] The above-described transistor may be included in the semiconductor device described in any one of the first to fourth embodiments. By applying the above, it is possible to suppress the discharge of the battery in the standby state. This makes it possible to reduce the standby power consumption of the semiconductor device. By suppressing this, the life of the semiconductor device can be extended.

[0333] Furthermore, all of the transistors included in the semiconductor device shown in any of the first to fourth embodiments may be the same as those described above. By using transistors with the same structure, the manufacturing process can be reduced, and the yield can be improved. Manufacturing costs can be reduced.

[0334] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts.

[0335] (Embodiment 9) In this embodiment mode, an example of use of the semiconductor device described in any of the first to fourth embodiments will be described with reference to FIG. Please refer to the following for explanation.

[0336] As shown in FIG. 19, the semiconductor device has a wide range of uses. For example, Securities, bearer bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 19 (A)), recording media (DVD software, video tapes, etc., see Figure 19 (B)), packaging containers (wrapping paper, bottles, etc.) (See Fig. 19(C)), vehicles (bicycles, etc., See Fig. 19(D)), personal belongings (bags, etc. glasses, etc.), food, plants, animals, the human body, clothing, daily necessities, or electronic devices (liquid crystal display devices, EL display devices, television receivers, or mobile phones) or It can be used by attaching it to tags attached to goods (see Figure 19 (E) and Figure 19 (F)). Cut.

[0337] The semiconductor device 1500 can be mounted on a printed circuit board, attached to the surface, or embedded. For example, it can be embedded in the paper of a book, or it can be fixed in a package made of organic resin. If it is a package, it is embedded in the organic resin and fixed to each article. In order to achieve a small size, thinness, and light weight, the design of the item itself is compromised even after it is fixed to the item. In addition, there are no banknotes, coins, securities, bearer bonds, certificates, etc. that contain semiconductor devices. By providing the device 1500, an authentication function can be provided. In addition, it is possible to prevent counterfeiting of packaging containers, recording media, personal belongings, and food products. By attaching the semiconductor device of the present invention to items such as clothing, household goods, or electronic devices, This will improve the efficiency of systems such as inspection systems. By installing the conductor device 1500, security against theft etc. can be improved. can be done.

[0338] As described above, the semiconductor device described in the above embodiment can be used for each of the applications listed in the present embodiment. By using this, the data used in the exchange of information can be kept accurate. This makes it possible to enhance the authenticity or security of the item.

[0339] The contents of this embodiment or a part of the contents may be the same as the contents of other embodiments or a part of the contents of other embodiments. It can be freely combined with the other parts. [Explanation of symbols]

[0340] 10 Antennas 11 Batteries 12 Demodulation circuit 13 Signal Processing Section 14 Power Control Circuit 15 Transistor 20 Antenna 21 Batteries 22 Timer 23 Signal Processing Section 24 Power Control Circuit 25 Transistor 30 Antenna 31 Secondary battery 32 Rectifier circuit 33 Charging circuit 34 Stabilized power supply circuit 35 Demodulation circuit 36 Signal Processing Section 37 Power Control Circuit 38 Transistor 40 Antenna 41 Secondary battery 42 Rectifier circuit 43 Charging circuit 44 Stabilized power supply circuit 45 Demodulation circuit 46 Signal Processing Section 47 Power Control Circuit 48 Logic Circuits 49 Clock Generation Circuit 50 Sensors 51 Memory Circuit 52 Modulation circuit 80 P-type transistors 81 N-type transistor 82 N-type transistor 83 P-type transistor 84 P-type transistor 85 N-type transistor 86 N-type transistor 87 N-type transistor 88 P-type transistor 89 P-type transistor 90 N-type transistor 91 N-type transistor 92 N-type transistor 100 Substrates 102 Protective layer 104 Semiconductor area 106 Element isolation insulating layer 108a Gate insulating layer 108b Insulating layer 110a Gate electrode layer 110b Electrode layer 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulating layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a Source electrode layer 130b Drain electrode layer 130c electrode layer 132 Insulating Layer 134 Conductive Layer 136a Electrode layer 136b Electrode layer 136c electrode layer 136d Gate electrode layer 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode layer 142b Drain electrode layer 144 Protective Insulation Layer 146 Interlayer Insulation Layer 148 Conductive Layer 150a electrode layer 150b electrode layer 150c electrode layer 150d electrode layer 150e electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154c electrode layer 154d electrode layer 160 P-type transistor 164 N-type transistor 320 Substrate 322 Gate Insulation Layer 323 Protective Insulation Layer 332 Oxide semiconductor layer 360 Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel Formation Region 364a Source Region 364b Drain region 365a Source electrode layer 365b Drain electrode layer 366 Oxide Insulating Layer 390 Transistors 391 Gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Film 394 Substrate 395a Source electrode layer 395b Drain electrode layer 396 Oxide Insulating Layer 397 Gate Insulation Layer 398 Protective Insulation Layer 399 Oxide Semiconductor Layer 423 Aperture 450 Substrate 452 Gate insulation layer 457 Insulating Layer 460 Transistors 461 Gate electrode layer 461a Gate electrode layer 461b Gate electrode layer 462 Oxide Semiconductor Layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 1500 Semiconductor equipment

Claims

[Claim 1] The antenna, Batteries and a demodulation circuit that demodulates a signal input from the antenna; a signal processing unit that operates using the signal input from the demodulation circuit and a power supply voltage supplied from the battery; a power control circuit controlled by a signal input from the demodulation circuit; The signal processing unit includes: a transistor whose switching is controlled by a signal input from the power control circuit; a functional circuit electrically connected to the anode or cathode of the battery via the transistor; The channel formation region of the transistor has a hydrogen concentration of 5×10 １９ (atoms / cm ３ 2. A semiconductor device including the following oxide semiconductor:

Images