Semiconductor device

Abstract

To provide a semiconductor device capable of reducing inductance.SOLUTION: A semiconductor device 20 configures a vertical arm circuit. A semiconductor element 40 includes a drain electrode 40D and a source electrode 40S provided on a surface opposite the drain electrode 40D. The source electrode 40S is connected to a substrate 60. The substrate 60 includes an insulating base material 61, a front-surface metal body 62 to which the source electrode 40S is electrically connected, and a back-surface metal body 63. The front-surface metal body 63 includes an N-wire 64 which is a first wire, and a relay wire 65 which is at a different electric potential from that of the first wire and is a second wire disposed at a predetermined distance from the first wire. The distance between the N-wire 64 and the relay wire 65 is not greater than a thickness of the front-surface metal body 62.SELECTED DRAWING: Figure 79

Description

[Technical field]

[0001] The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device that configures upper and lower arm circuits. The semiconductor device includes a semiconductor element having main electrodes on both sides and a substrate having metal bodies disposed on both sides of an insulating base material. The contents of the prior art document are incorporated by reference as explanations of technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-150021 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned semiconductor device, a surge voltage occurs when the semiconductor element is switched on and off. In order to reduce the surge voltage, it is necessary to reduce the inductance of the main circuit wiring. In the above-mentioned respects and other respects not mentioned, further improvements are required in the semiconductor device.

[0005] One disclosed object is to provide a semiconductor device capable of reducing inductance. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises: A semiconductor device constituting an upper and lower arm circuit (9), A semiconductor element (40) having main electrodes (40D, 40S) on both sides; A substrate (50, 60) is provided having an insulating base material (51, 61), a front surface metal body (52, 62) arranged on the front surface of the insulating base material and electrically connected to a main electrode, and a back surface metal body (53, 63) arranged on the back surface of the insulating base material, the surface metal body has a first wiring (64) extending in a predetermined direction, and a second wiring (65) having a different potential from the first wiring and extending in the predetermined direction with a predetermined gap between it and the first wiring; The first wiring and the second wiring have currents flowing in opposite directions along a predetermined direction, The distance between the first wiring and the second wiring is equal to or smaller than the thickness of the surface metal body.

[0007] In the disclosed semiconductor device, since the interval is equal to or less than the thickness, the cancellation effect between the magnetic flux caused by the current flowing through the first wiring and the magnetic flux caused by the current flowing through the second wiring is enhanced, and the inductance can be reduced. Also, since the surface metal body is thick, the cross-sectional area of ​​the current path is large, and the inductance can be reduced. As a result, a semiconductor device capable of reducing inductance can be provided.

[0008] The various aspects disclosed in this specification adopt different technical means to achieve their respective objectives. The claims and the parenthetical symbols described in this section are merely illustrative of the corresponding relationship with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; [Diagram 2] FIG. 1 is a perspective view showing a semiconductor device. [Diagram 3] FIG. 1 is a perspective view showing a semiconductor device. [Figure 4] FIG. 1 is a plan view showing a semiconductor device. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is an enlarged view of region IX shown in FIG. [Figure 10] FIG. 2 is an exploded perspective view for explaining a semiconductor device. [Figure 11] 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. [Figure 12] FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. [Figure 13] FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. [Figure 14] FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the drain electrode side. [Figure 15] FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and a terminal on the source electrode side. [Figure 16] FIG. 13 is a plan view showing a current loop of a reference example. [Figure 17] FIG. 2 is a plan view showing a current loop. [Figure 18] FIG. 2 is a side view showing a current loop. [Figure 19] FIG. 13 is a diagram showing current density in a reference example. [Figure 20] FIG. 4 is a diagram showing current density for this embodiment. [Figure 21] FIG. [Figure 22] FIG. [Diagram 23] FIG. 13 is a plan view showing a circuit pattern on a substrate on the drain electrode side in a modified example. [Figure 24] FIG. 13 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. [Diagram 25]FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 26] FIG. 13 is a diagram for explaining the effect of inductance Ls. [Figure 27] FIG. 13 is a diagram for explaining the effect of inductance Ls. [Figure 28] FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. [Figure 29] FIG. [Diagram 30] FIG. 4 is a cross-sectional view showing an arm connection portion. [Diagram 31] FIG. 13 is a plan view showing a modified example of the substrate on the source electrode side. [Diagram 32] 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. [Diagram 33] FIG. [Diagram 34] FIG. 13 is a plan view showing a modified example of the substrate on the drain electrode side. [Diagram 35] FIG. [Diagram 36] 13 is a cross-sectional view showing a modified example of the arm connection portion. FIG. [Figure 37] 13 is a cross-sectional view showing a modified example of the arm connection portion. FIG. [Figure 38] FIG. 13 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. [Figure 39] FIG. 1 is a cross-sectional view showing warpage at high temperatures. [Diagram 40] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Diagram 41] FIG. 2 is a cross-sectional view showing a semiconductor device at room temperature. [Diagram 42] FIG. 1 is a cross-sectional view showing a semiconductor device at a high temperature. [Diagram 43] FIG. 11 is a diagram showing the relationship between the ratio of thicknesses T1 and T2 and the amount of warping. [Diagram 44] FIG. 11 is a cross-sectional view showing a modified example. [Diagram 45] FIG. 11 is a cross-sectional view showing a modified example. [Figure 46]13 is an enlarged plan view of the periphery of a signal terminal in the semiconductor device according to the fourth embodiment. FIG [Figure 47] FIG. 47 is a cross-sectional view taken along line XLVII-XLVII in FIG. 46. [Figure 48] FIG. 1 is a diagram illustrating wire bonding. [Figure 49] FIG. 11 is a cross-sectional view showing a modified example. [Figure 50] FIG. 11 is a cross-sectional view showing a modified example. [Figure 51] FIG. 11 is a cross-sectional view showing a modified example. [Figure 52] FIG. 11 is a cross-sectional view showing a modified example. [Figure 53] FIG. [Figure 54] FIG. [Figure 55] FIG. 54 is a cross-sectional view taken along the line LV-LV in FIG. 53. [Figure 56] FIG. 11 is a cross-sectional view showing a modified example. [Figure 57] FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 58] FIG. 58 is a plan view seen from the LVIII direction shown in FIG. 57. [Figure 59] FIG. 58 is an enlarged view of an area LIX shown in FIG. 57. [Figure 60] This is a diagram in which the bonding material is omitted, as compared to FIG. 59. [Figure 61] FIG. [Figure 62] 62 is a plan view seen from the direction LXII shown in FIG. 61. [Figure 63] FIG. [Figure 64] FIG. 11 is a cross-sectional view showing a modified example. [Figure 65] FIG. 65 is an enlarged view of area LXV shown in FIG. 64. [Figure 66] FIG. 11 is a cross-sectional view showing a modified example. [Figure 67] FIG. 67 is an enlarged view of area LXVII shown in FIG. 66. [Figure 68] FIG. 11 is a cross-sectional view showing a modified example. [Figure 69] FIG. 13 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 70] FIG. 4 is a diagram showing the relationship between the glass transition point and the linear expansion coefficient for the sealing body and the insulating base material. [Figure 71] FIG. 13 is a diagram showing warpage in a reference example. [Figure 72] FIG. 13 is a diagram showing warpage at high temperatures. [Figure 73] FIG. 13 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. [Figure 74] FIG. 74 is an enlarged view of region LXXIV of FIG. 73. [Figure 75] 1A to 1C are diagrams illustrating a method for forming a roughened portion. [Figure 76] FIG. 11 is a cross-sectional view showing a modified example. [Figure 77] FIG. 11 is a cross-sectional view showing a modified example. [Figure 78] FIG. 11 is a cross-sectional view showing a modified example. [Figure 79] FIG. 13 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. [Figure 80] FIG. 79 is an enlarged view of area LXXX in FIG. [Figure 81] FIG. 13 is a diagram showing the relationship between the interval, thickness and inductance. [Figure 82] FIG. 13 is a diagram showing a simulation result in the case where the distance is smaller than the thickness. [Figure 83] FIG. 13 is a diagram showing a simulation result in the case where the interval is greater than the thickness. [Figure 84] FIG. 13 is a cross-sectional view showing a semiconductor device according to a ninth embodiment. [Figure 85] FIG. [Figure 86] FIG. 85 is an enlarged view of area LXXXVI of FIG. 84. [Figure 87] FIG. 1 shows dimensions and angles. [Figure 88] FIG. [Figure 89] FIG. 23 is a cross-sectional view showing a semiconductor device according to a tenth embodiment. [Figure 90] FIG. 2 is a plan view showing a semiconductor element. [Figure 91] FIG. 89 is an enlarged view of region XCI in FIG. [Figure 92] FIG. 4 is a cross-sectional view showing the arrangement of sintered members. [Figure 93] 4A to 4C are cross-sectional views showing a joining method. [Figure 94] 13 is a diagram showing the relationship between the distance between the inner circumferential surface of the protective film and the sintered member and the strain amplitude of the base electrode. FIG. [Figure 95] FIG. 4 is a cross-sectional view showing the arrangement of solder as a bonding material. [Figure 96] FIG. 21 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment. [Figure 97] This is an enlarged view of area XCVII in Figure 96. [Figure 98] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. [Figure 99] FIG. 98 is an enlarged view of area XCIX in FIG. 97. [Figure 100] FIG. 11 is a cross-sectional view showing a modified example. [Figure 101] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. [Figure 102] FIG. 11 is a cross-sectional view showing a modified example. [Figure 103] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and a rough oxide film. [Figure 104] FIG. 11 is a cross-sectional view showing a modified example. [Figure 105] FIG. 23 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment. [Fig. 106] FIG. 106 is an enlarged view of area CVI in FIG. [Figure 107] FIG. 4 is a diagram showing the relationship between the Young's modulus and the yield stress of the base electrode, the sintered layer, and the brittle layer. [Figure 108] FIG. 11 is a cross-sectional view showing a modified example. [Fig. 109] FIG. 11 is a cross-sectional view showing a modified example. [Figure 110] FIG. 11 is a cross-sectional view showing a modified example. [Figure 111]FIG. 23 is a diagram showing a circuit configuration of a power conversion device to which the semiconductor device according to the thirteenth embodiment is applied. [Figure 112] FIG. 1 is a perspective view showing a semiconductor device. [Figure 113] FIG. 1 is a plan view showing a semiconductor device. [Fig. 114] 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. FIG. [Figure 115] FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. [Fig. 116] FIG. 2 is a plan view showing a circuit pattern of the substrate on the source electrode side. [Figure 117] FIG. 114 is a cross-sectional view taken along line CXVII-CXVII in FIG. [Fig. 118] FIG. 113 is a cross-sectional view taken along line CXVIII-CXVIII in FIG. [Figure 119] FIG. 114 is a cross-sectional view taken along the line CXIX-CXIX in FIG. [Figure 120] 114 is a cross-sectional view taken along line CXX-CXX in FIG. 113. [Figure 121] FIG. 121 is an enlarged view of area CXXI ​​in FIG. 120. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, several embodiments will be described with reference to the drawings. In addition, by assigning the same reference numerals to corresponding components in each embodiment, duplicated explanations may be omitted. When only a part of the configuration is described in each embodiment, the configuration of the other embodiment described above can be applied to the other parts of the configuration. In addition to the combination of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

[0011] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a moving body using a rotating electric machine as a drive source. The moving body is, for example, an electric vehicle such as an electric vehicle (EV), a hybrid vehicle (HV), a plug-in hybrid vehicle (PHV), an aircraft such as a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0012] (First embodiment) First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

[0013] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0014] The DC power supply 2 is a DC voltage source composed of a chargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0015] <Power conversion device> Next, a circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is the power conversion circuit.

[0016] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power supply line on the high potential side and an N line 8 which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0017] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 upon receiving rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0018] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. A connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a part of each of the P line 7, the N line 8, and the output line 10 is configured with a conductive member such as a bus bar.

[0019] In this embodiment, an n-channel MOSFET 11 is used as a switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited. There may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0020] As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two MOSFETs 11 connected in parallel are connected to the P line 7. In the lower arm 9L, the sources of the two MOSFETs 11 connected in parallel are connected to the N line 8. The sources of the two MOSFETs 11 connected in parallel in the upper arm 9H and the drains of the two MOSFETs 11 connected in parallel in the lower arm 9L are connected to each other. The two MOSFETs 11 connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0021] A freewheeling diode 12 is connected in anti-parallel to each of the MOSFETs 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20. Details of the semiconductor device 20 will be described later.

[0022] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. With this configuration, voltage can be increased and decreased. The power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0023] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0024] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0025] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured to include, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0026] <Semiconductor device> Next, the semiconductor device will be described with reference to Figs. 2 to 13. Fig. 2 is a perspective view of the semiconductor device 20. Fig. 3 is a perspective view of the semiconductor device 20 similar to Fig. 2. Fig. 3 is a see-through view showing the internal structure. Fig. 4 is a plan view of the semiconductor device 20. Fig. 4 is a see-through view showing the internal structure. Fig. 5 is a cross-sectional view taken along line VV in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 4. Fig. 9 is an enlarged view of region IX indicated by a dashed line in Fig. 8.

[0027] Fig. 10 is an exploded perspective view for explaining the semiconductor device 20. For convenience, a lead frame 94 is shown in Fig. 10. Fig. 11 is a plan view showing a state in which a semiconductor element 40 is mounted on a substrate 50. Fig. 12 is a plan view showing a circuit pattern of a front surface metal body 52 on the substrate 50. Fig. 13 is a plan view showing a circuit pattern of a front surface metal body 62 on a substrate 60.

[0028] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. The Y direction is perpendicular to the Z direction and is the direction in which the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L are arranged. The X direction is perpendicular to both the Z direction and the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words the shape along the XY plane defined by the X direction and the Y direction, is defined as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the arrangement is not limited to the mounting surface, and may be referred to as an arrangement when there is an overlapping positional relationship in a planar view.

[0029] 2 to 13, the semiconductor device 20 constitutes one of the above-mentioned upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuits 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90.

[0030] The encapsulant 30 encapsulates a portion of the other elements constituting the semiconductor device 20. The remaining portions of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of the resin is an epoxy resin. The encapsulant 30 is made of a resin and molded by, for example, a transfer molding method. Such an encapsulant 30 may be called an encapsulating resin body, a molded resin, or a resin molded body. The encapsulant 30 may be formed by using, for example, a gel. The gel is filled (placed) in, for example, the opposing regions of the pair of substrates 50, 60.

[0031] As shown in Figs. 2 to 4, the sealing body 30 has a generally rectangular shape in plan view. The sealing body 30 has one surface 30a as a surface forming an outer shell, and a back surface 30b that is the surface opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing body 30 also has side surfaces that connect the one surface 30a and the back surface 30b. The side surfaces include two side surfaces 30c and 30d from which the external connection terminals 90 protrude. The side surface 30d is the surface opposite to the side surface 30c in the X direction.

[0032] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide band gap semiconductor with a wider band gap than silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

[0033] The semiconductor element 40 of this embodiment is formed by forming the above-mentioned n-channel MOSFET 11 on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure so that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, as main electrodes, a drain electrode 40D is provided on one side, and a source electrode 40S is provided on a back side, which is the side opposite to the one side in the Z direction.

[0034] When the diode 12 is a parasitic diode, the source electrode 40S also serves as an anode electrode, and the drain electrode 40D also serves as a cathode electrode. The diode 12 may be configured on a chip separate from the MOSFET 11. The drain electrode 40D is a main electrode (first main electrode) on the high potential side, and the source electrode 40S is a main electrode (second main electrode) on the low potential side. Hereinafter, the drain electrode 40D and the source electrode 40S may be referred to as main electrodes 40D and 40S.

[0035] The semiconductor element 40 has a generally rectangular shape in plan view. As shown in FIG. 11, the semiconductor element 40 has a pad 40P formed on the back surface at a position different from the source electrode 40S. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed on almost the entire surface. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

[0036] The pad 40P is an electrode for signals. The pad 40P is electrically isolated from the source electrode 40S. The pad 40P is formed at an end on the opposite side to the formation region of the source electrode 40S in the Y direction. The pad 40P includes a pad for a gate electrode.

[0037] The semiconductor device 20 includes a plurality of semiconductor elements 40 having the above-described configuration. The configuration of each semiconductor element 40 is common to each other. The plurality of semiconductor elements 40 includes a semiconductor element 40H constituting an upper arm 9H and a semiconductor element 40L constituting a lower arm 9L. The semiconductor element 40H may be referred to as an upper arm element, and the semiconductor element 40L may be referred to as a lower arm element. Each of the semiconductor elements 40H and 40L is an arm element constituting one arm. The semiconductor device 20 of this embodiment includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction. The semiconductor elements 40H and 40L are aligned in the Y direction. The Y direction is a first direction perpendicular to the Z direction, which is the thickness direction of the semiconductor element 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and semiconductor elements 40L arranged along the Y direction.

[0038] The semiconductor elements 40 are disposed at approximately the same positions as one another in the Z direction. A drain electrode 40D of each semiconductor element 40 faces the substrate 50. A source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0039] The substrates 50 and 60 are disposed in the Z direction so as to sandwich the multiple semiconductor elements 40. The substrates 50 and 60 are disposed so as to at least partially face each other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 (40H, 40L) in a plan view.

[0040] The substrate 50 is disposed on the drain electrode 40D side with respect to the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side with respect to the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D as described later, and provides a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S, and provides a wiring function. For this reason, the substrates 50 and 60 are sometimes referred to as wiring substrates. The substrate 50 is sometimes referred to as a drain substrate, and the substrate 60 is sometimes referred to as a source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members. Of the pair of substrates 50 and 60 sandwiching the semiconductor element 40 in the Z direction, the substrate 50 is a first substrate, and the substrate 60 is a second substrate.

[0041] The substrate 50 has an opposing surface 50a facing the semiconductor element 40 and a back surface 50b opposite to the opposing surface 50a. The substrate 50 includes an insulating base material 51, a front metal body 52, and a back metal body 53. The substrate 50 is a substrate in which the insulating base material 51 and the metal bodies 52 and 53 are laminated. The substrate 60 has an opposing surface 60a facing the semiconductor element 40 and a back surface 60b opposite to the opposing surface 60a. The substrate 60 includes an insulating base material 61, a front metal body 62, and a back metal body 63. The substrate 60 is a substrate in which the insulating base material 61 and the metal bodies 62 and 63 are laminated. In the substrate 50, which is a first substrate, the insulating base material 51 is a first insulating base material, the front metal body 52 is a first front metal body, and the back metal body 53 is a first back metal body. In the substrate 60, which is the second substrate, the insulating base material 61 is a second insulating base material, the front surface metal body 62 is a second front surface metal body, and the back surface metal body 63 is a second back surface metal body. Hereinafter, the front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

[0042] The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes called insulating layers. The material of the insulating substrates 51 and 61 is resin or ceramic, which is an inorganic material. For example, epoxy resin or polyimide resin can be used as the resin. For example, Al2O3 (alumina) or Si3N4 (silicon nitride) can be used as the ceramic. When the insulating substrates 51 and 61 are resin, the substrates 50 and 60 are sometimes called metal-resin substrates. When the insulating substrates 51 and 61 are ceramic, the substrates 50 and 60 are sometimes called metal-ceramic substrates.

[0043] In the case of the insulating base material 51, 61 using a resin material, an inorganic filler (inorganic filling material) may be contained in the resin in order to improve heat dissipation and insulation properties. The linear expansion coefficient may be adjusted by adding a filler. Examples of the filler that can be used include Al2O3, SiO2 (silicon dioxide), AlN (aluminum nitride), and BN (boron nitride). The insulating base material 51, 61 may contain only one type of filler or multiple types of fillers.

[0044] Considering heat dissipation and insulation, in the case of a resin-based material, the thickness of each of the insulating base materials 51 and 61, that is, the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of a ceramic-based material, the thickness of the insulating base materials 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the front surface of the insulating base materials 51 and 61 is the inner surface, that is, the surface on the semiconductor element 40 side, and the back surface opposite the front surface in the Z direction is the outer surface. The insulating base materials 51 and 61 may have the same (identical) material composition, or may have different materials. In this embodiment, the resin-based insulating base materials 51 and 61 are adopted, and the material composition is the same. The linear expansion coefficient of the insulating base materials 51 and 61 is adjusted to be approximately the same as that of the sealing body 30 by adding a filler to the resin. By adding a filler to the resin, the linear expansion coefficient of the insulating base materials 51 and 61 and the sealing body 30 is close to that of the metal (Cu) constituting the metal bodies 52, 53, 62, and 63.

[0045] The metal bodies 52, 53, 62, 63 are provided as, for example, a metal plate or a metal foil. The metal bodies 52, 53, 62, 63 are formed of a metal having good electrical conductivity and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies 52, 53, 62, 63 is, for example, about 0.1 mm to 3 mm. The front surface metal body 52 is disposed on the front surface of the insulating base material 51 in the Z direction. The back surface metal body 53 is disposed on the back surface of the insulating base material 51. Similarly, the front surface metal body 62 is disposed on the front surface of the insulating base material 61 in the Z direction. The back surface metal body 63 is disposed on the back surface of the insulating base material 61. The insulating base materials 51 and 61 are opposed to the semiconductor element 40 in the Z direction. As shown in Figs. 5 to 9 and the like, in this embodiment, the front surface metal body 52 is thicker than the back surface metal body 53. The front surface metal body 62 is thicker than the back surface metal body 63. The front surface metal body 52 on the drain electrode 40D side is thicker than the front surface metal body 62 on the source electrode 40S side. Alternatively, the back surface metal bodies 53, 63 may be made thicker than the corresponding front surface metal bodies 52, 62. The front surface metal body 52 and the back surface metal body 53 may be made approximately equal in thickness, or the front surface metal body 62 and the back surface metal body 63 may be made approximately equal in thickness.

[0046] The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 provide wiring, that is, circuits. For this reason, the surface metal bodies 52, 62 may be referred to as a circuit pattern, a wiring layer, or a circuit conductor. The surface metal bodies 52, 62 may have a plating film of Ni-based or Au on the metal surface. Hereinafter, the pattern of the surface metal bodies 52, 62 may be referred to as a circuit pattern. The surface metal body 52 and the non-arrangement area of ​​the surface metal body 52 on the surface of the insulating base material 51 form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the non-arrangement area of ​​the surface metal body 62 on the surface of the insulating base material 61 form the opposing surface 60a of the substrate 60.

[0047] For example, the front surface metal bodies 52, 62 may be prepared by patterning into a predetermined shape by pressing or etching, and then attached to a two-layer laminate of the insulating base material 51, 61 and the back surface metal body 53, 63 to form the substrates 50, 60. After forming a three-layer laminate of the front surface metal bodies 52, 62, the insulating base material 51, 61, and the back surface metal bodies 53, 63, the front surface metal bodies 52, 62 may be patterned by cutting or etching.

[0048] 11 and other drawings, the surface metal body 52 has a P wiring 54 and a relay wiring 55. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined distance (gap). The sealing body 30 is filled in this gap.

[0049] The P wiring 54 is connected to a P terminal 91P and the drain electrode 40D of the semiconductor element 40H, which will be described later. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 may be referred to as a positive wiring or a high potential power supply wiring. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection part 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection part 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L to the output terminal 92. In the front surface metal body 52 (first front surface metal body), the P wiring 54 is a first power supply wiring, and the relay wiring 55 is a first relay wiring.

[0050] The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the output terminal 92 side. In other words, the P wiring 54 is arranged in a position close to the side surface 30c of the sealing body 30, and the relay wiring 55 is arranged in a position close to the side surface 30d.

[0051] The P wiring 54 has a notch 540. The notch 540 opens on one of the four sides of a substantially rectangular shape in plan, with the X direction as the longitudinal direction. The notch 540 is provided on the side facing the side surface 30c, at substantially the center in the X direction. The P wiring 54 has a base 541 and a pair of extensions 542. The base 541 and the pair of extensions 542 define the notch 540. The P wiring 54 has a substantially U-shape (concave shape) in plan.

[0052] The base portion 541 is a portion closer to the relay wiring 55 side than the cutout 540 and the extension portion 542, and has a generally rectangular shape in plan view. The base portion 541 overlaps the semiconductor element 40H in plan view. That is, the semiconductor element 40H is disposed on the base portion 541. The drain electrode 40D of the semiconductor element 40H is connected to the base portion 541.

[0053] The two extension parts 542 extend from the base 541 in the same direction, specifically, in the Y direction toward the side surface 30c of the sealing body 30. One of the extension parts 542 is connected to the vicinity of one end of the base 541 in the X direction, and the other is connected to the vicinity of the other end of the base 541. Both ends of the U-shape of the P wiring 54, that is, the ends of the two extension parts 542 opposite the base 541, are at approximately the same positions in the Y direction. The pair of extension parts 542 sandwich the notch 540 in the X direction. The length of the base 541 in the Y direction is longer than the depth of the notch 540 and the extension parts 542.

[0054] The relay wiring 55 also has a notch 550. The notch 550 opens on one of the four sides of the approximately rectangular shape in plan view. The notch 550 is provided in approximately the center in the X direction on the side opposite the side surface 30d. That is, the front surface metal body 52 has a notch 540 provided on one of the ends in the Y direction, and a notch 550 provided on the other end.

[0055] The relay wiring 55 has a base 551 and a pair of extensions 552. The base 551 and the pair of extensions 552 define a notch 550. The relay wiring 55 has a generally U-shape (concave shape) in plan view. The base 551 is a portion closer to the P wiring 54 than the notch 550 and the extensions 552, and has a generally rectangular shape in plan view. The base 551 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is disposed on the base 551. The drain electrode 40D of the semiconductor element 40L is connected to the base 551.

[0056] The two extension parts 552 extend from the base 551 in the same direction, specifically, in the Y direction toward the side surface 30d of the sealing body 30. One of the extension parts 552 is connected to the vicinity of one end of the base 551 in the X direction, and the other is connected to the vicinity of the other end of the base 551. Both ends of the U-shape of the relay wiring 55, that is, the ends of the two extension parts 552 opposite the base 551, are at approximately the same positions in the Y direction. The pair of extension parts 552 sandwich the notch 550 in the X direction. The length of the base 551 in the Y direction is longer than the depth of the notch 550 and the extension parts 552.

[0057] On the other hand, the front surface metal body 62 has an N wiring 64 and a relay wiring 65, as shown in Figures 10 and 13. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined interval (gap). The sealing body 30 is filled in this gap.

[0058] The N wiring 64 is connected to an N terminal 91N, which will be described later, and the source electrode 40S of the semiconductor element 40L. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The N wiring 64 is sometimes referred to as an N wiring. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connection portion 80. The relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connection portion 80. In the front surface metal body 62 (second front surface metal body), the N wiring 64 is a second power supply wiring, and the relay wiring 65 is a second relay wiring.

[0059] The N wiring 64 has a base 640 and a pair of extension parts 641. The N wiring 64 has a substantially U-shape in plan view. The base 640 is arranged side by side with the relay wiring 65 in the Y direction. The base 640 is arranged on the side of the side surface 30d in the Y direction. The base 640 has a substantially rectangular shape in plan view with the X direction as the longitudinal direction. As shown in FIG. 15, the base 640 overlaps with the semiconductor element 40L in a plan view. That is, the semiconductor element 40L is arranged on the base 640. The source electrode 40S of the semiconductor element 40L is connected to the base 640.

[0060] The two extension portions 641 extend from the base 640 in the same direction, specifically, in the Y direction toward the side surface 30c of the sealing body 30. One of the extension portions 641 is connected to the vicinity of one end of the base 640 in the X direction, and the other is connected to the vicinity of the other end of the base 640. Both ends of the U-shape of the N wiring 64, that is, the ends of the two extension portions 641 opposite the base 640, are at approximately the same position in the Y direction.

[0061] The pair of extension parts 641 form both ends of the front surface metal body 62 in the X direction. The pair of extension parts 641 are arranged near the end of the substrate 60. In a plan view, a portion of each of the pair of extension parts 641 overlaps the P wiring 54. The length of the extension part 641 in the Y direction is longer than that of the base part 640. The N wiring 64 also has a notch 642. The notch 642 opens on one of the four sides of a substantially rectangular shape in plan view with the Y direction as the longitudinal direction. The notch 642 is provided on the side facing the side surface 30c, approximately in the center in the X direction. The base part 640 and the pair of extension parts 641 define the notch 642.

[0062] As described above, the relay wiring 65 is arranged in line with the N wiring 64, specifically the base 640, in the Y direction. In the Y direction, the relay wiring 65 is arranged in a position close to the side surface 30c of the sealing body 30, and the base 640 is arranged in a position close to the side surface 30d. The relay wiring 65 is arranged between a pair of extension parts 641 in the X direction. The relay wiring 65 is sandwiched between the pair of extension parts 641. The relay wiring 65 is arranged in the cutout 642. The relay wiring 65 is arranged with a predetermined interval (gap) between it and the N wiring 64. In a plan view, a part of the relay wiring 65 overlaps with the P wiring 54, and another part overlaps with the relay wiring 55.

[0063] 15, the relay wiring 65 overlaps the semiconductor element 40H in a plan view. That is, the semiconductor element 40H is disposed on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65. A more detailed example of the circuit pattern of the front surface metal body 62 will be described later.

[0064] The back metal body 53, 63 is electrically isolated from the circuit including the semiconductor element 40 by the insulating substrate 51, 61. The back metal body 53, 63 is sometimes called a metal base substrate. Heat generated by the semiconductor element 40 is transferred to the back metal body 53, 63 through the front metal body 52, 62 and the insulating substrate 51, 61. The back metal body 53, 63 provides a heat dissipation function. The back metal body 53, 63 of this embodiment has a substantially rectangular shape in plan view, and its outer contour almost coincides with the outer contour of the front metal body 52, 62. The back metal body 53, 63 is a so-called solid conductor arranged over almost the entire area of ​​the back surface of the insulating substrate 51, 61. As described above, the linear expansion coefficient of the insulating substrate 51, 61 is adjusted by adding a filler, so that warping can be suppressed even if the patterns are changed on the front and back. Of course, the rear surface metal bodies 53, 63 may be patterned so as to coincide with the front surface metal bodies 52, 62 in a plan view.

[0065] The back surface metal body 53, 63 in this embodiment is disposed over almost the entire area of ​​the back surface of the corresponding insulating base material 51, 61. To further enhance the heat dissipation effect, at least one of the back surface metal bodies 53, 63 may be exposed from the sealing body 30. In this embodiment, the back surface metal body 53 is exposed from one surface 30a of the sealing body 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back surface metal body 63 is approximately flush with the back surface 30b. The back surface metal bodies 53, 63 form the back surfaces 50b, 60b of the substrates 50, 60.

[0066] The conductive spacer 70 provides a spacer function that ensures a predetermined distance between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located in the middle of the electrical conduction and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides a wiring function and a heat dissipation function. The conductive spacer 70 contains a metal material with good electrical conductivity and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a columnar body with a substantially rectangular shape in plan view that has approximately the same size as the source electrode 40S.

[0067] The conductive spacers 70 may be referred to as terminals, terminal blocks, or metal blocks. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the semiconductor device 20 includes four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40.

[0068] The arm connection part 80 electrically connects the relay wirings 55, 65. That is, the arm connection part 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection part 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. The arm connection part 80 is provided in an overlapping region of the relay wirings 55 and 65 in a plan view. The arm connection part 80 of this embodiment is configured to include a joint part 81 and a bonding material 103 described later.

[0069] The joint part 81 is a metal columnar body provided separately from the surface metal bodies 52, 62. Such a joint part 81 is sometimes called a joint terminal. In the Z direction, a bonding material 103 is interposed between one of the ends of the joint part 81 and the relay wiring 55, and a bonding material 103 is interposed between the other end and the relay wiring 65.

[0070] Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. That is, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not include the joint portion 81. That is, the arm connection portion 80 may include only the bonding material 103.

[0071] The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity such as copper. The external connection terminal 90 is, for example, a plate material. The external connection terminal 90 may be called a lead. The external connection terminal 90 includes a power terminal 91, an output terminal 92, and a signal terminal 93. The power terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals electrically connected to the main electrodes of the semiconductor element 40. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

[0072] The power supply terminal 91 is an external connection terminal 90 electrically connected to the above-mentioned power supply lines 7 and 8. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P may be referred to as a positive terminal or a high potential power supply terminal. The P terminal 91P is connected to the P wiring 54 of the front surface metal body 52. ​​In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

[0073] The P terminal 91P is connected to the P wiring 54 near one end in the Y direction. The P terminal 91P extends in the Y direction from a connection portion (joint portion) with the P wiring 54, and protrudes from the side surface 30c near the center in the Z direction to the outside of the sealing body 30. The semiconductor device 20 of this embodiment includes two P terminals 91P. As shown in FIG. 11, one of the P terminals 91P is connected to one of the pair of extension portions 542, and the other is connected to the other of the pair of extension portions 542. The P terminal 91P is disposed in a position close to the notch 540, that is, inward, in each of the extension portions 542 so as to be adjacent to the N terminal 91N in a plan view. The two P terminals 91P are disposed side by side in the X direction. The two P terminals 91P are disposed at approximately the same position in the Z direction.

[0074] The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N may be referred to as a negative terminal or a low potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the front surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

[0075] The N terminal 91N is connected to the N wiring 64 near one end in the Y direction. The N terminal 91N extends in the Y direction from a joint with the N wiring 64, and protrudes from near the center in the Z direction on the side surface 30c to the outside of the sealing body 30. The semiconductor device 20 includes two N terminals 91N. As shown in FIG. 15 and other figures, one of the N terminals 91N is connected to one of a pair of extension portions 641, and the other is connected to the other one of the pair of extension portions 641. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged at approximately the same position in the Z direction.

[0076] The two N terminals 91N are disposed outside the two P terminals 91P in the X direction. In a plan view, one of the N terminals 91N is disposed near one of the P terminals 91P, and the other N terminal 91N is disposed near the other P terminal 91P. The N terminal 91N and P terminal 91P adjacent to each other in the X direction have their side surfaces facing each other in parts including parts protruding from the sealing body 30.

[0077] The output terminal 92 is electrically connected to the winding 3a (stator coil) of the corresponding phase of the motor generator 3. The output terminal 92 may be referred to as an O terminal, an AC terminal, or the like. As shown in Fig. 3 and Fig. 7, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 of the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

[0078] The output terminal 92 is connected to the relay wiring 55 near one end in the Y direction. The output terminal 92 extends in the Y direction from a joint with the relay wiring 55, and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One of the output terminals 92 is connected to one of the pair of extension portions 552, and the other is connected to the other one of the pair of extension portions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are arranged at approximately the same position in the Z direction.

[0079] The signal terminal 93 is electrically connected to a drive circuit (driver) not shown. The signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connection member such as a bonding wire 110. The number of the signal terminals 93H is not particularly limited. The signal terminal 93H may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment includes two signal terminals 93H. One of the signal terminals 93H is a terminal for a gate electrode. The signal terminal 93H for the gate electrode is electrically connected to the pads 40P for the gate electrodes of the two semiconductor elements 40H. The signal terminal 93H is disposed at a position overlapping the notch 540 of the P wiring 54 in a plan view. In the signal terminal 93H, the joint with the bonding wire 110 faces the insulating base material 51, not the surface metal body 52. ​​The two signal terminals 93H are disposed side by side in the X direction.

[0080] The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110 and protrudes from near the center of the side surface 30c in the Z direction to the outside of the sealing body 30. At least a part of the protruding portion of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is disposed between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are disposed in the following order in the X direction: the N terminal 91N, the P terminal 91P, the two signal terminals 93H, the P terminal 91P, and the N terminal 91N.

[0081] The signal terminal 93L is electrically connected to the pad 40P of the semiconductor element 40L via a connection member such as a bonding wire 110. The number of the signal terminals 93L is not particularly limited. The signal terminal 93L may include at least a terminal for applying a driving voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment includes four signal terminals 93L. One of the signal terminals 93L is a terminal for a gate electrode. The signal terminal 93L for the gate electrode is electrically connected to the pads 40P for the gate electrodes of the two semiconductor elements 40L. The signal terminal 93L is arranged at a position overlapping the notch 550 of the relay wiring 55 in a plan view. In the signal terminal 93L, the joint with the bonding wire 110 faces the insulating base material 51, not the surface metal body 52. ​​The four signal terminals 93L are arranged side by side in the X direction.

[0082] The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110, and protrudes from near the center of the side surface 30d in the Z direction to the outside of the sealing body 30. At least a part of the protruding portion of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is disposed between the two output terminals 92 in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30d are disposed in the following order in the X direction: the output terminal 92, the four signal terminals 93L, and the output terminal 92.

[0083] The drain electrode 40D of the semiconductor element 40 is joined to the front surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is joined to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is joined to the front surface metal body 62 via a bonding material 102. The joint portion 81 is joined to the metal bodies 52, 62 via a bonding material 103. Of the external connection terminals 90, the P terminal 91P, the N terminal 91N, and the output terminal 92, which are main terminals, are joined to the corresponding front surface metal bodies 52, 62 via a bonding material 104.

[0084] The bonding materials 100 to 104 are conductive bonding materials. For example, solder can be used as the bonding materials 100 to 104. An example of the solder is a multi-element lead-free solder containing Cu, Ni, and the like in addition to Sn. A sintered bonding material such as sintered silver may be used instead of the solder. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the corresponding surface metal bodies 52 and 62 without the bonding material 104. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the surface metal bodies 52 and 62 by, for example, ultrasonic bonding, friction stir bonding, laser welding, or the like. When the joint portion 81 is provided separately from the substrates 50 and 60, the joint portion 81 may be directly bonded to the surface metal bodies 52 and 62.

[0085] As described above, in the semiconductor device 20, the multiple semiconductor elements 40 constituting the upper and lower arm circuits 9 for one phase are encapsulated by the encapsulant 30. The encapsulant 30 integrally encapsulates the multiple semiconductor elements 40, a portion of the substrate 50, a portion of the substrate 60, the multiple conductive spacers 70, the arm connection portion 80, and a portion of the external connection terminals 90. The encapsulant 30 encapsulates the insulating base materials 51, 61 and the surface metal bodies 52, 62 of the substrates 50, 60.

[0086] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60 disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0087] <Manufacturing method> Next, an example of a method for manufacturing the semiconductor device 20 will be described with reference to Fig. 10. In Fig. 10, the substrate 50 and the substrate 60 are shown facing each other to make the subsequent assembly easier to understand.

[0088] First, the semiconductor element 40, the substrates 50 and 60, the conductive spacer 70, the joint portion 81, and the lead frame 94 are prepared. As shown in Fig. 10, the lead frame 94 includes external connection terminals 90. The lead frame 94 is formed by subjecting a metal plate to processing such as pressing. The external connection terminals 90 are supported by an outer peripheral frame 94b via tie bars 94a.

[0089] Next, the semiconductor element 40, the joint portion 81, and the external connection terminal 90 are joined (connected) to the substrate 50. In addition, the conductive spacer 70 is joined to the semiconductor element 40.

[0090] At this time, the lead frame 94 and the semiconductor element 40 are placed on the substrate 50. In addition, a conductive spacer 70 is placed on the source electrode 40S of the semiconductor element 40. The lead frame 94 is placed so that each of the external connection terminals 90 partially overlaps the substrate 50 in a plan view. Specifically, the P terminal 91P and the N terminal 91N are placed so as to overlap the P wiring 54 of the front surface metal body 52, and the output terminal 92 is placed so as to overlap the relay wiring 55. In addition, the signal terminal 93H is placed so as to overlap the insulating base material 51 exposed from the cutout 540, and the signal terminal 93L is placed so as to overlap the insulating base material 51 exposed from the cutout 550.

[0091] Then, the drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 by a bonding material 100. The source electrode 40S is bonded to the conductive spacer 70 by a bonding material 101. The joint portion 81 is bonded to the surface metal body 52 by a bonding material 103. The P terminal 91P and the output terminal 92 are bonded to the surface metal body 52 by a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow. Figure 10 shows this bonded state.

[0092] Next, the pads 40P of the semiconductor element 40H and the signal terminals 93H are electrically connected by bonding wires 110. Similarly, the pads 40P of the semiconductor element 40L and the signal terminals 93L are electrically connected by bonding wires 110.

[0093] Next, the substrate 60 is bonded (connected). The source electrode 40S of the semiconductor element 40 and the front surface metal body 62 are bonded via a bonding material 102. The joint portion 81 and the front surface metal body 62 are bonded via a bonding material 103. The N terminal 91N and the front surface metal body 62 are bonded via a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow.

[0094] Next, the sealing body 30 is molded by a transfer molding method. Although not shown in the drawings, in this embodiment, the sealing body 30 is molded so as to completely cover the substrates 50 and 60, and is cut after molding. The sealing body 30 is cut together with a part of the rear metal bodies 53 and 63 of the substrates 50 and 60. This exposes the rear surfaces 50b and 60b. The rear surface 50b is approximately flush with one surface 30a of the sealing body 30, and the rear surface 60b is approximately flush with the rear surface 30b. The sealing body 30 may be molded in a state in which the rear surfaces 50b and 60b are pressed against the cavity wall surface of a molding die and in close contact with each other. In this case, the rear surfaces 50b and 60b are exposed from the sealing body 30 at the time when the sealing body 30 is molded. Therefore, cutting after molding is not required.

[0095] Next, unnecessary portions such as the tie bars 94a and the peripheral frame 94b are removed from the lead frame 94. In this manner, the semiconductor device 20 can be obtained.

[0096] <Location> Next, the positional relationship between the semiconductor element 40, the circuit patterns of the front surface metal bodies 52 and 62, the arm connection portion 80, and the external connection terminal 90 connected to the circuit pattern will be described with reference to Figs. 14 and 15. Fig. 14 is a diagram showing the arrangement of the circuit pattern of the front surface metal body 52, the semiconductor element 40, and the terminals. Fig. 15 is a diagram showing the arrangement of the circuit pattern of the front surface metal body 62, the semiconductor element 40, and the terminals. For convenience, Figs. 14 and 15 show only the external connection terminal 90 connected to the circuit pattern. In Fig. 14, D is indicated in the arrangement area of ​​the semiconductor element 40 so that the main electrode (drain electrode 40D) connected to the front surface metal body 52 can be easily seen. Similarly, in Fig. 15, S is indicated in the arrangement area of ​​the semiconductor element 40 so that the main electrode (source electrode 40S) connected to the front surface metal body 62 can be easily seen.

[0097] 14 is an imaginary line that passes through the midpoints of two semiconductor elements 40 that form one arm. The imaginary line CL1 passes through the midpoint (center) of the two semiconductor elements 40 in the arrangement direction, and extends in the Y direction. The imaginary line CL1 is, for example, a line that passes through the midpoint of two semiconductor elements 40H. It may be a line that passes through the midpoint of semiconductor element 40L instead of semiconductor element 40H.

[0098] 14, the arrangement of the two semiconductor elements 40H is approximately line-symmetric with respect to the imaginary line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also approximately line-symmetric with respect to the imaginary line CL1. Here, approximately line-symmetric allows for an error of the order of manufacturing variation. The circuit pattern of the front metal body 52 is also approximately line-symmetric with respect to the imaginary line CL1. That is, each of the P wiring 54 and the relay wiring 55 is approximately line-symmetric with respect to the imaginary line CL1.

[0099] The arrangement of the arm connection portion 80 connected to the relay wiring 55 is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the external connection terminals 90 connected to the front surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. In other words, the arrangement of the two P terminals 91P is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the two output terminals 92 is also approximately line-symmetrical with respect to the imaginary line CL1.

[0100] As in FIG. 14, a virtual line CL1 is shown in FIG. 15. The arrangement of the semiconductor elements 40H, 40L is the same as in FIG. 14. As shown in FIG. 15, the circuit pattern of the front surface metal body 62 is also approximately line-symmetrical with respect to the virtual line CL1. That is, each of the N wiring 64 and the relay wiring 65 is approximately line-symmetrical with respect to the virtual line CL1. As in FIG. 14, the arrangement of the arm connection portion 80 connected to the relay wiring 65 is also approximately line-symmetrical with respect to the virtual line CL1. The arrangement of the two N terminals 91N, which are external connection terminals 90 connected to the front surface metal body 62, is also approximately line-symmetrical with respect to the virtual line CL1.

[0101] <Circuit pattern> Next, the circuit pattern of the surface metal body 62 will be described in more detail with reference to Fig. 15. The dashed dotted lines shown in Fig. 15 indicate the boundaries of the respective regions.

[0102] As described above, the front surface metal body 62 of the substrate 60 has the N wiring 64 and the relay wiring 65. The N wiring 64 has a base 640 and a pair of extension parts 641. The pair of extension parts 641 extend from the base 640 in the Y direction toward the side surface 30c of the sealing body 30. The N wiring 64 defines the outer contour of the front surface metal body 62. The relay wiring 65 is sandwiched between the pair of extension parts 641. The relay wiring 65 is disposed in the cutout 642 of the N wiring 64.

[0103] As shown in FIG. 15, the relay wiring 65 has an end 650 as one end in the Y direction. The end 650 is an end on the base 640 side in the Y direction. On the other hand, the base 640 of the N wiring 64 has an opposing side 640a to the end 650. The opposing side 640a is a portion between a pair of extension parts 641 in the base 640. The base 640 also has an arrangement region 640b for the semiconductor element 40L. The arrangement region 640b is defined by the outer contour of the semiconductor element 40L as shown by a two-dot chain line in FIG. 15. The arrangement region 640b includes an area overlapping the semiconductor element 40L in a plan view, and also includes an area between the elements when multiple semiconductor elements 40L are included. The area between the elements is an opposing area between the semiconductor elements 40L in the arrangement direction of the semiconductor elements 40L.

[0104] Here, the lengths L1, L2, and L3 in the X direction are defined as follows. The length L1 is the length of the end portion 650 of the relay wiring 65 as shown in FIG. 15. The length L2 is the length of the opposing side 640a of the base portion 640. The length L3 is the length of the arrangement region 640b in the base portion 640. In the present embodiment, the relationship L1 < L2 < L3 is satisfied.

[0105] The relay wiring 65 of the present embodiment has a width-reducing portion 651a. The width-reducing portion 651a includes the end portion 650. The width-reducing portion 651a is a portion within a predetermined range in the Y direction from the end portion 650. The length in the X direction of the width-reducing portion 651a, that is, the width, is the smallest at the end portion 650. In the width-reducing portion 651a, the width W1 at an arbitrary first position is less than or equal to the width W2 at a second position farther from the end portion 650 than the first position.

[0106] The width of the width-reducing portion 651a may be reduced stepwise, for example, for each predetermined length in the Y direction. That is, the end in the X direction of the width-reducing portion 651a may change stepwise. In the present embodiment, the length in the X direction of the width-reducing portion 651a becomes shorter as it approaches the base portion 640. That is, the width of the width-reducing portion 651a continuously decreases toward the base portion 640. The arm connection portion 80 is arranged in the width-reducing portion 651a.

[0107] The relay wiring 65 may have only the width-reducing portion 651a including the end portion 650. In this case, the semiconductor element 40H is also arranged in the width-reducing portion 651a. The relay wiring 65 of the present embodiment has a constant-width portion 651b. The constant-width portion 651b is continuous with the width-reducing portion 651a and is a portion having a constant width over a predetermined range in the Y direction. And the semiconductor element 40H is arranged in the constant-width portion 651b.

[0108] The relay wiring 65 of this embodiment further has a reduced width portion 651c. The reduced width portion 651c includes an end portion 652 opposite to the end portion 650. The reduced width portion 651c is opposite to the reduced width portion 651a and is connected to the constant width portion 651b. The width of the reduced width portion 651c is smallest at the end portion 652. In the reduced width portion 651c, the width at an arbitrary first position is equal to or smaller than the width at a second position that is farther from the end portion 652 than the first position. In this embodiment, the width of the reduced width portion 651c is continuously reduced toward the end portion 652. In the relay wiring 65, the reduced width portions 651a and 651c become narrower as they move away from the constant width portion 651b.

[0109] In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is approximately constant throughout the opposing region. The extension portions 641 of the N wiring 64 are patterned so that the distance between the N wiring 64 and the relay wiring 65 is approximately constant. Each of the extension portions 641 has a widened portion 641a, a fixed width portion 641b, and a widened width portion 641c.

[0110] The widened portion 641a is connected to the base 640 and is a portion that is a predetermined range in the Y direction from the boundary with the base 640. The length in the X direction of the widened portion 641a, that is, the width, is maximum at the boundary with the base 640. In the widened portion 641a, the width at an arbitrary first position is equal to or greater than the width at a second position that is farther from the base 640 than the first position. The width of the widened portion 641a in this embodiment is continuously increased toward the base 640. The constant width portion 641b is connected to the widened portion 641a and is a portion whose width is constant over a predetermined range in the Y direction. The constant width portion 641b faces the constant width portion 651b of the relay wiring 65.

[0111] The widened portion 641c is opposite to the widened portion 641a and continues to the constant width portion 641b. The widened portion 641a extends to a position closer to the side surface 30c than the narrowed portion 651c. The widened portion 641c includes the tip portion 641d of the extension portion 641. The width of the widened portion 641c is maximum at the tip portion 641d. In the widened portion 641c, the width at an arbitrary first position is equal to or greater than the width at a second position farther from the tip portion 641d than the first position. In this embodiment, the width of the widened portion 641c is continuously widened toward the tip portion 641d in the portion facing the narrowed portion 651c. In the widened portion 641c, the portion closer to the tip portion 641d than the facing portion has a constant width. In the N wiring 64, a part of the widened portion 641c and the widened portion 641a are wider as they move away from the constant width portion 641b.

[0112] <Current path> Next, the current path will be described with reference to Figs. 16 to 20. Fig. 16 is a diagram showing a PN current loop of a reference example. In the reference example, the reference symbol of each element is the reference symbol of the related element of the semiconductor device 20 with r added to the end. The configuration of the reference example is almost the same as that of the semiconductor device 20, except that the number of signal terminals 93Lr and the patterns of the N wiring 64r and relay wiring 65r are different. Fig. 17 is a diagram showing a PN current loop in the semiconductor device 20 of this embodiment. Fig. 18 is a diagram showing a PN current loop in a side view of the semiconductor device 20 seen from the X direction. The PN current loop refers to the loop shape of the current path from the P terminal 91P to the N terminal 91N.

[0113] When examining inductance, a PN current loop of P terminal 91P → P wiring 54 → semiconductor element 40H → relay wiring 65 → arm connection portion 80 → relay wiring 55 → semiconductor element 40L → N wiring 64 → N terminal 91N is taken into consideration. For this reason, to make the PN current loop easier to understand, a continuous solid line is shown from the P terminal 91P to the N terminal 91N. In reality, the semiconductor elements 40H and 40L are controlled so that they are not turned on at the same time. For convenience, only the current path for one of the semiconductor elements 40H and one of the semiconductor elements 40L is shown, but the same is true for the other semiconductor element 40H and the other semiconductor element 40L.

[0114] Figures 19 and 20 show the results of electromagnetic field simulation. Figure 19 shows the current density of the reference example shown in Figure 18. Figure 20 shows the current density for the configuration of this embodiment shown in Figure 16. The conditions for the electromagnetic field simulation were the same for both, except that the circuit patterns of the surface metal body 62 were different. In Figures 19 and 20, the lower the current density, the coarser (lighter color) the color, and the higher the current density, the denser (darker color).

[0115] As shown in FIG. 16, in the semiconductor device 20r of the reference example, the relay wiring 65r has a substantially rectangular shape in plan. The length of the end 650r of the relay wiring 65r is substantially equal to the length of the arrangement region 640br of the semiconductor element 40Lr in the base 640r. The length of the opposing side 640ar in the base 640r is longer than the arrangement region 640br. Therefore, as shown by the solid arrow in FIG. 16, a current enters the substantially rectangular semiconductor element 40Lr from one side 400r and exits from another side 401r. The side 400r is the side opposite to the side where the two semiconductor elements 40Lr face each other. In this way, the current flows from the semiconductor element 40Lr to the outside in the X direction, so the PN current loop is large. It is clear from the simulation result shown in FIG. 19 that the current flows from the semiconductor element 40Lr to the outside in the X direction through the base 640r.

[0116] On the other hand, in the semiconductor device 20 of this embodiment, as described above, the N wiring 64 and the relay wiring 65 are patterned and satisfy a predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in FIG. 17, the N wiring 64 (extension portion 641) is also present above one side 400 of the semiconductor element 40L in a plan view. The side 400 is an opposite side to the relay wiring 65. Therefore, a current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. The Y-direction component of the current flowing from the semiconductor element 40L toward the N-terminal 91N increases especially in the vicinity of the semiconductor element 40L. It is also clear from the simulation result shown in FIG. 20 that the current flows from the semiconductor element 40L with a Y-direction component.

[0117] In this way, the current flowing through the N wiring 64 approaches the relay wiring 65, and the current path through the N wiring 64, i.e., the current path between the semiconductor element 40L and the N terminal 91N, becomes shorter. Therefore, the PN current loop is smaller than that of the reference example. As shown in FIG. 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Furthermore, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

[0118] <Summary of the First Embodiment> If the inductance of the main circuit wiring is large, the surge voltage will be large. If the semiconductor element is made thicker to ensure the withstand voltage, steady-state loss will increase. In order to reduce steady-state loss, the element area must be increased. Surge voltage can also be reduced by slowing down the switching speed. In this case, the output to the motor generator will be smaller. Thus, if the inductance is large, the size of the semiconductor element will be larger or the output will be smaller.

[0119] When components through which currents flow in opposite directions are arranged opposite to each other, the inductance can be reduced due to the cancellation effect of the magnetic fluxes generated by the currents. If the PN current loop of the main circuit wiring is smaller, the components through which currents flow in opposite directions are closer to each other, and the cancellation effect of the magnetic fluxes is enhanced, thereby reducing the inductance.

[0120] In this embodiment, the semiconductor elements 40H, 40L are arranged side by side in the Y direction, and the arm connection portion 80 is arranged between the semiconductor elements 40H, 40L. Of the main terminals, the power supply terminals 91 (91P, 91N) are drawn out in the same direction. In addition, in the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the opposite side. In the Y direction, the relay wiring 65 is arranged on the power supply terminal 91 side, and the base 640 of the N wiring 64 is arranged on the opposite side. Then, the extension portion 641 of the N wiring 64 extends to the power supply terminal 91 side so as to sandwich the relay wiring 65.

[0121] With such a configuration, the PN current loop becomes smaller. As a result, the inductance of the main circuit wiring can be reduced. For example, by arranging the P terminal 91P and the N terminal 91N in parallel, the inductance can be reduced. The relay wiring 65 and the N wiring 64 are also arranged (in parallel) with a predetermined interval therebetween. As a result, the inductance can be reduced. Further, the extended portion 641 of the N wiring 64 faces the P wiring 54. As a result, the inductance can be reduced.

[0122] In the present embodiment, the surface metal body 52 of the substrate 50 and the surface metal body 62 of the substrate 60 provide a wiring function for the semiconductor element 40. The surface metal bodies 52 and 62 are sealed by the sealing body 30. Since it is not necessary to secure a creepage distance as in the prior art, the N wiring 64 and the relay wiring 65 can be arranged closer to each other. As a result, the effect of magnetic flux cancellation is enhanced, and the inductance can be further reduced.

[0123] Also, as shown in FIG. 15, the length L1 of the end portion 650 of the relay wiring 65, the length L2 of the opposing side 640a of the base portion 640, and the length L3 of the arrangement region 640b of the semiconductor element 40L in the base portion 640 satisfy the relationship of L1 < L2 < L3. By satisfying this dimensional relationship, as described above, current enters from one side 400 of the semiconductor element 40L and exits from the same side 400. Among the currents flowing from the semiconductor element 40L toward the N terminal 91N, particularly in the vicinity of the semiconductor element 40L, the Y-direction component increases. As a result, the current path through the N wiring 64, that is, the current path between the semiconductor element 40L and the N terminal 91N becomes shorter, and the PN current loop becomes smaller. Therefore, the inductance of the main circuit wiring can be further reduced.

[0124] Also, the higher the frequency of the current, the more the current concentrates on the opposing sides of the extended portion 641 of the N wiring 64 and the relay wiring 65 due to the skin effect. As a result, the PN current loop can be further reduced, and thus the inductance can be further reduced.

[0125] In this embodiment, as shown in Fig. 15, the relay wiring 65 has a reduced width portion 651a. This allows the width of the portion of the extension portion 641 facing the reduced width portion 651a to be increased. This makes it possible to suppress heat generation due to current flow without changing the size of the front surface metal body 62 and thus the substrate 60. In other words, it is possible to suppress heat generation while reducing inductance.

[0126] Particularly in this embodiment, the length of the reduced width portion 651a in the X direction becomes shorter as it approaches the base 640. That is, the width of the reduced width portion 651a continuously decreases toward the base 640. The reduced width portion 651a of the relay wiring 65 has a tapered shape. This makes it easy to keep the distance between the relay wiring 65 and the extension portion 641 constant. That is, the extension portion 641 can be brought closer to the relay wiring 65, thereby making the PN current loop smaller. Furthermore, the width of the extension portion 641 can be increased to suppress heat generation.

[0127] In this embodiment, the relay wiring 65 has a constant width portion 651b. The semiconductor element 40H is disposed in the constant width portion 651b. The relay wiring 65 having the reduced width portion 651a and the constant width portion 651b has a shape identical to or similar to a baseball home base in a plan view. This allows the width of the extension portion 641 to be wider than in a configuration in which the semiconductor element 40H is disposed in the reduced width portion 651a. This makes it possible to suppress heat generation due to current flow without changing the size of the front surface metal body 62 and thus the substrate 60. In other words, it is possible to suppress heat generation while reducing inductance.

[0128] In this embodiment, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, the two semiconductor elements 40L are arranged side by side in the X direction. In this manner, the semiconductor elements 40 constituting one arm are arranged side by side in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the semiconductor elements 40H and 40L. In the X direction, a pair of extension parts 641 sandwich the relay wiring 65. This makes it possible to suppress current bias.

[0129] The semiconductor device 20 may include one N terminal 91N whose tip is branched into two so as to be individually connected to the pair of extension portions 641. In this embodiment, the semiconductor device 20 includes two N terminals 91N, and the N terminals 91N are individually connected to the pair of extension portions 641. This makes it easy to arrange another external connection terminal 90 between the two N terminals 91N. Since it is not necessary to avoid the external connection terminal 90 arranged therebetween, the size of the semiconductor device can be made smaller.

[0130] The semiconductor device 20 may include only one P terminal 91P. In this embodiment, the semiconductor device 20 includes two P terminals 91P. In addition, the N terminal 91N, the P terminal 91P, the signal terminal 93H, the P terminal 91P, and the N terminal 91N are arranged in this order in the X direction. The P terminal 91P and the N terminal 91N are arranged side by side at both ends in the X direction. This makes it easier to make the PN current loop small. In addition, since the external connection terminals 90 are arranged with regularity in the X direction, as described above, it is easier to ensure line symmetry for the circuit patterns of the semiconductor element 40, the front surface metal bodies 52 and 62, and the external connection terminals 90. This makes it possible to suppress current bias.

[0131] In this embodiment, the P terminal 91P and the N terminal 91N protrude from the side surface 30c of the sealing body 30, and the output terminal 92 protrudes from the side surface 30d. In this manner, the P terminal 91P and the N terminal 91N connected to the smoothing capacitor 5 are drawn out in the same direction, and the output terminal 92 is drawn out in the opposite direction. This improves the connectivity with the smoothing capacitor 5 and the connectivity with the motor generator 3. Furthermore, the inductance can be reduced by arranging the P terminal 91P and the N terminal 91N in parallel. This terminal arrangement makes it easier to make the PN current loop smaller.

[0132] <Modification> As an example of including a plurality of each of the semiconductor elements 40H and 40L, an example of including two of each has been shown, but the present invention is not limited thereto. Three or more may be included. For example, a configuration may be adopted in which three semiconductor elements 40H are arranged side by side in the X direction and three semiconductor elements 40L are arranged side by side in the X direction. The circuit pattern of the surface metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above-described examples. For example, the configuration may be as shown in FIGS. 21 and 22. In FIGS. 21 and 22, for convenience, the sealing body 30 on the back surface 30b side with respect to the insulating base material 51 is omitted from the illustration. Further, among the substrates 60, the insulating base material 61 and the back surface metal body 63 are omitted from the illustration. Similar to FIG. 17, the PN current loop is indicated by a solid line arrow. In FIGS. 21 and 22, the semiconductor device 20 includes two signal terminals 93L.

[0133] In FIG. 21, the semiconductor device 20 includes two arm connection portions 80. The relay wiring 65 has a substantially rectangular planar shape. The two arm connection portions 80 are arranged side by side in the X direction in the vicinity of the end portion 650. The interval between the two semiconductor elements 40L is larger than that in the above-described example (see FIG. 17). The length of the arrangement region 640b of the semiconductor element 40L is longer than that in the above-described example. As a result, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 can be shortened and the PN current loop can be made smaller. However, in the configuration shown in FIG. 17, the width of the N wiring 64, particularly the width of the extension portion 641, can be made wider. Further, in the case of the configuration shown in FIG. 17, only one arm connection portion 80 may be provided.

[0134] In FIG. 22, the semiconductor device 20 includes only one semiconductor element 40H and one semiconductor element 40L respectively. In this example, the arrangement region 640b coincides with the outer contour of the semiconductor element 40L. The length of one semiconductor element 40H or 40L in the X direction is longer than that in the above-described example (see FIG. 17). Thus, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 is shortened, and the PN current loop can be reduced.

[0135] The arrangement of the external connection terminals 90 is not limited to the above-described example. For example, the P terminal 91P may be arranged on the outer side in the X direction and the N terminal 91N may be arranged on the inner side. In this case, as shown in FIGS. 23 and 24, the semiconductor element 40 and the circuit pattern are also reversed. FIG. 23 shows the substrate 50. FIG. 24 shows the substrate 60.

[0136] As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. 15. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. 15. The semiconductor element 40H is arranged on the N wiring 64. The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. 15. The semiconductor element 40L and the arm connection portion 80 are arranged on the relay wiring 55.

[0137] As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. 14. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. 14. The semiconductor element 40L is arranged on the N wiring 64. The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. 14. The semiconductor element 40H and the arm connection portion 80 are arranged on the relay wiring 65.

[0138] In the case of the configurations shown in Figures 23 and 24, the above-mentioned relationship between the first and second elements is reversed. The semiconductor element 40L is the first element, and the semiconductor element 40H is the second element. The source electrode 40S is the first main electrode, and the drain electrode 40D is the second main electrode. The substrate 60 is the first substrate, and the substrate 50 is the second substrate. The insulating substrate 61 is the first insulating substrate, the front surface metal body 62 is the first front surface metal body, and the back surface metal body 63 is the first back surface metal body. The insulating substrate 51 is the second insulating substrate, the front surface metal body 52 is the second front surface metal body, and the back surface metal body 53 is the second back surface metal body.

[0139] Second embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress the transient current imbalance during switching, as described in this embodiment, the surface metal body to which the multiple semiconductor elements are connected in parallel may have a predetermined structure.

[0140] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 25 corresponds to Fig. 8.

[0141] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 15). The semiconductor device 20 constitutes upper and lower arm circuits 9 for one phase. As shown in Fig. 25, the semiconductor device 20 includes a plurality of semiconductor elements 40 including two semiconductor elements 40H that are upper arm elements, substrates 50 and 60 arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D that is the first main electrode on the high potential side of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S that is the second main electrode on the low potential side of the semiconductor element 40. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L that are lower arm elements.

[0142] The front surface metal body 62 is substantially symmetrical with respect to the imaginary line CL1, as in the preceding embodiment. As shown in Fig. 25, in this embodiment, the relay wiring 65 of the front surface metal body 62 has a slit 653. As will be described later, the N wiring 64 has a slit 643.

[0143] <Suppression effect of transient current imbalance> Next, the effect of suppressing transient current imbalance during switching will be described with reference to Fig. 26 and Fig. 27. Fig. 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) that constitute one arm. Fig. 27 is an image diagram (potential diagram) that clearly shows potentials.

[0144] 26 and 27, one of the parallel-connected MOSFETs 11 is shown as MOSFET1, and the other is shown as MOSFET2. The inductance of the wiring on the drain electrode side (hereinafter referred to as drain wiring) is shown as Ld, and the inductance of the wiring on the source electrode side (hereinafter referred to as source wiring) is shown as Ls. The gate potential is shown as Vg, the potential of the source electrode of MOSFET1 as Vks1, the potential of the source electrode of MOSFET2 as Vks1, and the common source potential as Vs. The midpoint potential of potentials Vks1 and Vks2 is shown as Vm. The midpoint potential Vm is constant. Vm = (Vks1 + Vks2) / 2.

[0145] Additionally, the gate voltage of MOSFET1 is shown as Vgs1, and the gate voltage of MOSFET2 is shown as Vgs2. The current flowing through MOSFET1 when it is turned on is shown as I1, and the voltage generated across inductance Ls when current I1 flows is shown as ΔVs1. Similarly, the current flowing through MOSFET2 when it is turned on is shown as I2, and the voltage generated across inductance Ls when current I2 flows is shown as ΔVs2. ΔVs1=Ls×dI1 / dt. ΔVs2=Ls×dI2 / dt.

[0146] Due to the characteristic variation of the MOSFET 11, it is assumed that a current I2 (I2>I1) larger than the current I1 flows as shown in FIG. 26. At this time, the voltage ΔVs generated in the inductance Ls is ΔVs1<ΔVs2. That is, as shown in FIG. 27, the potential Vks2 of the source electrode rises with respect to the midpoint potential Vm, and the potential Vks1 falls. Therefore, the gate voltage Vgs1>gate voltage Vgs2. To reduce the gate voltage Vgs2, the current I2 becomes smaller. In this way, the inductance Ls of the source wiring has the function of suppressing the transient current imbalance during switching caused by the characteristic variation of the semiconductor element 40 (MOSFET 11) connected in parallel.

[0147] However, if the inductance Ls of the source wiring is small, the function of suppressing the above-mentioned transient current imbalance is lost, which causes a bias in the switching loss and requires a margin in the thermal design.

[0148] <Circuit pattern on board> Next, the circuit pattern of the front surface metal body 62 in the semiconductor device 20 of this embodiment will be described with reference to Fig. 28. Fig. 28 corresponds to Fig. 15. In Fig. 28, like Fig. 15, the source electrode 40S is indicated as S in order to clarify the main electrode to be connected.

[0149] The N wiring 64 and the relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the preceding embodiment in that it has a slit 643. Similarly, the relay wiring 65 differs from the pattern of the preceding embodiment in that it has a slit 653. Except for the slits 643 and 653, the configuration is the same as that described in the preceding embodiment.

[0150] The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is provided at a position overlapping the opposing regions of the two semiconductor elements 40L in the base 640. The opposing regions are regions where the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L. That is, the slit 643 is provided between the semiconductor elements 40L that are the lower arm elements in a plan view in the Z direction. The slit 643 is provided at the base 640 between the electrical connection parts with the semiconductor element 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the arrangement direction of the semiconductor elements 40H and 40L. The slit 643 opens at the opposing side 640a of the base 640. The slit 643 is provided at approximately the center position of the N wiring 64 in the X direction.

[0151] In this way, the slit 643 extends in the Y direction from the source electrode 40S of the semiconductor element 40L to the side where the N terminal 91N, which is the main terminal, is arranged, that is, the side where the current flows. The slit 643 does not open to the end 640c of the base 640. The slit 643 is provided up to the vicinity of the lower end of the facing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into a region to which one of the semiconductor elements 40L is connected and a region to which the other one is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, that is, the source current path.

[0152] The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is provided in the relay wiring 65 at a position overlapping the opposing regions of the two semiconductor elements 40H. That is, the slit 653 is provided between the semiconductor elements 40H in a plan view. The slit 653 is provided in the relay wiring 65 between the electrical connection parts with the semiconductor element 40H. The slit 653 extends in the Y direction from between the semiconductor elements 40H. The slit 653 opens at the end 652. The slit 653 crosses between the end 652 and the semiconductor elements 40H (the opposing regions) and extends to the vicinity of the arm connection part 80. The slit 653 is provided at a substantially central position of the relay wiring 65 in the X direction.

[0153] In this way, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connection part 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where the current flows. The slit 653 does not open to the end part 650. The slit 643 is provided up to just before the arm connection part 80. The slit 653 divides the relay wiring 65 into an area to which one of the semiconductor elements 40H is connected and an area to which the other one is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, i.e., the source current path.

[0154] <Summary of the second embodiment> 29 shows the source current path. The solid arrow indicates the source current path on the semiconductor element 40H side, and the dashed arrow indicates the source current path on the semiconductor element 40L side. As described above, in this embodiment, the slits 643, 653 are provided in the front surface metal body 62 to which the source electrode 40S, which is the main electrode on the low potential side, is connected.

[0155] The slit 643 is provided between adjacent semiconductor elements 40L in the N wiring 64 to which the semiconductor elements 40L are connected in parallel. The slit 643 divides the N wiring 64 and separates the source current paths of the semiconductor elements 40L. This makes it possible to suppress the current (source current) coming out of the source electrode 40S of the semiconductor element 40L from joining in the vicinity of the source electrode 40S. That is, the joining point of the source current is moved away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40L (MOSFET 11), the inductance Ls of the source wiring can be made larger than a configuration without the slit 643. Since the inductance Ls is large, even if there is a variation (deviation) in the characteristics of the two semiconductor elements 40L, it is possible to suppress the transient current imbalance during switching. By providing the slit 643, it is possible to suppress the transient current imbalance while maintaining the high integration of the semiconductor elements 40L.

[0156] Similarly, the relay wiring 65 has a slit 653. The slit 653 is provided between the two semiconductor elements 40H. The slit 653 divides the relay wiring 65 and separates the source current paths of the semiconductor elements 40H. This makes it possible to suppress the current (source current) coming out of the source electrode 40S of the semiconductor element 40H from joining in the vicinity of the source electrode 40S. That is, the joining point of the source current is farther away from the source electrode 40S in a plan view. Therefore, in a parallel circuit of the two semiconductor elements 40H, the inductance Ls of the source wiring can be made larger than that of a configuration without the slit 653. Since the inductance Ls is large, even if there is a variation (deviation) in the characteristics of the two semiconductor elements 40H, it is possible to suppress the transient current imbalance during switching. By providing the slit 653, it is possible to suppress the transient current imbalance while maintaining the high integration of the semiconductor elements 40H.

[0157] In this embodiment, the slit 643 extends from between adjacent semiconductor elements 40L in the Y direction toward the N terminal 91N side. The slit 643 extends from the source electrode 40S of the semiconductor element 40L toward the side where the current flows. This allows the source current paths of the semiconductor elements 40L to be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor elements 40L, the inductance Ls of the source wiring can be made larger. In other words, the effect of suppressing the transient current imbalance can be improved.

[0158] Similarly, the slit 653 extends from between adjacent semiconductor elements 40H in the Y direction toward the arm connection portion 80. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where the current flows. This allows the source current paths of the semiconductor elements 40L to be separated by a longer distance. Therefore, in the parallel circuit of the semiconductor elements 40H, the inductance Ls of the source wiring can be made larger. In other words, the effect of suppressing the transient current imbalance can be improved.

[0159] Fig. 30 is a cross-sectional view taken along line XXX-XXX in Fig. 29. In this embodiment, the joint part 81, the bonding material 103 connecting the joint part 81 and the relay wiring 55, and the bonding material 103 connecting the joint part 81 and the relay wiring 65 constitute an arm connection part 80 that electrically connects the relay wirings 55, 65. The joint part 81 is a separate member from the substrates 50, 60. The arm connection part 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

[0160] <Modification> In the above example, the multiple semiconductor elements 40 include two each of the semiconductor elements 40H and 40L, but the present invention is not limited to this. The multiple semiconductor elements 40 may include two of the semiconductor elements 40H and 40L and one of the other. In this case, a slit may be provided in one of the two wirings (64, 65) of the front metal body 62 that connects the multiple semiconductor elements 40 in parallel to form one arm. For example, in the case of a configuration that includes two semiconductor elements 40H and one semiconductor element 40L, the slit 643 is not provided in the N wiring 64, but the slit 653 is provided in the relay wiring 65 to which the semiconductor element 40H is connected. In this way, the multiple semiconductor elements 40 may include two arm elements of at least one of the semiconductor elements 40H and 40L.

[0161] The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form one arm. For example, in the case of a configuration including three semiconductor elements 40H, slits 653 may be provided between the three semiconductor elements 40H arranged side by side in the X direction, adjacent semiconductor elements 40H in a plan view. The multiple semiconductor elements 40 may include multiple arm elements of at least one of the semiconductor elements 40H and 40L. The multiple arm elements may include multiple semiconductor elements 40H and multiple semiconductor elements 40L.

[0162] The arrangement of the N terminal 91N is not limited to the above example. For example, the P terminal 91P may protrude from the side surface 30c of the sealing body 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 has a shape similar to that of the P wiring 54 or the relay wiring 55. That is, the extension portion 641 extends from the base portion 640 to the side surface 30d of the sealing body 30. Even in this configuration, the slit 643 only needs to be provided at least between the semiconductor elements 40L. Moreover, by configuring the slit 643 to extend from the facing region of the semiconductor element 40L to the outside of the facing region toward the N terminal 91N side, the inductance Ls can be further increased.

[0163] Although the number of slits 643, 653 provided between the semiconductor elements 40 is one, the present invention is not limited to this. At least one of the slits 643, 653 may be provided in plurality.

[0164] Although an example in which the slits 643 and 653 open at one of the ends of the front surface metal body 62 has been shown, the present invention is not limited thereto. For example, in the example shown in FIG. 31 and FIG. 32, the slit 643 extends in the Y direction from the opposing side 640a of the base 640 to the end 640c. The slit 643 divides the base 640 and, in turn, the N wiring 64 into two. The slit 643 crosses the opposing region of the semiconductor element 40L. One of the semiconductor elements 40L is disposed in one of the divided N wirings 64, and the other one of the semiconductor elements 40L is disposed in the other one of the N wirings 64. Similarly, the slit 653 extends in the Y direction from the end 652 of the relay wiring 65 to the end 650. The slit 653 divides the relay wiring 65 into two. One of the semiconductor elements 40H is disposed in one of the divided relay wirings 65, and the other one of the semiconductor elements 40H is disposed in the other one of the relay wirings 65.

[0165] The slits 643 and 653 are connected to each other to form one slit extending in the Y direction. The front surface metal body 62 is substantially linearly symmetrical with respect to the imaginary line CL1. FIG. 33 shows the source current path. The solid line arrow indicates the source current path of the semiconductor element 40H, and the dashed line arrow indicates the source current path of the semiconductor element 40L. As described above, the slit 643 divides the N wiring 64 into two. This prevents one source current of the semiconductor element 40L and the other source current from joining together on the substrate 60. Since the joining point of the source currents is farther away, the inductance Ls of the source wiring can be further increased.

[0166] Similarly, slit 653 divides relay wiring 65 into two. This prevents the source current of semiconductor element 40H and another source current from joining together on substrate 60. Since the joining point of the source currents is farther away, the inductance Ls of the source wiring can be further increased. As a result, the effect of suppressing transient current imbalance can be improved. Figures 31, 32, and 33 are diagrams showing modified examples. Figure 31 corresponds to Figure 28. Figure 32 corresponds to Figure 11. Figure 33 corresponds to Figure 29.

[0167] 31 to 33, the arm connection parts 80 are divided into the same number as the relay wirings 65 in accordance with the division of the relay wirings 65. The arm connection parts 80 are individually connected to the relay wirings 65. This prevents the source currents from joining together at the arm connection parts 80 as well, making it possible to further increase the inductance Ls.

[0168] In the configuration of the above-described modified example, a slit may be further provided in the front surface metal body 52 of the substrate 50. As shown in Figs. 34 and 35, the relay wiring 55 of the front surface metal body 52 has a slit 553. The slit 553 opens at an end 551a of the relay wiring 55. The end 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, crosses the arm connection portion 80 divided into two, and reaches the opposing region (between) of the semiconductor element 40L. The slit 553 is provided up to the vicinity of the lower end of the opposing region of the semiconductor element 40L.

[0169] When such a configuration is adopted, as shown in FIG. 35, a first current path by one pair of semiconductor elements 40H, 40L and a second current path by another pair of semiconductor elements 40H, 40L are almost completely separated in the semiconductor device 20. The current joining point is provided outside the N terminal 91N. This allows the inductance Ls of the source wiring to be further increased. FIGS. 34 and 35 are diagrams showing modified examples. FIG. 34 corresponds to FIG. 32. FIG. 35 corresponds to FIG. 33. The semiconductor device 20 may include an N bus bar connecting multiple N terminals 91N. In this case, the currents join at the N bus bar. The N bus bar connecting the N terminals 91N may be provided, for example, on the smoothing capacitor 5 side.

[0170] Although an example has been shown in which the arm connection part 80 is configured by the joint part 81 and the bonding material 103 arranged on both ends of the joint part 81, the present invention is not limited to this. In the example shown in Fig. 36, the joint part 81 is provided integrally with the substrate 60. The joint part 81 is provided as a protrusion extending in the Z direction from the relay wiring 65. Like the joint part 81, the conductive spacer 70 is also provided integrally with the surface metal body 62 as a protrusion.

[0171] The surface metal body 62 having the protrusions may be formed, for example, by patterning a multi-gauge metal plate by press processing and attaching it to the insulating base material 61. The surface metal body 62 having the protrusions may be formed by etching thick Cu. It may also be formed by directly bonding a metal body that is a member separate from the substrate 60 to the surface metal body 62. In the configuration shown in FIG. 36, the joint portion 81 which is the protrusion of the relay wiring 65 and the bonding material 103 interposed between the tip of the joint portion 81 and the relay wiring 55 constitute the arm connection portion 80. FIG. 36 is a view corresponding to FIG. 30.

[0172] In the example shown in FIG. 37, the joint portion 81 is eliminated. The bonding material 103 electrically connects the relay wirings 55, 65. The bonding material 103 constitutes the arm connection portion 80. In FIG. 37, the conductive spacer 70 is also eliminated, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via the bonding material 101. Although not shown, the arm connection portion 80 may be configured to include only the joint portion 81 without including the bonding material 103. In this case, the joint portion 81 is directly bonded to the relay wirings 55, 65.

[0173] The circuit patterns of the substrates 50 and 60 are not limited to the above examples. The substrate 60 shown in FIG. 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in FIG. 24. In the example shown in FIG. 38, the slit 643 is provided between adjacent semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N-terminal 91N side, that is, the side where the source current flows. The slit 653 is provided between adjacent semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H in the Y direction toward the arm connection portion 80 side.

[0174] In this embodiment, the arrangement of the external connection terminals 90 is not limited to the example shown in the figure. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. The N terminal 91N may be connected to the N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extension portion 641. The extension portion 641 may be removed from the N wiring 64 and connected to the base portion 640. The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

[0175] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment and its modified examples.

[0176] Third embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used in this embodiment. In order to effectively dissipate heat from the semiconductor element, the thickness above the semiconductor element and the thickness below the semiconductor element may satisfy a predetermined relationship, as described in this embodiment.

[0177] <Warping at high temperatures> Through careful investigation, it has become clear that even if insulating base materials 51, 61 made of resin are used and the linear expansion coefficient is made closer to that of metal bodies 52, 53, 62, 63 by adding filler, warping may occur in semiconductor device 20 as shown in Fig. 39. Fig. 39 shows the state of semiconductor device 20 when semiconductor element 40 is in operation, that is, at high temperature. The dashed line in the figure is a reference line showing the direction of warping.

[0178] The configuration shown in FIG. 39 is the same as the configuration described in the preceding embodiment (see FIG. 5). For convenience, the external connection terminal 90 is omitted in FIG. 39. In FIG. 39, the semiconductor device 20 and the heat exchanger 121 of the cooler 120 are arranged side by side in the Z direction, which is a predetermined direction. The heat exchanger 121 is arranged on both sides of the semiconductor device 20 in the Z direction so as to sandwich the semiconductor device. A heat conductive member 130 such as silicone gel is arranged between each of the heat exchanger 121 and the semiconductor device 20. The cooler 120 cools the semiconductor device 20 by circulating a refrigerant in the flow path of the heat exchanger 121. As the refrigerant flowing in the flow path, a refrigerant that changes phase, such as water or ammonia, or a refrigerant that does not change phase, such as an ethylene glycol-based refrigerant, can be used. The heat conductive member 130 is sometimes called a thermal interface material (TIM). The heat conductive member 130 follows the opposing surfaces of the heat exchanger 121 and the semiconductor device 20 and fills the gap between the opposing surfaces.

[0179] As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low potential side. In addition, the conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas the conductive spacer 70 is not interposed between the drain electrode 40D and the substrate 50. In other words, the thermal resistance of the heat transfer path from the semiconductor element 40 to the substrate 50 is smaller than that of the heat transfer path from the semiconductor element 40 to the substrate 60. In the semiconductor device 20 having such a configuration, it is required to effectively dissipate heat to the substrate 50 side.

[0180] As shown in FIG. 39, when warping occurs with the substrate 50 side concave and the substrate 60 side convex, the distance between the back surface 50b of the substrate 50, which is the exposed surface, and the heat exchanger 121 becomes longer, and the intervening heat conductive member 130 becomes thicker. This increases the thermal resistance between the substrate 50 and the heat exchanger 121, making it difficult to transfer heat (exchange heat) between the semiconductor device 20 and the cooler 120 (heat exchanger 121). The warping state shown in FIG. 39 is not preferable for effectively releasing the heat of the semiconductor element 40, that is, for efficiently cooling the semiconductor device 20. FIG. 39 shows an example of a double-sided cooling structure in which the cooler 120 (heat exchanger 121) is arranged on both sides of the semiconductor device 20. However, a single-sided cooling structure in which the cooler 120 is arranged only on the substrate 50 side in the Z direction also has the same problem.

[0181] <Structure of Semiconductor Device> Through careful investigation, it has become clear that the warpage of the semiconductor device 20 can be controlled by controlling the relative thickness between the portion of the semiconductor device 20 closer to the substrate 50 than the semiconductor element 40 and the portion of the semiconductor device 20 closer to the substrate 60. The semiconductor device 20 of this embodiment has a configuration based on this finding. Fig. 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Fig. 40 shows an ideal state in which the semiconductor device 20 is free of warpage.

[0182] The semiconductor device 20 of this embodiment has the same configuration as that described in the preceding embodiment (see Figs. 2 to 13). In Fig. 40, similar to Fig. 39, the heat exchanger 121 of the cooler 120 and the heat conductive member 130 are shown together with the semiconductor device 20. That is, Fig. 40 shows a semiconductor module 140 including the semiconductor device 20, the cooler 120, and the heat conductive member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

[0183] The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed facing one surface 30a and the rear surface 50b of the sealing body 30, and the other of the heat exchanger sections 121 is disposed facing the rear surfaces 30b and 60b of the sealing body 30. A heat conductive member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchanger section 121.

[0184] The semiconductor device 20 is configured such that a thickness T1 on the substrate 50 side of the semiconductor element 40 and a thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship T1≧T2. The other configurations are the same as those described in the preceding embodiment (see FIG. 5). The thickness T1 is the total thickness of the bonding material 101, the conductive spacer 70, the bonding material 102, and the substrate 60. The thickness T2 is the total thickness of the bonding material 100 and the substrate 50. Since the relationship T1≧T2 is satisfied, the substrate 50 is thicker than the substrate 60. The substrate 50 is thicker than the conductive spacer 70. In the substrate 50, the metal bodies 52 and 53 are thicker than the insulating base material 51. In the substrate 60, the metal bodies 62 and 63 are thicker than the insulating base material 61. The configurations of the parts other than the thickness relationship are the same as those described in the first embodiment.

[0185] <Simulation results> 41 to 43 show the results of thermal stress simulation. FIG. 41 shows the state of the semiconductor device 20 shown in FIG. 40 at room temperature (RT). FIG. 42 shows the state of the semiconductor device 20 shown in FIG. 40 at high temperature. At high temperature, the semiconductor element 40 generates heat due to current flow, that is, when the semiconductor element 40 is in operation. As shown in FIG. 41 and FIG. 42, warping occurs in the semiconductor device 20 at high temperature. In this embodiment, since the relationship T1≧T2 is satisfied as described above, the expansion amount on the substrate 50 side is larger than the expansion amount on the substrate 60 side, as shown by the dashed arrow in FIG. 42. This is because the linear expansion coefficient of Cu constituting the metal bodies 52, 53, 62, and 63 is the largest, and the substrate 50 is thick. As a result, a convex warp occurs on the substrate 50 side, which is the first substrate, and a concave warp occurs on the substrate 60 side, which is the second substrate. The dashed line in FIG. 42 is a reference line indicating the direction of warping.

[0186] FIG. 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warping at high temperatures. In this simulation, the semiconductor element 40, the conductive spacer 70, and the bonding materials 100, 101, and 102 were all the same (common), and the thicknesses of the substrate 50 and the substrate 60 were adjusted so that the thickness ratio T1:T2 was a predetermined value. The material configuration was all the same (common). The vertical axis shown in FIG. 43 indicates the amount of warping, and is an arbitrary unit (au). The amount of warping indicates that the warping is convex toward the substrate 50 side and concave toward the substrate 60 side when it is above 0 (zero), and indicates that the warping is concave toward the substrate 50 side and convex toward the substrate 60 side when it is below 0 (zero). T1:T2 was set to four levels: 1:2, 1:1.3, 1:1, and 1.5:1.

[0187] As shown in FIG. 43, when T1:T2 = 1:2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of warping convex on the substrate 60 side was the largest among the four levels. When T1:T2 = 1:1.3, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of warping convex on the substrate 60 side became smaller than that when T1:T2 = 1:2. When T1:T2 = 1:1, it changed to a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. When T1:T2 = 1.5:1, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred, and the amount of warping convex on the substrate 50 side was the largest among the four levels.

[0188] Thus, it became clear that when T1 < T2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and when T1 ≧ T2, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred. That is, it became clear that by satisfying the relationship of T1 ≧ T2, the warp generated at high temperature can be controlled to a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. Also, it became clear that the larger T2 is with respect to T1, the larger the amount of warping convex on the substrate 60 side becomes, and the larger T1 is with respect to T2, the larger the amount of warping convex on the substrate 50 side becomes.

[0189] <Summary of the Third Embodiment> In this embodiment, the semiconductor device 20 satisfies the relationship of the above-described thickness T1 ≧ thickness T2. The thickness T1 on the side where the conductive spacer 70 is not interposed between the semiconductor element 40 and the substrate 50 is equal to or greater than the thickness T2 on the side where the conductive spacer 70 is interposed between the semiconductor element 40 and the substrate 60. Thereby, when the semiconductor element 40 operates (at high temperature), a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurs in the semiconductor device 20. Therefore, the facing distance between the semiconductor device 20 and the cooler 120 (heat exchange unit 121) on the substrate 50 side, which has a high contribution rate to heat dissipation, can be made narrower compared to a configuration that satisfies the relationship of thickness T1 < thickness T2. Since the facing distance becomes narrower, the thermal resistance between the semiconductor device 20 and the cooler 120 becomes smaller. Thereby, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20. In other words, the cooling efficiency of the semiconductor device 20 can be enhanced.

[0190] Specifically, the thickness of the heat conductive member 130 interposed between the semiconductor device 20 and the cooler 120 is thinner than in a configuration in which the relationship of thickness T1<thickness T2 is satisfied. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120, facilitating heat exchange between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20.

[0191] In this embodiment, the back surface metal body 53 is exposed from the sealant 30. Heat dissipation can be improved compared to a configuration in which the back surface metal body 53 is covered by the sealant 30. Similarly, the back surface metal body 63 is exposed from the sealant 30. Heat dissipation can be improved compared to a configuration in which the back surface metal body 63 is covered by the sealant 30.

[0192] <Modification> Although an example of a double-sided heat dissipation structure is shown, the present invention is not limited to this. It is desired that the semiconductor device 20 efficiently dissipates heat mainly from the substrate 50 side. Therefore, the cooler 120 (heat exchanger 121) may be arranged only on the substrate 50 side in the Z direction with respect to the semiconductor device 20. Even in such a single-sided heat dissipation structure, by satisfying the relationship T1≧T2, a convex warp is formed on the substrate 50 side at high temperatures. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently dissipated.

[0193] Although the example in which both the back surface metal bodies 53 and 63 are exposed from the sealing body 30 has been shown, the present invention is not limited to this. For example, a configuration in which only the back surface metal body 53 is exposed may also be used.

[0194] Although an example has been shown in which the semiconductor device 20 includes a semiconductor element 40H that configures the upper arm 9H and a semiconductor element 40 that configures the lower arm 9L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40. The semiconductor device 20 may include the semiconductor element 40, a pair of substrates 50, 60 arranged to sandwich the semiconductor element 40, and a conductive spacer 70 interposed between the semiconductor element 40 and the substrate 60.

[0195] No particular reference has been made to the relationship in thickness between the metal bodies 52 and 53 in the substrate 50. For example, as shown in FIG. 44, the front surface metal body 52 may be made thicker than the back surface metal body 53. The drain electrode 40D, which is the first main electrode of the semiconductor element 40, is joined to the front surface metal body 52. ​​The thermal resistance between the front surface metal body 52 and the semiconductor element 40 is small. By making the front surface metal body 52 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be effectively diffused. In other words, the heat of the semiconductor element 40 can be efficiently dissipated. FIG. 44 is a cross-sectional view showing a modified example. FIG. 44 corresponds to FIG. 41.

[0196] 44, the front surface metal body 62 may be made thicker than the back surface metal body 63. By making the front surface metal body 62 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be diffused more effectively.

[0197] As described above, the heat of the semiconductor element 40 having main electrodes on both sides is mainly transferred to the substrate 50 side having a smaller thermal resistance. For this reason, as shown in FIG. 45, the front metal body 62 may be made thinner than the back metal body 63. This allows the thickness of the substrate 60 to be reduced, and thus the size of the semiconductor device 20 to be made smaller. Since a thick metal body is not required, the cost can also be reduced. FIG. 45 is a cross-sectional view showing a modified example. FIG. 45 corresponds to FIG. 44. In FIG. 45, the front metal body 52 is thicker than the back metal body 53, and the front metal body 62 is thinner than the back metal body 63. Therefore, the size and cost can be reduced while efficiently dissipating the heat of the semiconductor element 40.

[0198] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, and the modified examples.

[0199] (Fourth embodiment) This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve connection reliability, the substrate and the signal terminals may be arranged to satisfy a predetermined positional relationship as described in this embodiment.

[0200] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 46 and Fig. 47. Fig. 46 shows the periphery of the signal terminal 93 in the semiconductor device 20 of this embodiment. In Fig. 46, some of the elements of the semiconductor device 20 are omitted in order to show the positional relationship between the substrate 50 and the signal terminal 93. Fig. 47 is a cross-sectional view taken along line XLVII-XLVII in Fig. 46. In Fig. 46 and Fig. 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

[0201] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 46, the semiconductor device 20 includes two semiconductor elements 40L. The semiconductor element 40L includes a drain electrode 40D as a first main electrode on one surface, and a source electrode 40S as a second main electrode and a signal pad 40P on a back surface. The semiconductor device 20 includes four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes to the outside from a side surface 30d of the sealing body 30. The four signal terminals 93L are arranged in the X direction between the output terminals 92 in a plan view in the Z direction.

[0202] <Signal terminal shape and arrangement> Next, the shape and arrangement of the signal terminals 93 will be described with reference to FIGS.

[0203] 46, each signal terminal 93L has an overlapping portion 930 that overlaps with the substrate 50 in a plan view, and a non-overlapping portion 931 that does not overlap with the substrate 50. The overlapping portion 930 faces the substrate 50 in the Z direction.

[0204] The overlapping portion 930 is a portion of the signal terminal 93L within a predetermined range from the end portion on the semiconductor element 40L side. The non-overlapping portion 931 is a portion excluding the overlapping portion 930. The overlapping portion 930 overlaps the insulating base material 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire overlapping portion 930 overlaps the insulating base material 51. The overlapping portion 930 overlaps the exposed portion 510 exposed from the front metal body 52 of the insulating base material 51. In this manner, the signal terminal 93L is extended onto the substrate 50. That is, the signal terminal 93L is inserted and disposed to a position where it overlaps the substrate 50 in a plan view.

[0205] Of the four signal terminals, two of the signal terminals 93L have a main portion 930a and a protruding portion 930b at the overlapping portion 930. The other two signal terminals 93L do not have a protruding portion 930b. The main portion 930a extends in the Y direction, which is the main extension direction of the signal terminal 93L. The protruding portion 930b is connected to the main portion 930a and protrudes from the main portion 930a. The protruding portion 930b extends in a direction different from that of the main portion 930a. The protruding portion 930b may be referred to as a branch portion. The planar shape of the main portion 930a may be various shapes such as a substantially L-shaped, a substantially Y-shaped, or a substantially T-shaped. In the example shown in FIG. 46, one of the signal terminals 93L has a substantially L-shaped planar shape, and the other signal terminal 93L has a substantially T-shaped planar shape.

[0206] As described in the preceding embodiment (see FIG. 11), the relay wiring 55 of the front metal body 52 has a notch 550. The overlapping portion 930 of the signal terminal 93L overlaps with a portion of the insulating base material 51 exposed from the notch 550. The four signal terminals 93L are arranged in the X direction between the output terminals 92 in a plan view. Each signal terminal 93L has a tie bar mark 93a. As described in the preceding embodiment (see FIG. 10), the tie bar mark 93a is a mark left on a side surface of the signal terminal 93L when the tie bar 94a of the lead frame 94 is cut off. The tie bar mark 93a is sometimes referred to as a cut mark. Each signal terminal 93L has a tie bar mark 93a on both side surfaces in the X direction. The tie bar mark 93a is provided in the non-overlapping portion 931 at an external position of the sealing body 30.

[0207] As shown in FIG. 47, each signal terminal 93L has a joint portion 93b, a tip portion 93c, a bent portion 93d, and an extended portion 93e. The joint portion 93b is a portion to which a bonding wire 110, which is a connection member, is joined. The joint portion 93b preferably includes a portion that is substantially parallel to the XY plane. The joint portion 93b is a portion of the signal terminal 93L that is closest to the surface of the insulating base material 51 (exposed portion 510). In this embodiment, the joint portion 93b is floating with respect to the surface of the insulating base material 51. The joint portion 93b is not in contact with the insulating base material 51, and the sealing body 30 enters into the gap between the lower surface of the joint portion 93b and the surface of the insulating base material 51 to fill the gap. The bonding wire 110 electrically connects the pad 40P formed on the same surface as the source electrode 40S to the signal terminal 93L.

[0208] The tip portion 93c is located on the tip side of the joint portion 93b, that is, on the semiconductor element 40 (40L) side. The tip portion 93c is located above the joint portion 93b, that is, at a position farther away from the surface of the insulating base material 51 in the Z direction. The tip portion 93c rises upward as it moves away from the joint portion 93b. The tip portion 93c has an R-shape in the ZY cross section. The bent portion 93d is provided between the joint portion 93b and the extension portion 93e, which is a portion on the rear end side of the joint portion 93b. The bent portion 93d is bent so that the extension portion 93e is located above the joint portion 93b, that is, farther away from the surface of the insulating base material 51. The bent portion 93d has a smaller cross-sectional area than other portions of the signal terminal 93, specifically the joint portion 93b, the tip portion 93c, and the extension portion 93e, due to the bending process. In other words, it is thin. The extension portion 93e is located on the rear end side of the joint portion 93b. The extension portion 93e extends in the Y direction and is disposed across the inside and outside of the sealing body 30.

[0209] At least a portion of the joint portion 93b, the tip portion 93c, and the bent portion 93d are included in the overlapping portion 930 described above. At least a portion of the extension portion 93e is included in the non-overlapping portion 931. In this embodiment, the entire extension portion 93e is included in the non-overlapping portion 931. Each signal terminal 93L is formed by press punching. In the signal terminal 93L, the surface facing the insulating base material 51 is a press R surface 93f, and the back surface of the facing surface is a burr surface 93g on which burrs are generated by punching. The configuration other than the above is the same as the configuration described in the first embodiment.

[0210] <Bonding wire connection method> Next, a method of connecting the signal terminal 93 having the above-mentioned structure and the bonding wire 110 will be described with reference to Fig. 48. Fig. 48 is a diagram for explaining wire bonding. Reference numeral 111 shown in Fig. 48 denotes a jig for holding the signal terminal 93L. Reference numeral 112 denotes a tool for ultrasonic bonding. The tool 112 is sometimes called an ultrasonic bonding device. The dashed line shown in Fig. 48 indicates the position of the signal terminal 93L that is bent when pressed by the jig 111.

[0211] 48, first, the signal terminal 93L is positioned so that the overlapping portion 930 overlaps the insulating base material 51, and the wire 110a is set in the portion to be joined. Then, pressure is applied in the Z direction by a jig 111 to elastically deform the signal terminal 93L, and the overlapping portion 930 is brought into contact with the surface of the insulating base material 51. The jig 111 presses the overlapping portion 930 of the signal terminal 93L or the vicinity thereof.

[0212] Then, with the signal terminal 93L in contact with the insulating base material 51, ultrasonic bonding is performed by the tool 112. Because the signal terminal 93L is received by the insulating base material 51, a separate receiving jig is not required. When the ultrasonic bonding is completed and the tool 112 and the jig 111 are released from the signal terminal 93L, the signal terminal 93L is released from its elastically deformed state and returns to its original position before pressure was applied. The signal terminal 93L is part of the lead frame 94. Since the signal terminal 93L is supported by the outer peripheral frame 94b via the tie bars 94a, it returns to its original position when pressure is released.

[0213] In the above, the signal terminal 93L has been described as an example. However, the above configuration may be applied to the signal terminal 93H on the upper arm 9H side. Both the signal terminals 93H and 93L may have the above configuration. In the configuration described in the preceding embodiment (see FIG. 11), each of the signal terminals 93H and 93L overlaps an exposed portion of the insulating base material 51. The P wiring 54 of the front metal body 52 has a notch 540, and the signal terminal 93H overlaps the surface of the insulating base material 51 exposed from the notch 540.

[0214] <Summary of the Fourth Embodiment> In this embodiment, the signal terminal 93 (93L) overlaps the exposed portion 510 of the insulating base material 51. However, the signal terminal 93 is not joined to the exposed portion 510. That is, the signal terminal 93 is not fixed to the insulating base material 51, and thus to the substrate 50. This allows the signal terminal 93 to absorb dimensional variations within the tolerances of the elements constituting the semiconductor device 20, as well as assembly variations when assembling the elements. Therefore, during molding of the sealing body 30, it is possible to suppress stress concentration on the electrical connection portion (joint portion) of the signal terminal 93 with the semiconductor element 40. As a result, it is possible to provide a semiconductor device 20 with high connection reliability.

[0215] In this embodiment, the signal terminal 93 is inserted and arranged up to a position where it overlaps with the substrate 50, that is, onto the substrate 50. By adopting such an arrangement, the signal terminal 93 approaches the pad 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, the length of the bonding wire 110, which is a connecting member, can be shortened compared to a configuration in which the signal terminal 93 is arranged only at a position where it does not overlap with the substrate 50. Since the length of the bonding wire 110 can be shortened, it is possible to suppress the occurrence of wire sweep, short circuit due to wire sweep, wire breakage, and the like when molding the sealing body 30 by a transfer molding method or the like.

[0216] In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating above the surface of the exposed portion 510 of the insulating base material 51. The sealing body 30 is interposed between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The sealing body 30 is also interposed between the joint portion 93b and the exposed portion 510. This makes it possible to absorb the manufacturing variation even if it is large in the plate thickness direction. In addition, since the signal terminal 93 is located above the insulating base material 51, it is easy to ensure an insulation distance from the back surface metal body 53.

[0217] In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at an end in the Y direction, which is a direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 exposed from the notch 550. By providing the notch 550 in the surface metal body 52 of the substrate 50 in this manner, it is possible to ensure the insulation distance between the surface metal body 52 and the signal terminal 93 while suppressing an increase in the size of the substrate 50.

[0218] In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has a tie bar mark 93a. As described above, the signal terminal 93L is a part of the lead frame 94, and is supported by the tie bar 94a on the outer peripheral frame 94b. Therefore, the signal terminal 93 is bent by applying pressure to contact the exposed portion 510 of the insulating base material 51, and in this contact state, the bonding wire 110 can be joined by ultrasonic bonding. Then, by releasing the pressure after the joining is completed, the signal terminal 93 returns to its original position.

[0219] In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extension portion 93e. Due to the bent portion 93d, the extension portion 93e is disposed at a position farther away from the exposed portion 510 (insulating base material 51) in the Z direction than the joint portion 93b. By having the bent portion 93d in this manner, it is possible to ensure an insulation distance between the signal terminal 93 and the back surface metal body 53 while suppressing an increase in the physical size in the Z direction.

[0220] In this embodiment, the signal terminal 93 has a tip portion 93c. The tip portion 93c is farther from the exposed portion 510 (insulating base material 51) in the Z direction than the joint portion 93b. This makes it possible to prevent the tip of the signal terminal 93 from scratching the insulating base material 51 during the above-mentioned joining (ultrasonic joining) and the like. In other words, it is possible to prevent the insulation performance from deteriorating. Particularly in this embodiment, since the tip portion 93c is raised upward as it is farther from the joint portion 93b, the tip portion 93c is less likely to come into contact with the insulating base material 51. In addition, since the tip portion 93c has an R-shape in the ZY cross section, it is possible to prevent the insulating base material 51 from being scratched even if it comes into contact.

[0221] If the opposing surface is a burred surface 93g, the insulating base material 51 may be scratched, and the insulating performance may be deteriorated. In this embodiment, the signal terminal 93 is configured so that the surface facing the exposed portion 510 is a pressed round surface 93f, and the back side of the opposing surface is a burred surface 93g. This makes it possible to prevent the insulating performance of the insulating base material 51 from being deteriorated.

[0222] <Modification> The non-bonding configuration between the signal terminal 93 and the exposed portion 510 is not limited to the above example. For example, in FIG. 49, the overlapping portion 930 of the signal terminal 93 is floating above the insulating base material 51 with a slight gap between the overlapping portion 930 and the surface of the exposed portion 510 so that the sealing body does not enter. The sealing body 30 has a gap 31 between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The signal terminal 93 is not fixed to the insulating base material 51 (exposed portion 510). Therefore, the same effect as the configuration shown in FIG. 47 can be achieved. FIG. 49 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

[0223] In Fig. 50, overlapping portion 930 of signal terminal 93 is in contact with the surface of exposed portion 510. Signal terminal 93 is in contact with insulating base material 51 (exposed portion 510) but is not fixed thereto. Therefore, an effect equivalent to that of the configuration shown in Fig. 47 can be achieved. Fig. 50 is a cross-sectional view showing a modified example and corresponds to Fig. 47. Note that an arrangement may be adopted in which part of the lower surface of joint portion 93b is in contact with insulating base material 51 and the other part is not in contact.

[0224] In the example shown in FIG. 47, the substrate 60 is arranged so as not to overlap the signal terminal 93 in a plan view. That is, the substrate 60 is not arranged above the signal terminal 93. By adopting such an arrangement, the size of the substrate 60 can be reduced. In addition, it is easy to ensure an insulating distance between the front metal body 62 and the signal terminal 93. However, the positional relationship between the signal terminal 93 and the substrate 60 is not limited to the example shown in FIG. 47. For example, as shown in FIG. 51, the overlapping portion 930 of the signal terminal 93 also overlaps with the substrate 60. The front metal body 62 of the substrate 60 overlaps with the overlapping portion 930 and the exposed portion 510 of the insulating base material 51 in a plan view. This can improve heat dissipation. FIG. 51 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

[0225] 52, unlike FIG. 51, the front surface metal body 62 is patterned so as not to overlap with the overlapping portion 930 of the signal terminal 93. The insulating base material 61 and the back surface metal body 63 are located above the overlapping portion 930. By making the front surface metal body 62 smaller, it becomes easier to ensure the insulation distance between the front surface metal body 62 and the signal terminal 93. Since the back surface metal body 63 is large, heat dissipation can be improved. FIG. 52 is a cross-sectional view showing a modified example and corresponds to FIG. 47.

[0226] An example has been shown in which the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 into the substrate 50. Alternatively, the length of the bonding wire 110 may be shortened by using the relay substrate 150 shown in Figs. 53 to 55. Fig. 53 is a plan view showing a modified example, and corresponds to Fig. 46. In Fig. 53, some of the elements of the semiconductor device 20 are omitted in order to show the positional relationship between the substrate 50, the signal terminal 93, and the relay substrate 150. Fig. 54 is a cross-sectional view showing the relay substrate. Fig. 55 is a cross-sectional view taken along the line LV-LV in Fig. 53. Here, the relay wiring 55 and the signal terminal 93L are shown as an example, but the same configuration can also be adopted for the P wiring 54 and the signal terminal 93H.

[0227] The semiconductor device 20 further includes an intermediate substrate 150. As shown in Figs. 53 and 55, the intermediate substrate 150 is disposed on the surface metal body 52 (relay wiring 55) of the substrate 50. As shown in Fig. 54, the intermediate substrate 150 has an insulating base material 151 and a conductor portion 152 disposed on the insulating base material 151. A part of the conductor portion 152 provides a wiring function. The intermediate substrate 150 is sometimes referred to as a printed circuit board or a wiring board.

[0228] The conductor portion 152 has lands 152a and 152b. The lands 152a and 152b are exposed on one surface of the relay substrate 150. Specifically, the lands 152a and 152b are exposed from a solder resist 153 provided on one surface 151a of the insulating base material 151. The land 152a is electrically connected to the pad 40P via a bonding wire 110. The signal terminal 93 overlaps with the substrate 50 in a plan view. The signal terminal 93 is connected to the land 152b.

[0229] The conductor portion 152 has a wiring 152c and a via conductor 152d other than the lands 152a and 152b. At least a part of the wiring 152c is an inner layer wiring arranged inside the insulating base material 151. The land 152a and the land 152b are electrically connected via the wiring 152c and the via conductor 152d. The multiple lands 152a include two lands 152a individually connected to pads 40P for gate electrodes of two semiconductor elements 40. The two lands 152a for the gate electrode are electrically connected to one land 152b for the gate electrode via the wiring 152c and the via conductor 152d.

[0230] In this way, by using the relay board 150, the connection target (land 152a) of the bonding wire 110 can be brought closer to the pad 40P. This allows the length of the bonding wire 110 that electrically connects the pad 40P and the signal terminal 93 to be shortened. Also, the wiring 152c can be freely routed within the relay board 150. This makes it possible to prevent the bonding wires 110 from crossing each other in a configuration in which the semiconductor elements 40 are connected in parallel. Therefore, it is possible to prevent the wires from contacting each other when the sealing body 30 is formed. Also, by using fine wiring technology for printed circuit boards, it is possible to achieve a size reduction to the same extent as the configuration shown in FIG.

[0231] The conductor portion 152 further has a fixing land 152e. The fixing land 152e is a land for fixing the relay substrate 150 to the substrate 50. The fixing land 152e does not provide an electrical connection function, that is, a wiring function. The fixing land 152e is disposed on the rear surface 151b of the insulating base material 151. The fixing land 152e (relay substrate 150) is bonded to the front surface metal body 52 via a bonding material 154. As the bonding material 154, for example, solder can be used.

[0232] In this way, since the relay board 150 is fixed to the front metal body 52, wire bonding can be stably performed. Solder containing Ni balls may be used as the bonding material 154. In this case, the Ni balls can control the thickness of the bonding material 154. Also, the inclination of the relay board 150 can be suppressed.

[0233] The wiring function provided by the conductor portion 152 is electrically separated from the front surface metal body 52 by the insulating base material 151. For example, the insulating base material 151 may have a non-arrangement area 151c in which the conductor portion 152 is not arranged and an arrangement area 151d in which the conductor portion 152 is arranged in the Z direction. In the Z direction, the non-arrangement area 151c is provided in the center of the insulating base material 151, and the arrangement area 151d is provided on the surface layer on both sides. The non-arrangement area 151c is sometimes referred to as a core layer. In this way, the insulating base material 151 has the non-arrangement area 151c, so that the conductor portion 152 providing the wiring function arranged on the one surface 151a side can be electrically separated from the fixing land 152e and therefore from the front surface metal body 52.

[0234] The solder resist 153 has low adhesion to the sealing body 30. Moreover, peeling of the sealing body 30 due to thermal stress progresses from the outer peripheral edge of the relay substrate 150. For example, the insulating base material 151 may have an exposed portion 151e exposed from the solder resist 153. The exposed portion 151e is provided on the outer peripheral edge of one surface 151a of the insulating base material 151. The insulating base material 151 has higher adhesion to the sealing body 30 than the solder resist 153. At the exposed portion 151e, the sealing body 30 is in close contact with the relay substrate 150. This makes it possible to suppress peeling of the sealing body 30 from the relay substrate 150. Since the sealing body 30 is in close contact with the outer peripheral edge, the conductor portions 152 such as the lands 152a and 152b exposed from the solder resist 153 can be protected.

[0235] As shown in FIG. 55, the signal terminal 93 (93L) has a first extension portion 93h, a second extension portion 93i, and a bent portion 93j. The first extension portion 93h and the second extension portion 93i extend in the Y direction. The first extension portion 93h is disposed inside the sealing body 30. The second extension portion 93i is disposed across the inside and outside of the sealing body 30. The bent portion 93j is provided between the first extension portion 93h and the second extension portion 93i. The first extension portion 93h is a portion closer to the tip side than the bent portion 93j, and the second extension portion 93i is a portion closer to the rear end side than the bent portion 93j.

[0236] The signal terminal 93 may have a protrusion 93k. The protrusion 93k is provided near the tip of the signal terminal 93. The protrusion 93k protrudes from the first extension 93h toward the land 152b in the Z direction. The protrusion 93k is joined to the land 152b. In the signal terminal 93, the tip of the first extension 93h and the protrusion 93k overlap with the land 152b in a plan view in the Z direction. The portion where the tip of the first extension 93h and the protrusion 93k are connected is a thick portion, and the other portion of the signal terminal 93 is a thin portion. By providing the protrusion 93k in this manner, the signal terminal 93 (first extension 93h) is away from the front metal body 52, making it easier to ensure an insulation distance between the front metal body 52 and the signal terminal 93.

[0237] Fig. 56 shows another example different from Fig. 54. Fig. 56 corresponds to Fig. 54. In Fig. 56, relay board 150 is fixed to exposed portion 510 of insulating base material 51. In this case, the thickness of bonding material 154 and relay board 150 can ensure the insulation distance between signal terminal 93 and rear surface metal body 53. If the solder containing Ni balls is used as bonding material 154, a predetermined thickness can be ensured, making it easier to ensure the insulation distance. In addition, the inclination of relay board 150 can be suppressed.

[0238] The front surface metal body 52 (relay wiring 55) has a notch 550 as shown in FIG. 46 , for example, to expose the insulating base material 51. For example, the front surface metal body 52 may have a chamfered portion 554. The chamfered portion 554 is provided at least on a surface of the end face that defines the notch 550, where an imaginary straight line connecting the semiconductor element 40 and the relay substrate 150 intersects. The chamfered portion 554 is provided on the upper end of the end face. This makes it possible to ensure an insulation distance between the bonding wire 110 and the front surface metal body 52.

[0239] An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S. That is, an example of a semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, the present invention is not limited to this example. It is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only a substrate 50 to which a drain electrode 40D (first main electrode) is connected. An example has been shown in which both of the rear surface metal bodies 53, 63 are exposed from the sealing body 30, but the present invention is not limited to this example.

[0240] Although an example has been shown in which the semiconductor device 20 includes the semiconductor element 40H that configures the upper arm 9H and the semiconductor element 40 that configures the lower arm 9L, the present invention is not limited to this. The semiconductor device 20 may include only the semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0241] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, and third embodiments, and the modified examples.

[0242] Fifth embodiment This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to ensure insulation reliability while reducing the size, the connection between the metal member and the surface metal body via the bonding material may be of a predetermined structure as described in this embodiment.

[0243] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 57. Fig. 57 corresponds to Fig. 5.

[0244] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 57, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 52 is connected to the P terminal 91P, which is the main terminal, and the output terminal 92 via a bonding material 104. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The surface metal body 62 is connected to the N terminal 91N (not shown), which is the main terminal, via the bonding material 104. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, parts of the main terminals, and the bonding material 104.

[0245] <Main terminal joint structure> Next, the joining structure of the main terminal will be described with reference to Figs. 57 to 60. Fig. 58 is a plan view of the periphery of the output terminal 92 in Fig. 57 as viewed from the LVIII direction. In Fig. 58, some parts are hatched for clarity. Fig. 59 is an enlarged view of the area LIX shown by the dashed line in Fig. 57. Fig. 60 is a view showing a state in which the joining material 104 has been removed from Fig. 59. For convenience, the sealing body 30 is omitted in Figs. 59 and 60.

[0246] As shown in FIG. 57, the joint structure of the P terminal 91P and the output terminal 92, which are main terminals, and the substrate 50 differs from the configuration described in the preceding embodiment (see FIG. 5). Although not shown, the joint structure of the N terminal 91N, which is also a main terminal, is also different. The other configurations are the same as those described in the preceding embodiment. The output terminal 92 will be described below as an example. The bonding material 104 wets and spreads over the metal surface when bonded. As an example, the bonding material 104 is solder.

[0247] As shown in Fig. 57, the substrate 50 has ends 50c and 50d in the Y direction. The end 50c is the end on the side surface 30c side of the sealing body 30, and the end 50d is the end on the side surface 30d side. The output terminal 92 extends in the Y direction, straddling the end 50d of the substrate 50. In a plan view in the Z direction, a part of the output terminal 92 overlaps with the front metal body 52 (relay wiring 55), and another part does not overlap. As shown in Figs. 58 to 60, the output terminal 92 has an opposing surface 920 and an accommodating portion 921.

[0248] The facing surface 920 is a portion of the lower surface of the output terminal 92 that faces the front metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. The facing surface 920 is a flat surface in a macroscopic sense, and ideally the entire surface of the facing surface 920 contacts the top surface 52a of the front metal body 52. ​​The facing surface 920 has minute irregularities on its surface in a microscopic sense, and at least a portion of the facing surface 920 contacts the top surface 52a. The facing surface 920 is sometimes referred to as a metal touch surface. In a plan view, the facing surface 920 is a portion of a predetermined range in the Y direction from a position where the facing surface 920 overlaps with the end 52b of the front metal body 52. ​​The end 52b is an end surface (side surface) on the side of the side surface 30d of the sealing body 30 in the Y direction, and is continuous with the top surface 52a. The end 52b forms a part of the end 50d. The facing surface 920 is substantially rectangular in plan view.

[0249] The storage portion 921 is provided adjacent to the facing surface 920 and provides a storage space for the bonding material 104. For example, the storage portion 921 is a recess recessed in a direction away from the upper surface 52a with respect to the facing surface 920. The recessed storage portion 921 is a surface including a Z-direction component, and has a side surface 921a continuing to the facing surface 920 and a bottom surface 921b continuing to the side surface 921a. The side surface 921a is, for example, a surface that is approximately parallel to the Z direction. The storage portion 921 opens to a tip surface 922 that is a side surface on the front side of the output terminal 92 in the Y direction. The storage portion 921 opens to side surfaces 923 and 924 on both sides of the output terminal 92 in the X direction. The storage portion 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92 in the Y direction. The storage portion 921 has a substantially rectangular shape in plan view. The storage portion 921 is provided in the Y direction in line with the X direction.

[0250] The output terminal 92 accommodates the bonding material 104 in the accommodation portion 921 with the opposing surface 920 in contact with the front surface metal body 52. ​​The bonding material 104 may be disposed only in the accommodation portion 921, or as shown in FIG. 59, a part of the bonding material 104 may be disposed outside the accommodation portion 921. In FIG. 59, the bonding material 104 forms a fillet with respect to the tip surface 922. The output terminal 92 is connected (joined) to the front surface metal body 52 via the bonding material 104 disposed in the accommodation portion 921.

[0251] <Main terminal joining method> The joint structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows. With the bonding material 104 (solder) placed in the accommodation portion 921, the upper portion of the opposing surface 920 of the output terminal 92 is pressed toward the substrate 50 in the Z direction so that the opposing surface 920 is in strong contact with the upper surface 52a. Reflow is performed with the opposing surface 920 in strong contact with the upper surface 52a. For this reason, the bonding material 104 does not spread toward the opposing surface 920 during reflow, or even if it does spread, it only penetrates into the concaves of the minute concaves and convexes on the surface of the opposing surface 920.

[0252] <Summary of the Fifth Embodiment> In this embodiment, the opposing surface 920 of the output terminal 92, which is a metal member, comes into contact (metal touch) with the upper surface 52a of the front metal body 52. ​​This makes it possible to prevent the bonding material 104 from overflowing from the accommodation portion 921 to the opposing surface 920 side. This makes it possible to prevent the bonding material 104 from spreading wet in unintended directions and ensure insulation reliability. In addition, the output terminal 92, which is a single member, has both the accommodation portion 921 and the opposing surface 920. As a result, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

[0253] In the configuration including the substrate 50, when the bonding material 104 spreads over the end 52b (end face) of the front metal body 52 and further over the insulating base material 51, the portion having the same potential as the front metal body 52 spreads, and the distance to the back metal body 53 becomes closer. There is a risk that the bonding material 104 may come into contact with the back metal body 53. In this embodiment, the facing surface 920 is provided at a position closer to the end 50d of the substrate 50, that is, the end 52b of the front metal body 52, than the housing portion 921. By disposing the facing surface 920 on the end 52b side, it is possible to prevent the bonding material 104 from spreading over the surface of the output terminal 92 and / or the front metal body 52 and reaching the end 52b and further the insulating base material 51. This makes it possible to improve insulation reliability without increasing the physical size.

[0254] As described above, the metal member having an opposing surface and a housing portion can also be applied to the other main terminals, the P terminal 91P and the N terminal 91N. The P terminal 91P is connected to the front metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. The opposing surface of the P terminal 91P comes into contact with the front metal body 52, thereby preventing the bonding material 104 from overflowing from the housing portion of the P terminal 91P to the opposing surface side. As shown in FIG. 57, by providing the opposing surface on the end portion 50c side of the substrate 50, the bonding material 104 can be prevented from spreading over the end portion of the front metal body 52 and the insulating base material 51.

[0255] The N terminal 91N is connected to the front metal body 62 (N wiring 64) of the substrate 60 via a bonding material 104. The opposing surface of the N terminal 91N comes into contact with the front metal body 62, thereby preventing the bonding material 104 from overflowing from the accommodation portion of the N terminal 91N to the opposing surface side. Furthermore, by providing the opposing surface on the end portion 60c side of the substrate 60 shown in FIG. 57, the bonding material 104 can be prevented from spreading wet onto the end portion of the front metal body 62 and the insulating base material 61. The end portion 60c is an end face (side surface) on the side of the side surface 30c of the sealing body 30 in the Y direction.

[0256] <Modification> The arrangement of the opposing surface 920 and the storage portion 921 is not limited to the above example. For example, the configurations shown in Figs. 61 and 62 may be adopted. Fig. 61 is a plan view showing a modified example and corresponds to Fig. 58. Fig. 62 is a plan view seen from the LXII direction shown in Fig. 61. In this example, the storage portion 921 does not open to the side surfaces 923 and 924, but only opens to the tip surface 922. The storage portion 921 has an opening 921c in the tip surface 922, which is a side surface.

[0257] The facing surface 920 has a first facing portion 920a and a second facing portion 920b. The first facing portion 920a is provided on the opposite side of the opening 921c with respect to the housing portion 921. In the Y direction, which is the extension direction of the output terminal 92, the first facing portion 920a is adjacent to the housing portion 921. The second facing portion 920b is adjacent to the housing portion in the X direction. In the example shown in FIG. 61 and FIG. 62, the facing surface 920 has a pair of second facing portions 920b. The pair of second facing portions 920b sandwich the housing portion 921 in the X direction. The facing surface 920 has a planar substantially U-shaped shape. Since the facing surface 920 is disposed on three sides with respect to the housing portion 921, the overflow direction of the bonding material 104 from the housing portion 921 can be limited to one direction on the opening 921c side. This can further improve the insulation reliability.

[0258] The opposing surface 920 may have only one second opposing portion 920b. In this case, the opposing surface 920 has a generally L-shaped planar shape. Since the opposing surfaces 920 are disposed on two sides of the accommodation portion 921, the overflow direction of the bonding material 104 from the accommodation portion 921 can be restricted compared to the arrangement in FIG. 58. This can improve the insulation reliability.

[0259] Although an example in which the storage section 921 opens on the side surface of the output terminal 92 has been shown, the present invention is not limited to this. In addition, the planar shape of the storage section 921 is not limited to a substantially rectangular shape. For example, as shown in FIG. 63, the storage section 921 may be provided without an opening on the side surface. FIG. 63 is a plan view showing a modified example, and corresponds to FIG. 58. In FIG. 63, the storage section 921 has a substantially circular planar shape. The storage section 921 is a hole that opens on the lower surface of the output terminal 92. The storage section 921 shown in FIG. 63 is a non-through hole. The storage section 921 that is a non-through hole has a side surface 921a and a bottom surface 921b that are continuous with the opposing surface 920, similar to the storage section 921 described above. Instead of this, a through hole that opens on the upper surface of the output terminal 92 may be adopted. The storage section 921 that is a through hole does not have a bottom surface 921b, but has a side surface 921a.

[0260] The metal member having the opposing surface and the housing portion is not limited to the main terminal. For example, as shown in Fig. 64 and Fig. 65, in the semiconductor device 20 constituting the upper and lower arm circuits 9, the joint portion 81 may be provided with the opposing surface and the housing portion. Fig. 64 is a cross-sectional view showing a modified example, and corresponds to Fig. 57. Fig. 65 is an enlarged view of the region LXV shown by the dashed line in Fig. 64. For convenience, Fig. 65 omits the sealing body 30.

[0261] As described in the preceding embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is a first semiconductor element constituting the upper arm 9H, and a semiconductor element 40L, which is a second semiconductor element constituting the lower arm 9L. The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal columnar body extending in the Z direction. An end portion 81a of the joint portion 81 is connected to the relay wiring 55, which is the first wiring of the substrate 50, via a bonding material 103. An end portion 81b opposite to the end portion 81a is connected to the relay wiring 65, which is the third wiring of the substrate 60, via a bonding material 103. The front surface metal body 52 has a P wiring 54, which is the second wiring, provided with a predetermined interval between it and the relay wiring 55. The front surface metal body 62 has an N wiring 64, which is the fourth wiring, provided with a predetermined interval between it and the relay wiring 65.

[0262] In the example shown in Figs. 64 and 65, an opposing surface 810 and a storage portion 811 are provided at each of the ends 81a and 81b of the joint portion 81. The configurations of the opposing surface 810 and the storage portion 811 are similar to those of the opposing surface 920 and the storage portion 921 described above. At the end 81a, the opposing surface 810 faces the upper surface 52a of the front metal body 52 (relay wiring 55). The opposing surface 810 is in contact with the upper surface 52a. The storage portion 811 is a recess recessed relative to the opposing surface 810. The storage portion 811 has a side surface 811a continuing to the opposing surface 810, and a bottom surface 811b. The storage portion 811 stores the bonding material 103.

[0263] The opposing surface 810 and the accommodating portion 811 are arranged side by side in the Y direction. The opposing surface 810 is provided on the side of the wiring gap 52G separating the relay wiring 55 and the P wiring 54, that is, at a position close to the P wiring 54 which is a wiring separate from the relay wiring 55 to which the joint portion 81 is connected. The accommodating portion 811 opens to a side surface 812 of the joint portion 81 in the Y direction, and does not open to a side surface 813 opposite the side surface 812. The accommodating portion 811 may open only to the side surface 812, or may open to three side surfaces including two side surfaces adjacent to the side surface 812.

[0264] In this manner, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 52. ​​This makes it possible to prevent the bonding material 103 from overflowing from the housing portion 811 to the opposing surface 810. This makes it possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

[0265] Furthermore, when the bonding material 103 spreads into the inter-wiring gap 52G of the front surface metal body 52, the portion having the same potential as the relay wiring 55 spreads, and the distance to the P wiring 54 becomes closer. There is a risk that the bonding material 103 may come into contact with the P wiring 54. In contrast, in the above example, the opposing surface 810 is provided at a position closer to the P wiring 54, i.e., the inter-wiring gap 52G, than the housing portion 811. This makes it possible to prevent the bonding material 103 from reaching the inter-wiring gap 52G. Therefore, it is possible to improve the insulation reliability without increasing the physical size.

[0266] The configuration of the end 81b is the same as that of the end 81a. In the end 81b, the facing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The facing surface 810 is in contact with the upper surface 52a. The accommodation portion 811 is a recess. The accommodation portion 811 accommodates the bonding material 103. The facing surface 810 and the accommodation portion 811 are arranged side by side in the Y direction. The facing surface 810 is provided on the side of the wiring gap 62G separating the relay wiring 65 and the N wiring 64, that is, in a position close to the N wiring 64, which is a wiring different from the relay wiring 65 to which the joint portion 81 is connected. The accommodation portion 811 opens to a side surface 813 of the joint portion 81 in the Y direction, and does not open to a side surface 812. The accommodation portion 811 may open only to the side surface 813, or may open to three side surfaces including two side surfaces adjacent to the side surface 813.

[0267] In this manner, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 62. This makes it possible to prevent the bonding material 103 from overflowing from the accommodation portion 811 to the opposing surface 810. This makes it possible to provide a semiconductor device 20 that can achieve both insulation reliability and compact size. In addition, the opposing surface 810 is provided at a position closer to the N wiring 64, i.e., the inter-wiring gap 62G, than the accommodation portion 811. This makes it possible to prevent the bonding material 103 from reaching the inter-wiring gap 62G. This makes it possible to improve insulation reliability without increasing the size.

[0268] In the above example, overflow of the bonding material is suppressed by contact of the front metal body with the opposing surface of the metal member. The function of suppressing overflow may be enhanced by further adding a rough oxide film formed by laser irradiation to this configuration. An example is shown in Figs. 66 and 67. Fig. 66 is a cross-sectional view corresponding to Fig. 65, and for convenience, the sealing body 30 is omitted. Fig. 67 is an enlarged view of the area LXVII indicated by the dashed line in Fig. 66, and only the front metal body 52 is shown.

[0269] In the example shown in FIG. 66, uneven oxide films 520, 620 are provided on the surface metal bodies 52, 62, respectively, corresponding to the joint portion 81. The uneven oxide film 520 will be described below as an example. As shown in FIG. 67, the surface metal body 52 has a base material 521, and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 forms a main part of the surface metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed containing a material having higher wettability to solder than the base material 521. The metal film 522 is formed over the entire area of ​​the upper surface 52a. The metal film 522 of this embodiment is formed over the entire area of ​​the surface of the base material 521. The uneven oxide film 520 is formed locally on the upper surface 52a.

[0270] The uneven oxide film 520 is formed locally on the metal film 522 on the upper surface 52a by irradiating the metal film 522 with a laser beam. The metal film 522 has an undercoat film mainly composed of Ni (nickel) and an overcoat film mainly composed of Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the undercoat film. When the bonding material 103 is solder, the overcoat film (Au) of the metal film 522 exposed from the uneven oxide film 520 in the portion in contact with the bonding material 103 diffuses into the solder during reflow. The overcoat film (Au) of the metal film 522 in the portion where the uneven oxide film 520 is to be formed is removed by irradiation with a laser beam when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. For example, the components constituting the uneven oxide film 520 are 80% NI2O3, 10% NiO, and 10% Ni.

[0271] The recesses 523 on the surface of the metal film 522 are formed by irradiation with a pulsed laser beam. One recess 523 is formed for each pulse. The uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the metal film 522 by irradiation with the laser beam. The uneven oxide film 520 is an oxide film derived from the metal film 522. The uneven oxide film 520 is a film of oxide of the metal (Ni) that is the main component of the metal film 522. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. The unevenness is formed on the surface of the uneven oxide film 520 at a pitch finer than the width of the recesses 523. That is, very fine unevenness (roughened portion) is formed.

[0272] Such an uneven oxide film 520 can be formed by the process described below. First, a pulsed laser beam is irradiated onto the upper surface 52a of the surface metal body 52, which has a metal film 522 formed on a base material 521, to melt and evaporate the surface of the metal film 522. The pulsed laser beam has an energy density of 0 J / cm 2 Greater than 100J / cm 2 The pulse width is adjusted to be 1 μs or less and the energy density is adjusted to be 1 J / cm or less. To meet this condition, a YAG laser, YVO4 laser, fiber laser, etc. can be used. For example, in the case of a YAG laser, the energy density is 1 J / cm 2 For example, 5 J / cm for electroless Ni plating. 2 The metal film 522 can be processed even if the thickness is only slightly increased.

[0273] At this time, the laser light source and the surface metal body 52 are moved relatively to scan the laser light and irradiate the laser light to a plurality of positions in sequence. The laser light is irradiated to melt and vaporize the surface of the metal film 522, forming recesses 523 on the surface of the metal film 522. The average thickness of the portion of the metal film 522 irradiated with the laser light is thinner than the average thickness of the portion not irradiated with the laser light. The recesses 523 formed corresponding to the spots of the laser light are connected to each other, for example, in a scale shape. The spot is the range irradiated by one pulse. For example, the laser light is scanned so that adjacent spots of the laser light in the X direction partially overlap and adjacent spots of the laser light in the Y direction partially overlap.

[0274] Next, the molten metal film 522 is solidified. Specifically, the molten and vaporized metal film 522 is deposited on the portion irradiated with the laser light and its surrounding area. In this manner, the molten and vaporized metal film 522 is deposited to form an uneven oxide film 520 on the surface of the metal film 522.

[0275] In FIG. 66, the uneven oxide film 520 is not provided in a first region 524 of the upper surface 52a of the front metal body 52 that overlaps with the accommodation portion 811 of the joint portion 81 in a plan view. The uneven oxide film 520 is selectively provided in a second region 525 that overlaps with the opposing surface 810. The configurations of the front metal body 62 and the uneven oxide film 620 are similar to those of the front metal body 52 and the uneven oxide film 520. The uneven oxide film 620 is not provided in a first region 624 of the upper surface 62a of the front metal body 62 that overlaps with the accommodation portion 811 of the joint portion 81 in a plan view. The uneven oxide film 620 is selectively provided in the second region 625 that overlaps with the opposing surface 810.

[0276] The oxide film (uneven oxide film 520, 620) has a lower wettability with respect to the bonding material 103 than the metal film. Since the uneven oxide film 520, 620 has fine unevenness on the surface, the contact area with the bonding material 103 is small, and a part of the bonding material 103 becomes spherical due to surface tension. That is, the contact angle is large. As a result, the wettability with respect to the bonding material 103 is low. Therefore, due to the effect of the wettability reduction by the uneven oxide film 520, 620 and the effect of contact with the opposing surface 810, the bonding material 103 is unlikely to pass between the opposing surface 810 and the second region 525, 625. As a result, the overflow of the bonding material 103 can be more effectively suppressed. Since the uneven oxide film 520, 620 is formed using a laser beam as described above, patterning is easy.

[0277] As shown in FIG. 68, the uneven oxide films 520, 620 may be provided in the peripheral regions 526, 626. The peripheral region 526 is a region around the second region 525 in a plan view, excluding the first region 524. The peripheral region 626 is a region around the second region 625 in a plan view, excluding the first region 624. Even if the bonding material 103 passes directly under the opposing surface 810 of the joint portion 81, it can be blocked by the uneven oxide films 520, 620. In addition, since very fine unevenness is formed on the surface of the uneven oxide films 520, 620, the plug 30 is entangled, and an anchor effect is generated. In addition, the contact area with the plug 30 is increased. Therefore, the adhesion force of the surface metal bodies 52, 62 to the plug 30 can be increased.

[0278] The uneven oxide films 520, 620 may be provided in the second regions 525, 625 and the peripheral regions 526, 626. Only one of the uneven oxide films 520, 620 may be provided. The uneven oxide films 520, 620 may be used for the junctions with the main terminals, which are metal members, that is, the P terminal 91P, the N terminal 91N, and the output terminal 92.

[0279] An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S (second main electrode). That is, an example of a semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, the present invention is not limited to this example. It is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In the semiconductor device 20 including a pair of substrates 50, 60, the above structure may be applied only to the joint between one of the substrates 50, 60 and the metal member. An example has been shown in which both of the back metal bodies 53, 63 are exposed from the sealing body 30, but the present invention is not limited to this example.

[0280] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0281] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, and fourth embodiments, and the modified examples.

[0282] Sixth embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the reliability of the semiconductor device, the physical properties of the sealing body and the physical properties of the insulating base material may satisfy a predetermined relationship as described in this embodiment.

[0283] <Semiconductor device and heat dissipation structure> The semiconductor device 20 of this embodiment and its heat dissipation structure will be described with reference to Fig. 69. Fig. 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 69 is an enlarged view of a portion of Fig. 5. In Fig. 69, the external connection terminals 90 are omitted for convenience.

[0284] The semiconductor device 20 of this embodiment has a structure similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 69, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The back metal bodies 53 and 63 are exposed from the sealing body 30. The insulating base materials 51 and 61 contain resin. The sealing body 30 contains resin. Although not shown, the semiconductor device 20 includes a semiconductor element 40L.

[0285] 69 shows the semiconductor device 20 together with the heat exchanger 121 of the cooler 120 and a heat conductive member 130 such as a heat dissipation gel. That is, FIG. 69 shows a semiconductor module 140 including the semiconductor device 20, the cooler 120, and the heat conductive member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged side by side with the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

[0286] The rear surface metal bodies 53, 63 are exposed from the sealing body 30 as rear surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed facing one surface 30a and the rear surface 50b of the sealing body 30, and the other of the heat exchanger sections 121 is disposed facing the rear surfaces 30b and 60b of the sealing body 30. A heat conductive member 130 is disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger section 121. The heat conductive member 130 is in close contact with the semiconductor device 20 and the heat exchanger section 121.

[0287] <Relationship to glass transition temperature> Next, the relationship between the glass transition points of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to FIGS.

[0288] FIG. 70 is a diagram showing an example of the relationship between the glass transition point Tgs and the linear expansion coefficient αs of the sealing body 30 and the glass transition point Tgi and the linear expansion coefficient αi of the insulating base material 51, 61. In FIG. 70, the vertical axis indicates the linear expansion coefficient α, and the horizontal axis indicates the temperature. In FIG. 70, the solid line indicates the linear expansion coefficient αs of the sealing body 30, and the dashed line indicates the linear expansion coefficient αi of the insulating base material 51, 61. Among the linear expansion coefficients αs, α1s indicates the linear expansion coefficient at a temperature lower than the glass transition point Tgs, that is, the linear expansion coefficient of the α1 region. α2s indicates the linear expansion coefficient at a temperature higher than the glass transition point Tgs, that is, the linear expansion coefficient of the α2 region. The same is true for the linear expansion coefficient αi, where α1i indicates the linear expansion coefficient of the α1 region and α2s indicates the linear expansion coefficient of the α2 region.

[0289] 69, the sealing body 30 is in close contact with the semiconductor element 40. The insulating base materials 51, 61 are thermally connected to the semiconductor element 40 via the bonding materials 100, 101, 102 and the surface metal bodies 52, 62. Therefore, when the semiconductor element 40 is in operation (heat generation), the temperature of a peripheral position MP1 of the sealing body 30 around the semiconductor element 40 is higher than the temperatures of positions MP2, MP3 of the insulating base materials 51, 61 that overlap with the semiconductor element 40. In this way, the sealing body 30 has a higher temperature than the insulating base materials 51, 61.

[0290] When the temperature of the encapsulant 30 exceeds the glass transition point Tgs, the Young's modulus decreases, and the encapsulant 30's sealing function decreases. The decrease in sealing function may cause thermal stress to concentrate on the drain electrode 40D, the source electrode 40S, and their junctions, which may cause cracks or the like. In other words, there is a risk of a decrease in connection reliability. In contrast, in this embodiment, as shown in FIG. 70, the relationship Tgs>Tgi is satisfied.

[0291] <Relationship to linear expansion coefficient> Next, the relationship between the linear expansion coefficient of the sealing body 30 and the insulating base materials 51, 61 will be described with reference to Figs. 70 to 72. Figs. 71 and 72 are conceptual diagrams showing warping of the semiconductor device 20. Figs. 71 and 72 show only the resin elements that configure the semiconductor device 20, that is, only the sealing body 30 and the insulating base materials 51, 61.

[0292] When the semiconductor element 40 is in operation (heat generation), if the linear expansion coefficient αs of the sealing body 30 is larger than the linear expansion coefficient αi of the insulating base materials 51 and 61, the amount of expansion of the sealing body 30 becomes larger than the amount of expansion of the insulating base materials 51 and 61, as shown by the dashed arrows in Fig. 71. That is, the amount of expansion becomes larger at the center in the Z direction and smaller at both ends. Therefore, both ends in the Z direction become concave.

[0293] In this embodiment, as shown in FIG. 70, the relationship αi>αs is satisfied. Specifically, the relationship α1i>α1s is satisfied in the α1 region, and the relationship α2i>α2s is satisfied in the α2 region. As described above, since the relationship Tgs>Tgi is satisfied, the relationship αi>αs is satisfied over the entire operating temperature range. Therefore, when the semiconductor element 40 is in operation (when generating heat), the amount of expansion of the insulating base material 51, 61 is larger than the amount of expansion of the sealing body 30, as shown by the dashed arrow in FIG. 72. That is, the amount of expansion is smaller at the center in the Z direction and larger at both ends. Therefore, as shown in FIG. 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

[0294] <Summary of the Sixth Embodiment> According to this embodiment, the glass transition point Tgs of the sealing body 30 is higher than the glass transition points Tgi of the insulating substrates 51 and 61. Thereby, when the semiconductor element 40 is operating, for the sealing body 30 which reaches a higher temperature, it becomes difficult for the temperature to exceed the glass transition point Tgs. The temperature of the sealing body 30 either does not exceed the glass transition point Tgs or, if it does, only slightly. Therefore, the Young's modulus of the sealing body 30 can be reduced, and it is possible to suppress a decline in the sealing function. Since a decline in the sealing function can be suppressed, it is possible to suppress stress concentration at the drain electrode 40D, the source electrode 40S, which are main electrodes, and their junction portions. That is, the connection reliability can be enhanced.

[0295] The glass transition point Tgs of the sealing body 30 may be made substantially equal to the glass transition points Tgi of the insulating substrates 51 and 61. Compared with Tgs < Tgi, for the sealing body 30 which reaches a higher temperature during heat generation, it becomes difficult for the temperature to exceed the glass transition point Tgs.

[0296] Also, the linear expansion coefficients αi of the insulating substrates 51 and 61 are higher than the linear expansion coefficient αs of the sealing body 30. Thereby, when the semiconductor element 40 is operating, the amount of expansion of the insulating substrates 51 and 61 becomes larger than the amount of expansion of the sealing body 30. That is, the amount of expansion is small at the center in the Z direction and large at both ends. As a result, a convex warp occurs on the outside in the Z direction in the semiconductor device 20. Therefore, the facing distance between the semiconductor device 20 and the cooler 120(121) becomes narrow, and the thermal resistance between the semiconductor device 20 and the cooler 120 becomes small. Specifically, the thickness of the heat conducting member 130 becomes thin, and the thermal resistance becomes small. Since the heat of the semiconductor element 40 can be efficiently dissipated, it is possible to suppress the semiconductor element 40 from entering an overheated state. That is, the heat dissipation performance can be enhanced.

[0297] The linear expansion coefficients αi of the insulating substrates 51 and 61 may be made substantially equal to the linear expansion coefficient αs of the sealing body 30. In this case, the amount of expansion becomes substantially equal at the center and both ends in the Z direction, and it is possible to suppress the formation of a concave shape in which both ends in the Z direction are recessed. That is, it is possible to suppress an increase in the thermal resistance between the semiconductor device 20 and the cooler 120 due to the formation of the concave shape.

[0298] In this manner, by satisfying the relationships Tgs≧Tgi and αi≧αs, a highly reliable semiconductor device 20 can be provided.

[0299] <Modification> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited to this example. The present invention can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected.

[0300] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0301] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, and fifth embodiments, and the modified examples.

[0302] Seventh embodiment This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress peeling of the sealing body, the surface metal body may have a predetermined structure as described in this embodiment.

[0303] <Semiconductor device> 73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG 73 corresponds to FIG 8.

[0304] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 73, the semiconductor device 20 includes two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, via a bonding material 100. The front surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, via a bonding material 102. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back surface metal bodies 53 and 63 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L.

[0305] As shown in FIG. 73, the surface metal bodies 52, 62 have roughened portions 527, 627 and non-roughened portions 528, 628.

[0306] <Uneven oxide film> Next, uneven oxide film 520 constituting roughened portion 527 will be described in detail with reference to Fig. 74 and Fig. 75. Fig. 74 is an enlarged view of region LXXIV in Fig. 73. Fig. 75 is a view showing a method for forming a roughened portion.

[0307] The front surface metal bodies 52, 62 have uneven oxide films 520, 620, similar to the configuration described in the modified example of the fifth embodiment (see Figs. 66 and 67). The uneven oxide films 520, 620 provide roughened portions 527, 627 on the surfaces of the front surface metal bodies 52, 62. Portions of the surfaces of the front surface metal bodies 52, 62 where the uneven oxide films 520, 620 are not formed provide non-roughened portions 528, 628. The following description will be given taking the front surface metal body 52 as an example.

[0308] As shown in FIG. 74, the front metal body 52 has a base material 521, and a plating film 522p and a rough oxide film 520 provided on the surface of the base material 521. The base material 521 forms a main part of the front metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The plating film 522p is formed containing a material having higher wettability with respect to the bonding material 100 such as solder than the base material 521. The plating film 522p is formed over the entire upper surface 52a and the entire side surface 52c of the front metal body 52. ​​The side surface 52c is a surface that connects the upper surface 52a and the lower surface 52d facing the insulating base material 51 in the front metal body 52.

[0309] The uneven oxide film 520 is formed by irradiating the plating film 522p with a laser beam as described in the modified example of the fifth embodiment. In this embodiment, the upper surface 52a and the side surface 52c of the front metal body 52 are irradiated with a laser beam. The roughened portion 527 provided by the uneven oxide film 520 is a portion of the upper surface 52a excluding the non-roughened portion 528. As an example, the roughened portion 527 is formed over the entire side surface 52c. At the end of the front metal body 52, the roughened portion 527 is continuously provided from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a part of the upper surface 52a and on the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a part of the upper surface 52a and includes at least the arrangement area (bonding area) of the bonding material 100. Non-roughened portion 528 may be provided only in the bonding region, or may include a region other than the bonding region. Roughened portion 527 is provided on at least a portion of side surface 527. Roughened portion 527 may be provided on only a portion of side surface 527. For example, roughened portion 527 may be provided on only a portion of side surface 527 so that uneven oxide film 520 does not contact insulating base material 51.

[0310] The plating film 522p of this embodiment has an undercoat film mainly composed of Ni (nickel) and an upper layer mainly composed of Au (gold). Specifically, an electroless Ni plating film containing P (phosphorus) is used as the undercoat film. When the bonding material 100 is solder, the upper layer (Au) of the plating film 522p exposed from the uneven oxide film 520, which is in contact with the bonding material 100, diffuses into the solder during reflow. The upper layer (Au) of the plating film 522p, where the uneven oxide film 520 is to be formed, is removed by irradiation with a laser beam when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. The uneven oxide film 520 is continuously provided from the side surface 52c to the upper surface 52a at the end of the surface metal body 52.

[0311] As described in the modified example of the fifth embodiment, the uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the plating film 522p by irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the plating film 522p. The uneven oxide film 520 is a film of oxide of the metal (Ni) that is the main component of the plating film 522p. Fine unevenness (roughened portion) is always formed on the surface of the uneven oxide film 520. The uneven oxide film 520 has a continuously uneven surface.

[0312] In this embodiment, the surface area of ​​the front metal body 52 is larger on the lower surface 52d than on the upper surface 52a. Therefore, as shown in Fig. 74, the lower surface 52d protrudes from the upper surface 52a. That is, in a plan view in the Z direction, at least a part of the side surface 52c is located outside the upper surface 52a. Therefore, as shown in Fig. 75, by irradiating the laser light in the Z direction, it is possible to form an uneven oxide film 520 on the upper surface 52a and the side surface 52c.

[0313] <Summary of the Seventh Embodiment> In a configuration in which the plating film 522p is provided on the upper surface 52a and the side surface 52c of the front metal body 52, the sealer 30 is likely to peel off from the end of the front metal body 52, i.e., the side surface 52c, due to thermal stress. In contrast, in this embodiment, the roughened portion 527 is provided on the part of the upper surface 52a excluding the non-roughened portion 528 and on the side surface 52c. This makes the adhesion between the sealer 30 and the side surface 52c of the front metal body 52 stronger than in a configuration in which the roughened portion 527 is not provided. Therefore, it is possible to suppress peeling of the sealer 30 from occurring on the side surface 52c of the front metal body 52. ​​By suppressing peeling, it is possible to suppress concentration of thermal stress on the bonding portion of the bonding material 100 and the like in the front metal body 52. ​​As a result, it is possible to provide a highly reliable semiconductor device 20.

[0314] The front surface metal body 62 has the same configuration as the front surface metal body 52. ​​The front surface metal body 62 has a roughened portion 627 on a portion of the top surface 62a excluding the non-roughened portion 628 and on the side surface 62c. This makes it possible to suppress peeling of the sealer 30 on the side surface 62c of the front surface metal body 62.

[0315] In this embodiment, the roughened portions 527, 627 are provided continuously over the side surfaces 52c, 62c and the upper surfaces 52a, 62a. This makes it possible to prevent peeling of the plug 30 near the ends of the surface metal bodies 52, 62.

[0316] The roughening treatment for forming the roughened portions 527, 627 may be roughening plating, sandblasting, chemical treatment, or the like. In this embodiment, laser roughening is used. The uneven oxide films 520, 620 are formed by irradiating the plating film with laser light. The surface metal bodies 52, 62 have the uneven oxide films 520, 620 on the roughened portions 527, 627.

[0317] The uneven oxide film 520, 620 has a surface with continuous unevenness, and the sealing body 30 is entangled to generate an anchor effect. In addition, the contact area with the sealing body 30 is increased. Therefore, the adhesion force to the sealing body 30 can be increased in the roughened portion 527, 627. In addition, the uneven oxide film 520, 620 has a lower wettability with the bonding material 100, 102 than the plating film (plating film 522p). Since the uneven oxide film 520, 620 has fine unevenness on the surface, the contact area with the bonding material 100, 102 is reduced, and a part of the bonding material 100, 102 becomes spherical due to the surface tension. In other words, the contact angle is increased. Therefore, the overflow of the bonding material 100, 102 can be suppressed. In this way, by adopting the uneven oxide film 520, 620, the adhesion force to the sealing body 30 can be increased and the overflow of the bonding material 100, 102 from the bonding portion can be suppressed.

[0318] In this embodiment, the surface area of ​​the surface metal body 52, 62 is larger on the lower surface 52d, 62d than on the upper surface 52a, 62a. The lower surface 52d, 62d protrudes from the upper surface 52a, 62a. Therefore, it is easy to perform physical roughening on the side surface 52c, 62c from the Z direction. In the case of the above-mentioned laser roughening, by irradiating the laser light in the Z direction, the uneven oxide film 520, 620 can be formed not only on the upper surface 52a, 62a but also on the side surface 52c, 62c.

[0319] <Modification> The side shape of the front surface metal bodies 52, 62 is not limited to the above-mentioned examples. When the front surface metal bodies 52, 62 are patterned by pressing, etching, cutting, or the like, the side surface can be processed into a predetermined shape. FIG. 76 is a cross-sectional view showing a modified side surface shape. In FIG. 76, the front surface metal body 52 is shown as an example, and for convenience, the plating film 522p is omitted. Although not shown, a similar configuration can also be adopted for the front surface metal body 62.

[0320] In the example shown in FIG. 76, the surface metal body 52 has a side surface 52c that is approximately parallel to the Z direction. In other words, the area of ​​the surface metal body 52 is approximately constant in the Z direction. To physically roughen such a surface metal body 52, for example, the top surface 52a and the side surface 52c may be roughened separately. In the case of laser roughening, the side surface 52c is irradiated with laser light from a direction different from the direction of irradiation of the top surface 52a with the laser light, for example, from a direction tilted with respect to the Z direction. This allows an uneven oxide film 520 to be provided on the side surface 52c.

[0321] Fig. 77 is a cross-sectional view showing a modified example of the side shape, and corresponds to Fig. 76. In the example shown in Fig. 77, the area of ​​the front surface metal body 52 perpendicular to the Z direction becomes larger toward the lower surface 52d. The side surface 52c has an R-shape. In this case, the entire area of ​​the side surface 52c is located outside the upper surface 52a in a plan view. Therefore, it is easier to perform physical roughening of the side surface 52c from the Z direction, for example, laser roughening, than the configuration shown in Fig. 75.

[0322] Fig. 78 is a cross-sectional view showing a modified example of the side shape, and corresponds to Fig. 76. In the example shown in Fig. 78, the area of ​​the front-surface metal body 52 perpendicular to the Z direction increases toward the lower surface 52d. The front-surface metal body 52 has a substantially trapezoidal shape in the ZY plane, for example. In this case, too, the entire side surface 52c is located outside the upper surface 52a in a plan view, so that the side surface 52c can be easily physically roughened from the Z direction.

[0323] Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. It is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the above-mentioned structure of the roughened portion including the side surface may be applied to only one of the substrates 50, 60.

[0324] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0325] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, and sixth embodiments, and the modified examples.

[0326] Eighth embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to reduce inductance, the thickness of the surface metal body and the spacing between the wirings may satisfy a predetermined relationship, as described in this embodiment.

[0327] <Semiconductor device> First, the semiconductor device 20 according to this embodiment, particularly the circuit pattern of the front surface metal bodies 52 and 62, will be described with reference to Fig. 79. Fig. 79 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 79 illustrates a part of the configuration (see Fig. 8) described in the preceding embodiment.

[0328] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 79, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back metal bodies 53 and 63 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes a semiconductor element 40L that constitutes a lower arm 9L.

[0329] <Relationship between Wiring Spacing and Thickness> Next, based on FIGS. 79 and 80, the relationship between the wiring spacing and the thickness will be described. FIG. 80 is an enlarged view of region LXXX in FIG. 79. In FIG. 80, only the substrate 60 is shown.

[0330] The surface metal bodies 52 and 62 have wiring gaps 52G and 62G, similar to the configuration described in the previous embodiment (see FIG. 65). As shown in FIGS. 79 and 80, the wiring gap 62G separates the adjacent N-wiring 64 and the relay wiring 65. The wiring gap 62G is a predetermined gap provided between wirings with different potentials in the surface metal body 62.

[0331] As shown in FIG. 80, in this embodiment, the distance L10 between the N-wiring 64 and the relay wiring 65 is equal to or less than the thickness T10 of the surface metal body 62 (L10 ≦ T10). The distance L10 is the length of the wiring gap 62G, that is, the pattern distance between the N-wiring 64 and the relay wiring 65. In FIGS. 79 and 80, the distance L10 and the thickness T10 in the surface metal body 62 satisfy the relationship L10 < T10. Although not shown, the substrate 50 provided with the surface metal body 52 has the same configuration as the substrate 60. In the surface metal body 52, the distance L10 between the P-wiring 54 and the relay wiring 55 is equal to or less than the thickness T10 of the surface metal body 52 (L10 ≦ T10).

[0332] <Simulation Results> Figures 81 to 83 show the results of electromagnetic field simulation. Figure 81 is a diagram summarizing the simulation results in terms of the relationship between length (spacing, thickness) and inductance. The circles at the measurement points show the results for three levels of thickness T10 (0.3 mm, 1.5 mm, 2.5 mm) when the spacing L10 is fixed at 1.5 mm. The solid line in the figure shows the change in inductance accompanying the change in thickness T10 when the spacing L10 is fixed. The squares at the measurement points show the results for three levels of spacing L10 (0.5 mm, 1.5 mm, 2.5 mm) when the thickness T10 is fixed at 1.5 mm. The dashed line in the figure shows the change in inductance accompanying the change in spacing L10 when the thickness T10 is fixed. The length on the horizontal axis shown in Figure 81 indicates the length of thickness T10 when the spacing L10 is fixed, and indicates the length of spacing L10 when the thickness T10 is fixed.

[0333] Figure 82 is a diagram showing the simulation results when L10 > T10. Figure 82 shows the simulation results under the first condition C1 shown in Figure 81, specifically when the spacing L10 = 1.5 mm and the thickness T10 = 0.3 mm. Figure 83 is a diagram showing the simulation results when L10 < T10. Figure 83 shows the simulation results under the second condition C2 shown in Figure 81, specifically when the spacing L10 = 1.5 mm and the thickness T10 = 2.5 mm. In the simulation, the conditions other than the spacing L10 and the thickness T10 are common.

[0334] From the results shown in Figure 81, it is clear that the inductance can be reduced in the range satisfying the relationship L10 ≤ T10. In particular, it is clear that the inductance can be effectively reduced in the range satisfying the relationship L10 < T10.

[0335] As shown in FIG. 82, when L10 > T10, although the current is dispersed in the width direction in the extended portion 641 of the N wiring 64, it flows biased toward the end side of the surface metal body 62 (substrate 60). For this reason, the PN current loop (see FIG. 17) described in the previous embodiment is large. Since the current path flowing through the extended portion 421 is far from the relay wiring 65, the canceling effect of the magnetic flux by the current of the reverse direction component is weakened. FIG. 82 shows that the inductance becomes larger compared to the case where the relationship of L10 ≤ T10 is satisfied.

[0336] As shown in FIG. 83, when L10 < T10, the current flows biased toward the end on the relay wiring 65 side in the width direction of the extended portion 641. For this reason, the PN current loop is small. Since the current path flowing through the extended portion 421 is close to the relay wiring 65, the canceling effect of the magnetic flux by the current of the reverse direction component is enhanced. FIG. 83 shows that the inductance becomes smaller compared to the case where the relationship of L10 > T10 is satisfied.

[0337] <Summary of the Eighth Embodiment> In the present embodiment, the surface metal body 52 has a P wiring 54 that is a first wiring and a relay wiring 55 that is a second wiring having a different potential from the first wiring. And the interval L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the surface metal body 52 satisfy the relationship of L10 ≤ T10. Similarly, the surface metal body 62 has an N wiring 64 that is a first wiring and a relay wiring 65 that is a second wiring having a different potential from the first wiring. And the interval L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the surface metal body 62 satisfy the relationship of L10 ≤ T10.

[0338] When the relationship of L10≤T10 is satisfied, since the distance between adjacent wirings is narrow, the cancellation effect between the magnetic flux due to the current flowing through the first wiring and the magnetic flux due to the current flowing through the second wiring is enhanced, and the inductance can be reduced. Further, since the surface metal body is thick, the cross-sectional area of the current path becomes large, and the inductance can be reduced. As described above, the semiconductor device 20 of the present embodiment can reduce the inductance. In particular, when the relationship of L1<T10 is satisfied, the above-described effect is enhanced, and the inductance can be more effectively reduced.

[0339] <Modification Example> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, the present invention is not limited thereto. The present invention is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, only one of the surface metal bodies 52 and 62 may satisfy the above-described relationship of L10≤T10. That is, in at least one substrate electrically connected to the main electrode of the semiconductor element, the surface metal body may have a first wiring and a second wiring and satisfy the relationship of L10≤T10. Further, although an example in which the relationship of L10≤T10 is satisfied in all of the opposing regions between the N wiring 64 as the first wiring and the relay wiring 65 as the second wiring having a different potential from the first wiring has been shown, the present invention is not limited thereto. In at least a part of the opposing region, the relationship of L10≤T10 may be satisfied. The same applies to the opposing region between the P wiring 54 as the first wiring and the relay wiring 55 as the second wiring having a different potential from the first wiring.

[0340] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, the present invention is not limited thereto. The semiconductor device 20 may include only the semiconductor element 40 that constitutes one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0341] The configuration described in the present embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the modification example.

[0342] Ninth embodiment This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation and reliability, the side shape of the substrate may be a predetermined shape as described in this embodiment.

[0343] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 84. Fig. 84 is a cross-sectional view corresponding to Fig. 5. In Fig. 84, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

[0344] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 84, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102.

[0345] <Substrate> Next, the substrates 50 and 60 will be described with reference to Figs. 84 to 86. Fig. 85 is a plan view showing the center of the substrate. Fig. 85 corresponds to Fig. 12. Fig. 86 is an enlarged view of the area LXXXVI shown by the dashed line in Fig. 84. In the following, "inside" and "outside" indicate a relative positional relationship with the centers 50sc and 60sc of the substrates 50 and 60 in a plan view in the Z direction as the reference positions. The side closer to the center is the inside, and the side farther from the center is the outside. Fig. 85 shows the center 50sc of the substrate 50 as an example. Fig. 84 is a cross-sectional view, but for convenience of explanation, the centers 50sc and 60sc are shown.

[0346] In the substrates 50 and 60 of this embodiment, the insulating base material 51 and 61 contain resin. The surface metal bodies 52 and 62 are disposed on the surfaces 51a and 61a of the insulating base material 51 and 61. The surface metal bodies 52 and 62 are patterned as described in the preceding embodiment. As a result, the insulating base material 51 and 61 have exposed portions 510 and 610 exposed from the surface metal bodies 52 and 62. The exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, at least partially overlap each other in a plan view in the Z direction. The exposed portions 510 and 610 overlap each other. That is, at least a portion of the exposed portion 510 faces the exposed portion 610 in the Z direction.

[0347] The back metal body 53, 63 is disposed on the back surface 51b, 61b of the insulating base material 51, 61. The back metal body 53, 63 is exposed from the sealing body 30. In the back metal body 53, 63, the surface opposite to the surface 53a, 63a facing the insulating base material 51 is the exposed surface 53b, 63b. The exposed surface 53b is exposed substantially flush with the one surface 30a of the sealing body 30. The exposed surface 63b is exposed substantially flush with the back surface 30b of the sealing body 30. The exposed surfaces 53b, 63b form the back surfaces 50b, 60b of the substrates 50, 60. The sealing body 30 has a side surface 30e as a second surface continuing to the one surface 30a, which is the first surface, and the back surface 30b. The side surface 30e includes the side surfaces 30c, 30d in the Y direction, and also includes the side surface in the X direction. The side surface 30e includes all the side surfaces. The side surface 30e, which is the second surface, is a tapered surface inclined in the Z direction for removal from the mold during molding. The side surface 30e has a draft gradient. In the preceding embodiment, the draft gradient is omitted for convenience. The side surface 30e has a bent portion approximately in the center in the Z direction, and the closer to the one surface 30a and the back surface 30b from the bent portion, the closer to the semiconductor element 40 in a plan view in the Z direction. In other words, in a plan view, the bent portion is on the outside, and the one surface 30a and the back surface 30b are on the inside. Hereinafter, the one surface 30a and the back surface 30b of the sealing body 30 may be referred to as the first surface 30a, 30b.

[0348] As shown in FIG. 84 and FIG. 86, the substrate 50, 60 has a laminate 500, 600. The laminate 500 is a laminate of a two-layer structure of an insulating base material 51 and a back metal body 53. Similarly, the laminate 600 is a laminate of a two-layer structure of an insulating base material 61 and a back metal body 63. In the laminates 500, 600, the side surfaces connecting the surfaces 51a, 61a of the insulating base materials 51, 61 and the exposed surfaces 53b, 63b of the back metal bodies 53, 63 have a so-called V-cut shape. The side surfaces of the laminates 500, 600 have a shape in which the center portion is convex outward with respect to the surfaces 51a, 61a at the upper end and the exposed surfaces 53b, 63b at the lower end.

[0349] The side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601, second inclined portions 502 and 602, and intermediate portions 503 and 603. First, the laminate 500 will be described.

[0350] The first inclined portion 501 is a portion within a predetermined range from the surface 51a. The first inclined portion 501 has an inclination such that the distance to the center 50sc is closest at the upper end on the surface 51a side in a plan view, and is farther away from the upper end at the lower end. In other words, the lower end of the first inclined portion 501 is located outside the upper end. As shown in FIG. 85, the first inclined portion 501 is provided on the edge portion of the substrate 50. The first inclined portion 501 is annular so as to surround the surface metal body 52.

[0351] In this embodiment, the first inclined portion 501 has an inclination that is more distant from the center 50sc in a plan view as it is farther from the surface 51a in the Z direction. That is, in the upper portion of the laminate 500 including the first inclined portion 501, the area perpendicular to the Z direction at the surface 51a is the smallest, and the area becomes larger as it is farther from the surface 51a. The inclination of the first inclined portion 501 can tolerate manufacturing variations. The first inclined portion 501 has the inclination described above from a macroscopic perspective. The first inclined portion 501 is a tapered surface.

[0352] The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. The second inclined portion 502 has an inclination such that the distance to the center 50sc is closest at the lower end on the exposed surface 53b side in a plan view, and is farther away at the upper end than the lower end side. In other words, the upper end of the second inclined portion 502 is located outside the lower end. The second inclined portion 502 is provided on the edge portion of the substrate 50, similar to the first inclined portion 501. The second inclined portion 502 is annular so as to surround the back surface metal body 53.

[0353] In this embodiment, the second inclined portion 502 has an inclination that is more distant from the center 50sc in plan view as it is farther from the exposed surface 53b in the Z direction. That is, in the lower portion of the laminate 500 including the second inclined portion 502, the area is smallest at the exposed surface 53b, and the area becomes larger as it is farther from the exposed surface 53b. The inclination of the second inclined portion 502 can tolerate manufacturing variations. The second inclined portion 502 has the above-mentioned inclination from a macroscopic perspective. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is a forward taper, the second inclined portion 502 is a reverse taper.

[0354] The intermediate portion 503 is connected to the first inclined portion 501 and the second inclined portion 502. The intermediate portion 503 is a portion that connects the first inclined portion 501 and the second inclined portion 502, and has a predetermined length in the Z direction. The intermediate portion 503 is the apex portion of the side surface of the laminate 500. The side surface of the laminate 500 is farthest from the center 50sc at the intermediate portion 503. The intermediate portion 503 is the outermost portion of the laminate 500 in a planar view. The laminate 500 has the largest area perpendicular to the Z direction at the intermediate portion 503. At the intermediate portion 503, the area of ​​the laminate 500 is almost constant. The distance between the first inclined portion 501 and the center 50sc in a planar view is shorter as the first inclined portion 501 is farther from the intermediate portion 503. The distance between the second inclined portion 502 and the center 50sc in a planar view is shorter as the second inclined portion 502 is farther from the intermediate portion 503.

[0355] The laminate 600 has the same configuration as the laminate 500. The first inclined portion 601 is a portion within a predetermined range from the surface 61a. The first inclined portion 601 has an inclination such that the distance to the center 60sc is closest at the upper end on the surface 61a side in a plan view, and the lower end is farther away from the upper end. In other words, the lower end of the first inclined portion 601 is located outside the upper end. The first inclined portion 601 is provided on the edge portion of the substrate 60. The first inclined portion 601 is annular so as to surround the surface metal body 62.

[0356] In this embodiment, the first inclined portion 601 has an inclination that is more distant from the center 60sc in a plan view as it is farther from the surface 61a in the Z direction. That is, in the upper portion of the laminate 600 including the first inclined portion 601, the area perpendicular to the Z direction at the surface 61a is the smallest, and the area becomes larger as it is farther from the surface 61a. The inclination of the first inclined portion 601 can tolerate manufacturing variations. The first inclined portion 601 has the above-mentioned inclination from a macroscopic perspective. The first inclined portion 601 is a tapered surface.

[0357] The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. The second inclined portion 602 has an inclination such that the distance to the center 60sc is closest at the lower end on the exposed surface 63b side in a plan view, and is farther away at the upper end than at the lower end. In other words, the upper end of the second inclined portion 602 is located outside the lower end. The second inclined portion 602 is provided on the edge portion of the substrate 60, similar to the first inclined portion 501. The second inclined portion 602 is annular so as to surround the back surface metal body 63.

[0358] In this embodiment, the second inclined portion 602 has an inclination that is more distant from the center 60sc in plan view as it is farther from the exposed surface 63b in the Z direction. That is, in the lower portion of the laminate 600 including the second inclined portion 602, the area is smallest at the exposed surface 63b, and the area becomes larger as it is farther from the exposed surface 63b. The inclination of the second inclined portion 602 can tolerate manufacturing variations. The second inclined portion 602 has the above-mentioned inclination from a macroscopic perspective. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is a forward taper, the second inclined portion 602 is a reverse taper.

[0359] The intermediate portion 603 is connected to the first inclined portion 601 and the second inclined portion 602. The intermediate portion 603 is a portion that connects the first inclined portion 601 and the second inclined portion 602, and has a predetermined length in the Z direction. The intermediate portion 603 is the apex portion of the side surface of the laminate 600. The side surface of the laminate 600 is farthest from the center 60sc at the intermediate portion 603. The intermediate portion 603 is the outermost portion of the laminate 600 in a planar view. The laminate 600 has the largest area at the intermediate portion 603. At the intermediate portion 603, the area of ​​the laminate 600 is almost constant. The distance between the first inclined portion 601 and the center 60sc in a planar view is shorter as the first inclined portion 601 is farther from the intermediate portion 603. The distance between the second inclined portion 602 and the center 60sc in a planar view is shorter as the second inclined portion 602 is farther from the intermediate portion 603.

[0360] <Dimensions and angles> Next, the dimensions and angles of the laminates 500 and 600 will be described with reference to Fig. 87. Fig. 87 is a diagram corresponding to Fig. 86, and shows the dimensions and angles. In the following, the laminate 500 will be described as an example.

[0361] The length L11 shown in FIG. 87 is the length of the first inclined portion 501 in plan view, that is, the width of the annular first inclined portion 501. The length L12 is the length of the second inclined portion 502 in plan view, that is, the width of the annular second inclined portion 502. The length L21 is the length of the first inclined portion 501 in the Z direction, that is, the height of the first inclined portion 501. The length L22 is the length of the second inclined portion 502 in the Z direction, that is, the height of the second inclined portion 502. The length L23 is the length of the intermediate portion 503 in the Z direction, that is, the height of the intermediate portion 503. The length L24 is the length of the insulating base material 51 in the Z direction, that is, the thickness of the insulating base material 51. The length L25 is the length of the back surface metal body 53 in the Z direction, that is, the thickness of the back surface metal body 53.

[0362] The angle R1 is the inclination angle of the back surface metal body 53 with respect to the Z direction, which is the thickness direction of the semiconductor element 40, in the first inclined portion 501. The angle R2 is the inclination angle of the back surface metal body 53 with respect to the Z direction in the second inclined portion 502. The angle R3 is the inclination angle of the insulating base material 51 with respect to the Z direction in the first inclined portion 501. The angle R4 is the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53. The angle R5 is the inclination angle of the side surface 30e with respect to one surface 30a of the sealing body 30.

[0363] As shown in FIG. 87, in the present embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501. That is, the relationship L11 > L12 is satisfied. The angle R1 satisfies the relationship 0° < R1 ≦ 45°, and the angle R2 satisfies the relationship 0° < R2 < 45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be dissipated. The closer the angle R2 is to 45°, the lower the thermal resistance can be, as will be described later.

[0364] Furthermore, the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, and the second inclined portion 502 is provided on the back surface metal body 53. That is, the relationship of L21 > L24 and L22 < L25 is satisfied. In the configuration including the intermediate portion 503, the intermediate portion 503 is provided on the back surface metal body 53. That is, the relationship of L24 < (L24 + L25 - L23) / 2 is satisfied.

[0365] Furthermore, in the configuration in which the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, the inclination angle of the back surface metal body 53 and the inclination angle of the insulating base material 51 are substantially equal. That is, the relationship of R1 = R3 is satisfied.

[0366] Furthermore, the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) with respect to one surface 30a (first surface) of the sealing body 30. That is, the relationship of R4 < R5 is satisfied. Although the description is omitted, the laminate 600 also has the same configuration as the laminate 500.

[0367] <Manufacturing method of laminate> Next, an example of the manufacturing method of the above-described laminate 500 will be described. First, a mother substrate having a two-layer structure of an insulating base material 51 containing resin and a back surface metal body 53 is formed. Next, by a blade, cutting (V-cut) is simultaneously performed from both sides of the surface 51a of the insulating base material 51 and the exposed surface 53b. In this cutting, the first inclined portion 501 and the second inclined portion 502 are formed without completely separating the mother substrate. In the mother substrate, adjacent laminates 500 are connected at the intermediate portion 503. Then, by separating (cutting off) the adjacent laminates 500 at the intermediate portion 503, a laminate 500 having a V-cut-shaped side surface can be obtained.

[0368] Fig. 88 is a side view of the laminate 500 obtained by the above-mentioned manufacturing method. The first inclined portion 501 has a cut mark 501a along the circumferential direction due to cutting (cutting) using a blade. Similarly, the second inclined portion 502 has a cut mark 502a along the circumferential direction. Since the adjacent laminates 500 are separated at the intermediate portion 503, the intermediate portion 503 has an uneven portion 503a. Although the explanation is omitted, the laminate 600 is also formed by the same method as the laminate 500.

[0369] <Summary of the ninth embodiment> In this embodiment, the side surface of the laminate 500, 600 has a first inclined portion 501, 601 and a second inclined portion 502, 602. That is, the side surface has a curved shape (approximately V-shaped). As a result, even if peeling that occurs in the sealing body 30 starting from the interface with the exposed surface 53b, 63b progresses along the second inclined portion 502, 602, the curved shape can suppress the progress to the first inclined portion 501, 601. Therefore, it is possible to suppress the progress of peeling to the front surface metal body 52, 62, the semiconductor element 40, and the joint between the front surface metal body 52, 62 and the semiconductor element 40, etc. In other words, it is possible to suppress the concentration of thermal stress on the front surface metal body 52, 62, the semiconductor element 40, etc., and the like, and the decrease in connection reliability, etc. can be suppressed. Therefore, reliability can be ensured.

[0370] Since the second inclined portions 502, 602 are provided, it is also possible to prevent the back surface metal bodies 53, 63 from falling off (falling off) from the sealing body 30 when the above-mentioned peeling occurs.

[0371] Ideally, heat spreads at an angle of 45 degrees. In this embodiment, the stack 500, 600 has the first inclined portion 501, 601 on the semiconductor element 40 side in the Z direction. This allows the heat generated by the semiconductor element 40 to diffuse above the bent portion, that is, in the portion corresponding to the first inclined portion 501, 601. On the other hand, by having the second inclined portion 502, 602, the heat transfer path of the portion corresponding to the second inclined portion 502, 602 is narrower than the heat transfer path of the portion corresponding to the first inclined portion 501, 601. The narrow heat transfer path increases the thermal resistance. In this embodiment, the length L12 of the second inclined portion 502, 602 is made shorter than the length L11 of the first inclined portion 501, 601 (L11>L12). This allows the length L22 of the second inclined portions 502, 602 in the Z direction to be shorter than in a configuration that satisfies L11≦L12, and thus allows the thermal resistance below the bent portion to be reduced. In other words, the heat diffused in the upper portion of the laminates 500, 600 can be efficiently dissipated from the exposed surfaces 53b, 63b. As a result, the semiconductor device 20 of this embodiment can ensure reliability while improving heat dissipation.

[0372] The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided on the back metal body 53, 63. The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided across the insulating substrate 51, 61 and the back metal body 53, 63. In this embodiment, the first inclined portions 501, 601 are provided across the insulating substrate 51, 61 and the back metal body 53, 63, and the second inclined portions 502, 602 are provided on the back metal body 53, 63. That is, the bent portion exists in the back metal body 53, 63. Therefore, even if peeling that occurs in the sealing body 30 starts from the interface with the exposed surface 53b, 63b and progresses along the second inclined portions 502, 602, the peeling can be prevented from progressing to the interface with the insulating substrate 51, 61. This makes it possible to prevent the thermal stress from concentrating on the insulating base materials 51 and 61 and to prevent a decrease in the insulation reliability, which in turn makes it possible to further improve the reliability.

[0373] The first inclined portions 501 and 601 and the second inclined portions 502 and 602 may be configured to be continuous. In the present embodiment, intermediate portions 503 and 603 are provided between the first inclined portions 501 and 601 and the second inclined portions 502 and 602. In this configuration, the intermediate portions 503 and 603 form bent portions. By providing the intermediate portions 503 and 603, as described above, even when cutting (machining) simultaneously from both the front surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the back surface metal bodies 53 and 63, contact between the blades can be avoided. Further, since the intermediate portions 503 and 603 are provided on the back surface metal bodies 53 and 63, progress of peeling up to the interface with the insulating substrates 51 and 61 can be suppressed, as described above.

[0374] In a configuration in which the first inclined portions 501 and 601 are provided from the insulating substrates 51 and 61 to the back surface metal bodies 53 and 63, the inclination angle R1 of the back surface metal bodies 53 and 63 and the inclination angle R3 of the insulating substrates 51 and 61 may be made different. For example, when R1 < R3, since thermal stress concentrates at the ends of the insulating substrates 51 and 61 containing resin, there is a risk of deterioration of the insulation performance. When R1 > R3, thermal stress concentrates at the interface between the insulating substrates 51 and 61 and the back surface metal bodies 53 and 63, and there is a risk of interface peeling. In the present embodiment, the inclination angle R1 and the inclination angle R3 are made substantially equal (R1 = R3). That is, in the first inclined portions 501 and 601, the inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are substantially flush and continuous. The inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are continuous and form a single flat surface. Thereby, concentration of thermal stress at the triple point of the sealing body 30, the insulating substrates 51 and 61, and the back surface metal bodies 53 and 63 can be suppressed.

[0375] The inclination angles R4 of the second inclined portions 502 and 602 with respect to the exposed surfaces 53b and 63b may be set to be equal to or greater than the inclination angle R5 of the side surface 30e (second surface) with respect to the first surfaces 30a and 30b of the sealing body 30. In the present embodiment, the inclination angle R4 is made smaller than the inclination angle R5 (R4 < R5). As described in the previous embodiment (see, for example, FIG. 72), when the semiconductor element 40 generates heat, the semiconductor device 20 warps. As described above, when adopting a configuration that forms a warped shape with high heat dissipation, peeling is likely to occur at the interface between the back surface metal bodies 53 and 63 and the sealing body 30 due to the warp convex in the Z direction. By adopting a configuration that satisfies the relationship of R4 < R5, even if peeling occurs, it is possible to suppress the back surface metal bodies 53 and 63 from falling off from the sealing body 30.

[0376] In the present embodiment, the exposed portion 510 of the insulating base material 51 which is the first exposed portion and the exposed portion 610 of the insulating base material 61 which is the second exposed portion overlap each other in a plan view in the Z direction. Thereby, it is possible to suppress the imbalance in the arrangement of the surface metal body 52 of the substrate 50 which is the first substrate and the surface metal body 62 of the substrate 60 which is the second substrate, and thus suppress the imbalance in the warp of the semiconductor device 20. It is possible to suppress the occurrence of interface peeling between the back surface metal bodies 53 and 63 and the sealing body 30 on the side where the deformation is large due to the bias of the warp.

[0377] In the present embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a and 502a along the circumferential direction. By having the cutting marks 501a and 502a, an anchor effect is generated and the adhesion to the sealing body 30 is enhanced. Thereby, it is possible to suppress the peeling of the sealing body 30 from the laminated bodies 500 and 600. Note that cutting marks along the circumferential direction may be provided only on one of the first inclined portion 501 and the second inclined portion 502. In the present embodiment, since the intermediate portion 503 also has the uneven portion 503a, it is possible to expect suppression of peeling due to the anchor effect.

[0378] <Modification Example> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. It is also possible to apply the present invention to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the above-mentioned structure (V-cut shape) may be applied to only one of the substrates 50, 60.

[0379] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0380] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, and eighth embodiments, and the modified examples.

[0381] Tenth embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve the connection reliability, the sintered members, which are the joining materials, may be arranged in a predetermined manner as described in this embodiment.

[0382] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 89. Fig. 89 is a cross-sectional view corresponding to Fig. 5. In Fig. 89, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

[0383] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 89, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 that are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 that is the first wiring member is connected to the drain electrode 40D that is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 that is the second wiring member is connected to the source electrode 40S that is the second main electrode of the semiconductor element 40 via the conductive spacer 70 that is the second wiring member. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The source electrode 40S and the conductive spacer 70 are bonded by a sintered member 101A that is a bonding material 101.

[0384] <Semiconductor element> Next, the semiconductor element 40 will be described with reference to Fig. 90 and Fig. 91. Fig. 90 is a plan view showing the semiconductor element 40 (40H). Fig. 91 is an enlarged view of the region XCI in Fig. 89. Fig. 91 is a cross-sectional view corresponding to the line XCI-XCI in Fig. 90. Although Fig. 91 illustrates the semiconductor element 40H, the semiconductor element 40L also has a similar configuration, and therefore will be described below as the semiconductor element 40.

[0385] As described above, the semiconductor element 40 has a semiconductor substrate 41 on which a switching element is formed. The semiconductor substrate 41 has a generally rectangular shape in plan view. The drain electrode is provided on one surface of the semiconductor substrate 41, and the source electrode 40S and the pad 40P are provided on the rear surface of the semiconductor substrate 41. The source electrode 40S has a multi-layer structure. The source electrode 40S has a base electrode 42 and a connection electrode 43. The pad 40P has the same configuration as the source electrode 40S.

[0386] The semiconductor element 40 further has a protective film 44. The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral portion of the source electrode 40S. For example, polyimide, silicon nitride film, or the like can be used as the material of the insulating film. The protective film 44 has an opening 440 that defines a connection region of the source electrode 40S. The opening 440 exposes the source electrode 40S so as to be bondable. The protective film 44 has an opening 441 that defines a connection region of the pad 40P. The openings 440 and 441 are both through holes that penetrate the protective film 44 in the Z direction. A portion of the source electrode 40S (connection electrode 43) that is exposed from the opening 440 of the protective film 44 forms a bond between the sintered member 101A and the source electrode 40S.

[0387] The protective film 44 in this embodiment is made of polyimide. The protective film 44 covers a peripheral portion 420 of the base electrode 42, which will be described later. The protective film 44 is not provided in a scribe region that is a predetermined range from the outer circumferential edge of the semiconductor substrate 41, for example. The opening shape of the opening 440, i.e., an inner circumferential surface 442 of the protective film 44 that defines the opening 440, has a substantially rectangular shape in plan view. The inner circumferential surface 442 may be referred to as the inner circumferential edge or the opening edge.

[0388] The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the source electrode 40S having a multi-layer structure. The base electrode 42 may be referred to as a lower electrode, a lower layer electrode, a wiring electrode, a base layer, a first metal layer, etc. The base electrode 42 is connected to the rear surface of the semiconductor substrate 41. The base electrode 42 is formed using a material containing Al (aluminum) as a main component, for example. In this embodiment, an AlSi-based alloy such as AlSi or AlSiCu is used as the material.

[0389] In a plan view, the base electrode 42 includes an element region (active region) (not shown) of the semiconductor substrate 41 and extends onto an outer peripheral region surrounding the element region. A peripheral portion 420 of the base electrode 42 has a generally rectangular ring shape in plan view. The peripheral portion 420 is covered with a protective film 44.

[0390] The connection electrode 43 is disposed on the base electrode 42. The connection electrode 43 is also referred to as an upper electrode, an upper electrode, an upper layer electrode, an upper layer, or a second metal layer. The connection electrode 43 contains at least a precious metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101A. The connection electrode 43 may contain a base metal in addition to the precious metal.

[0391] The connection electrode 43 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy constituting the base electrode 42. The connection electrode 43 contains Ni and a precious metal, such as Au or Ag. The connection electrode 43 is formed in multiple layers by, for example, a plating method. At least a part of the precious metal of the connection electrode 43 diffuses into the sintered member 101A during joining.

[0392] The connection electrode 43 is disposed in an opening 440 of the protective film 44, stacked on the base electrode 42. The outer circumferential end of the connection electrode 43 is in contact with an inner circumferential surface 442 of the protective film 44 along its entire periphery.

[0393] <Joining structure> Next, the joining structure of the semiconductor element 40 will be described with reference to Figs. 90 to 92. In Fig. 90, the outer peripheral edge of the sintered member 101A is indicated by a dashed line, and the outer peripheral edge of the conductive spacer 70 is indicated by a two-dot chain line. Fig. 92 is a cross-sectional view showing the arrangement of the sintered member 101A. Fig. 92 corresponds to Fig. 91. In the following, "inside" and "outside" indicate the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

[0394] In this embodiment, the substrate 60 and the conductive spacer 70 are a wiring member (second wiring member) electrically connected to the source electrode 40S. As shown in Fig. 90 and Fig. 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer 70. The sintered member 101A joins the source electrode 40S and the conductive spacer 70.

[0395] The sintered member 101A is made of Ag or Cu. The sintered member 101A is a sintered body made of Ag particles or Cu particles. The sintered member 101A can be bonded at a lower temperature than solder. As shown in FIG. 92, the sintered member 101A is disposed with a predetermined distance L30 between it and the inner peripheral surface 442 of the protective film 44. As shown in FIGS. 90 to 92, the sintered member 101A is disposed inside the inner peripheral surface 442. The sintered member 101A has, for example, a substantially rectangular shape in plan view. The outer peripheral end of the sintered member 101A is not in contact with the protective film 44 all around. That is, the inner peripheral surface 442 of the protective film 44 includes the sintered member 101A in plan view.

[0396] The conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101A. The metal film contains at least a precious metal, similar to the connection electrode 43. In this embodiment, the metal film is a plating film containing Ni and a precious metal, for example, Au or Ag.

[0397] As shown in Figs. 90 to 92, the conductive spacer 70 is disposed inside the inner peripheral surface 442. The conductive spacer 70 has, for example, a substantially rectangular shape in plan view. The outer peripheral end of the conductive spacer 70 is disposed outside the outer peripheral end of the sintered member 101A in plan view or so as to be substantially aligned with the outer peripheral end of the sintered member 101A in plan view. In other words, the conductive spacer 70 is disposed so as to include the sintered member 101A or so as to be substantially aligned with the sintered member 101A in plan view. In this embodiment, the conductive spacer 70 includes the sintered member 101A.

[0398] <Joining method> Next, a method for forming the above-mentioned joint structure, that is, a joining method, will be described with reference to Fig. 93. Fig. 93 is a cross-sectional view showing the joining method. Fig. 93 corresponds to Fig. 91.

[0399] In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 may be referred to as a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in FIG. 93, the sintered sheet 105 is placed on the source electrode 40S (connection electrode 43) of the semiconductor element 40. The sintered sheet 105 has a predetermined size that does not contact the protective film 44 in a plan view.

[0400] Next, the conductive spacer 70 is placed on the sintered sheet 105. Then, while heating, pressure is applied from the conductive spacer 70 side by a pressure device (not shown). As a result, the sintered sheet 105 is pressed and spread between the opposing surfaces of the connection electrode 43 and the conductive spacer 70 to reduce its thickness, and is sintered to become the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A has the above-mentioned predetermined positional relationship with the inner circumferential surface 442 of the protective film 44 and the conductive spacer 70.

[0401] <Simulation results> Fig. 94 shows the results of a thermal stress simulation. In this simulation, the strain amplitude generated in base electrode 42 was measured in a power cycle test in which room temperature and 150°C were alternately repeated. Fig. 94 shows the relationship between distance L30 and strain amplitude. In Fig. 94, distance L30 of 0 (zero) is a position that coincides with inner circumferential surface 442 of protective film 44 in a plan view. Negative values ​​for distance L30 indicate the distance inward from inner circumferential surface 442, and positive values ​​indicate the distance outward.

[0402] 94, it has been revealed that when the distance L30 is 5 μm or more, the distortion amplitude generated in the base electrode 42 becomes almost 0 (zero). Based on this finding, in the present embodiment, the predetermined distance L30 is set to 5 μm.

[0403] <Summary of the Tenth Embodiment> FIG. 95 shows a connection structure using solder 101B as the bonding material 101. FIG. 95 corresponds to FIG. 93. In the case of solder 101B, the solder 101B is reflowed to perform bonding. During bonding, the molten solder 101B wets and spreads over the surface of the connection electrode 43. Therefore, as shown by the dashed line in FIG. 95, a triple junction is formed between the sealing body 30, the source electrode 40S (connection electrode 43), and the solder 101B (bonding material 101). Thermal stress is concentrated at the triple junction due to the difference in linear expansion coefficient. The thermal stress is concentrated in the base electrode 42, directly below the outer circumferential end of the connection electrode 43. Therefore, there is a risk that cracks will occur in the base electrode 42, and ultimately damage will occur in the semiconductor substrate 41.

[0404] In this embodiment, a sintered member 101A is used instead of the solder 101B. The sintered member 101A is formed by heating at a temperature lower than the melting point. The sintered member 101A does not become molten during bonding, unlike the solder 101B. The sintered member 101A has lower wettability with respect to the connection electrodes 43 and the conductive spacer 70 than the solder 101B. Therefore, the sintered member 101A does not wet and spread over the surfaces of the connection electrodes 43 and the conductive spacer 70 during bonding, unlike the solder 101B.

[0405] The sintered member 101A can be easily held in a predetermined position and can be disposed with a predetermined distance L30 between it and the inner peripheral surface 442 of the protective film 44. This prevents a triple point between the sealing body 30, the source electrode 40S (connection electrode 43), and the sintered member 101A (bonding material 101) from being formed. This makes it possible to provide a semiconductor device 20 that is suppressed from concentrating thermal stress and has high connection reliability. In addition, the sintered member 101A has a higher thermal conductivity than the solder 101B. This also makes it possible to improve heat dissipation.

[0406] The distance L30 is not particularly limited. The sintered member 101A only needs to be spaced apart from the inner peripheral surface 442. In this embodiment, the distance L30 between the sintered member 101A and the inner peripheral surface 442 of the protective film 44 is set to 5 μm or more. This makes it possible to effectively reduce the distortion amplitude of the base electrode 42 due to thermal stress. In other words, the connection reliability can be further improved.

[0407] In plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, the sintered member 101A may protrude from the conductive spacer 70 in plan view. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles by heating and pressurizing. The portion protruding from the conductive spacer 70 is not pressurized, and therefore may remain unsintered and may fall off as a conductive foreign body. In other words, there is a risk of a short circuit or the like occurring.

[0408] In this embodiment, in plan view, the inner circumferential surface 442 of the protective film 44 contains the conductive spacer 70, and the conductive spacer 70 coincides with or contains the sintered component 101A. This allows pressure to be applied to the entire area of ​​the sintered component 101A (sintered sheet 105) before sintering via the conductive spacer 70. Therefore, it is possible to prevent contact between the sintered component 101A and the protective film 44 and to suppress the occurrence of unsintered parts.

[0409] <Modification> Although the sintered sheet 105 is used to form the sintered member 101A, the present invention is not limited to this. For example, a sintering paste having Ag particles or Cu particles dispersed in a solvent may be used. The sintered sheet 105 is easier to hold in place than the sintering paste.

[0410] Although an example has been shown in which the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, the present invention is not limited to this. Instead of the conductive spacer 70, a convex portion may be provided on the front surface metal body 62. In other words, the second wiring member may be configured to include only the substrate 60 without including the conductive spacer 70. In this case, the sintered member 101A is interposed between the tip face of the convex portion of the front surface metal body 62 and the source electrode 40S (connection electrode 43).

[0411] Although a substrate 50 has been shown as an example of the first wiring member, the present invention is not limited to this. A metal plate (lead frame) may be used instead of the substrate 50. Although a substrate 60 has been shown as an example of the second wiring member, the present invention is not limited to this. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and a conductive spacer 70, or a convex portion may be provided on a metal plate instead of the conductive spacer 70.

[0412] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0413] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth embodiments, and the modified examples.

[0414] Eleventh embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation, a sintered member may be used at the joint between the main electrode and the wiring member, as described in this embodiment.

[0415] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 96. Fig. 96 is a cross-sectional view corresponding to Fig. 5. In Fig. 96, for the sake of convenience, the external connection terminals 90 are omitted from illustration.

[0416] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see Figs. 2 to 13). As shown in Fig. 96, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 that are wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D that is the first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S that is the second main electrode of the semiconductor element 40 via a conductive spacer 70. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The drain electrode 40D and the surface metal body 52 of the substrate 50 are bonded to each other by a sintered member 100A that is a bonding material 100.

[0417] <Arrangement of sintered parts and uneven oxide film> Next, the arrangement of the sintered member 100A and the uneven oxide film 520 relative to the semiconductor element 40 will be described with reference to Figs. 97 to 99. Fig. 97 is an enlarged view of region XCVII in Fig. 96. Fig. 98 is a plan view showing the positional relationship between the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. Fig. 99 is an enlarged view of region XCVIX in Fig. 97.

[0418] 97 and 98, the upper surface 52a of the front metal body 52 has a mounting portion 529a, an outer periphery 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer periphery 529b and the intermediate portion 529c.

[0419] The mounting portion 529a includes a portion overlapping with the semiconductor element 40 (drain electrode 40D) in a plan view in the Z direction, and is a portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b includes a portion outside the outer peripheral end 402 of the semiconductor element 40 in a plan view, and is a portion surrounding the semiconductor element 40. The intermediate portion 529c is a portion between the mounting portion 529a and the outer peripheral portion 529b, and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a approximately coincides with the semiconductor element 40 (drain electrode 40D) in a plan view. The intermediate portion 529c has a substantially rectangular ring shape in a plan view, and the inner peripheral end of the intermediate portion 529c approximately coincides with the outer peripheral end 402 of the semiconductor element 40. The entire intermediate portion 529c is located outside the semiconductor element 40 in a plan view.

[0420] 97 to 99, similar to the configuration described in the preceding embodiment (see FIGS. 67 and 74), the front surface metal body 52 of the substrate 50 has an uneven oxide film 520. As shown in FIG. 99, the front surface metal body 52 has a base material 521, and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521.

[0421] The metal film 522 of this embodiment has an undercoat film mainly made of Ni and an upper layer mainly made of a precious metal capable of bonding to the sintered member 100A, such as Au or Ag. Specifically, a Ni plating film containing P and an Au plating film are adopted as the undercoat film. A plurality of recesses 523 are formed in the outer peripheral portion 529b of the upper surface 52a of the metal film 522. The recesses 523 are not formed in the mounting portion 529a and the intermediate portion 529c. In the portion where the recesses 523 are not formed, the film thickness of the metal film 522 is, for example, about 10 μm. That is, the film thickness before the irradiation of the laser light is about 10 μm. The recesses 523 are formed by irradiation of a pulsed laser light. One recess 523 is formed for each pulse. In the outer peripheral portion 529b, the surface of the metal film 522 is scale-like due to the plurality of recesses 523. The outer peripheral portion 529b is an area to be irradiated with laser light, and the mounting portion 529a and the intermediate portion 529c are areas not to be irradiated with laser light.

[0422] The uneven oxide film 520 is formed on the metal film 522. The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and the intermediate portion 529c which are the portions surrounding the mounting portion 529a. As described in the preceding embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with a laser beam. The uneven oxide film 520 is a laser irradiated film formed by irradiating the laser beam. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522.

[0423] In the outer peripheral portion 529b, that is, the area irradiated with the laser light, the average thickness of the uneven oxide film 520 is 10 nm to several hundreds of nm. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. Furthermore, the unevenness is formed on the surface of the uneven oxide film 520 at a pitch finer than the width of the recesses 523. That is, very fine unevenness (roughened portion) is formed. In other words, a plurality of protrusions 520a (columnar bodies) are formed at a fine pitch. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average interval between the protrusions 520a is 1 nm to 300 nm. Furthermore, the average height of the protrusions 520a is 10 nm to several hundreds of nm.

[0424] The uneven oxide film 520 is formed by irradiating the metal film 522 with a laser beam and melting and depositing the surface layer of the metal film 522, and is therefore formed not only in the outer peripheral portion 529b, which is the area irradiated with the laser beam, but also in the periphery (vicinity) of the outer peripheral portion 529b. In this embodiment, the uneven oxide film 520 is formed over the entire intermediate portion 529c, which is an area not irradiated with the laser beam, and the uneven oxide film 520 is not formed on the mounting portion 529a. The width of the intermediate portion 529c having the uneven oxide film 520 over its entire area is, for example, 0.2 mm to 0.3 mm.

[0425] The average thickness of the uneven oxide film 520 in the intermediate portion 529c is thinner than the average thickness of the uneven oxide film 520 in the outer peripheral portion 529b and thicker than the natural oxide film because the intermediate portion 529c is not directly irradiated with laser light. Specifically, it is 0.1 nm to 10 nm. The height of the protrusions 520a on the surface of the uneven oxide film 520 is also lower than that of the outer peripheral portion 529b. Specifically, it is 0.1 nm to 10 nm. The average width and average interval of the protrusions 520a are approximately the same as those of the outer peripheral portion 529b.

[0426] In this way, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is a portion of the uneven oxide film 520 that is provided in the laser light irradiated area, i.e., the outer peripheral portion 529b. The thin film portion 520Y is a portion of the uneven oxide film 520 that is provided in the laser light non-irradiated area, i.e., the intermediate portion 529c. The thin film portion 520Y is thinner than the thick film portion 520X in thickness of the uneven oxide film 520, and the height of the convex portion 520a is lower. The thick film portion 520X is provided in the outer peripheral portion 529b. The thin film portion 520Y is provided in the intermediate portion 529c.

[0427] Since the protrusions 520a of the thick film portion 520X are higher than those of the thin film portion 520Y, the plug 30 is entangled therewith, and an anchor effect is generated. In addition, the contact area with the plug 30 increases. As a result, the plug 30 is in close contact with the outer periphery 529b. The thick film portion 520X may be referred to as a roughened portion or an intimate contact portion.

[0428] The sintered member 100A is made of Ag or Cu, similarly to the sintered member 101A described in the preceding embodiment. The sintered member 100A is a sintered body made of Ag particles or Cu particles. The sintered member 100A can be bonded at a lower temperature than solder. The sintered member 100A is formed by heating and pressing a sintered sheet or a sintered paste. The sintered member 100A protrudes outward from the outer peripheral end 402 of the semiconductor element 40 in a plan view. The sintered member 100A is disposed so as to overlap the mounting portion 529a and the intermediate portion 529c in a plan view. In this embodiment, the outer peripheral end of the sintered member 100A is substantially coincident with the outer peripheral end of the intermediate portion 529c. The sintered member 100A overlaps the entire area of ​​the mounting portion 529a and the entire area of ​​the intermediate portion 529c in a plan view.

[0429] <Summary of the eleventh embodiment> As described above, the intermediate portion 529c has the thin film portion 520Y of the uneven oxide film 520. Due to the presence of the thin film portion 520Y, the intermediate portion 529c has a lower wettability with solder than the mounting portion 529a. This makes it difficult for the solder to spread from the mounting portion 529a to the intermediate portion 529c.

[0430] In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than the melting point. The sintered member 100A does not become molten when joined, unlike solder. The sintered member 100A does not wet and spread over the surface of the surface metal body 52 when joined, unlike solder.

[0431] The sintered member 100A is expanded between the opposing surfaces of the drain electrode 40D and the surface metal body 52 during pressure sintering. By expanding, the sintered member 100A is disposed on not only the mounting portion 529a but also the intermediate portion 529c. The sintered member 100A does not wet and spread, but is expanded by pressure and contacts the thin film portion 520Y. As a result, not only the joint between the sintered member 100A and the mounting portion 529a, but also the contact portion between the sintered member 100A and the intermediate portion 529c functions as a heat dissipation path. As a result, a semiconductor device 20 with high heat dissipation properties can be provided. In addition, the sintered member 100A has a higher thermal conductivity than solder. This can also improve heat dissipation.

[0432] Moreover, the height of the convex portion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. That is, the adhesion of the intermediate portion 529c to the sealing body 30 is lower than that of the outer peripheral portion 529b. As a result, the sealing body 30 is less likely to adhere to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion of the upper surface 52a where the adhesion is low. Therefore, it is possible to suppress the sealing body 30 from peeling off from the upper surface 52a around (near) the semiconductor element 40. This suppresses the concentration of thermal stress on the joint portion of the sintered member 100A and the drain electrode 40D, and thus improves the connection reliability.

[0433] In this embodiment, the entire intermediate portion 529c is located outside the semiconductor element 40. This allows the joint between the sintered member 100A and the mounting portion 529a to be made larger. In addition, the contact portion between the sintered member 100A located outside the semiconductor element 40 and the intermediate portion 529c also functions as a heat dissipation path. This further improves heat dissipation.

[0434] <Modification> Although an example in which the sintered member 100A overlaps the entire intermediate portion 529c has been shown, this is not limiting. The sintered member 100A only needs to overlap at least a portion of the intermediate portion 529c. In other words, the sintered member 100A only needs to contact at least a portion of the thin film portion 520Y of the uneven oxide film 520. This can expand the heat dissipation path and improve the heat dissipation performance.

[0435] The arrangement of the intermediate portion 529c is not limited to the above example. Only a portion of the intermediate portion 529c in the width direction may be located outside the semiconductor element 40. By providing at least a portion of the intermediate portion 529c in the width direction outside the semiconductor element 40, the joint portion can be enlarged and the heat dissipation path can be enlarged. Therefore, the heat dissipation performance can be improved.

[0436] Furthermore, at least a portion of the intermediate portion 529c in the width direction may be located inside the outer circumferential end 402 of the semiconductor element 40. With this, the sintered member 100A comes into contact with the thin film portion 520Y (intermediate portion 529c), thereby improving heat dissipation, and the position of the outer circumferential portion 529b can be brought closer to the semiconductor element 40. In other words, peeling of the sealing body 30 around the semiconductor element 40 can be suppressed.

[0437] In the example shown in Fig. 100 and Fig. 101, the intermediate portion 529c straddles the outer peripheral end 402 of the semiconductor element 40 in a plan view. That is, a part of the intermediate portion 529c in the width direction is located outside the outer peripheral end 402, and another part is located inside the outer peripheral end 402. The sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c in a plan view. As a result, as described above, it is possible to improve heat dissipation and prevent peeling of the sealing body 30 around the semiconductor element 40. Fig. 100 and Fig. 101 are diagrams showing modified examples. Fig. 100 corresponds to Fig. 97, and Fig. 101 corresponds to Fig. 98.

[0438] In the example shown in Fig. 102 and Fig. 103, the outer peripheral end of the intermediate portion 529c is approximately aligned with the outer peripheral end 402 of the semiconductor element 40 in plan view. The outer peripheral end of the sintered member 100A is also approximately aligned with the outer peripheral end 402 of the semiconductor element 40 in plan view. This allows the outer peripheral portion 529b (thick film portion 520X) to be located adjacent to the semiconductor element 40 in plan view. Therefore, the contact of the sintered member 100A with the intermediate portion 529c can enhance heat dissipation, while more effectively suppressing peeling of the sealing body 30 around the semiconductor element 40. Fig. 102 and Fig. 103 are diagrams showing modified examples. Fig. 102 corresponds to Fig. 97, and Fig. 103 corresponds to Fig. 98.

[0439] In the example shown in FIG. 104, a part of the outer peripheral portion 529b overlaps with the semiconductor element 40 in a plan view. The middle portion 529c is located inside the outer peripheral end 402 of the semiconductor element 40. FIG. 104 is a diagram showing a modified example. FIG. 104 corresponds to FIG. 98. In this case, the sintered member 100A may be in contact with only the thin film portion 520Y. The sintered member 100A may be in contact with the thin film portion 520Y and the portion of the thick film portion 520X directly below the semiconductor element 40.

[0440] Although an example in which the uneven oxide film 520 is provided only on the front metal body 52 to which the drain electrode 40D is connected has been shown, the present invention is not limited to this. In addition to the front metal body 52, the uneven oxide film 520 may be provided on the side of the conductive spacer 70 to which the source electrode 40S is connected and / or on the front metal body 62 of the substrate 60. As described above, the thick film portion 520X of the uneven oxide film 520 provides a function of increasing the adhesion to the sealing body 30 and a function of suppressing the spreading of the solder, which is a bonding material. The uneven oxide film 520 may be provided in a place where it is desired to suppress the overflow of the solder or to increase the adhesion to the sealing body 30.

[0441] Although the substrate 50 is shown as an example of the wiring member, the present invention is not limited to this. A metal plate (lead frame) may be used instead of the substrate 50. Also, a metal plate (lead frame) may be used instead of the substrate 60. Instead of the conductive spacer 70, a protrusion may be provided on the metal plate on the source electrode 40S side.

[0442] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include only one semiconductor element 40, for example.

[0443] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth embodiments, and the modified examples.

[0444] Twelfth embodiment This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to suppress cracks occurring in the main electrode, the sintered member, which is the bonding material, may have a multi-layer structure as described in this embodiment.

[0445] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 105. Fig. 105 is a cross-sectional view corresponding to (a part of) Fig. 7. For convenience, the external connection terminals 90 and ...

Claims

[Claim 1] A semiconductor device constituting an upper and lower arm circuit (9), A semiconductor element (40) having main electrodes (40D, 40S) on both sides; a substrate (50, 60) having an insulating base material (51, 61), a front surface metal body (52, 62) disposed on a front surface of the insulating base material and electrically connected to the main electrode, and a back surface metal body (53, 63) disposed on a back surface of the insulating base material, The surface metal body has a first wiring (64) extending in a predetermined direction, and a second wiring (65) having a different potential from the first wiring and extending in the predetermined direction with a predetermined interval between the first wiring, The first wiring and the second wiring have currents flowing in opposite directions along the predetermined direction, a distance between the first wiring and the second wiring being equal to or smaller than a thickness of the front surface metal body.

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