Method for forming wiring pattern

Abstract

To improve throughput in wiring pattern formation of FO-WLP.SOLUTION: A method for forming a wiring pattern includes: performing a position measurement being measurement of respective positions of a plurality of chips contained in a first substrate disposed on a first tray, and respective positions of a plurality of chips contained in a second substrate disposed on the first tray; and performing data creation being creation of first pattern data being pattern data on wiring for connecting the plurality of chips contained in the first substrate on the basis of the respective positions of the plurality of chips contained in the first substrate, and second pattern data being pattern data on wiring for connecting the plurality of chips contained in the second substrate on the basis of the respective positions of the plurality of chips contained in the second substrate, where the data creation starts in a time period for performing the position measurement.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a method for forming a wiring pattern. [Background technology]

[0002] In recent years, semiconductor device packages called Fan Out Wafer Level Package (FO-WLP) and Fan Out Plate Level Package (FO-PLP) have become known.

[0003] For example, in the manufacture of FO-WLPs, multiple semiconductor chips are arranged on a wafer-shaped support substrate and then solidified with a molding material such as resin to form a pseudo-wafer, and an exposure device is used to form a rewiring layer that connects the pads of the semiconductor chips.

[0004] There is a demand for an improvement in throughput in forming redistribution layers in FO-WLP and FO-PLP (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-081281 A Summary of the Invention

[0006] According to an aspect of the disclosure, there is provided an exposure apparatus comprising: a spatial light modulator; a creation unit that acquires measurement results from a measurement system that measures the positions of the semiconductor chips included in each of a set of semiconductor chips arranged on a first substrate, determines a wiring pattern connecting the semiconductor chips included in each of the sets based on the measurement results, creates first control data to be used for controlling the spatial light modulator when generating the determined wiring pattern, and stores the first control data in a first memory unit; and an exposure processing unit that controls the spatial light modulator using the first control data stored in the first memory unit to expose a wiring pattern connecting the semiconductor chips included in each of the sets, wherein at least one of measuring the positions of the semiconductor chips on the first substrate, acquiring the measurement results, determining the wiring pattern, creating the first control data, and storing the first control data in the first memory unit is performed while the exposure processing unit is exposing a second substrate different from the first substrate.

[0007] According to an aspect of the disclosure, a wiring pattern forming method includes performing position measurement, which is measuring the position of each of a plurality of chips included in a first substrate arranged on a first tray, and the position of each of a plurality of chips included in a second substrate arranged on the first tray, and performing data creation, which is creating first pattern data, which is pattern data of wiring connecting the plurality of chips included in the first substrate based on the position of each of the plurality of chips included in the first substrate, and second pattern data, which is pattern data of wiring connecting the plurality of chips included in the second substrate based on the position of each of the plurality of chips included in the second substrate, wherein the data creation is started during a period in which the position measurement is performed.

[0008] The configurations of the embodiments described below may be appropriately improved, and at least a part of them may be replaced with other components. Furthermore, components that are not particularly limited in terms of their location may be located in any location that achieves their function, not limited to the location disclosed in the embodiments. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a top view showing an overview of a wiring pattern forming system for a FO-WLP including an exposure apparatus according to a first embodiment. [Diagram 2] FIG. 2 is a perspective view that shows roughly the configuration of the exposure apparatus according to the first embodiment. [Diagram 3] 3A and 3B are diagrams for explaining the wiring pattern formed by the wiring pattern forming system. [Figure 4] FIG. 4 is a diagram for explaining the module arranged on the optical base. [Diagram 5] Figure 5(A) is a diagram showing the optical system of the illumination and projection module, Figure 5(B) is a diagram showing the DMD generally, Figure 5(C) is a diagram showing the DMD when the power is OFF, Figure 5(D) is a diagram explaining the mirror in the ON state, and Figure 5(E) is a diagram explaining the mirror in the OFF state. [Figure 6] Figure 6 is an enlarged view of the illumination and projection module and its surroundings. [Figure 7] FIG. 7 is a block diagram showing a control system of the exposure apparatus according to the first embodiment. [Figure 8] FIG. 8A is a schematic diagram showing a wafer WF in which all chips are arranged in their designed positions, and FIG. 8B is a schematic diagram showing a wafer WF in which chips are arranged deviated from their designed positions. [Figure 9] FIG. 9 is a conceptual diagram showing a procedure for forming a wiring pattern on a FO-WLP in an exposure apparatus. [Figure 10] FIG. 10 is a top view showing an overview of a wiring pattern forming system according to the second embodiment. [Figure 11] FIG. 11 is a conceptual diagram of a manufacturing procedure for the FO-WLP in the second embodiment. [Figure 12] FIG. 12 is a top view showing an overview of a wiring pattern forming system according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] First Embodiment An exposure apparatus according to the first embodiment will be described with reference to FIGS. 1 to 9. In the following description, when simply referring to a substrate P, it refers to a rectangular substrate, and a wafer-shaped substrate is referred to as a wafer WF. In addition, the normal direction of the substrate P or wafer WF placed on a substrate stage 30 described later is referred to as a Z-axis direction, the direction in which the substrate P or wafer WF is relatively scanned with respect to a spatial light modulator (SLM: Spatial Light Modulator) in a plane perpendicular to the Z-axis direction is referred to as an X-axis direction, the direction perpendicular to the Z-axis and Y-axis is referred to as a Y-axis direction, and the directions of rotation (tilt) around the X-axis, Y-axis, and Z-axis are respectively referred to as θx, θy, and θz directions. Examples of the spatial light modulator include a liquid crystal element, a digital mirror device (digital micromirror device, DMD), and a magneto-optic spatial light modulator (MOSLM: Magneto Optic Spatial Light Modulator). The exposure apparatus EX according to the first embodiment includes a DMD 204 as a spatial light modulator, but may include other spatial light modulators.

[0011] Fig. 1 is a top view showing an overview of a wiring pattern forming system 500 for FO-WLPs and FO-PLPs, including an exposure apparatus EX according to an embodiment of the present invention. Fig. 2 is a perspective view showing a schematic configuration of the exposure apparatus EX.

[0012] The wiring pattern forming system 500 is a system for forming wiring patterns that connect between semiconductor chips (hereinafter referred to as chips) arranged on a wafer WF, as shown in FIG. 3(A), or between chips arranged on a substrate P, as shown in FIG. 3(B).

[0013] In this embodiment, a wiring pattern is formed that connects between chips C1 and C2 included in each set (indicated by two-dot chain lines) of chips arranged on the wafer WF or substrate P. Note that, in this embodiment, the number of chips included in each set is two, but this is not limited to this and may be three or more.

[0014] In the following, a case will be described where a wiring pattern for connecting between chips arranged on a wafer WF is formed.

[0015] As shown in FIG. 1, a wiring pattern forming system 500 includes a coater developer apparatus CD and an exposure apparatus EX.

[0016] The coater developer device CD applies a photosensitive resist to the wafer WF. The wafer WF coated with the resist is carried into a buffer unit PB that can store a plurality of wafers WF. The buffer unit PB also serves as a transfer port for the wafer WF.

[0017] More specifically, the buffer section PB is composed of an input section and an output section. Wafers WF coated with resist are loaded one by one from the coater developer device CD into the input section. The resist-coated wafers WF are loaded one by one from the coater developer device CD into the input section at a predetermined time interval, but since multiple wafers are loaded together on a tray TR (described later), the input section functions as a buffer for storing the wafers WF.

[0018] The unloading section also functions as a buffer when unloading the exposed wafers WF to the coater-developer device CD. The coater-developer device CD can only unload exposed wafers WF one by one. Therefore, a tray TR on which multiple exposed wafers WF are mounted is placed in the unloading section. This allows the coater-developer device CD to unload the exposed wafers WF one by one from the tray TR.

[0019] The exposure apparatus EX is made up of a main body 1 and a substrate exchange unit 2. As shown in Fig. 1, a robot RB is installed in the substrate exchange unit 2. The robot RB arranges a plurality of wafers WF placed in a buffer unit PB on one tray TR.

[0020] 1 and 2, in the first embodiment, 4 wafers WF in 3 rows can be placed on the substrate stages 30R and 30L described below. The tray TR according to the first embodiment is a lattice-shaped tray that can sequentially place 4 wafers WF in 1 row on the substrate stages 30R and 30L. The tray TR may be a tray that can place the wafers WF all over the entire surface of the substrate stages 30R and 30L at once (i.e., a tray that can arrange 4 wafers WF in 3 rows).

[0021] 2, the substrate exchange unit 2 includes exchange arms 20R and 20L. The exchange arm 20R loads and unloads a wafer WF (more specifically, a tray TR on which a plurality of wafers WF are placed) onto and from a substrate holder PH of the substrate stage 30R, and the exchange arm 20L loads and unloads a wafer WF onto and from the substrate holder PH of the substrate stage 30L. In the following description, when there is no need to distinguish between the exchange arms 20R and 20L, they will be referred to as exchange arm 20. In addition, the substrate holder PH is not shown in any figures other than FIG. 2.

[0022] Generally, the exchange arms 20R and 20L are provided with two arms, a carry-in arm for carrying in the tray TR and a carry-out arm for carrying out the tray TR. This allows the tray TR to be exchanged at high speed. When carrying in the wafer WF, the lattice-shaped tray TR is supported by the substrate exchange pins 10. When the substrate exchange pins 10 are lowered, the tray TR sinks into a groove (not shown) formed in the substrate stage 30, and the wafer WF is attracted and held by the substrate holder PH on the substrate stage 30. When a row of substrates is placed on the tray TR as shown in FIG. 2, the positions of the substrate stages 30R and 30L or the positions of the exchange arms 20R and 20L are changed according to the positions where the trays TR are placed on the substrate stages 30R and 30L.

[0023] When the wafer WF is attracted to the substrate holder PH, the position of the alignment marks or wiring pads of the wafer WF is measured by the alignment system ALG-R or ALG-L mounted on the optical table 110. Usually, the position of each wafer WF is measured by determining the number and arrangement of measurement points so that six parameters of the wafer WF placed on the substrate holder PH can be calculated: X-direction shift (X), Y-direction shift (Y), rotation (Rot), X-direction magnification (X_Mag), Y-direction magnification (Y_Mag), and orthogonality (Oth).

[0024] As shown in FIG. 4, a plurality of illumination and projection modules 200, an autofocus system AF, and alignment systems ALG_R, ALG_L, and ALG_C are arranged on an optical base 110 that is kinematically supported on a column 100.

[0025] As shown in Fig. 2, in this embodiment, multiple rows (four rows in Fig. 2) are arranged, each row including a plurality of illumination and projection modules 200. Note that, for simplification, Fig. 1 illustrates only one row including a plurality of illumination and projection modules 200. Also, for simplification, alignment systems ALG_R and ALG_L are not illustrated in Fig. 2.

[0026] Note that a plurality of illumination and projection modules 200 may be provided so as to be able to expose wiring patterns in different sets at once, and the number of rows of illumination and projection modules 200 may be one to three rows, or five or more rows. The number of illumination and projection modules 200 included in each row may be two or more. When a plurality of wafers WF are placed on the substrate holder, the different sets exposed by the illumination and projection modules 200 at once may be different sets within the same wafer WF, or may be sets within different wafers WF.

[0027] 5A is a diagram showing the optical system of the illumination and projection module 200. The illumination and projection module 200 includes a collimator lens 201, a fly's eye lens 202, a main condenser lens 203, a DMD 204, and the like.

[0028] Laser light emitted from a light source LS is taken in by a delivery fiber FB into an illumination and projection module 200. The laser light passes through a collimator lens 201, a fly-eye lens 202, and a main condenser lens 203, and illuminates a DMD 204 almost uniformly.

[0029] Fig. 5(B) is a diagram showing a schematic view of the DMD 204, and Fig. 5(C) shows the DMD 204 when the power is OFF. Note that in Fig. 5(B) to Fig. 5(E), mirrors that are in the ON state are indicated by hatching.

[0030] The DMD 204 has a plurality of micromirrors 204a whose reflection angles can be changed. Each micromirror 204a is turned on by tilting around the Y axis. FIG. 5D shows a case where only the central micromirror 204a is turned on, and the other micromirrors 204a are in a neutral state (neither on nor off). Each micromirror 204a is turned off by tilting around the X axis. FIG. 5E shows a case where only the central micromirror 204a is turned off, and the other micromirrors 204a are in a neutral state. The DMD 204 generates an exposure pattern (hereinafter, referred to as a wiring pattern) of wiring connecting chips by switching between the on and off states of each micromirror 204a.

[0031] Illumination light reflected by a mirror in the OFF state is absorbed by an OFF light absorbing plate 205, as shown in Fig. 5(A). The illumination / projection module 200 has a magnification for projecting one pixel of the DMD 204 at a predetermined size, and the magnification can be slightly corrected by focusing by driving the lens in the Z axis and by driving some of the lenses. In addition, the DMD 204 itself can be driven in the X, Y, and θz directions, and, for example, a deviation from a target value of the substrate stage 30 is corrected.

[0032] In addition, since the DMD 204 has been described as an example of a spatial light modulator, it has been described as a reflective type that reflects laser light, but the spatial light modulator may be a transmissive type that transmits laser light, or a diffractive type that diffracts laser light. The spatial light modulator can modulate the laser light spatially and temporally.

[0033] 4, the autofocus system AF is disposed so as to sandwich the illumination / projection module 200. This allows measurement to be performed by the autofocus system AF before the exposure operation for forming the wiring pattern that connects between the chips arranged on the wafer WF, regardless of the scanning direction of the wafer WF.

[0034] Fig. 6 is an enlarged view of the vicinity of the illumination and projection module 200. As shown in Fig. 6, a fixed mirror 54 for measuring the position of the substrate stage 30 is provided near the illumination and projection module 200.

[0035] 6, an alignment device 60 is provided on the substrate stage 30. The alignment device 60 includes a reference mark 60a and a two-dimensional image sensor 60e. The alignment device 60 is used to measure and calibrate the positions of various modules, and is also used to calibrate alignment systems ALG_R, ALG_L, and ALG_C arranged on the optical base 110.

[0036] The position of each module is measured and calibrated by projecting a calibration DMD pattern onto the reference mark 60a of the alignment device 60 using the illumination and projection module 200, and measuring the relative position of the reference mark 60a and the DMD pattern.

[0037] Furthermore, the calibration of alignment systems ALG_R, ALG_L, and ALG_C can be performed by measuring the reference mark 60a of the alignment device 60 with the alignment systems ALG_R, ALG_L, and ALG_C. That is, by measuring the reference mark 60a of the alignment device 60 with the alignment systems ALG_R, ALG_L, and ALG_C, the positions of alignment systems ALG_R, ALG_L, and ALG_C can be obtained. Furthermore, the relative position with respect to the position of the module can be obtained by using the reference mark 60a.

[0038] The substrate stage 30 is also provided with a moving mirror MR, a DM monitor 70, and the like, which are used to measure the position of the substrate stage 30.

[0039] Alignment systems ALG_R and ALG_L are equipped with multiple measurement microscopes, and measure the position of a chip arranged on each wafer WF placed on the substrate holder of the substrate stage 30 or the position of a pad of a chip to be wired, using a reference mark 60a of the alignment device 60 as a reference. More specifically, alignment systems ALG_R and ALG_L measure the position of each chip based on the design position of each chip, using the reference mark 60a as a reference. The measurement results are output to a data creation device 300, which will be described later.

[0040] Before the start of exposure, the alignment system ALG_C measures the position of the wafer WF placed on the substrate holder of the substrate stage 30, using as a reference a reference mark 60a of the alignment device 60. Based on the measurement result of the alignment system ALG_C, the positional deviation of the wafer WF with respect to the substrate stage 30 is detected, and the exposure start position, etc. are changed.

[0041] 7 is a block diagram showing a control system 600 of the exposure apparatus EX according to this embodiment. As shown in FIG. 7, the control system 600 includes a data creating device 300, a first storage device 310R, a second storage device 310L, and an exposure control device 400.

[0042] The data creating device 300 receives from the alignment systems ALG_R and ALG_L the measurement results of the position of each chip or the position of the pads of each chip provided on the wafer WF placed on the substrate holder of the substrate stage 30. The data creating device 300 determines a wiring pattern connecting the chips based on the measurement results of the position of each chip, and creates control data to be used for controlling the DMD 204 when generating the determined wiring pattern. Next, the creation of the control data will be described in more detail.

[0043] FIG. 8(A) is a schematic diagram showing a wafer WF in a state where all chips are arranged at their designed positions (hereinafter, referred to as the design positions). As shown in FIG. 8(A), a wiring pattern WL connecting chips C1 and C2 is exposed (formed) by an exposure apparatus EX. Here, in the FO-WLP, the chips are solidified on the wafer WF with a molding material such as resin, so that the positions of the individual chips may be shifted from their designed positions, as shown in FIG. 8(B). In this case, if the DMD 204 is controlled to expose the wiring pattern using data (hereinafter, referred to as the design value data) showing the wiring pattern connecting chips at the designed positions, the wiring pattern may be shifted from the pad positions, resulting in poor connection or short circuit.

[0044] Therefore, in this embodiment, the position of each chip included in each set of chips arranged on the wafer WF is measured by the alignment system ALG_R or ALG_L. The data creating device 300 creates wiring pattern data by correcting a part of the design value data based on the measurement result acquired from the alignment system ALG_R or ALG_L.

[0045] The created wiring pattern data is stored in the first storage device 310R or the second storage device 310L. The first storage device 310R and the second storage device 310L are, for example, SSDs (Solid State Drives).

[0046] The first storage device 310R stores wiring pattern data used to control the DMD 204 when exposing the wafer WF placed on the substrate stage 30R. The second storage device 310L stores wiring pattern data used to control the DMD 204 when exposing the wafer WF placed on the substrate stage 30L. The wiring pattern data stored in the first storage device 310R or the second storage device 310L is transferred to the exposure control device 400.

[0047] Next, an example of a procedure for forming a wiring pattern of the FO-WLP in the exposure apparatus EX according to this embodiment will be described. Fig. 9 is a conceptual diagram of a procedure for forming a wiring pattern of the FO-WLP in the exposure apparatus EX.

[0048] 9, in this embodiment, for example, while the wafer WF on the substrate stage 30R is being exposed, the wafer WF is loaded onto the substrate stage 30L, and the alignment system ALG_L measures the chip position. Based on the measurement results of the chip position, the data creation device 300 sequentially creates wiring pattern data, and stores (transfers) the created wiring pattern data to the second storage device 310L. The wiring pattern data stored in the second storage device 310L is sequentially transferred to the exposure control device 400 in accordance with the start of exposure of the wafer WF on the substrate stage 30L.

[0049] In addition, when the wafers WF are arranged in one row of four on one tray TR as shown in FIG. 2, when four wafers WF are placed on one tray TR, the tray TR may be placed on the substrate stage 30L, and the alignment system ALG_L may start measuring the chip positions. In this case, the measurement of the chip positions by the alignment system ALG_L and the process of placing another wafer WF on the next tray TR can be performed in parallel. Then, in parallel with the process of placing the tray TR on which another wafer WF is arranged on the substrate stage 30L, the wiring pattern data of the wafer WF whose chip position has already been measured can be created based on the measurement result by the alignment system ALG_L and stored in the second storage device 310L. Such parallel processing is particularly effective when it takes time to create, transfer, and store the wiring pattern data. In addition, when the time required for measuring the chip position and creating and storing the wiring pattern data is shorter than the exposure time, for example, 4 wafers×3 rows of wafers WF may be placed on one tray TR, and then the wafers may be carried onto the substrate stage 30L and measured by the alignment system ALG_L. In addition, in the placement process, it is sufficient to perform either a placement operation for placing the wafer WF on the tray TR or a placement preparation operation for preparing to place the wafer WF on the tray TR.

[0050] On the other hand, when exposure of the wafer WF on the substrate stage 30L starts, the exposed wafer WF on the substrate stage 30R is removed, and then a new wafer WF is loaded onto the substrate stage 30R. Then, the alignment system ALG_R measures the chip position. Based on the measurement results of the chip position, the data creation device 300 sequentially creates wiring pattern data and transfers the created wiring pattern data to the first storage device 310R. The wiring pattern data stored in the first storage device 310R is sequentially transferred to the exposure control device 400 in accordance with the start of exposure of the wafer WF on the substrate stage 30R.

[0051] In this embodiment, while the exposure process is being performed using one of the two substrate stages 30R and 30L, the other substrate stage carries out the unloading of the exposed wafer, the loading of a new wafer, the measurement of the chip position, and the creation and transfer of wiring pattern data. In this way, by performing parallel processing using the two substrate stages 30R and 30L, the time required for the measurement of the chip position and the creation and transfer of wiring pattern data can be hidden in the time required for the exposure process. This can improve the throughput in the formation of the wiring pattern of the FO-WLP. The exposure process includes a series of operations from driving the substrate stage for exposure to driving the substrate stage to the substrate exchange position after the exposure is completed.

[0052] As described above in detail, the exposure apparatus EX according to the first embodiment includes a spatial light modulator (DMD 204 in the first embodiment), a data creating device 300, and an exposure control device 400. The exposure apparatus EX also includes a plurality of substrate stages 30R, 30L, and alignment systems ALG_R, ALG_L. The alignment system ALG_L measures the positions of the chips C1 and C2 included in each of the sets of semiconductor chips arranged on the wafer WF placed on the substrate stage 30L while a wiring pattern is exposed on the wafer WF placed on the substrate stage 30R. The data creating device 300 acquires the measurement result from the alignment system ALG_L, and determines the wiring pattern WL that connects between the chips C1 and C2 included in each of the sets of chips arranged on the wafer WF on the substrate stage 30L based on the measurement result. Then, the data creating device 300 creates wiring pattern data used for controlling the DMD 204 when generating the determined wiring pattern WL, and stores the data in the second storage device 310L. When the exposure process on the substrate stage 30R is completed, the exposure control device 400 uses the wiring pattern data stored in the second storage device 310L to control the DMD 204 to expose the wiring pattern WL connecting the chips C1 and C2 included in each set on the wafer WF placed on the substrate stage 30L. This makes it possible to measure the chip positions on the substrate placed on the substrate stage 30L and create and transfer wiring pattern data based on the measurement results while the wafer WF on the substrate stage 30R is being exposed. This allows time to be used effectively, improving the throughput in forming the wiring pattern of the FO-WLP.

[0053] Furthermore, in the first embodiment, a plurality of wafers WF are arranged on the substrate stages 30R, 30L of the exposure apparatus EX. This allows wiring patterns for connecting semiconductor chips to each other to be formed on a plurality of wafers WF, thereby improving the throughput in forming the wiring patterns of the FO-WLP.

[0054] Furthermore, in the first embodiment, the exposure apparatus EX includes a plurality of exchange arms 20R, 20L that exchange the wafer WF held by each of the substrate stages 30R, 30L. For example, while the wafer WF on the substrate stage 30R is being exposed, the exchange arm 20L exchanges the wafer WF on the substrate stage 30L. This allows time to be used effectively, thereby improving the throughput in forming the wiring pattern of the FO-WLP.

[0055] Furthermore, in the first embodiment, the exposure apparatus EX includes a plurality of DMDs 204, and each of the plurality of DMDs 204 forms a wiring pattern that connects between semiconductor chips in different sets. This makes it possible to simultaneously form wiring patterns that connect between semiconductor chips in different sets, thereby improving the throughput in forming the wiring pattern of the FO-WLP.

[0056] In the first embodiment, while an exposure process is being performed using one of the two substrate stages 30R and 30L, the other substrate stage carries out an exposed wafer, carries in a new wafer, measures the chip position, and creates and transfers wiring pattern data, but this is not limited to this. It is sufficient that while an exposure process is being performed using one of the two substrate stages 30R and 30L, at least one of the following is performed on the other substrate stage: carrying out an exposed wafer, carrying in a new wafer, measuring the chip position, and creating and transferring wiring pattern data.

[0057] (Modification) The data generating device 300 may generate drive data that specifies the drive amount of the DMD 204 and the drive amount of the lens actuator, instead of the wiring pattern data. That is, the DMD 204 may generate a wiring pattern using design value data, and by changing the drive amount of the DMD 204 and the drive amount of the lens actuator, the position of the projection image of the wiring pattern projected onto the wafer WF may be changed, thereby changing the shape of the wiring pattern formed on the wafer WF. The shape of the wiring pattern may be changed by optically correcting the image of the wiring pattern.

[0058] Second Embodiment Since the process of attaching the chips to the wafer WF is performed before the formation of the wiring pattern in the exposure apparatus EX, the data creation apparatus 300 may create wiring pattern data or drive data using measurement data acquired in an inspection process that inspects the position of each chip relative to the wafer WF.

[0059] 10 is a top view showing an overview of a wiring pattern forming system 500A according to the second embodiment. The wiring pattern forming system 500A according to the second embodiment includes a chip measurement station CMS that measures the position of a chip on a wafer WF.

[0060] The chip measurement station CMS includes a plurality of measuring microscopes 61, and measures the positions of chips in different sets. Here, the positions of chips in different sets measured by the plurality of measuring microscopes 61 may be the positions of chips in different sets on the same wafer WF, or the positions of chips in each set on different wafers WF. In this embodiment, the plurality of measuring microscopes 61 measure the positions of chips in each set on different wafers WF.

[0061] The measurement result of the chip position is transmitted to the data creating device 300. The data creating device 300 creates wiring pattern data (or driving data) based on the measurement result of the chip position received from the chip measurement station CMS. The wiring pattern data created by the data creating device 300 is stored in a storage device different from the storage device that stores the wiring pattern data used for exposure control of the substrate currently being exposed. In other words, when the wiring pattern data used for exposure control of the wafer WF currently being exposed is stored in the first storage device 310R, the data creating device 300 stores (transfers) the created wiring pattern data in the second storage device 310L.

[0062] In the exposure apparatus EX-A according to the second embodiment, the main body 1A is equipped with one substrate stage 30. Note that in the second embodiment, since the chip position is measured by the chip measurement station CMS, alignment systems ALG_L and ALG_R can be omitted.

[0063] After the chip position measurement is completed, the wafer WF is coated with a photosensitive resist by a coater developer device CD and then carried into the buffer unit PB. The wafers WF placed in the buffer unit PB are arranged on one tray TR (in the second embodiment, 4 wafers x 3 rows) by a robot RB installed in the substrate exchange unit 2A, carried into the main body unit 1A, and placed on the substrate holder of the substrate stage 30.

[0064] Alignment system ALG_C measures the position of each wafer WF relative to the substrate holder and corrects the exposure start position, etc. If the wafer WF rotates around the Z axis when placed on the substrate holder, causing the chip position to shift from the position of the wiring pattern data created by data creation device 300, there is a risk that the chips will not be connected correctly when wiring is formed using the wiring pattern data.

[0065] In this case, the data creating device 300 may correct the shape of the wiring pattern so that the chips are connected by creating wiring pattern data or driving data as described in the first embodiment and its modified examples. For example, the data creating device 300 detects the positional deviation of each chip from the position of the wiring pattern data from the position of each wafer WF measured by the alignment system ALG_C based on the chip position relative to the position of each wafer WF measured by the chip measuring station CMS. The data creating device 300 corrects the wiring pattern data or creates driving data based on the deviation. This makes it possible to form wiring that connects the chips even if the wafer WF rotates around the Z axis when placed on the substrate holder.

[0066] Incidentally, alignment system ALG_C may use an alignment mark of the chip to measure the position of wafer WF.

[0067] 11 is a conceptual diagram of a procedure for forming a wiring pattern of an FO-WLP in the second embodiment. As in the first embodiment, during the exposure process in the main body 1A, measurement of the chip position, creation and transfer of wiring pattern data (which may be driving data), application of resist to the wafer WF, and placement of the wafer WF on the tray TR are performed, thereby improving the throughput in forming the wiring pattern of the FO-WLP.

[0068] The exposure apparatus EX according to the second embodiment includes a spatial light modulator (DMD204), a data creating device 300, and an exposure control device 400. The data creating device 300 acquires measurement results from a chip measuring station CMS that measures the positions of chips C1 and C2 included in each set of semiconductor chips arranged on a wafer WF, and determines a wiring pattern WL that connects between the chips C1 and C2 included in each set based on the measurement results, creates wiring pattern data used to control the DMD204 when generating the determined wiring pattern WL, and stores the wiring pattern data in the first storage device 310R or the second storage device 310L. The exposure control device 400 controls the DMD204 using the wiring pattern data stored in the first storage device 310R or the second storage device 310L to expose the wiring pattern WL that connects between the chips C1 and C2 included in each set. The measurement of the positions of the chips on the wafer WF is performed while a set of wafers WF different from the set of wafers WF whose chip positions are measured together with the wafer WF is being exposed. This makes it possible to measure the chip position and create and transfer wiring pattern data based on the measurement results during the relatively time-consuming exposure process, thereby enabling efficient use of time and improving the throughput in forming wiring patterns for FO-WLPs.

[0069] Third Embodiment The wafer WF may be attached to a base substrate B, and the position of each chip with respect to the base substrate B may be measured in a chip measurement station CMS.

[0070] 12 is a top view showing an overview of a wiring pattern forming system 500B according to the third embodiment. The wiring pattern forming system 500B according to the third embodiment has a wafer placement device WA that attaches a plurality of wafers WF, on which chips are placed, to a base substrate B. The wafer placement device WA prevents the position of the wafer WF relative to the base substrate B from being changed.

[0071] The base substrate B, to which a plurality of wafers WF have been attached by the wafer placement device WA, is carried into the chip measurement station CMS.

[0072] The chip measurement station CMS includes a plurality of measuring microscopes 61, and measures the position of each chip with respect to the base substrate B. The plurality of measuring microscopes 61 measure the positions of chips in different sets. The measurement results of the chip positions are transmitted to the data generating device 300.

[0073] The data creating device 300 creates wiring pattern data (or driving data) based on the measurement result of the chip position received from the chip measuring station CMS. The wiring pattern data created by the data creating device 300 is stored in a storage device different from the storage device that stores the wiring pattern data used for the exposure control of the wafer WF on the base substrate B currently being exposed. In other words, when the wiring pattern data used for the exposure control of the wafer WF on the base substrate B currently being exposed is stored in the first storage device 310R, the data creating device 300 stores (transfers) the created wiring pattern data in the second storage device 310L.

[0074] After the chip position measurement is completed, the wafer WF is carried into a coater developer device CD together with the base substrate B, and after being coated with a photosensitive resist, is carried into the port PT of the substrate exchange unit 2B. After that, the wafer WF together with the base substrate B is placed on the substrate holder of the substrate stage 30.

[0075] Subsequent processing is the same as in the second embodiment, and detailed description thereof will be omitted. In the third embodiment, everything can be managed and exposed using the position of the base substrate B on which the wafer WF is placed and fixed. For example, EGA measurement and correction can be performed on the base substrate B during alignment as well. In other words, since the wafer WF is placed and fixed on the base substrate B, alignment for each wafer WF / each chip is not required when the base substrate B is placed on the substrate holder of the substrate stage 30, and alignment of only the base substrate B can be performed. Note that, although the wafer placement device WA attaches the wafer WF to the base substrate B, the wafer WF may be placed and fixed directly on the tray TR.

[0076] In the third embodiment, too, the throughput in forming the rewiring layer of the FO-WLP can be improved by measuring the chip position, creating and transferring wiring pattern data, and applying resist to the wafer WF during the exposure process in the main body 1A.

[0077] (Modification) In the third embodiment, the wafer placement device WA and the chip measurement station CMS are separate devices, but the present invention is not limited to this configuration. The measuring microscope 61 may start measuring the chip position from the wafer WF attached to the base substrate B by the wafer placement device WA. In other words, the measuring microscope 61 performs the measuring operation in parallel with the attaching operation of the plurality of wafers WF to the base substrate B. The measuring microscope 61 may start the measuring operation after one wafer WF is attached to the base substrate B, or may start the measuring operation after the plurality of wafers WF are attached to the base substrate B. The measuring microscope 61 may temporarily suspend the measuring operation at the timing when the wafer WF is placed on the base substrate B. This is to prevent the vibration generated when the wafer WF is placed on the base substrate B from affecting the measurement result of the measuring microscope 61.

[0078] In the above first to third embodiments and their modifications, the first storage device 310R and the second storage device 310L are separate storage devices. However, data (at least one of wiring pattern data and driving data) used in the exposure process of the wafer WF placed on the substrate stage 30R and data (at least one of wiring pattern data and driving data) used in the exposure process of the wafer WF placed on the substrate stage 30L may be stored in different storage areas of one storage device. However, when using different storage areas of one storage device, since one storage area cannot be accessed while the other storage area is being accessed, there is a risk that the overall processing time will be long. In addition, SSDs deteriorate with each write, and the usage time also affects their lifespan. Therefore, since the number of times data is written to the storage device in this first embodiment is relatively high, when one SSD is used, there is a possibility that the SSD will need to be replaced in a short period of time. Therefore, it is preferable to use two storage devices.

[0079] In the above first to third embodiments and their modified examples, a case has been described in which a plurality of wafer-shaped substrates are placed on the substrate stage 30. However, a plurality of rectangular substrates may also be placed on the substrate stage 30.

[0080] Moreover, the first to third embodiments and their modifications can also be applied to the formation of a wiring pattern that connects chips on the substrate P shown in FIG. 3(B).

[0081] The above-described embodiment is a preferred example of the present invention, but the present invention is not limited to this embodiment and can be modified in various ways without departing from the scope of the present invention. [Explanation of symbols]

[0082] EX, EX-A, EX-B exposure equipment 204 DMD 204a Micromirror 300 Data Creation Device 310R 1st storage device 310L 2nd storage device 400 Exposure control device C1, C2 Semiconductor chip WF wafer P board

Claims

1. performing position measurement, which is measurement of the positions of each of a plurality of chips included in a first substrate placed on a first tray and the positions of each of a plurality of chips included in a second substrate placed on the first tray; and performing data creation, which is creation of first pattern data that is pattern data of wiring connecting the multiple chips included in the first substrate based on the respective positions of the multiple chips included in the first substrate, and second pattern data that is pattern data of wiring connecting the multiple chips included in the second substrate based on the respective positions of the multiple chips included in the second substrate, The data creation is started during the period in which the position measurement is performed. A wiring pattern forming method.

2. performing data transfer, which is transfer of the first pattern data and the second pattern data to an exposure device including a spatial light modulator; During the data creation period, the data transfer is started. The method for forming a wiring pattern according to claim 1 .

3. performing substrate exposure, which is exposure of a plurality of substrates arranged on a second tray by the exposure device; during a period in which the substrate exposure is performed, the position measurement, the data creation, and the data transfer are started; The wiring pattern forming method according to claim 2 .

4. storing the first pattern data and the second pattern data in a first storage device; the storage is performed during a period in which pattern data used for exposing the plurality of substrates arranged on the second tray is transferred from a second storage device different from the first storage device to the exposure device; The method for forming a wiring pattern according to claim 3 .

5. The wiring pattern forming method according to claim 1 , wherein the substrate is a wafer substrate.

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