Semiconductor storage device

Abstract

To provide a semiconductor storage device capable of suppressing the occurrence of void.SOLUTION: A semiconductor storage device comprises a first chip and a second chip bonded on the first direction side with respect to the first chip. The first chip includes a plurality of first bonding electrodes provided on a first bonding surface to which the second chip is bonded. The second chip includes a plurality of second bonding electrodes provided on a second bonding surface to which the first chip is bonded. The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of junction electrodes. The plurality of junction electrodes include junction electrodes arranged adjacently on one side in a third direction with respect to a second insulation layer as a first junction electrode, and junction electrodes arranged adjacently on the other side in the third direction with respect to the second insulation layer as a second junction electrode. The plurality of first junction electrodes and the plurality of second junction electrodes are arranged in a mutually zigzag manner in a second direction and the third direction.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] A NAND flash memory in which memory cell transistors are arranged three-dimensionally is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-048249 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the disclosed embodiment, a semiconductor memory device capable of suppressing the occurrence of voids is provided. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a first chip and a second chip attached to the first chip in a first direction. The first chip includes a stacked body in which first conductive layers and first insulating layers are alternately stacked in a first direction, a memory pillar that penetrates the stacked body in the first direction and whose intersection with the first conductive layer functions as a memory cell transistor, and a plurality of first bonding electrodes provided on a first bonding surface to which the second chip is attached. The second chip includes a plurality of second bonding electrodes provided on a second bonding surface to which the first chip is attached. The plurality of first bonding electrodes and the plurality of second bonding electrodes are bonded to each other to form a plurality of bonding electrodes. The stacked body is provided to extend in a second direction intersecting with the first direction, and includes a second insulating layer to divide at least a part of the stacked body in a third direction intersecting with both the first direction and the second direction. The plurality of bonding electrodes include first bonding electrodes arranged adjacent to each other on one side of the second insulating layer in the third direction and spaced a predetermined distance apart in the second direction, and second bonding electrodes arranged adjacent to each other on the other side of the second insulating layer in the third direction and spaced a predetermined distance apart in the second direction. The plurality of first bonding electrodes and the plurality of second bonding electrodes are arranged in a staggered pattern in the second and third directions. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a memory system according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing an equivalent circuit of a memory cell array included in a semiconductor memory device according to a first embodiment. [Diagram 3] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a first embodiment. [Figure 4] 2 is an enlarged cross-sectional view showing a cross-sectional structure around a memory pillar of the semiconductor memory device according to the first embodiment. [Diagram 5] 4 is a cross-sectional view showing a cross-sectional structure taken along line VV in FIG. 3. [Figure 6] 3 is a cross-sectional view showing a cross-sectional structure around a bonding pad and a dummy pad according to the first embodiment; [Figure 7] FIG. 7 is a cross-sectional view showing a cross-sectional structure taken along line VII-VII in FIG. [Figure 8] FIG. 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device of a comparative example. [Figure 9] FIG. 11 is a cross-sectional view showing a cross-sectional structure around a bonding pad according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a second embodiment. [Figure 11] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a first modification of the second embodiment. [Figure 12] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a second modification of the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to a third modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In order to facilitate understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and duplicated description will be omitted.

[0008] 1. First embodiment A description will be given of a semiconductor memory device according to a first embodiment. The semiconductor memory device according to this embodiment is a non-volatile memory device configured as a NAND type flash memory.

[0009] 1.1 Configuration of semiconductor memory device 1 is a block diagram showing an example of a schematic configuration of a memory system 3 including a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 is controlled by an external memory controller 2. A combination of the semiconductor memory device 1 and the memory controller 2 can configure the memory system 3. The memory system 3 is, for example, a memory card such as an SDTM card, or an SSD (Solid State Drive).

[0010] The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard. In the communication between the semiconductor memory device 1 and the memory controller 2, for example, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready busy signal RBn, and an input / output signal I / O are used.

[0011] The input / output signal I / O is, for example, an 8-bit signal, and may include a command CMD, address information ADD, and data DAT. In the following description, both write data and read data are denoted by the reference symbol DAT. The semiconductor memory device 1 receives the command CMD, address information ADD, and write data DAT from the memory controller 2 via the input / output signal I / O.

[0012] The command latch enable signal CLE is used to notify the semiconductor memory device 1 of the period during which the command CMD is transmitted via the signal I / O. The address latch enable signal ALE is used to notify the semiconductor memory device 1 of the period during which the address information ADD is transmitted via the signal I / O. The write enable signal WEn is used to enable the semiconductor memory device 1 to input the signal I / O. The read enable signal REn is used to enable the semiconductor memory device 1 to output the signal I / O. The ready / busy signal RBn is used to notify the memory controller 2 that the semiconductor memory device 1 is in either a ready state or a busy state. In the ready state, the semiconductor memory device 1 is capable of accepting commands from the memory controller 2. In the busy state, the semiconductor memory device 1 does not accept commands from the memory controller 2, with some exceptions.

[0013] The semiconductor memory device 1 includes a memory cell array 11 and a peripheral circuit PRC. The peripheral circuit PRC includes a row decoder 12, a sense amplifier 13, and a sequencer 14. The memory cell array 11 includes blocks BLK0 to BLK(n-1) (n is an integer equal to or greater than 1). The block BLK includes a plurality of non-volatile memory cells associated with bit lines and word lines, and is, for example, a data erase unit.

[0014] The sequencer 14 controls the operation of the entire semiconductor memory device 1 based on the received command CMD. For example, the sequencer 14 controls the row decoder 12, the sense amplifier 13, etc. to execute various operations such as a write operation and a read operation. In a write operation, write data DAT received by the semiconductor memory device 1 is stored in the memory cell array 11. In a read operation, read data DAT is read from the memory cell array 11.

[0015] The row decoder 12 selects a predetermined block BLK on which various operations such as a read operation and a write operation are to be performed based on the received address information ADD, and transfers a voltage to the word line of the selected block BLK. The sense amplifier 13 executes a transfer operation of data DAT between the memory controller 2 and the memory cell array 11 based on the received address information ADD. That is, in a write operation, the sense amplifier 13 holds the received write data DAT and applies a voltage to the bit line based on the write data DAT. In a read operation, the sense amplifier 13 applies a voltage to the bit line, reads out data stored in the memory cell array 11 as read data DAT, and outputs the read data DAT to the memory controller 2.

[0016] 1.2 Configuration of memory cell array 11 2 is a circuit diagram showing an example of an equivalent circuit of the memory cell array 11 included in the semiconductor memory device 1 of the first embodiment. As an example of the circuit configuration of the memory cell array 11, an example of the circuit configuration of a predetermined block BLK of the memory cell array 11 is shown. Each of the other blocks BLK of the memory cell array 11 has a circuit configuration similar to that shown in FIG.

[0017] The block BLK includes, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are associated one-to-one with m bit lines BL0 to BL(m-1) (m is an integer equal to or greater than 1). Each NAND string NS is connected to an associated bit line BL and includes, for example, memory cell transistors MT0 to MT7 and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate (hereinafter also referred to as a gate) and a charge storage layer, and can store data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select the NAND string NS including the selection transistors ST1 and ST2 during various operations.

[0018] The drain of the select transistor ST1 of each NAND string NS is connected to a bit line BL associated with the NAND string NS. The memory cell transistors MT0 to MT7 are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The source of the select transistor ST2 is connected to a source line SL.

[0019] The gates of the select transistors ST1 of the NAND strings NS included in the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3. The gates of the select transistors ST2 of the NAND strings NS included in the block BLK are commonly connected to a select gate line SGS. The gates of the memory cell transistors MT0 to MT7 of the NAND strings NS included in the block BLK are commonly connected to word lines WL0 to WL7.

[0020] Each bit line BL is connected to the drain of the select transistor ST1 of the associated NAND string NS included in the string unit SU of the block BLK. The source line SL is commonly connected to the source of the select transistor ST2 of each of the NAND strings NS included in the block BLK, and is thereby shared between the string units SU of the block BLK. The source line SL is shared between the blocks BLK, for example, by being connected in the same way in different blocks BLK.

[0021] A set of memory cell transistors MT commonly connected to one word line WL in one string unit SU is called, for example, a cell unit CU. For example, a set of one-bit data of the same order held in each of the memory cell transistors MT in a cell unit CU is called "one page data." For example, when multiple bits of data are held in each memory cell by the MLC method or the like, multiple "one page data" can be held in one cell unit CU.

[0022] Although the circuit configuration of the memory cell array 11 has been described above, the circuit configuration of the memory cell array 11 is not limited to the above. For example, the number of string units SU included in each block BLK can be designed to be any number. Also, the number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number. The number of word lines WL and select gate lines SGD and SGS can be changed based on the number of memory cell transistors MT and select transistors ST1 and ST2 in the NAND string NS. It is also possible to include dummy memory cell transistors in the NAND string NS that have the same structure as the memory cell transistors MT and do not store valid data.

[0023] 1.3 Structure of the semiconductor memory device 1 3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device 1 of the first embodiment. As shown in FIG. 3, the semiconductor memory device 1 has a structure in which a peripheral circuit chip 30 and a cell chip 40 are bonded together in the Z direction. The peripheral circuit chip 30 is provided with a peripheral circuit PRC. The cell chip 40 is provided with a stacked body 410 that functions as a part of the memory cell array 11. In this embodiment, the cell chip 40 corresponds to the first chip, and the peripheral circuit chip 30 corresponds to the second chip.

[0024] In the following, for convenience, the directions are defined based on the semiconductor substrate SB11 included in the peripheral circuit chip 30. Two directions parallel to a predetermined surface of the semiconductor substrate SB11, for example, perpendicular to each other, are defined as the X direction and the Y direction. A direction intersecting a predetermined surface of the semiconductor substrate SB11 and in which peripheral circuit elements are formed based on the surface is defined as the Z direction. The Z direction will be described as being perpendicular to the X direction and the Y direction, but is not necessarily limited to this. In the following description, the Z direction will be described as "up" and the direction opposite to the Z direction will be described as "down", but this notation is merely for convenience and is unrelated to, for example, the direction of gravity. In this embodiment, the Z direction corresponds to the first direction, the X direction corresponds to the second direction intersecting the first direction, and the Y direction corresponds to the third direction perpendicular to both the first direction and the second direction.

[0025] 1.3.1 Peripheral circuit chip structure The semiconductor substrate SB11 of the peripheral circuit chip 30 includes, for example, silicon (Si). On the upper surface of the semiconductor substrate SB11, a plurality of MOS (Metal Oxide Semiconductor) transistors Tr11 and Tr12 are provided as peripheral circuit elements included in the peripheral circuit PRC. Each of the transistors Tr11 and Tr12 includes a gate insulator provided on the upper surface of the semiconductor substrate SB11, a gate electrode provided on the upper surface of the gate insulator, and a pair of source / drain regions sandwiching a region of the semiconductor substrate SB11 below the gate insulator.

[0026] Conductive layers D11 and D12 are provided above the transistors Tr11 and Tr12. Each of the conductive layers D11 and D12 includes a plurality of wirings insulated from each other. Through these wirings, the source, drain, and gate of each of the transistors Tr11 and Tr12 can be electrically connected to other components.

[0027] A via V11 is provided above a predetermined source region, drain region, and gate region of transistor Tr11. An upper surface of the via V11 contacts a predetermined wiring in conductive layer D11. A via V12 is provided on the upper surface of the predetermined wiring in conductive layer D11. An upper surface of the via V12 contacts a predetermined wiring in conductive layer D12. A via V13 is provided on the upper surface of the predetermined wiring in conductive layer D12. A conductive layer PD11 is provided on the upper surface of the via V13.

[0028] The conductive layer PD11 includes a metal material such as copper (Cu). The upper surface of the conductive layer PD11 constitutes a part of the upper surface 300 of the peripheral circuit chip 30, and is located at substantially the same position in the Z direction as the upper surface 300 of the peripheral circuit chip 30. The conductive layer PD11 functions as an electrode pad used for electrical connection with other chips. Hereinafter, a conductor provided on the upper surface 300 of the peripheral circuit chip 30 and functioning as an electrode pad will be referred to as a bonding pad PD11. Moreover, the conductor functioning as an electrode pad in this way will be given the symbol PD.

[0029] In addition to the bonding pad PD11, a bonding pad PD12 is provided on the upper surface 300 of the peripheral circuit chip 30. The bonding pad PD12 is electrically connected to the transistor Tr12 via a via V13, a conductive layer D12, a via V12, a conductive layer D11, and a via V11.

[0030] In this specification, for example, the via V12 and the wiring in the conductive layer D12 are distinguished from each other, but they may be integrated. The same applies to other vias and conductive layers. In this embodiment, the bonding pads PD11 and PD12 correspond to the second bonding electrodes. The connection via the wiring in the conductive layers D11 and D12 is merely one example. In the peripheral circuit chip 30, various vias V11 to V13, wiring in the conductive layers D11 and D12, and bonding pad PD11 as described above are also provided. For convenience, all of such various vias V11 to V13, wiring in the conductive layers D11 and D12, and bonding pads PD11 and PD12 are not necessarily shown in FIG. 3.

[0031] An interlayer insulating layer 31 is provided between the semiconductor substrate SB11 and the upper surface of the peripheral circuit chip 30. The interlayer insulating layer 31 is provided in a portion where, for example, the transistors Tr11, Tr12, the various vias V11 to V13, the wiring in the conductive layers D11, D12, and the bonding pads PD11, PD12 are not provided. The interlayer insulating layer 31 contains, for example, oxygen and silicon (for example, SiO2). The interlayer insulating layer 31 may further contain nitrogen or carbon.

[0032] 1.3.2 Cell chip structure A bottom surface 400 of the cell chip 40 is attached to an upper surface 300 of the peripheral circuit chip 30. In this embodiment, the bottom surface 400 of the cell chip 40 corresponds to a first attachment surface, and the upper surface of the peripheral circuit chip 30 corresponds to a second attachment surface. The cell chip 40 includes a stacked body 410 that functions as a part of the memory cell array 11. More specifically, each of the memory pillars PL included in the stacked body 410 functions as, for example, one NAND string NS. The memory pillars PL are formed so as to penetrate the stacked body 410 in the Z direction.

[0033] The laminate 410 is formed by alternately laminating a conductive layer 411 and an insulating layer 412 in the Z direction. The conductive layer 411 is formed in a plate shape extending in the X direction. The conductive layer 411 may include a laminate film of a barrier conductive film containing nitrogen and titanium (e.g., TiN) and a metal film such as tungsten (W). The conductive layer 411 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The multiple conductive layers 411 function as, for example, word lines and gate electrodes of multiple memory transistors connected thereto. The insulating layer 412 includes oxygen and silicon (e.g., SiO2). In this embodiment, the conductive layer 411 corresponds to a first conductive layer, and the insulating layer 412 corresponds to a first insulating layer.

[0034] One or more conductive layers 411 at the top and bottom ends of the stack 410 in the Z direction function, for example, as a source side select gate line SGS and a drain side select gate line SGD. The source side select gate line SGS is provided in an upper region of the stack 410, and the drain side select gate line SGD is provided in a lower region of the stack 410. The conductive layer 411 disposed between the source side select gate line SGS and the drain side select gate line SGD functions as a word line WL.

[0035] Fig. 4 is an enlarged cross-sectional view showing a cross-sectional structure around the memory pillar PL shown in Fig. 3. When the memory pillar PL is cut in the XY plane, the memory pillar PL has, for example, a circular or elliptical cross-sectional shape. The memory pillar PL has a core portion 81, a semiconductor layer 82, and a gate insulating film 83.

[0036] The core portion 81 is provided in the center portion of the memory pillar PL and is formed in a substantially cylindrical shape. The core portion 81 is made of an insulator containing silicon, oxygen, and the like.

[0037] The semiconductor layer 82 is formed in a substantially cylindrical shape and is provided so as to surround the outer periphery of the core portion 81. For example, polysilicon (Poly-Si) is used for the semiconductor layer 82. The semiconductor layer 82 is a portion in which channels of the memory cell transistors MT and the like are formed. The gate insulating film 83 is formed in a substantially cylindrical shape and is provided so as to surround the outer periphery of the semiconductor layer 82. The gate insulating film 83 has a tunnel insulating film 831, a charge storage film 832, and a block insulating film 833 which are stacked between the semiconductor layer 82 and the conductive layer 411.

[0038] The tunnel insulating film 831 is provided so as to cover the outer periphery of the semiconductor layer 82. For example, a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen is used for the tunnel insulating film 831. The tunnel insulating film 831 functions as a potential barrier between the semiconductor layer 82 and the charge storage film 832. For example, when electrons are injected from the semiconductor layer 82 to the charge storage film 832 (during a write operation), the electrons pass (tunnel) through the potential barrier of the tunnel insulating film 831. When holes are injected from the semiconductor layer 82 to the charge storage film 832 (during an erase operation), the holes pass through the potential barrier of the tunnel insulating film 831.

[0039] The charge storage film 832 is provided so as to cover the outer periphery of the tunnel insulating film 831. The charge storage film 832 is, for example, a film containing silicon and nitrogen. The charge storage film 832 has trap sites that trap charges in the film. A portion of the charge storage film 832 sandwiched between the conductive layer 411 and the semiconductor layer 82 is used as a storage region of the memory cell transistor MT.

[0040] The block insulating film 833 is provided so as to cover the outer periphery of the charge storage film 832. The block insulating film 833 is a film for suppressing back tunneling of charges from the conductive layer 411 to the gate insulating film 83. The block insulating film 833 is a film containing, for example, silicon and oxygen or a metal and oxygen. The film containing a metal and oxygen is, for example, a film containing aluminum oxide.

[0041] The outer periphery of the conductive layer 411 is covered with a barrier insulating film 413. For example, when tungsten is used for the conductive layer 411, a laminated film of a film containing silicon and nitrogen and a film containing titanium is selected as the barrier insulating film 413. Instead of the barrier insulating film 413, a conductive film such as a film containing titanium and nitrogen may be used.

[0042] In the memory pillar PL, the portion located inside each conductive layer 411, in other words, the intersection portion with the conductive layer 411, functions as a transistor. That is, in the memory pillar PL, a plurality of transistors are electrically connected in series along the longitudinal direction. Each conductive layer 411 functions as a gate of each transistor. The semiconductor layer 82 functions as a channel of each transistor.

[0043] Some of the transistors arranged in series along the longitudinal direction of the memory pillar PL function as the memory cell transistors MT shown in Fig. 2. Moreover, the transistors provided at both ends of the memory cell transistors MT arranged in series function as the select transistors ST1, ST2 shown in Fig. 2.

[0044] 3, a bonding pad PD21 is provided on the bottom surface 400 of the cell chip 40. The bonding pad PD21 is bonded to the upper surface of the bonding pad PD11 of the peripheral circuit chip 30. The bottom surface of each bonding pad PD21 constitutes a part of the bottom surface 400 of the cell chip 40, and is located at substantially the same position in the Z direction as the bottom surface 400 of the cell chip 40. The bonding pad PD21 includes a metal material such as copper (Cu).

[0045] A via V21 is provided on the upper surface of the bonding pad PD21. The upper surface of the via V21 is connected to a predetermined wiring in the conductive layer D21. A via V22 is provided on the upper surface of the predetermined wiring in the conductive layer D21. The upper surface of the via V22 is connected to a predetermined wiring in the conductive layer D22. A via V23 is provided on the upper surface of the predetermined wiring in the conductive layer D22. The upper surface of the via V23 is connected to the lower end of a predetermined memory pillar PL of the stack 410. Of the wiring in the conductive layer D22, the wiring electrically connected to the via V23 functions as a part of the bit line BL. Of the conductive layer D22, the part that functions as the bit line BL is formed to extend in the Y direction.

[0046] A staircase portion 414 is formed at an end of the laminate 410. In the staircase portion 414, a conductive layer 411 functioning as a word line WL is electrically connected to a bonding pad PD22 via a contact C20, a conductive layer D22, a via V22, a conductive layer D21, and a via V21. The bottom surface of the bonding pad PD22 forms a part of the bottom surface 400 of the cell chip 40, and is located at substantially the same position as the bottom surface 400 of the cell chip 40 in the Z direction.

[0047] Fig. 5 is a cross-sectional view showing a cross-sectional structure taken along line VV in Fig. 3. As shown in Fig. 5, a part of the laminate 410 is divided in the X direction by an interblock insulating layer 106. Each part divided by the interblock insulating layer 106 constitutes a block BLK shown in Fig. 2. In this embodiment, the interblock insulating layer 106 corresponds to the second insulating layer.

[0048] As shown in FIGS. 3 and 5, the cell chip 40 includes a semiconductor layer 100, an insulating layer 101, and an insulating layer 102 in this order above a stacked body 410.

[0049] The semiconductor layer 100 is a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B). A metal such as tungsten (W) or a silicide such as tungsten silicide (WSi) may be provided between the semiconductor layer 100 and the insulating layer 101. The insulating layer 101 is an insulating layer containing, for example, oxygen and silicon (for example, SiO2). The insulating layer 101 covers, for example, the entire upper surface of the semiconductor layer 100. The insulating layer 102 is a passivation layer containing, for example, polyimide.

[0050] In the cell chip 40, an interlayer insulating layer 44 is provided on at least a portion of the area where the bonding pads PD21, PD22, the vias V21 to V23, the conductive layers D21, D22, the laminate 410, etc. are not provided. The interlayer insulating layer 44 contains, for example, oxygen and silicon. The interlayer insulating layer 44 may further contain nitrogen or carbon.

[0051] 1.3.3 Bonding pad structure Next, the structure of the bonding pad will be specifically described. Note that the junction structure of the bonding pad PD11 of the peripheral circuit chip 30 and the bonding pad PD21 of the cell chip 40 is the same as or similar to the junction structure of the bonding pad PD12 of the peripheral circuit chip 30 and the bonding pad PD22 of the cell chip 40, so the junction structure of the bonding pad PD11 of the peripheral circuit chip 30 and the bonding pad PD21 of the cell chip 40 will be representatively described below.

[0052] FIG. 6 is a cross-sectional view showing a cross-sectional structure around the bonding pad PD21 and the dummy pad DP of the cell chip 40. As shown in FIG. 6, the interlayer insulating layer 31 includes insulating layers 31a to 31f. Each of the insulating layers 31a, 31c, and 31e is an insulating layer containing silicon and oxygen (e.g., SiO2) formed by using, for example, dTEOS. The insulating layer 31b is disposed so as to be sandwiched between the two insulating layers 31a and 31c in the Z direction. The insulating layer 31d is disposed so as to be sandwiched between the two insulating layers 31c and 31e in the Z direction. The insulating layer 31f is disposed below the insulating layer 31e in the Z direction. The insulating layers 31b, 31d, and 31f are insulating layers containing, for example, silicon and nitrogen (e.g., SiN).

[0053] Insulating layers 31a and 31b have recesses 32 that open to the top surface of insulating layer 31a. Insulating layers 31c and 31d have recesses 33 that open to the bottom surface of recess 32. Insulating layers 31e and 31f have recesses 34 that open to the bottom surface of recess 33.

[0054] A bonding pad PD11 is embedded in the recess 32. The bonding pad PD11 includes a barrier metal layer PD11a and a pad material layer PD11b. The barrier metal layer PD11a is formed in a thin film on the inner wall surface and bottom surface of the recess 32. Insulating layers 31a and 31b are provided on the outside of the barrier metal layer PD11a. The pad material layer PD11b is provided inside the recess 32 via the barrier metal layer PD11a. In this embodiment, the bonding pad PD11 corresponds to a second bonding electrode and a second pad.

[0055] A via V13 is embedded in the recess 33. The via V13 includes a barrier metal layer V13a and a via material layer V13b. The barrier metal layer V13a is formed as a thin film on the inner wall surface of the recess 33 and on the boundary between the via V13 and the conductive layer D12. Insulating layers 31c and 31d are provided on the outside of the barrier metal layer V13a. The via material layer V13b is embedded inside the recess 33 via the barrier metal layer V13a. In this embodiment, the conductive layer D12 corresponds to the third conductive layer, and the via V13 corresponds to the second via.

[0056] A conductive layer D12 is embedded in the recess 34. The conductive layer D12 includes a barrier metal layer D12a and a conductive material layer D12b. The barrier metal layer D12a is formed as a thin film on the inner wall surface of the recess 34. The conductive material layer D12b is embedded inside the recess 34 via the barrier metal layer D12a.

[0057] The interlayer insulating layer 44 includes insulating layers 44a to 44f, similar to the interlayer insulating layer 31. Each of the insulating layers 44a, 44c, and 44e is an insulating layer containing silicon and oxygen (e.g., SiO2) formed, for example, using dTEOS. The insulating layer 44b is disposed so as to be sandwiched between the two insulating layers 44a and 44c in the Z direction. The insulating layer 44d is disposed so as to be sandwiched between the two insulating layers 44c and 44e in the Z direction. The insulating layer 44f is disposed above the insulating layer 44e in the Z direction. The insulating layers 44b, 44d, and 44f are insulating layers containing, for example, silicon and nitrogen (e.g., SiN).

[0058] Insulating layers 44a and 44b have recesses 45 that open to the bottom surface of insulating layer 44a. Insulating layers 44c and 44d have recesses 46 that open to the bottom surface of recess 45. Insulating layer 44e has recesses 47 that open to the bottom surface of recess 46.

[0059] The bonding pad PD21 is embedded in the recess 45. The bonding pad PD21 includes a barrier metal layer PD21a and a pad material layer PD21b. The barrier metal layer PD21a is formed in a thin film on the inner wall surface and the bottom surface of the recess 45. Insulating layers 44a and 44b are provided on the outside of the barrier metal layer PD21a. The pad material layer PD21b is provided inside the recess 45 via the barrier metal layer PD21a. The pad material layer PD21b is bonded to the pad material layer PD11b provided therebelow. That is, the bonding pad PD11 and the bonding pad PD21 are electrically connected. In this embodiment, the bonding pad PD21 corresponds to the first bonding electrode and the first pad.

[0060] A via V21 is embedded in the recess 46. The via V21 includes a barrier metal layer V21a and a via material layer V21b. The barrier metal layer V21a is formed as a thin film on the inner wall surface of the recess 46 and on the boundary between the via V21 and the conductive layer D21. Insulating layers 44c and 44d are provided on the outside of the barrier metal layer V21a. The via material layer V21b is embedded inside the recess 46 via the barrier metal layer V21a. In this embodiment, the via V21 corresponds to a first via.

[0061] A conductive layer D21 is embedded in the recess 47. The conductive layer D21 includes a barrier metal layer D21a and a conductive material layer D21b. The barrier metal layer D21a is formed as a thin film on the inner wall surface of the recess 47. The conductive material layer D21b is embedded inside the recess 47 via the barrier metal layer D21a. In this embodiment, the conductive layer D21 corresponds to a second conductive layer.

[0062] The peripheral circuit chip 30 further has a recess 35 formed therein so as to open to its upper surface 300. A pad PD13 is embedded in the recess 35. The pad PD13 includes a barrier metal layer PD13a and a pad material layer PD13b, similar to the bonding pad PD11. Unlike the bonding pad PD11, the pad PD13 is not connected to the conductive layer D12. The pad PD13 is not shown in FIGS. 3 and 5.

[0063] The cell chip 40 further has a recess 48 formed therein so as to open to its bottom surface 400. A pad PD23 is embedded in the recess 48. The pad PD23 includes a barrier metal layer PD23a and a pad material layer PD23b, similar to the bonding pad PD21. Unlike the bonding pad PD21, the pad PD23 is not connected to the conductive layer D21. The pad PD23 is not shown in FIGS. 3 and 5.

[0064] The pad material layer PD13b of the pad PD13 and the pad material layer PD23b of the pad PD23 are bonded to each other. As described above, the pads PD13 and PD23 are not electrically connected to the conductive layers D12 and D21, and therefore, hereinafter, the pads PD13 and PD23 are referred to as "dummy pads."

[0065] Each of the barrier metal layers D12a, V13a, PD11a, PD13a, PD21a, PD23a, V21a, and D21a is a metal layer containing, for example, Ti (titanium) or Ta (tantalum). The pad material layers PD11b, PD13b, PD21b, and PD23b, the via material layers V13b and V21b, and the conductive material layers D12b and D21b are metal layers containing, for example, Cu. Hereinafter, the bonding pads PD11 and PD21 bonded to each other are collectively referred to as "bonding pads BP." Also, the dummy pads PD13 and PD23 bonded to each other are collectively referred to as "dummy pads DP." In this embodiment, the bonding pads BP correspond to the bonding electrodes, and the dummy pads DP correspond to the dummy electrodes.

[0066] Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, in other words, a cross-sectional view showing the structure of the bottom surface 400 of the cell chip 40. As shown in Fig. 7, the bonding pad BP and the dummy pad DP have a polygonal cross-sectional shape perpendicular to the Z direction, specifically a rectangular shape. More specifically, the bonding pad BP has two opposing sides S11, S12 parallel to the X direction and two other opposing sides S13, S14 parallel to the Y direction, forming a rectangular shape. The same is true for the dummy pad DP.

[0067] A plurality of interblock insulating layers 106a, 106b are arranged at predetermined intervals in the Y direction on the cell chip 40. Each of the interblock insulating layers 106a, 106b is formed to extend in the X direction.

[0068] A bonding pad arrangement region A10 is provided between the inter-block insulating layers 106a, 106b. In the bonding pad arrangement region A10, a plurality of bonding pads BPa are arranged in a staggered manner in the X and Y directions. The plurality of bonding pads BPa are arranged at a predetermined pitch Px10 in the X direction. The plurality of bonding pads BPa are arranged at a predetermined pitch Py10 in the Y direction. The pitch Px10 and the pitch Py10 are set to the same value, for example.

[0069] A bonding pad arrangement region A11 is provided on the opposite side of the inter-block insulating layer 106a in the Y direction from the portion where the bonding pads BPa are provided. In the bonding pad arrangement region A11, a plurality of bonding pads BPb are arranged in a staggered pattern, similar to the bonding pad arrangement region A10.

[0070] A dummy pad arrangement region A21 is provided on the opposite side in the Y direction from the portion where the inter-block insulating layer 106a is provided with respect to the bonding pad arrangement region A11. A plurality of dummy pads DPa are provided in the dummy pad arrangement region A21. The dummy pads DPa are arranged in a staggered manner in the X and Y directions. The plurality of dummy pads DPa are arranged at a predetermined pitch Px11 in the X direction. The plurality of dummy pads DPa are arranged at a predetermined pitch Py11 in the Y direction. The pitch Px11 and the pitch Py11 are set to different values, for example.

[0071] A bonding pad arrangement region A12 is provided on the opposite side of the inter-block insulating layer 106b in the Y direction from the portion where the bonding pads BPa are provided. In the bonding pad arrangement region A12, a plurality of bonding pads BPc are arranged in a staggered pattern, similar to the bonding pad arrangement region A10.

[0072] A dummy pad arrangement region A22 is provided on the opposite side in the Y direction from the portion where the inter-block insulating layer 106b is provided with respect to the bonding pad arrangement region A12. In the dummy pad arrangement region A22, a plurality of dummy pads DPb are arranged in a staggered pattern, similar to the dummy pad arrangement region A21.

[0073] In FIG. 7, among the bonding pads BPa arranged in the bonding pad arrangement area A10, the bonding pad BPa arranged adjacent to the inter-block insulating layer 106a is indicated by the symbol BPa10. Also, among the bonding pads BPb arranged in the bonding pad arrangement area A11, the bonding pad BPb arranged adjacent to the inter-block insulating layer 106a is indicated by the symbol BPb10. The bonding pads BPa10 and the bonding pads BPb10 are arranged in a staggered manner in the X direction and the Y direction. The bonding pads BPa10 and the bonding pads BPb10 are arranged at a predetermined pitch Px10 in the X direction. The bonding pads BPa10 and the bonding pads BPb10 are arranged at a predetermined pitch Py10 in the Y direction. In this case, the bonding pad BPa10 corresponds to the first bonding electrode, and the bonding pad BPb10 corresponds to the second bonding electrode.

[0074] 7, of the bonding pads BPa arranged in the bonding pad arrangement area A10, the bonding pad arranged adjacent to the inter-block insulating layer 106b is indicated by the symbol BPa11. Also, of the bonding pads BPc arranged in the bonding pad arrangement area A12, the bonding pad BPc arranged adjacent to the inter-block insulating layer 106b is indicated by the symbol BPc10. The bonding pads BPa11 and the bonding pads BPc10 are also arranged in a staggered pattern in the X and Y directions, similar to the bonding pads BPa10 and BPb10. In this case, the bonding pad BPa11 corresponds to the first bonding electrode, and the bonding pad BPc10 corresponds to the second bonding electrode.

[0075] 1.4 Functions and Effects of the Semiconductor Memory Device of the Present Embodiment 8 shows a cross-sectional structure of a semiconductor memory device 200 of a comparative example. In the semiconductor memory device 200 of the comparative example shown in FIG. 8, a plurality of bonding pads BPa10 arranged in a bonding pad arrangement region A10 and a plurality of bonding pads BPb10 arranged in a bonding pad arrangement region A11 are arranged so as to be adjacent to each other in the Y direction. In the case of such an arrangement, the bonding pads BPa10 and BPb10 are arranged close to each other. Therefore, for example, the coverage of the bonding pads BPa10, BPb10 in the region A30 indicated by the two-dot chain line in FIG. 8 becomes large. The coverage is the ratio of the area of ​​the pads such as the bonding pads BPa10, BPb10 to the total area of ​​the region indicated by the two-dot chain line. If the coverage of the bonding pads BPa10, BPb10 becomes large, for example, when the bottom surface 400 of the cell chip 40 is polished using CMP (Chemical Mechanical Polishing) or the like, the region A31 located between the bonding pads BPa10 and BPb10 in the interlayer insulating layer 44 may be removed to a greater extent. A similar problem may occur when the top surface 300 of the peripheral circuit chip 30 is polished using CMP or the like. If the region A31 is removed to a greater extent, a void may be formed in that portion, resulting in a defective product.

[0076] 7, in the semiconductor memory device 1 of this embodiment, the multiple bonding pads BPa10 and the multiple bonding pads BPb10 arranged on either side of the inter-block insulating layer 106a are arranged in a staggered manner in the X and Y directions. In other words, the multiple bonding pads BPa10 and the multiple bonding pads BPb10 are alternately provided in the X direction and alternately provided in the Y direction. This configuration makes it possible to reduce the coverage of the bonding pads BPa10, BPb10 in the area A30 indicated by the two-dot chain line in Fig. 7. As a result, it becomes possible to suppress the formation of voids in the area A30.

[0077] 2. Second embodiment Next, a second embodiment of the semiconductor memory device 1 will be described. The following mainly describes the differences from the semiconductor memory device 1 of the first embodiment.

[0078] 2.1 Bonding pad structure FIG. 9 is a cross-sectional view showing a cross-sectional structure around the bonding pad PD21 of the cell chip 40 of this embodiment. FIG. 10 is a cross-sectional view showing a cross-sectional structure of the cell chip 40 of this embodiment, which corresponds to the cross-sectional structure along the line VII-VII of FIG. 6. As shown in FIG. 9, the peripheral circuit chip 30 of this embodiment is not provided with a bonding pad PD11. A via V13 is exposed on the upper surface 300 of the peripheral circuit chip 30. The via V13 is bonded to the bonding pad PD21 of the cell chip 40. In this embodiment, the bonding pad BP includes the via V13 and the bonding pad PD21. In this embodiment, the via V13 corresponds to the second bonding electrode.

[0079] The semiconductor memory device 1 of this embodiment differs from the semiconductor memory device 1 of the first embodiment in that it is not provided with dummy pads DP. Therefore, as shown in FIG 10, dummy pads DPa, DPb are not arranged in the dummy pad arrangement areas A21, A22.

[0080] 2.2 Functions and Effects of the Semiconductor Memory Device of the Present Embodiment In the semiconductor memory device 1 of the first embodiment, as shown in Figures 6 and 7, dummy pads DP are provided in the area where the bottom surface 400 of the cell chip 40 and the top surface 300 of the peripheral circuit chip 30 are bonded to each other. In contrast, in the semiconductor memory device 1 of the present embodiment, as shown in Figures 9 and 10, dummy pads DP are not provided in the area where the bottom surface 400 of the cell chip 40 and the top surface 300 of the peripheral circuit chip 30 are bonded to each other.

[0081] According to this configuration, since the dummy pads DP are not arranged in the dummy pad arrangement area A22, it is possible to increase the coverage difference between the coverage of the pads in the bonding pad arrangement area A12 where the bonding pads BPc are arranged and the coverage of the pads in the dummy pad arrangement area A22. This makes it possible to further suppress the formation of voids on the bonding surface between the cell chip 40 and the peripheral circuit chip 30.

[0082] (First Modification) Next, a first modification of the semiconductor memory device 1 of the second embodiment will be described.

[0083] Fig. 11 is a cross-sectional view showing a cross-sectional structure of the cell chip 40 of this embodiment, which corresponds to the cross-sectional structure taken along line VII-VII in Fig. 6. As shown in Fig. 11, the bonding pad BP of this modified example has a quadrangular cross-sectional shape perpendicular to the Z direction, in which two opposing sides S11, S12 intersect with the X direction at an angle of 45 degrees, and the other two opposing sides S13, S14 intersect with the Y direction at an angle of 45 degrees.

[0084] According to this configuration, the distance between, for example, adjacent bonding pads BP30 and BP31 among the multiple bonding pads BP can be increased, thereby suppressing the formation of voids in the area between bonding pads BP30 and BP31.

[0085] (Second Modification) Next, a second modification of the semiconductor memory device 1 of the second embodiment will be described.

[0086] Fig. 12 is a cross-sectional view showing a cross-sectional structure of the cell chip 40 of this embodiment, which corresponds to the cross-sectional structure taken along line VII-VII in Fig. 6. As shown in Fig. 12, the bonding pad BP of this modification is formed so that the cross-sectional shape perpendicular to the Z direction is circular. With this configuration, the distance between, for example, adjacent bonding pads BP30 and BP31 among the multiple bonding pads BP can be increased, thereby suppressing the formation of voids in the region between the bonding pads BP30 and BP31.

[0087] (Third Modification) Next, a third modification of the semiconductor memory device 1 of the second embodiment will be described.

[0088] Fig. 13 is a cross-sectional view showing a cross-sectional structure of the cell chip 40 of this embodiment, which corresponds to the cross-sectional structure taken along line VII-VII in Fig. 6. As shown in Fig. 13, in the semiconductor memory device 1 of this modified example, the pitch Px10 and the pitch Py10 are set to different values. Even with this configuration, it is possible to obtain the same or similar actions and effects as the semiconductor memory device 1 of the second embodiment.

[0089] 3. Other embodiments The present disclosure is not limited to the above specific examples. 5 is formed so as to cut the stack 410 in the Z direction, more specifically, to cut all of the conductive layers 411 that function as the select gate lines SGS, the word lines WL, and the select gate lines SGD. Alternatively, the interblock insulating layer 106 may be formed in the stack 410 so as to cut only the conductive layers 411 that function as the select gate lines SGD.

[0090] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0091] BP: bonding pad (bonding electrode), BPa10: bonding pad (first bonding electrode), BPa11: bonding pad (first bonding electrode), BPb10: bonding pad (second bonding electrode), BPc10: bonding pad (second bonding electrode), D12: conductive layer (third conductive layer), D21: conductive layer (second conductive layer), PL: memory pillar, PD11: bonding pad (second bonding electrode, second pad), PD21: bonding pad (first bonding electrode, first pad), V13: via (second via, second bonding electrode), V21: via (first via), 1: semiconductor memory device, 30: peripheral circuit chip (second chip), 40: cell chip (first chip), 106: inter-block insulating layer (second insulating layer), 410: laminate, 411: conductive layer (first conductive layer), 412: insulating layer (first insulating layer).

Claims

1. A first chip; a second chip attached to a first direction side of the first chip, The first chip includes: a laminate in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in the first direction; a memory pillar that penetrates the stack in the first direction and whose intersection with the first conductive layer functions as a memory cell transistor; a plurality of first bonding electrodes provided on a first bonding surface to which the second chip is bonded; The second chip is a second bonding surface to which the first chip is bonded, and a plurality of second bonding electrodes are provided on the second bonding surface; The first and second bonding electrodes are bonded to each other to form a plurality of bonded electrodes; the laminate is provided so as to extend in a second direction intersecting the first direction, and includes a second insulating layer so as to divide at least a portion of the laminate in a third direction intersecting both the first direction and the second direction; the plurality of bonding electrodes include first bonding electrodes arranged adjacent to each other on one side of the second insulating layer in the third direction and spaced apart at a predetermined interval in the second direction, and second bonding electrodes arranged adjacent to each other on the other side of the second insulating layer in the third direction and spaced apart at a predetermined interval in the second direction, The first bonding electrodes and the second bonding electrodes are arranged in a staggered manner in the second direction and the third direction. Semiconductor memory device.

2. The first chip includes a second conductive layer electrically connected to the first bonding electrode; A first via is provided between the first adhesive electrode and the second conductive layer, The second chip further includes a third conductive layer electrically connected to the second bonding electrode, The second bonding electrode is a second via connected to the third conductive layer.

2. The semiconductor memory device according to claim 1.

3. The first chip includes a second conductive layer and A first via is provided between the first adhesive electrode and the second conductive layer, The second chip includes a third conductive layer; A second via provided between the second adhesive electrode and the third conductive layer.

2. The semiconductor memory device according to claim 1.

4. The first chip further includes a second conductive layer electrically connected to the first bonding electrode, The second chip further includes a third conductive layer electrically connected to the second bonding electrode, A dummy electrode that is not electrically connected to the second conductive layer and the third conductive layer is further provided in a portion where the first bonding surface of the first chip and the second bonding surface of the second chip are bonded to each other.

2. The semiconductor memory device according to claim 1.

5. The first chip further includes a second conductive layer electrically connected to the first bonding electrode, The second chip further includes a third conductive layer electrically connected to the second bonding electrode, A dummy electrode that is not electrically connected to the second conductive layer and the third conductive layer is not provided in a portion where the first bonding surface of the first chip and the second bonding surface of the second chip are bonded to each other.

2. The semiconductor memory device according to claim 1.

6. The first bonding electrodes and the second bonding electrodes are arranged in a staggered pattern at the same pitch in the second direction and the third direction.

2. The semiconductor memory device according to claim 1.

7. The first bonding electrodes and the second bonding electrodes are arranged in a staggered pattern at different pitches in the second direction and the third direction.

2. The semiconductor memory device according to claim 1.

8. The joining electrode has a polygonal cross section perpendicular to the first direction.

2. The semiconductor memory device according to claim 1.

9. The joining electrode has a cross section perpendicular to the first direction that is formed in a rectangular shape.

9. The semiconductor memory device according to claim 8.

10. The joining electrode has a cross-sectional shape perpendicular to the first direction that is formed into a quadrangle shape in which two opposing sides are parallel to the second direction and the other two opposing sides are parallel to the first direction.

10. The semiconductor memory device according to claim 9.

11. The joining electrode has a cross-sectional shape perpendicular to the first direction that is formed into a quadrangle shape in which two opposing sides intersect with the first direction and the second direction and other two opposing sides intersect with the first direction and the second direction.

10. The semiconductor memory device according to claim 9.

12. The joining electrode has a circular cross-sectional shape perpendicular to the first direction.

2. The semiconductor memory device according to claim 1.

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