Pixel binning device and method for electric charge area CMOS TDI imaging

Abstract

To provide a pixel binning device of an electric charge area complementary metal-oxide-semiconductor (CMOS) time delay integration (TDI) image sensor.SOLUTION: A pixel binning device (202a) comprises: a column of a first transfer gate (302a) coupled to a first column (110) of a plurality of pixel registers; a plurality of binning registers (304a) coupled to the first transfer gate (302a); a plurality of second transfer gates (306a, 306b, 306c, and 306d) couples to the plurality of binning registers (304a); and a storage resister (308a) coupled to the plurality of second transfer gates.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to the field of pixel binning in charge-domain complementary metal-oxide semiconductor (CMOS) time-delay integration (TDI) image sensors.

[0002] In part, in one aspect, the disclosure relates to a pixel charge binning apparatus for a CMOS TDI image sensor, the binning apparatus comprising: a row of first transfer gates coupled to a first row of a plurality of pixel registers arranged in a matrix, a plurality of binning registers coupled to the first transfer gates, a plurality of second transfer gates coupled to the plurality of binning registers, and a row of storage registers coupled to the plurality of second transfer gates.

[0003] In another aspect, the present disclosure relates to a bi-directional CMOS TDI image sensor comprising a plurality of pixel registers, a first binning device coupled to one end of the plurality of pixel registers, and a second binning device coupled to the other end of the plurality of pixel registers.

[0004] While the present disclosure is directed to different aspects and embodiments, it is understood that the different aspects and embodiments disclosed herein may be integrated, combined, or used together as appropriate, either as a combined system or, in part, as separate components, devices, and systems. Thus, each embodiment disclosed herein may be incorporated into each aspect to greater or lesser extents, as appropriate for a given implementation.

[0005] These and other features of the applicants' teachings are set forth herein. [Brief description of the drawings]

[0006] Unless otherwise specified, the accompanying drawings illustrate aspects of the innovations described herein. Referring to the drawings, in which like numerals refer to like parts in the several views and throughout this specification, several embodiments of the presently disclosed principles are illustrated by way of example, and not by way of limitation. The drawings are not intended to be to scale. A more complete understanding of the present disclosure can be realized by reference to the accompanying drawings, in which:

[0007] [Figure 1] Block diagram of a conventional CMOS TDI image sensor.

[0008] [Diagram 2] FIG. 1 is a block diagram of a pixel binning CMOS TDI image sensor according to an exemplary embodiment of the present disclosure.

[0009] [Diagram 3] 3 is a detailed view of the image sensor of FIG. 2 according to an exemplary embodiment of the present disclosure.

[0010] [Figure 4A] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4B] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4C] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4D] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4E] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4F] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4G]4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4H] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. [Figure 4I] 4 is a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure.

[0011] [Diagram 5] 4A-4C are timing diagrams of the operation of a pixel binning apparatus according to an exemplary embodiment of the present disclosure.

[0012] [Figure 6] 4 is a logic flow diagram of a method of operation of a pixel binning apparatus in accordance with an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present disclosure is directed to implementing pixel binning in the charge domain of a CMOS TDI image sensor. Pixel binning is a technique that combines the charges collected by adjacent pixels. In some imaging applications, pixel binning achieves high speed or high sensitivity at the expense of the spatial resolution of the image sensor.

[0014] 1 is a block diagram of a conventional CMOS TDI image sensor 100. The conventional CMOS TDI image sensor 100 includes a number of pixel registers 102 arranged in a matrix and a number of corresponding column-parallel circuits 106a, 106b. Light-shielding regions 104a, 104b are provided at both ends of the pixel registers. The pixel registers 102 move pixel charges along each column of the matrix in either one TDI scanning direction indicated by an arrow A or the other TDI scanning direction indicated by an arrow A', and read out the charges to the corresponding column-parallel circuit 106a or 106b. A channel stop 108 separates the charges between adjacent columns 102a and 102b.

[0015] Due to this column-based structure, it is not possible to move charge across multiple columns in the charge region beyond the channel stops 108 for lateral binning (i.e., charge binning transverse to the longitudinal direction indicated by arrows A or A'). Thus, the binning operation is performed digitally in conventional CMOS TDI image sensors. However, digital binning is inferior to charge binning in terms of signal-to-noise ratio because it is not a noiseless summation.

[0016] 2 is a CMOS TDI image sensor 200 employing pixel binning in the charge domain according to an exemplary embodiment of the present disclosure. The image sensor 200 includes a first pixel binning device 202a and a second pixel binning device 202b, which are inserted in the first light-shielding region 104a and the second light-shielding region 104b of the image sensor 200, respectively.

[0017] In one general aspect of the present disclosure, the first pixel binning device 202a comprises a first transfer gate 302a arranged along a row and coupled to one end of the plurality of pixel registers 102 (i.e., row 110), a first plurality of binning registers 304a coupled to the first transfer gate 302a, a plurality of second transfer gates 306 coupled to the first plurality of binning registers 304a, and a first row of a plurality of first storage registers 308a coupled to the plurality of second transfer gates 306. These configurations are shown in more detail in FIG.

[0018] In one general aspect of the present disclosure, the second pixel binning device 202b comprises a third transfer gate arranged along the row and coupled to the other end of the plurality of pixel registers 102, a second plurality of binning registers coupled to the third transfer gate, a plurality of fourth transfer gates coupled to the second plurality of binning registers, and a first row of a plurality of second storage registers coupled to the plurality of fourth transfer gates.

[0019] 3 is a detailed diagram 300 of an image sensor 200 showing a plurality of pixel registers 102 and a first pixel binning device 202a for a four-times binning operation according to an exemplary embodiment of the present disclosure. The first pixel binning device 202a comprises a row of a first transfer gate 302a (TG1) coupled between a first row 110 of the plurality of pixel registers 102 and four columns of a binning register 304a. A second transfer gate group 306 (TG2) comprising a first second transfer gate 306a (TG2-1), a second second transfer gate 306b (TG2-2), a third second transfer gate 306c (TG2-3), and a fourth second transfer gate 306d (TG2-4) is coupled between the binning register 304a and a first row of a storage register 308a. The binning register 304a, which is oriented orthogonal to the plurality of pixel registers 102, does not have a channel stop 108. This structure allows the binning register 304a to transfer charge laterally relative to the pixel registers 102, as shown by arrows B and B' in Figure 2. In various embodiments, the second group of transfer gates 306 can include more or fewer second transfer gates for more, fewer, or more binning times.

[0020] 4A-4I show a detailed operation sequence of a pixel binning device for four-times binning according to an exemplary embodiment of the present disclosure. Now, referring to FIG. 4A in conjunction with FIG. 2 and FIG. 3, the first pixel binning device 202a comprises a first transfer gate 302a coupled to a first row 110 of the plurality of pixel registers 102, four columns of a binning register 304a coupled to the first transfer gate 302a, a group of four second transfer gates 306 coupled to the four columns of the binning register 304a, and a storage register 308a coupled to the group of four second transfer gates 306.

[0021] 4A, a first row 110 of the plurality of pixel registers 102 stores charges (a, b, c, d) in each pixel register. A first transfer gate 302a is clocked low (shown by the thick solid line) to store the charge in the pixel register.

[0022] In the second phase shown in Figure 4B, the first transfer gate 302a is clocked high (indicated by the thick dashed line) to move the charges (a, b, c, d) from each of the pixel registers 102 down to the corresponding binning register 304a. The first row 110 receives the next charges (e, f, g, h) for each pixel. The first transfer gate 302a is clocked low to hold the charges (e, f, g, h) in the first row 110 until the binning operation illustrated in Figures 4C-4I is completed.

[0023] 4C, the first second transfer gate 306a is clocked high to transfer the first charge (a) stored in the first binning register above the first second transfer gate 306a to the storage register 308a below the first second transfer gate 306a. The second second transfer gate 306b, the third second transfer gate 306c, and the fourth second transfer gate 306d are clocked low to store the remaining charges (b, c, d) in the remaining binning registers 304a, respectively.

[0024] In the fourth stage shown in Figure 4D, the binning register 304a shifts the remaining charges (b, c, d) stored in the binning register 304a laterally by one column. The binning register 304a does not have a channel stop 108 to prevent the charges from being shifted. The second charge (b) is now located in the first column of the binning register 304a.

[0025] 4E, the first second transfer gate 306a transfers the second charge (b) to the storage register 308a. The first charge (a) and the second charge (b) are added (a+b) in the storage register 308a. The second second transfer gate 306b, the third second transfer gate 306c, and the fourth second transfer gate 306d are clocked low to store the remaining charges (c, d) in the remaining binning registers 204b, respectively.

[0026] In the sixth stage illustrated in Figure 4F, the binning register 304a shifts the remaining charges (c, d) stored in the binning register 304a laterally by one column. The third charge (c) is now located in the first column of the binning register 304a.

[0027] 4G, the first second transfer gate 306a transfers the third charge (c) to the storage register 308a. The first charge (a), the second charge (b), and the third charge (c) are summed (a+b+c) in the storage register 308a. The second second transfer gate 306b, the third second transfer gate 306c, and the fourth second transfer gate 306d are clocked low to store the remaining charge (d) in the binning register 304a.

[0028] In the eighth stage illustrated in Figure 4H, the binning register 304a shifts the remaining charges (d) stored in the binning register 304a laterally by one column. The fourth charge (d) is now located in the first column of the binning register 304a.

[0029] In the ninth step shown in FIG. 4I, the first second transfer gate 306a transfers a fourth charge (d) to the storage register 308a. The first charge (a), the second charge (b), the third charge (c), and the fourth charge (d) are summed (a+b+c+d) in the storage register 308a. The second second transfer gate 306b, the third second transfer gate 306c, and the fourth second transfer gate 306d are clocked low. This completes four binning operations.

[0030] The steps described in relation to Figures 4A-4I are repeated for the next column of charges (e, f, g, h), etc.

[0031] The steps illustrated in Figures 4A-4I are exemplary of four-times binning. In general, for n-times binning, a first row of transfer gates moves a row of charge from a number of pixel registers to a number of binning registers. The first of every n transfer gates of the second transfer gates moves the charge stored in the first binning register to a storage register below the first second transfer gate while retaining the remainder of the charge in the binning register. The binning register then shifts the remaining row of charge horizontally by one column. The process of moving to the storage register and shifting horizontally is repeated a total of n-1 times to sum the n columns of charge.

[0032] When binning is disabled, only the first phase (310a, 310b, 310c, 310d, 310e) of the binning registers between adjacent binning register columns is clocked low, while a row of signal charge from the multiple pixel registers is moved through the multiple binning registers by a row of first transfer gates and then to a row of storage registers by a multiple second transfer gates.

[0033] 5 is a timing diagram 500 of an n-times binning operation of a pixel binning apparatus according to an exemplary embodiment of the present disclosure. Referring now to FIG. 5 in conjunction with FIGS. 2, 3, and 4A-4I, a row of first transfer gates (TG1) has a timing waveform 530. When the first transfer gates (TG1) are clocked high, a row of charges stored in a first row of the plurality of pixel registers is transferred to the plurality of binning registers. The first transfer gates (TG1) are then clocked low to hold the next row of charges in the first row of the plurality of pixel registers.

[0034] 5, along with FIGS. 2, 3, and 4A-4I, the first second transfer gate (TG2-1) has a timing waveform 532. The remaining second transfer gates (TG2-2, TG2-3, ..., TG2-n) have a timing waveform 534. After the row of charges has been transferred to the multiple binning registers, the first second transfer gate (TG2-1) is clocked high to transfer the first charges from the first binning register down to the storage register, and the remaining second transfer gates (TG2-2, TG2-3, ..., TG2-n) are clocked low.

[0035] After the charges in the binning column above the first second transfer gate (TG2-1) are transferred to the storage register, the first second transfer gate (TG2-1) is clocked low. The binning register transfers the remaining charges laterally by one column. The charge transfer to the storage register and the lateral transfer of the remaining charges is repeated n times. The whole process is then repeated with the next plurality of charges.

[0036] FIG. 6 is a logic flow diagram 600 of a method of operating a pixel binning device according to an exemplary embodiment of the present disclosure. Referring now to FIG. 6 in conjunction with FIGS. 2-5, in the method 600 of operating a pixel binning device, a first row of transfer gates transfers a row of charges from a plurality of pixel registers to a plurality of binning registers (602). Then, in the method 600 of pixel binning, one of every N of the second transfer gates transfers only the first charge from the binning register coupled to the second transfer gate to a storage register coupled to the second transfer gate and holds the remaining charge in the remaining binning register (604). In the method 600 of operating a pixel binning device, the first charge is stored in the storage register (606) and the remainder of the charges in the binning registers are shifted by one column (608). According to the method 600 of operating a pixel binning device, the second transfer gate transfers only the second charge from the binning register coupled to the second transfer gate to a storage register coupled to the second transfer gate and retains the remainder of the charge in the remaining portion of the binning register (610). The first charge and the second charge are added to generate a sum of the charges (612). According to the method 600 of operating a pixel binning device, the final steps of transferring (610) and adding (612) are repeated (614) until n bins have been achieved.

[0037] In one embodiment, according to a method 600 of operating a pixel binning apparatus, a row of first transfer gates is coupled to a first end of a plurality of pixel registers and another row of first transfer gates is coupled to a second end of the plurality of pixel registers. The method 600 of operating a pixel binning apparatus is performed using one of two rows of first transfer gates depending on the direction of TDI scan for bidirectional operation.

[0038] Thus, although certain aspects and embodiments of the technology of the present application have been described, it will be appreciated that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be within the scope of the technology described in the present application. Accordingly, the foregoing embodiments are presented by way of example only, and it will be understood that, within the scope of the appended claims and their equivalents, the embodiments of the present invention may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, and / or methods described herein is included within the scope of the present disclosure, if such features, systems, articles, materials, and / or methods are not mutually inconsistent.

[0039] Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable manner. Thus, what may be shown as sequential acts in an example embodiment may include some acts being performed simultaneously, and embodiments may be constructed in which acts are performed in an order different than that shown.

[0040] In the claims and in the specification above, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," "composed of," and the like, are to be understood to be open-ended, i.e., to mean including, but not limited to, and the transitional phrases "consisting of" and "consisting essentially of" are to be closed-ended or semi-closed-ended transitional phrases, respectively.

Claims

1. a first row of transfer gates coupled to a first row of the plurality of pixel registers; a plurality of binning registers coupled to the first transfer gate; a plurality of second transfer gates coupled to the plurality of binning registers; a row of storage registers coupled to the plurality of second transfer gates. Pixel binning device.

2. The pixel binning apparatus of claim 1 , wherein the binning registers are orthogonal to the pixel registers.

3. 2. The pixel binning apparatus of claim 1, wherein channel stops disposed between adjacent pixel registers of the plurality of pixel registers are not present in the binning register.

4. A plurality of pixel registers arranged in a matrix; a first binning device coupled to one end of the plurality of pixel registers; a second binning device coupled to the other end of the plurality of pixel registers; Image sensor.

5. The image sensor of claim 4 , wherein the first binning device and the second binning device are disposed in a light-shielded region of the image sensor.

6. 5. The image sensor of claim 4, wherein the image sensor is a charge-domain CMOS time-delay-integration (TDI) image sensor.

7. 1. A method of pixel binning comprising the steps of: a transferring step of transferring rows of charges from a plurality of pixel registers to a plurality of binning registers by a first row of transfer gates, the binning being effective for n pixel columns; a holding step of moving only one first charge from every n of a plurality of second transfer gates from a binning register coupled to the second transfer gate to a storage register coupled to the second transfer gate and holding the remaining charges in the remainder of the binning registers; storing the first charge in the storage register; a shifting step of shifting the charges remaining in the binning register by one column; a second holding step of moving only a second charge by the second transfer gate from the binning register coupled to the second transfer gate to the storage register coupled to the second transfer gate and holding the remaining charge in the remainder of the binning register; adding the first charge and the second charge to generate a total charge; and repeating the shifting and adding until n binnings are achieved. method.

8. a second transfer step of transferring rows of signal charges from the plurality of pixel registers to the plurality of binning registers by the first row of transfer gates; 8. The method of claim 7, further comprising a third transfer step of disabling binning by causing the plurality of second transfer gates to transfer rows of charge from the plurality of binning registers to rows of the storage register.

9. the first row of transfer gates is coupled to a first end of the plurality of pixel registers; another row of the first transfer gates is coupled to a second end of the plurality of pixel registers; 8. The method of claim 7, wherein the method is performed using either the first row of transfer gates or another row of the first transfer gates depending on a direction of a TDI scan for bidirectional operation.

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