System and method for tuning to reduce reflected power in multiple states

Abstract

To provide a system and a method for tuning to reduce reflected power in multiple states.SOLUTION: A method includes determining values of one or more parameters of an impedance matching circuit such that reflected power is reduced for multiple states, and such reduction in reflected power extending the life of a radio frequency generator connected to the impedance matching circuit while processing the substrate using the plurality of conditions.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present embodiments relate to systems and methods for tuning to reduce reflected power in multiple states. [Background technology]

[0002] Generally, a plasma tool includes a radio frequency generator, an impedance matching network, and a plasma chamber. The radio frequency generator provides power to the plasma chamber through an impedance matching network. When power is provided, one or more gases are also provided to the plasma chamber to generate a plasma in the plasma chamber. The plasma is used for various cleaning and other operations performed on the wafer in the plasma chamber.

[0003] However, when power is applied, the power of the plasma is reflected back towards the RF generator, which generates standing waves on the transmission line between the source and the load, which can lead to damage to the output drive of the RF generator.

[0004] It is against this background that the embodiments described in this disclosure arise. Summary of the Invention

[0005] The embodiments of the present disclosure provide a system and method for tuning to reduce reflected power in multiple states. It should be appreciated that the embodiments can be embodied in numerous forms, such as a process, an apparatus, a system, a device, or a method recorded on a computer readable medium. Some embodiments are described below.

[0006] During semiconductor plasma processing, the applied radio frequency (RF) power is pulsed at a frequency between 1 Hertz and 50 kilohertz. A tuned matching network is utilized to couple the RF power to the plasma to ensure efficient coupling between the RF generator and the plasma. During continuous wave (CW) or single level pulsing, the matching network is fixed. However, in some instances, two or more levels of pulsing are utilized, in which case two or more matching network positions, e.g., capacitor values, inductor values, etc., are used. The matching network uses variable reactive components, e.g., capacitors and inductors. These variable reactive components have mechanical components, which move slowly compared to multi-level pulsing. The slow response of the mechanical components makes it difficult to keep up with the multiple power levels of multi-level pulsing. This can be partially mitigated by using frequency tuning between the multiple power levels. However, frequency tuning alone cannot accommodate widely differing power levels. The method and system describes how to optimize the matching network positions to maximize matching efficiency across a process for multi-level pulsing. The matching efficiency is improved and the power reflected back towards the RF generator is reduced. The average reflected RF power towards the RF generator is reduced, allowing for a wider operating space.

[0007] In some embodiments, a method for tuning to reduce reflected power in multiple states is described. The method comprises providing power by an RF generator during a first state of a digital pulse signal to a plasma chamber through an impedance matching circuit. The method further comprises measuring an amount of power reflected back to an output of the RF generator during the first state. The method comprises providing power by the RF generator during a second state of the digital pulse signal to the plasma chamber through an impedance matching circuit. The method further comprises measuring an amount of power reflected back to an output of the RF generator during the second state. The method comprises controlling parameters of the impedance matching circuit to reduce an amount of power measured during the first state to a minimum value and to reduce an amount of power measured during the second state to a minimum value.

[0008] In various embodiments, a system for tuning to reduce reflected power in a plurality of states is described. The system includes an RF generator configured to provide power during a first state of a digital pulse signal. The system further includes an impedance matching circuit connected to the RF generator via an RF cable and a plasma chamber connected to the impedance matching circuit via an RF transmission line. The system includes a sensor connected to an output of the RF generator. The sensor is configured to measure an amount of power reflected back to the output of the RF generator during the first state. The RF generator is configured to provide power during a second state of the digital pulse signal through the impedance matching circuit to the plasma chamber. The sensor is configured to measure an amount of power reflected back to the output of the RF generator during the second state. The system includes a processor connected to a parameter of the impedance matching circuit to control the parameter. The parameter is controlled to reduce an amount of power measured during the first state to a minimum value and to reduce an amount of power measured during the second state to a minimum value.

[0009] In various embodiments, a non-transitory computer readable medium storing a program that causes a computer to execute a method is described. The method includes providing power by an RF generator during a first state of a digital pulse signal to a plasma chamber through an impedance matching circuit. The method further includes receiving a measurement of an amount of power reflected back to an output of the RF generator during the first state. The method includes providing power by the RF generator during a second state of the digital pulse signal to the plasma chamber through an impedance matching circuit. The method includes receiving a measurement of an amount of power reflected back to an output of the RF generator during the second state. The method includes controlling a parameter of the impedance matching circuit to reduce the amount of power measured during the first state to a minimum value and to reduce the amount of power measured during the second state to a minimum value.

[0010] Some advantages of the systems and methods described herein for tuning to reduce reflected power in the multiple states. For example, if the series circuit of the impedance matching circuit has a value A and / or the shunt circuit of the impedance matching circuit has a value B, the power reflected towards the RF generator is reduced for the multiple states S0, S1, S2, S3, etc., compared to the power reflected towards the RF generator for any one of the states S0, S1, S2, S3, etc., where the series circuit has a value C and / or the shunt circuit has a value D. Such reduction in reflected power for the multiple states extends the life of the RF generator to which the power is reflected. Additionally, the multiple states are utilized to perform various operations on the substrate. For example, during one of the multiple states, a material (such as an oxide) is deposited on the substrate, and during another of the multiple states, the substrate or material is etched. As another example, during one of the multiple states, a deposition operation is performed on the substrate, and during another of the multiple states, the substrate is cleaned. As yet another example, during one of the states, a deposition operation is performed on the substrate, during another of the states, the substrate is cleaned, and during yet another of the states, an etching operation is performed on the substrate. If the impedance match circuit has values ​​A and B and power is reduced in the states, various operations are performed on the substrate while protecting the RF generator components.

[0011] Also, the efficiency of the impedance matching circuit is improved as the reflected power is reduced for states S0, S1, S2, S3, etc. The impedance matching circuit allows a higher amount of power to be delivered to the plasma chamber when the series circuit of the impedance matching circuit has a value A and / or the shunt circuit of the impedance matching circuit has a value B. The delivery of a higher amount of power is important for the low amplitude RF signal delivered by the RF generator.

[0012] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0013] The embodiments are best understood by reference to the following description taken in conjunction with the accompanying drawings.

[0014] [Figure 1A] FIG. 1 illustrates an embodiment of a system illustrating the determination of series and shunt circuit parameters to reduce power reflected toward a x megahertz (MHz) radio frequency (RF) generator at multiple states S(n-N) to S(n).

[0015] [Figure 1B] FIG. 1 is a diagram of one embodiment of a system for illustrating the reduction of reflected power to an x ​​MHz RF generator and the reduction of reflected power to a y MHz RF generator in states S(nN) to S(n).

[0016] [Figure 1C] A diagram of one embodiment of a system for illustrating the reduction of reflected power to the x MHz RF generator, the reduction of reflected power to the y MHz RF generator, and the reduction of reflected power to the z MHz RF generator in states S(nN) to S(n).

[0017] [Figure 2A] FIG. 2 shows a graph of a digital pulse signal and a graph of an RF signal provided by an RF generator to illustrate two states of the RF signal.

[0018] [Figure 2B] FIG. 2 illustrates an embodiment of a graph of an RF signal having three states.

[0019] [Figure 2C] FIG. 2 illustrates an embodiment of a graph of an RF signal having four states.

[0020] [Figure 3A] FIG. 1 is a diagram of one embodiment of a system to illustrate control of series and shunt circuits of an impedance matching circuit during states S(nN) through S(n).

[0021] [Figure 3B] FIG. 1 is a diagram of one embodiment of a system to illustrate control of series and shunt circuits during states S(nN) through S(n).

[0022] [Figure 3C] FIG. 1 illustrates an embodiment of a system for illustrating an impedance matching circuit with any number of series circuits and any number of shunt circuits.

[0023] [Figure 3D] FIG. 1 is a diagram of one embodiment of a system to illustrate an impedance matching circuit that is an L-network.

[0024] [Figure 3E] FIG. 1 is a diagram of one embodiment of a system to illustrate an impedance matching circuit that is a π network.

[0025] [Figure 3F] FIG. 1 illustrates an embodiment of a system for illustrating an impedance matching circuit that is a π network including two L networks.

[0026] [Figure 4] FIG. 13 is a diagram of one embodiment of a method to illustrate the determination of values ​​of one or more parameters of an impedance matching circuit at which the power reflected back to the RF generator is reduced for states S(nN) to S(n).

[0027] [Figure 5A] FIG. 13 is a diagram for explaining a method for determining the capacitance Cseries of the series circuit of the impedance matching circuit and the capacitance Cshunt of the shunt circuit of the impedance matching circuit in order to reduce the reflected power at the output of the RF generator for states S(nN) to S(n).

[0028] [Figure 5B]FIG. 1 illustrates an embodiment of a graph to explain the technical advantage of applying a tuning method to reduce reflected power in states S(nN) to S(n).

[0029] [Figure 6] FIG. 1 illustrates an embodiment of a machine learning network for determining values ​​of one or more parameters that minimize the values ​​of variables for states S(nN) through S(n). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The following embodiments describe tuning systems and methods for reducing reflected power in multiple states. It will be apparent that the embodiments may be practiced without some or all of these specific details. Additionally, detailed descriptions of well-known process operations have been omitted in order to avoid unnecessarily obscuring the embodiments.

[0031] 1A is a diagram of one embodiment of a system 100 illustrating the determination of parameters of a series circuit 102 and a shunt circuit 104 to reduce power reflected back toward an x ​​megahertz (MHz) radio frequency (RF) generator. The system 100 includes an x ​​megahertz RF generator, an impedance matching circuit (IMC) 106, a plasma chamber 108, a host computer 110, a motor M1, a motor M2, a driver (DRVR) D1, and a driver D2.

[0032] An example of a x megahertz RF generator is a 2 MHz RF generator. The impedance matching circuit 106 comprises one or more series circuits, e.g., the series circuit 102, and one or more shunt circuits, e.g., the shunt circuit 104. The output of each shunt circuit is connected to ground, e.g., zero potential, non-zero reference potential, etc. Each shunt circuit or each series circuit comprises one or more electrical components, e.g., one or more capacitors, or one or more resistors, or one or more inductors, or a combination of one or more capacitors and one or more resistors, or a combination of one or more capacitors and one or more inductors, or a combination of one or more resistors and one or more inductors, or a combination of one or more capacitors, one or more resistors and one or more inductors. Some of the one or more electrical components are connected to each other in series or parallel. An end of the series circuit 102 is connected to an input 132 of the impedance matching circuit 106, and another end of the series circuit 102 is connected to an output 134 of the impedance matching circuit 106. Furthermore, an end of the shunt circuit 104 is connected to the series circuit 102 and the output 134 of the impedance matching circuit 106, and another end of the shunt circuit 104 is connected to ground.

[0033] The plasma chamber 108 includes a chuck 110, e.g., an electrostatic chuck (ESC), on which a substrate 112 is disposed, an upper electrode 114, and other components (not shown), such as an upper dielectric ring surrounding the upper electrode 114, an upper electrode extension surrounding the upper dielectric ring, a lower dielectric ring surrounding a lower electrode of the chuck 110, a lower electrode extension surrounding the lower dielectric ring, an upper plasma exclusion zone (PEZ) ring, a lower PEZ ring, etc. Examples of the substrate 112 include wafers on which integrated circuits have been or are to be processed. Each of the upper electrode 114 and the chuck 110 is formed of a metal, e.g., aluminum, an aluminum alloy, copper, a combination of copper and aluminum, etc.

[0034] Examples of the host computer 110 include a desktop computer, a laptop computer, a tablet, a smartphone, etc. The host computer 110 includes one or more processors, such as the processor 116, and one or more memory devices, such as the memory device 118. A processor, as used herein, is an application specific integrated circuit (ASIC), a programmable logic device, a microprocessor, or a central processing unit (CPU). Furthermore, a memory device, as used herein, is a random access memory (RAM), a read only memory (ROM), or a combination of RAM and ROM. Examples of motors described herein include electric machines that convert electrical energy into mechanical energy. For example, the motor includes a rotor and a stator. The rotor rotates when an electric current is supplied to the windings of the stator to convert electrical energy into mechanical energy. Examples of drivers described herein include one or more transistors that generate a current signal upon receiving a control signal from the processor 116.

[0035] The x megahertz RF generator is connected to the impedance matching circuit 106 via an RF cable 126. The impedance matching circuit 106 is further connected to the chuck 110 via an RF transmission line 128. The RF transmission line 128 is an RF cylinder, e.g., a tunnel. Within the cavity of the RF cylinder are an insulator and an RF rod. The RF rod is surrounded by an insulator, which is surrounded by the RF cylinder.

[0036] The x megahertz RF generator comprises a control system 120, a sensor 122, and an RF power supply 124. Examples of the control system described herein include one or more power controllers, one or more automatic frequency regulators (AFTs), or a combination of one or more power controllers and one or more automatic frequency regulators. The control system further comprises a digital signal processor (DSP) connected to the one or more power controllers and the one or more automatic frequency regulators. Examples of the sensors described herein include a power sensor, or a complex voltage and current sensor. Examples of the RF power supply described herein include a driver and an RF oscillator connected to each other. Upon receiving a current signal from the driver, the RF oscillator generates a high frequency oscillating signal (e.g., a sinusoidal RF signal).

[0037] The sensors described herein are connected to the processor 116 via a data cable, such as a serial transfer cable, a parallel transfer cable, or a Universal Serial Bus (USB) cable. Similarly, the control systems described herein (e.g., the control system's DSP) are connected to the processor 116 via a data cable. The motors described herein are connected to a series or shunt circuit via one or more connection mechanisms, such as one or more rods, a combination of one or more rods and one or more gears, etc.

[0038] The processor 116 generates a digital pulse signal 130 and provides the digital pulse signal 130 to the control system 120. The digital pulse signal 130 has two or more states (e.g., state S(nN) to state S(n)), where n is an integer equal to or greater than 1, N is also an integer equal to or greater than 1, and n is greater than N. For example, if S(n) is S2, then S(nN) is S1. As another example, if S(n) is S3, then S(nN) is S1, and there is an intermediate state S2 between the two states S1 and S3.

[0039] The control system 120, e.g., a DSP, receives the digital pulse signal 130 and determines whether the digital pulse signal 130 has a state S(nN) or a state S(n) based on the logic level of the digital pulse signal 130. For example, the state S(nN) has a logic level 0, and the state S(n) has a logic level 1. As another example, the state S0 has a logic level L1, the state S1 has a logic level L2, the state S2 has a logic level L3, and the state S3 has a logic level L4. The logic level L4 is greater than the logic level L3, and the logic level L3 is greater than the logic level L2. The logic level L2 is greater than the logic level L1.

[0040] Upon determining that the state of the digital pulse signal 130 is S(nN), the control system 120 identifies a power level for state S(nN) and a frequency level for state S(nN) and provides the power level and frequency level to the RF power supply 124. For example, the controller for state S(nN) in the power controller identifies a power level for state S(nN) and provides the power level to the RF power supply 124 upon receiving an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(nN). Further, in this example, the adjuster for state S(nN) in the automatic frequency adjuster identifies a frequency level for state S(nN) and provides the frequency level to the RF power supply 124 upon receiving an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(nN). As an example, the power level and frequency level for state S(nN) are received by the control system 120 from the processor 116. Upon receiving the power and frequency levels for state S(nN), RF power supply 124 generates an RF signal having the power and frequency levels for state S(nN) and provides the RF signal for state S(nN) to impedance matching circuit 106 via output 136 and RF cable 126. Output 136 is the output of the x MHz RF generator.

[0041] Similarly, upon determining that the state of the digital pulse signal 130 is S(n), the control system 120 identifies a power level for state S(n) and a frequency level for state S(n) and provides the power level and frequency level to the RF power supply 124. For example, the controller for state S(n) in the power controller identifies a power level for state S(n) and provides the power level to the RF power supply 124 upon receiving an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(n). Further, in this example, the adjuster for state S(n) in the automatic frequency adjuster identifies a frequency level for state S(n) and provides the frequency level to the RF power supply 124 upon receiving an indication from the digital signal processor of the control system 120 that the state of the digital pulse signal 130 is S(n). As an example, the power level and frequency level for state S(n) are received by the control system 120 from the processor 116. Upon receiving the power level and frequency level for state S(n), RF power supply 124 generates an RF signal having a power level and frequency level for state S(n) and transmits the RF signal for state S(n) to impedance matching circuit 106 via RF cable 126.

[0042] When an RF signal for state S(nN) is received by impedance matching circuit 106 from the x MHz RF generator, impedance matching circuit 106 matches the impedance of a load connected to output 134 of impedance matching circuit 106, e.g., RF transmission line 128 and plasma chamber 108, with the impedance of a source connected to input 132 of impedance matching circuit 106, e.g., RF cable 126 and the x megahertz RF generator. Impedance matching circuit 106 matches the impedance to produce a modulated RF signal for state S(nN) that is provided from impedance matching circuit 106 to chuck 110 via output 134 and RF transmission line 128.

[0043] Similarly, when an RF signal for state S(n) is received by the impedance matching circuit 106 from the x MHz RF generator, the impedance matching circuit 106 matches the impedance of a load connected to an output 134 of the impedance matching circuit 106 with the impedance of a source connected to an input 132 of the impedance matching circuit 106. The impedance matching circuit 106 matches the impedance to produce a modulated RF signal for state S(n) that is provided from the impedance matching circuit 106 to the chuck 110 via the RF transmission line 128.

[0044] When the modulated RF signal is provided to the chuck 110, one or more process gases are provided to the plasma chamber 108 for processing the substrate 112. Examples of process gases include oxygen-containing gases and fluorine-containing gases. Examples of fluorine-containing gases include tetrafluoromethane (CF4), sulfur hexafluoride (SF6), hexafluoroethane (C2F6), and the like. When the modulated RF signal is provided to the chuck 110 and one or more process gases are provided to the plasma chamber 108, for example, through one or more holes in the upper electrode 114, a plasma is ignited in the plasma chamber 108, and the plasma is used to process the substrate 112. Examples of processing the substrate 112 include etching the substrate 112, depositing a material, such as an oxide layer, a metal layer, a copper layer, and the like, on the substrate 112, sputtering the substrate 112, cleaning the substrate 112, and the like, for fabricating one or more integrated circuit chips on the substrate 112.

[0045] During state S(nN), the sensor 122 connected to the x MHz RF generator output 136 senses the values ​​of variables, such as complex voltages and currents, complex power, complex reflected power, etc. Reflected power is the power reflected from the plasma in the plasma chamber 108, through the RF transmission line 128, the impedance match circuit 106, and the RF cable 126, towards the x MHz RF generator output 136. Similarly, during state S(n), the sensor 122 senses the values ​​of variables.

[0046] Values ​​of the sensed variables during states S(nN) through S(n) (e.g., multiple occurrences of states S(nN) through S(n), multiple cycles of states S(nN)) and S(n), multiple occurrences of states S(nN) and S(n), etc.) are continuously provided from sensor 122 to processor 116 via data cable. Processor 116 determines values ​​of one or more parameters of one or more electrical components of impedance matching circuit 106 from the sensed variables during states S(nN) through S(n) until the reflected power is simultaneously reduced for states S(nN) through S(n) compared to the reflected power being reduced for one of states S(nN) through S(n) but not reduced for the other of states S(nN) through S(n). For example, the values ​​of the one or more parameters are determined such that the amount of power reflected to the output 136 for all states S(nN)-S(n) is less than the amount of power reflected to the output 136 for any one of the states S(nN)-S(n). To further explain, if the capacitance value of the series circuit 102 is C1 and the capacitance value of the shunt circuit 104 is C2, the amount of power reflected toward the output 136 during state S1 is Pr1. However, if the same values ​​of C1 and C2 are used for state S2, the amount of power reflected toward the output 136 during state S2 is Pr2, which is substantially greater than Pr1. The same values ​​of C1 and C2 are used due to physical limitations of one or more electrical components, e.g., capacitors, inductors, etc., whose values ​​cannot be changed as quickly as the states S(nN)-S(n) change. The components are components of the impedance matching circuit 106. When the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 106, e.g., the value C3 of the parameter of the series circuit 102 and the value C4 of the parameter of the shunt circuit 104, are determined from the variables sensed during the states S(nN) to S(n) such that the reflected power is simultaneously reduced for the states S(nN) to S(n), the reflected power is a power of an amount Pr3. The value Pr3 is less than the value Pr2 but greater than the value Pr1. In some embodiments, the value Pr3 is less than or equal to the value Pr1. Examples of parameters include inductance and capacitance.

[0047] As another example, if the capacitance value of the series circuit 102 is C1 and the capacitance value of the shunt circuit 104 is C2, the amount of power reflected toward the output 136 during state S1 is Pr1. The value Pr1 is a minimum value, as described in more detail below, for state S1. Furthermore, if the capacitor value of the series circuit 102 is C5 and the capacitor value of the shunt circuit 104 is C6, the amount of power reflected toward the output 136 during state S2 is Pr4. The value Pr4 is a minimum value, as described in more detail below, for state S2. The average of the values ​​C1 and C5 is used as the capacitance for the series circuit 102 for states S1 and S2. Furthermore, the average of the values ​​C2 and C6 is used as the capacitance for the series circuit 102 for states S1 and S2. For the average of the values ​​C1 and C5 and the average of the values ​​C2 and C6, the power reflected toward the x MHz RF generator is reduced for states S1 and S2.

[0048] As yet another example, if values ​​of one or more parameters of the impedance matching circuit 106 (e.g., the value C3 of the parameter of the series circuit 102 and the value C4 of the parameter of the shunt circuit 104) are determined from variables sensed during states S(nN) to S(n) such that the reflected power is simultaneously reduced for states S(nN) to S(n), the reflected power is a power of an amount Pr3 for state S(nN) and a power of an amount Pr4 for state S(n). The value Pr3 is the minimum value for state S(nN) among the values ​​of the reflected power for state S(nN). The multiple values ​​of the reflected power for state S(nN) are achieved when the frequency of the x MHz RF generator and / or the power of the RF signal supplied by the x MHz RF generator are changed during state S(nN). The value Pr4 is the minimum value for state S(n) among the values ​​of the reflected power for state S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the x MHz RF generator and / or the power of the RF signal provided by the x MHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of the minimum values ​​are less than a predetermined level of reflected power. In some embodiments, the terms predetermined level and predetermined limit are used interchangeably herein. Value Pr2 is greater than the predetermined level and value Pr1 is less than the predetermined level.

[0049] During states S(nN) to S(n), the processor 116 transmits a control signal to the driver D1 indicative of a value of the parameter for states S(nN) to S(n) and continues to transmit until the reflected power decreases at the output 136 for states S(nN) to S(n). Upon receiving the control signal, the motor M1 rotates to change the value of the parameter of the series circuit 102 via one or more connection mechanisms connecting the motor M1 to the series circuit 102. Similarly, during states S(nN) to S(n), the processor 116 transmits a control signal to the driver D2 indicative of a value of the parameter for states S(nN) to S(n) and continues to transmit until the reflected power decreases at the output 136 for states S(nN) to S(n). Upon receiving the control signal, the motor M2 rotates to change the value of the parameter of the shunt circuit 104 via one or more connection mechanisms connecting the motor M2 to the shunt circuit 104.

[0050] The reduction in reflected power at output 136 extends the life of the x MHz RF generator. Reflected power can cause damage to components of the x MHz RF generator, such as the control system 120, the RF power supply 124, etc. The reduction in reflected power at output 136 for states S(nN) to S(n) reduces the likelihood of damage to the x MHz RF generator components, extending the life of the components.

[0051] In some embodiments, a y megahertz RF generator or a z megahertz RF generator is used instead of the x megahertz RF generator. An example of a y megahertz RF generator is a 27 MHz RF generator, and an example of a z megahertz RF generator is a 60 MHz RF generator. In various embodiments, an a kHz RF generator, for example a 400 kHz RF generator, is used instead of the x megahertz RF generator.

[0052] In various embodiments, instead of the digital pulse signal 130 being generated by the processor 116, a digital clock source is used to generate the digital pulse signal 130. The digital clock source may be located within or outside the host computer 110.

[0053] In some embodiments in which digital pulse signal 130 has more than two states, multiple clock sources are used to generate digital pulse signal 130. For example, to generate digital pulse signal 130 having more than two states, clock signals from multiple clock sources are summed, for example, by a summing circuit, processor 116, etc. The clock signals are out of phase with each other.

[0054] In various embodiments, a control signal is sent to the series circuit 102 for control but not to the shunt circuit 104 until the reflected power is reduced at the output 136 for states S(nN) to S(n). In various embodiments, a control signal is sent to the shunt circuit 104 for control but not to the series circuit 102 until the reflected power is reduced at the output 136 for states S(nN) to S(n).

[0055] In some embodiments, the sensors described herein are connected to the output of the RF generator and are located outside the RF generator.

[0056] In some embodiments, the terms minuma and minimum are used interchangeably herein.

[0057] 1B is a diagram of one embodiment of a system 150 for illustrating the reduction of reflected power to the x MHz RF generator and the y MHz RF generator for states S(nN) to S(n). The system 150 includes an x ​​MHz RF generator, a y MHz RF generator, a host computer 110, an impedance matching circuit 152, a plasma chamber 108, motors M1 and M2, drivers D1 and D2, a motor M3, a motor M4, a driver D3, and a driver D4. The impedance matching circuit 152 includes a series circuit 166 and a shunt circuit 168 connected together. The impedance matching circuit 152 also includes a series circuit 102 and a shunt circuit 104.

[0058] An output 158 ​​of the y MHz RF generator is connected to an input 160 of the impedance matching circuit 152 via an RF cable 162. The y MHz RF generator comprises a control system 152, an RF power supply 154, and a sensor 156. The sensor 156 is connected to an output 158 ​​of the y MHz RF generator. Furthermore, the sensor 156 is connected to the processor 116 via a data cable, and the processor 116 is connected to the control system 152 via a data cable.

[0059] The processor 116 is connected to a driver D3, which is connected to a motor M3. The motor M3 is connected to a series circuit 166 via one or more connection mechanisms. The processor 116 is further connected to a driver D4, which is connected to a motor M4. The motor M4 is connected to a shunt circuit 168 via one or more connection mechanisms.

[0060] An end of the series circuit 166 is connected to the input 160, and another end of the series circuit 166 is connected to the output 134. Furthermore, an end of a shunt circuit 168 is connected to the series circuit 166 and the output 134 of the impedance matching circuit 152, and another end of the shunt circuit 168 is connected to ground.

[0061] The processor 116 transmits the digital pulse signal 130 to the y MHz RF generator control system 152 via the data cable. Upon receiving the digital pulse signal 130, the control system 152 provides the power level and frequency level for state S(nN) to the RF power supply 154 in the manner described above in which the x MHz RF generator control system 120 provides the power level and frequency level for state S(nN) to the x MHz RF generator RF power supply 124. The RF power supply 154 generates an RF signal having a power level and frequency level for state S(nN) in the manner in which the x MHz RF generator RF power supply 124 generates an RF signal having a power level and frequency level for state S(nN). The RF power supply 154 provides the RF signal to an input 160 of the impedance matching circuit 152 via an RF cable 162.

[0062] Similarly, upon receiving the digital pulse signal 130, the control system 152 provides a power level and frequency level for state S(n) to the RF power supply 154 in the manner described above in which the x MHz RF generator's control system 120 provides a power level and frequency level for state S(n) to the x MHz RF generator's RF power supply 124. The RF power supply 154 generates an RF signal having a power level and frequency level for state S(n) in the manner in which the x MHz RF generator's RF power supply 124 generates an RF signal having a power level and frequency level for state S(nN). The RF power supply 154 provides the RF signal to an input 160 of the impedance matching circuit 152 via an RF cable 162.

[0063] When an RF signal for state S(nN) is received by impedance matching circuit 152 from the y MHz RF generator in addition to the RF signal for state S(nN) from the x MHz RF generator, impedance matching circuit 152 matches the impedance of a load, e.g., RF transmission line 128 and plasma chamber 108, connected to output 134 of impedance matching circuit 152 with sources, e.g., RF cable 126, the x megahertz RF generator, RF cable 162, and the y MHz RF generator, connected to inputs 132 and 160 of impedance matching circuit 152. Impedance matching circuit 152 matches the impedance and further combines, e.g., sums, the RF signals transmitted through branch 165 and branch 170 of impedance matching circuit 152 during state S(nN) to generate a modulated RF signal for state S(nN) that is provided from impedance matching circuit 152 to chuck 110 via output 134 and RF transmission line 128. The circuit 165 includes a series circuit 102 and a shunt circuit 104 .

[0064] Similarly, when an RF signal for state S(n) is received by the impedance matching circuit 152 from the y MHz RF generator in addition to the RF signal for state S(n) from the x MHz RF generator, the impedance matching circuit 152 matches the impedance of a load connected to the output 134 of the impedance matching circuit 152 with the impedance of a source connected to the inputs 132 and 160 of the impedance matching circuit 152. The impedance matching circuit 152 matches the impedance and further combines (e.g., sums) the RF signals transmitted through the branches 165 and 170 of the impedance matching circuit 152 during state S(n) to generate a modulated RF signal for state S(n) that is provided from the impedance matching circuit 152 to the chuck 110 via the output 134 and the RF transmission line 128. The substrate 112 is processed when the modulated RF signal is received from the impedance matching circuit 152 via the RF transmission line 128 in addition to one or more process gases.

[0065] During state S(nN), a sensor 156 connected to the output 158 ​​of the y MHz RF generator senses the value of a variable, e.g., reflected power, at the output 158. Reflected power is the power reflected from the plasma in the plasma chamber 108 through the RF transmission line 128, the branch circuit 170 with the series circuit 166 and the shunt circuit 168, and the RF cable 162 toward the output 158 ​​of the y MHz RF generator. Similarly, during state S(n), the sensor 156 senses the value of the variable reflected toward the output 158 ​​of the y MHz RF generator.

[0066] Values ​​of the sensed variables during the states S(nN)-S(n), e.g., multiple occurrences of states S(nN)-S(n), are continuously provided from the sensor 156 to the processor 116 via a data cable. The processor 116 determines values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 152 from the sensed variables during the states S(nN)-S(n) until the reflected power at the output 158 ​​of the y MHz RF generator is simultaneously reduced for the states S(nN)-S(n) compared to the reflected power that is reduced at the output 158 ​​for one of the states S(nN)-S(n) but not reduced for the other of the states S(nN)-S(n). For example, the values ​​of the one or more parameters are determined such that the amount of power reflected to the output 158 ​​of the y MHz RF generator for all states S(nN)-S(n) is less than the amount of power reflected to the output 158 ​​for any one of the states S(nN)-S(n). To further explain, if the capacitance value of the series circuit 166 is CA and the capacitance value of the shunt circuit 168 is CB, then an amount of power PrA is reflected toward the output 158 ​​of the y MHz RF generator during state S1. However, if the same values ​​of CA and CB are used for state S2, then the amount of power reflected toward the output 158 ​​during state S2 is PrB, which is substantially greater than PrA. If the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 152, e.g., the value CC of the parameter of the series circuit 166 and the value CD of the parameter of the shunt circuit 168, are determined from variables sensed by the sensor 156 during states S(nN)-S(n), such that the reflected power at the output 158 ​​is simultaneously reduced for states S(nN)-S(n), then the reflected power is a power of an amount PrC. The value PrC is less than the value PrB, but greater than the value PrA. In some embodiments, the value PrC is less than or equal to the value PrA.

[0067] As another example, if the values ​​of one or more parameters of the impedance matching circuit 152, e.g., the value CC of the parameter of the series circuit 166 and the value CD of the parameter of the branch circuit 168, are determined from variables sensed during states S(n-N) to S(n) such that the reflected power is simultaneously reduced for states S(n-N) to S(n), the reflected power is a power of an amount PrD for states S(n-N) and a power of an amount PrE for state S(n). The value PrD is the minimum value for state S(nN) among the values ​​of the reflected power for states S(nN). The multiple values ​​of the reflected power for state S(nN) are achieved when the frequency of the y MHz RF generator and / or the power of the RF signal provided by the y MHz RF generator are changed during state S(nN). The value PrD is the minimum value for state S(n) among the values ​​of the reflected power for states S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the y MHz RF generator and / or the power of the RF signal provided by the y MHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of the minimum values ​​are less than a predetermined level of reflected power. The value PrB is greater than the predetermined level and the value PrA is less than the predetermined level.

[0068] During states S(nN) to S(n), the processor 116 transmits a control signal to the driver D3 indicative of a value of a parameter for states S(nN) to S(n) and continues to transmit until the reflected power is reduced at the output 158 ​​of the y MHz RF generator for states S(nN) to S(n). Upon receiving the control signal, the motor M3 rotates to change the value of the parameter of the series circuit 166 via one or more connection mechanisms connecting the motor M3 to the series circuit 166. Similarly, during states S(nN) to S(n), the processor 116 transmits a control signal to the driver D4 indicative of a value of a parameter for states S(nN) to S(n) and continues to transmit until the reflected power is reduced at the output 158 ​​for states S(nN) to S(n). Upon receiving the control signal, the motor M4 rotates to change the value of the parameter of the shunt circuit 168 via one or more connection mechanisms connecting the motor M4 to the shunt circuit 168. The reduction in the reflected power at the output 158 ​​also extends the life of the y MHz RF generator.

[0069] In some embodiments, processor 116 simultaneously controls values ​​of one or more parameters of one or more of series circuit 102, shunt circuit 104, series circuit 166, and shunt circuit 168 until the reflected power at output 158 ​​is reduced for states S(nN) to a level that is within a predetermined range of the level at which the reflected power is reduced at output 136 for states S(nN) to S(n). For example, the value PrC at output 158 ​​is within a predetermined range of the value Pr3 of the reflected power at output 136.

[0070] In various embodiments, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 158 ​​is reduced for the states S(nN) to a level that is within a predetermined range from the level at which the reflected power is reduced at the output 136 for the states S(nN) to S(n). Further, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 136 and the reflected power at the output 158 ​​are less than the predetermined limit. For example, the value PrC at the output 158 ​​is within a predetermined range from the value Pr3 of the reflected power at the output 136, and the values ​​PrC and Pr3 are less than the predetermined limit of the reflected power. The predetermined range and the predetermined limit are stored in the memory device 118 for access by the processor 116.

[0071] In some embodiments, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 158 ​​is reduced for state S(nN) to a level that is within a predetermined range from the level at which the reflected power is reduced at the output 136 for state S(nN). Additionally, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 158 ​​is reduced for state S(n) to a level that is within a predetermined range from the level at which the reflected power is reduced at the output 136 for state S(n). For example, the value PrD at the output 158 ​​is within a predetermined range from the value Pr4 of the reflected power at the output 136, and the value PrE at the output 158 ​​is within a predetermined range from the value Pr5 of the reflected power at the output 136.

[0072] In various embodiments, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 158 ​​is reduced for state S(nN) to a level that is within a predetermined range from the level at which the reflected power would be reduced at the output 136 for state S(nN). Additionally, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 158 ​​is reduced for state S(n) to a level that is within a predetermined range from the level at which the reflected power would be reduced at the output 136 for state S(n). Further, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, and the shunt circuit 168 until the reflected power at the output 136 and the reflected power at the output 158 ​​are less than the predetermined limit. For example, the value PrD at the output 158 ​​is within a predetermined range of the value Pr4 of the reflected power at the output 136, and the values ​​PrD and Pr4 are less than the predetermined limit of the reflected power. Further, the value PrE at the output 158 ​​is within a predetermined range of the value Pr5 of the reflected power at the output 136, and the values ​​PrE and Pr5 are less than the predetermined limit of the reflected power.

[0073] 1C is a diagram of an embodiment of a system 180 for illustrating the reduction of reflected power to the x MHz RF generator, the y MHz RF generator, and the z MHz RF generator in states S(nN) to S(n). The system 180 includes the x MHz RF generator, the y MHz RF generator, the z MHz RF generator, a host computer 110, an impedance matching circuit 182, a plasma chamber 108, motors M1 to M4, drivers D1 to D4, a motor M5, a motor M6, a driver D5, and a driver D6. The impedance matching circuit 182 includes a series circuit 196 and a shunt circuit 198 connected to each other.

[0074] The output 184 of the z MHz RF generator is connected to an input 186 of the impedance match circuit 182 via an RF cable 188. The z MHz RF generator comprises a control system 190, an RF power supply 192, and a sensor 194. The sensor 194 is connected to the output 184 of the z MHz RF generator. In addition, the sensor 194 is connected to the processor 116 via a data cable, and the processor 116 is connected to the control system 190 via a data cable.

[0075] The processor 116 is connected to a driver D5, which is connected to a motor M5. The motor M5 is connected to a series circuit 196 via one or more connection mechanisms. The processor 116 is further connected to a driver D6, which is connected to a motor M6. The motor M6 is connected to a shunt circuit 198 via one or more connection mechanisms.

[0076] The impedance matching circuit 182 includes a series circuit 102, a shunt circuit 104, a series circuit 164, a shunt circuit 166, a series circuit 196, and a shunt circuit 198. An end of the series circuit 196 is connected to the input 186, and another end of the series circuit 196 is connected to the output 134. Furthermore, an end of the shunt circuit 198 is connected to the series circuit 196 and the output 134 of the impedance matching circuit 182, and another end of the shunt circuit 198 is connected to ground.

[0077] The processor 116 transmits the digital pulse signal 130 to the z MHz RF generator control system 190 via the data cable. Upon receiving the digital pulse signal 130, the control system 190 provides the power level and frequency level for state S(nN) to the RF power supply 192 in the manner described above in which the x MHz RF generator control system 120 provides the power level and frequency level for state S(nN) to the x MHz RF generator RF power supply 124. The RF power supply 192 generates an RF signal having a power level and frequency level for state S(nN) in the manner in which the x MHz RF generator RF power supply 124 generates an RF signal having a power level and frequency level for state S(nN). The RF power supply 192 provides the RF signal to the input 186 of the impedance matching circuit 182 via an RF cable 188.

[0078] Similarly, upon receiving the digital pulse signal 130, the control system 190 provides a power level and frequency level for state S(n) to the RF power supply 192 in the manner described above in which the x MHz RF generator control system 120 provides a power level and frequency level for state S(n) to the x MHz RF generator RF power supply 124. The RF power supply 192 generates an RF signal having a power level and frequency level for state S(n) in the manner in which the x MHz RF generator RF power supply 124 generates an RF signal having a power level and frequency level for state S(n). The RF power supply 192 provides the RF signal to the input 186 of the impedance matching circuit 182 via the RF cable 162.

[0079] When the RF signal for state S(nN) is received by the impedance matching circuit 182 from the z MHz RF generator in addition to the RF signals for state S(nN) from the x and y MHz RF generators, the impedance matching circuit 182 matches the impedance of the load, e.g., RF transmission line 128 and plasma chamber 108, connected to the output 134 of the impedance matching circuit 182 with the sources, e.g., RF cable 126, x megahertz RF generator, RF cable 162, y MHz RF generator, RF cable 188, and z MHz RF generator, connected to the inputs 132, 160, and 186 of the impedance matching circuit 182. The impedance matching circuit 182 generates the modulated RF signal for state S(nN) by matching the impedances and combining the RF signals transmitted via the sub-circuits 165 (FIG. 1B), 170, and 199. The modulated RF signal for state S(nN) is provided from the impedance matching circuit 182 to the chuck 110 via the output 134 and the RF transmission line 128. The branch circuit 199 includes a series circuit 196 and a shunt circuit 198 .

[0080] Similarly, when an RF signal for state S(n) is received by impedance matching circuit 182 from z MHz RF generator in addition to RF signals for state S(n) from x and y MHz RF generators, impedance matching circuit 182 matches the impedance of a load connected to output 134 of impedance matching circuit 182 with the impedance of a source connected to inputs 132, 160, and 186 of impedance matching circuit 182. Impedance matching circuit 182 generates a modulated RF signal for state S(n) by matching impedances and combining RF signals transmitted via sub-circuits 165 (FIG. 1B), 170, and 199. The modulated RF signal for state S(n) is provided from impedance matching circuit 182 to chuck 110 via RF transmission line 128. Substrate 112 is processed when the modulated RF signal is received from impedance matching circuit 152 via RF transmission line 128 in addition to one or more process gases.

[0081] During state S(nN), a sensor 194 connected to the output 184 of the z MHz RF generator senses the value of a variable at the output 184, e.g., reflected power. Reflected power is the power reflected from the plasma in the plasma chamber 108, through the RF transmission line 128, the branch 199 of the impedance match circuit 182, and the RF cable 188, toward the output 184 of the z MHz RF generator. Similarly, during state S(n), the sensor 194 senses the value of the variable reflected toward the output 184 of the z MHz RF generator.

[0082] Values ​​of the sensed variables during states S(nN)-S(n), e.g., multiple occurrences of states S(nN)-S(n), are continuously provided from sensor 194 to processor 116 via data cable. Processor 116 determines values ​​of one or more parameters of one or more electrical components of impedance matching circuit 182 from the sensed variables during states S(nN)-S(n) until the reflected power at output 184 is simultaneously reduced for states S(nN)-S(n) compared to the reflected power that is reduced at output 184 for one of states S(nN)-S(n) but not reduced for other of states S(nN)-S(n). For example, values ​​of the one or more parameters are determined such that the amount of power reflected to output 184 for all states S(nN)-S(n) is reduced compared to an amount of power reflected to output 184 that is reduced for any one of states S(nN)-S(n) but not reduced for the remaining states of states S(nN)-S(n). To further explain, if the capacitance value of series circuit 196 is Ca and the capacitance value of shunt circuit 198 is Cb, then an amount of power Pra is reflected toward output 184 during state S1. However, if the same values ​​of Ca and Cb are used for state S2, then the amount of power reflected toward output 184 during state S2 is Prb, which is substantially greater than Pra. When the values ​​of one or more parameters of one or more electrical components of the impedance matching circuit 182, e.g., the value Cc of the parameter of the series circuit 196 and the value Cd of the parameter of the shunt circuit 198, are determined from variables sensed by the sensor 194 during states S(nN) and S(n), such that the reflected power at the output 184 is simultaneously reduced for states S(nN) and S(n), the reflected power is a power of an amount Prc. The value Prc is less than the value Prb but greater than the value Pra. In some embodiments, the value Prc is less than or equal to the value Pra.

[0083] As another example, if the values ​​of one or more parameters of the impedance matching circuit 182, e.g., the value Cc of the parameter of the series circuit 196 and the value Cd of the parameter of the branch circuit 198, are determined from variables sensed during states S(n-N) to S(n) such that the reflected power is simultaneously reduced for states S(n-N) to S(n), the reflected power is a power of an amount Prd for states S(n-N) and a power of an amount Pre for state S(n). The value Prd is the minimum value for state S(nN) among the values ​​of reflected power for states S(nN). The multiple values ​​of reflected power for state S(nN) are achieved when the frequency of the z MHz RF generator and / or the power of the RF signal supplied by the z MHz RF generator are changed during state S(nN). The value Prd is the minimum value for state S(n) among the values ​​of reflected power for states S(n). Multiple values ​​of reflected power for state S(n) are achieved when the frequency of the z MHz RF generator and / or the power of the RF signal provided by the z MHz RF generator are changed during state S(n). In various embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n). In some embodiments, the minimum value for state S(nN) is within a predetermined threshold of the minimum value for state S(n), and both of the minimum values ​​are less than a predetermined level of reflected power. The value Prb is greater than the predetermined level and the value Pra is less than the predetermined level.

[0084] During states S(nN)-S(n), the processor 116 transmits a control signal to the driver D5 indicative of a value of a parameter for states S(nN)-S(n) and continues to transmit until the reflected power is reduced at the output 184 of the z MHz RF generator for states S(nN)-S(n). Upon receiving the control signal, the motor M5 rotates to change the value of the parameter of the series circuit 196 via one or more connection mechanisms connecting the motor M5 to the series circuit 196. Similarly, during states S(nN)-S(n), the processor 116 transmits a control signal to the driver D6 indicative of a value of a parameter for states S(nN)-S(n) and continues to transmit until the reflected power is reduced at the output 184 for states S(nN)-S(n). Upon receiving the control signal, the motor M6 rotates to change the value of the parameter of the shunt circuit 198 via one or more connection mechanisms connecting the motor M6 to the shunt circuit 198. The reduction in the reflected power at the output 184 also extends the life of the z MHz RF generator.

[0085] In some embodiments, processor 116 simultaneously controls values ​​of one or more parameters of one or more of series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced for states S(nN)-S(n) to a level that is within a predetermined range of the level at which reflected power is reduced at output 136 for states S(nN)-S(n) and the level at which reflected power is reduced at output 158 ​​for states S(nN)-S(n). For example, the value Prc at output 184 is within a predetermined range of the value Pr3 of the reflected power at output 136 and the value PrC of the reflected power at output 158.

[0086] In various embodiments, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, the shunt circuit 168, the series circuit 196, and the shunt circuit 198 until the reflected power at the output 184 is reduced for the states S(nN)-S(n) to a level that is within a predetermined range of the level at which the reflected power is reduced at the output 136 for the states S(nN)-S(n) and the level at which the reflected power is reduced at the output 158 ​​for the states S(nN)-S(n). Additionally, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, the shunt circuit 168, the series circuit 196, and the shunt circuit 198 until the reflected power at the output 136, the reflected power at the output 158, and the reflected power at the output 184 are below predetermined limits. For example, the value PrC at output 158 ​​is within a predetermined range from the value Pr3 of the reflected power at output 136 and the value Prc at output 184, and the values ​​PrC, Pr3, and Prc are less than the predetermined limit for the reflected power.

[0087] In some embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, the shunt circuit 168, the series circuit 196, and the shunt circuit 198 until the reflected power at the output 184 is reduced for state S(nN) to a level that is within a predetermined range of the level at which the reflected power is reduced at the output 136 for state S(nN) and the level at which the reflected power is reduced at the output 158 ​​for state S(nN). Further, the processor 116 simultaneously controls values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, the shunt circuit 168, the series circuit 196, and the shunt circuit 198 until the reflected power at the output 184 is reduced for the state S(n) to a level that is within a predetermined range of the level at which the reflected power is reduced at the output 136 for the state S(n) and the level at which the reflected power is reduced at the output 158 ​​for the state S(n). For example, the value Prd at the output 184 is within a predetermined range of the value Pr4 of the reflected power at the output 136 and the value PrD of the reflected power at the output 158. Also, the value Pre at the output 184 is within a predetermined range of the value Pr5 of the reflected power at the output 136 and the value PrE of the reflected power at the output 158.

[0088] In various embodiments, the processor 116 simultaneously controls the values ​​of one or more parameters of one or more of the series circuit 102, the shunt circuit 104, the series circuit 166, the shunt circuit 168, the series circuit 196, and the shunt circuit 198 until the reflected power at the output 184 is reduced for state S(nN) to a level that is within a predetermined range of the level at which the reflected power is reduced at the output 136 for state S(nN) and the level at which the reflected power is reduced at the output 158 ​​for state S(nN). Further, processor 116 simultaneously controls values ​​of one or more parameters of one or more of series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 184 is reduced for state S(n) to a level that is within a predetermined range of the level at which the reflected power is reduced at output 136 for state S(n) and the level at which the reflected power is reduced at output 158 ​​for state S(n). Further, processor 116 simultaneously controls values ​​of one or more parameters of one or more of series circuit 102, shunt circuit 104, series circuit 166, shunt circuit 168, series circuit 196, and shunt circuit 198 until the reflected power at output 136, the reflected power at output 158, and the reflected power at output 184 are below predetermined limits. For example, the value Prd at output 184 is within a predetermined range of the value Pr4 of the reflected power at output 136 and the value PrD of the reflected power at output 158. Also, the value Pre at output 184 is within a predetermined range of the value Pr5 of the reflected power at output 136 and the value PrE of the reflected power at output 158. All of the values ​​Prd, Pr4, PrD, Pre, Pr5, and PrE are less than the predetermined limits.

[0089] In some embodiments, each circuit component of the impedance matching circuits described herein, e.g., inductors, capacitors, etc., is electronically controlled, e.g., no motors are utilized to control the circuit components.

[0090] FIG. 2A illustrates an embodiment of a graph 202 of a digital pulse signal 206 and a graph 204 illustrating an embodiment of an RF signal 208 provided by an RF generator, e.g., an xMHz RF generator, or a yMHz RF generator, or a zMHz RF generator. The digital pulse signal 206 is an example of a digital pulse signal 130 (FIGS. 1A-1C). The graph 202 plots logic levels versus time. Additionally, the graph 204 plots the power level of the RF signal 208 versus time. As an example, the power level of the RF signal is the envelope of the RF signal (e.g., amplitude from zero to peak, etc.). As another example, the power level of the RF signal is the root mean square value of the amplitude of the RF signal.

[0091] During state S0, when the digital pulse signal 206 has a logic level of 0, the power level of the RF signal 208 is P1, where p1 is zero or a positive quantity. Furthermore, during state S1, when the digital pulse signal 206 has a logic level of 1, the power level of the RF signal 208 is P2. The power level P2 is greater than the power level P1. Furthermore, when the digital pulse signal 206 transitions from state S0 to state S1, the RF signal 208 transitions from the power level P1 to the power level P2. When the digital pulse signal 206 transitions from state S1 to state S0, the RF signal 208 transitions from the power level P2 to the power level P1. In this manner, the digital pulse signal 206 is synchronized with the RF signal 208.

[0092] Note that state S0 of digital pulse signal 206 occurs during clock cycle period t1. Additionally, state S1 of digital pulse signal 206 occurs during clock cycle period t2.

[0093] FIG. 2B is an embodiment of a graph 210 of an RF signal 212 having three states S0, S1, and S2. The RF signal 212 is an example of an RF signal provided by an x ​​MHz RF generator, a y MHz RF generator, or a z MHz RF generator. During state S0, the RF signal 212 has a power level P1. Furthermore, during state S1, the RF signal 212 has a power level P3. Furthermore, during state S2, the RF signal 212 has a power level P2. The power level P3 is lower than the power level P2 but higher than the power level P1. When the digital pulse signal 130 (FIGS. 1A-1C) transitions from state S0 to state S1, the RF signal 212 transitions from the power level P1 to the power level P3. Furthermore, when the digital pulse signal 130 transitions from state S1 to state S2, the RF signal 212 transitions from the power level P3 to the power level P2. Also, when the digital pulse signal 130 returns from state S2 to state S0, the RF signal 212 returns from power level P2 to power level P1. States S0 to S2 of the RF signal 212 occur during a clock cycle that is the sum of periods t1 and t2.

[0094] FIG. 2C is an embodiment of a graph 214 of an RF signal 216 having four states S0, S1, S2, and S3. The RF signal 216 is an example of an RF signal provided by an x ​​MHz RF generator, a y MHz RF generator, or a z MHz RF generator. During state S0, the RF signal 216 has a power level P1. Additionally, during state S1, the RF signal 216 has a power level P2. Additionally, during state S2, the RF signal 216 has a power level P3. During state S3, the RF signal 216 has a power level P4. The power level P4 is lower than the power level P3 but higher than the power level P1. When the digital pulse signal 130 (FIGS. 1A-1C) transitions from state S0 to state S1, the RF signal 216 transitions from the power level P1 to the power level P2. Furthermore, when the digital pulse signal 130 transitions from state S1 to state S2, the RF signal 216 transitions from power level P2 to power level P3. Also, when the digital pulse signal 130 transitions from state S2 to state S3, the RF signal 216 transitions from power level P3 to power level P4. Also, when the digital pulse signal 130 returns from state S3 to state S0, the RF signal 216 transitions from power level P4 back to power level P1. States S0 to S3 of the RF signal 216 occur during a clock cycle that is the sum of periods t1 and t2.

[0095] FIG. 3A is a diagram of an embodiment of a system 300 to illustrate the control of a series circuit 306 and a shunt circuit 308 during states S(nN)-S(n). The series circuit 306 is an example of a series circuit 102, 166, or 196 (FIG. 1C). Additionally, the shunt circuit 308 is an example of a shunt circuit 104, 168, or 198 (FIG. 1C). The system 300 includes an RF generator 302, such as an x ​​MHz RF generator, a y MHz RF generator, or a z MHz RF generator. The RF generator 302 has an output 370, which is an example of an output 136, an output 158, or an output 184 (FIG. 1C). Additionally, the system 300 includes an impedance matching circuit 304, which is an example of an impedance matching circuit 106 (FIG. 1), a branch circuit 170 (FIG. 1B), or a branch circuit 199 (FIG. 1C).

[0096] The RF generator 302 is connected to the impedance matching circuit 304 via an RF cable 310, which is an example of the RF cable 126, the RF cable 162, or the RF cable 188 (FIG. 1C). The output 134 of the impedance matching circuit 304 is connected to the plasma chamber 108 via an RF transmission line 128.

[0097] The system 300 further includes a motor 312 and a motor 314. The motor 312 is an example of a motor M1, a motor M3, or a motor M5 (FIG. 1C). The motor 314 is an example of a motor M2, a motor M4, or a motor M6 (FIG. 1C).

[0098] The series circuit 306 is connected to the RF cable 310 via an input 316 of the impedance matching circuit 304. The input 316 is an example of the input 132, the input 160, or the input 186 (FIG. 1C). The series circuit comprises an inductor L1 in series with a capacitor C1, which is variable. An end of the inductor L1 is connected to the input 316, and another end of the inductor L1 is connected to the capacitor C1. The shunt circuit 308 comprises an inductor L2 in series with a capacitor C2, which is also variable. An end of the inductor L2 is connected to the output 134, which is connected to an end of the capacitor C1. Furthermore, another end of the inductor L2 is connected to the capacitor C2, which is connected to ground at the other end. The inductors L1 and L2 are fixed, not variable.

[0099] Motor 312 is connected to capacitor C1 via one or more connection mechanisms and rotates to change the distance or area between the parallel plates of capacitor C1. For example, the parallel plates of the capacitor move, e.g., rotate, relative to one another to change the distance or area between the parallel plates. The change in distance or area changes, e.g., increases or decreases, the capacitance of the capacitor. Similarly, motor 314 is connected to capacitor C2 via one or more connection mechanisms and rotates to change the distance or area between the parallel plates of capacitor C2.

[0100] 3B is a diagram of an embodiment of a system 320 to illustrate control of series circuit 324 and shunt circuit 326 during states S(nN)-S(n). Series circuit 324 is an example of series circuit 102, 166, or 196 (FIG. 1C). Additionally, shunt circuit 326 is an example of shunt circuit 104, 168, or 198 (FIG. 1C). System 320 includes an RF generator 302. Additionally, system 320 includes an impedance matching circuit 322, which is an example of impedance matching circuit 106 (FIG. 1), branch circuit 170 (FIG. 1B), or branch circuit 199 (FIG. 1C).

[0101] The RF generator 302 is connected to an impedance matching circuit 322 via an RF cable 310. The output 134 of the impedance matching circuit 322 is connected to the plasma chamber 108 via an RF transmission line 128.

[0102] System 320 further includes motor 312, motor 314, motor 328, and motor 330. Motor 328 is an example of motor M1, motor M3, or motor M5 (FIG. 1C). Motor 330 is an example of motor M2, motor M4, or motor M6 (FIG. 1C).

[0103] The series circuit 324 is connected to the RF cable 310 via an input 332 of the impedance matching circuit 322. The input 332 is an example of the input 132, the input 160, or the input 186 (FIG. 1C). The series circuit includes an inductor L3 in series with a capacitor C1. An end of the inductor L3 is connected to the input 332, and another end is connected to the capacitor C1. The shunt circuit 326 includes an inductor L4 in series with a capacitor C2. An end of the inductor L4 is connected to the output 134 and an end of the capacitor C1. Furthermore, another end of the inductor L4 is connected to the capacitor C2, and the capacitor C2 is connected to ground at the other end. The inductors L3 and L4 are variable.

[0104] Motor 328 is connected to inductor L3 via one or more connection mechanisms and rotates to vary the overlap area between the core of inductor L3 and the coil of inductor L3. For example, the core of the inductor surrounded by the coil of the inductor is moved relative to the coil to vary the inductance of the inductor. The change in the overlap area causes the inductance of the inductor to, for example, increase or decrease. Similarly, motor 330 is connected to inductor L4 via one or more connection mechanisms and rotates to vary the overlap area between the core of inductor L4 and the coil of inductor L4.

[0105] In some embodiments, inductors L1 and L2 are controlled to vary the inductance of the inductors, and fixed capacitors are used in place of capacitors C1 and C2 in impedance matching circuit 322. In various embodiments, one or more of capacitor C1, capacitor C2, inductor L1, and inductor L2 are controlled to reduce reflected power at output 370 for states S(nN) to S(n).

[0106] 3C is a diagram of an embodiment of a system 350 to illustrate an impedance matching circuit 352 with any number of series circuits and any number of shunt circuits. System 350 includes RF generator 302, impedance matching circuit 352, plasma chamber 108, motors 312 and 314, motor 362, and motor 364.

[0107] The RF generator 302 is connected to an input 366 of the impedance matching circuit 352 via an RF cable 310. The impedance matching circuit 352 includes a series circuit 354, a shunt circuit 356, another series circuit 358, and another shunt circuit 360. An end of the series circuit 354 is connected to the input 366, and another end of the series circuit 354 is connected to an end of the shunt circuit 356. Furthermore, another end of the series circuit 354 is connected to an end of the series circuit 358. Another end of the shunt circuit 356 is connected to ground. Furthermore, another end of the series circuit 358 is connected to an end of the shunt circuit 360 and to the output 134 of the impedance matching circuit 352. Another end of the shunt circuit 360 is connected to ground.

[0108] Motor 312 is connected to series circuit 354 via one or more connection mechanisms. Motor 314 is also connected to shunt circuit 356 via one or more connection mechanisms. Motor 362 is also connected to series circuit 358 via one or more connection mechanisms. Motor 364 is connected to shunt circuit 360 via one or more connection mechanisms.

[0109] Upon receiving current signals from drivers (not shown) connected to motors 312, 314, 362, and 364, motor 312 operates to change a parameter of series circuit 354, motor 314 operates to change a parameter of shunt circuit 356, motor 362 operates to change a parameter of series circuit 358, and motor 364 operates to change a parameter of shunt circuit 360. The parameters of circuits 354, 356, 358, and 360 are controlled for states S(nN)-S(n) such that the reflected power at output 370 of RF generator 302 is reduced for states S(nN)-S(n) compared to the reflected power being reduced for one of states S(nN)-S(n) but not reduced for other states of states S(nN)-S(n).

[0110] In some embodiments, the impedance matching circuit 352 includes a greater number of series circuits and a greater number of shunt circuits than are shown in Figure 3C. For example, an end of the shunt circuit 360 connected to the series circuit 358 is connected to another series circuit (not shown), which is connected to another shunt circuit (not shown). An end of the shunt circuit (not shown) is connected to the output 134. Another end of the other shunt circuit (not shown) is connected to ground.

[0111] FIG. 3D is a diagram of an embodiment of a system 380 to illustrate an impedance matching circuit 382 that is an L network. The impedance matching circuit 382 comprises an inductor X1 and a capacitor X2. It is noted that X as described herein represents the reactance of a circuit component, e.g., an inductor, a capacitor, etc. For example, X1 is the reactance of inductor X1, and X2 is the reactance of capacitor X2. Inductor X1 may be variable or fixed. Similarly, capacitor X2 may be variable or fixed. An end of capacitor X2 is connected to ground, and an end of capacitor X2 is connected to an end of inductor X1 and to an input 384 of the impedance matching circuit 382. Another end of inductor X1 is connected to the output 134 of the impedance matching circuit 382.

[0112] It should be noted that impedance matching circuit 382 may be substituted for any of the other impedance matching circuits described herein. For example, impedance matching circuit 382 may be substituted for impedance matching circuit 106, branch circuit 170, or branch circuit 199 (FIG. 1C). Impedance matching circuit 382 has an input 384, which is an example of input 132, input 160, or input 186 (FIG. 1C).

[0113] Note that the RF power supply is shown in Figure 3B as being connected to a resistor Rs, which is the resistance of the source connected to the input 384. Additionally, a resistor Rp is shown in Figure 3B. Resistor Rp comprises the resistance of the load connected to the output 134.

[0114] FIG. 3E is a diagram of an embodiment of a system 386 for illustrating an impedance matching circuit 388 that is a Π network. The impedance matching circuit 386 includes an inductor X2, a capacitor X3, and a capacitor X4. The inductor X2 is variable or fixed. Similarly, each of the capacitors X3 and X4 is variable or fixed. An end of the capacitor X3 is connected to ground, and another end of the capacitor X3 is connected to an end of the inductor X2 and to an input 390 of the impedance matching circuit 388. Furthermore, another end of the inductor X2 is connected to an end of the capacitor X4, and another end of the capacitor X4 is connected to ground. Another end of the inductor X2 is connected to an output 134 of the impedance matching circuit 388. Additionally, a resistor RI is shown in FIG. 3C. The resistor RI has a resistance of a load connected to the output 134.

[0115] FIG. 3F is a diagram of an embodiment of an impedance matching circuit 392 that is a Π network. The Π network is represented by two L networks. The impedance matching circuit 392 includes an inductor X21, a capacitor X3, a resistor Rx, another inductor X22, and a capacitor X4. Each of the capacitors X21 and X22 is variable or fixed. Similarly, each of the capacitors X3 and X4 is variable or fixed. An end of the capacitor X3 is connected to ground, and another end of the capacitor X3 is connected to an end of the inductor X21 and to an input 394 of the impedance matching circuit 392. Furthermore, another end of the inductor X21 is connected to an end of a resistor Rx, and another end of the resistor Rx is connected to ground. Also, another end of the inductor X21 is connected to an end of an inductor X22, and another end of the inductor X22 is connected to an end of a capacitor X4. Another end of the capacitor X4 is connected to ground. The other end of the inductor X22 and an end of the capacitor X4 are connected to the output 134 of the impedance matching circuit 392.

[0116] It should be noted that impedance matching circuit 388 may be substituted for any other impedance matching circuit described herein, for example, impedance matching circuit 388 may be substituted for impedance matching circuit 106, branch circuit 170, or branch circuit 199 (FIG. C).

[0117] FIG. 4 is a diagram of an embodiment of a method 400 for illustrating the determination of values ​​of one or more parameters at which the power reflected toward the RF generator is reduced for states S(nN) to S(n). The method 400 comprises measuring 402 the reflected power at the output of the RF generator for state S(nN). For example, during a period when the RF signal generated by the RF generator has state S(nN), the reflected power is measured at the output of the RF generator. A sensor of the RF generator (e.g., a sensor connected to the output of the RF generator) measures the reflected power. The sensor is located inside or outside the RF generator. The sensor provides a value of the reflected power measured during state S(nN) to the processor 116 (FIG. 1C).

[0118] Further, in step 404 of method 400, during state S(nN), the processor 116 changes the value of one or more parameters, such as inductance, capacitance, etc., of an impedance matching circuit connected to the RF generator via an RF cable, such that the power reflected to the output of the RF generator is reduced. For example, when the reflected power measured during state S(nN) is PRF1, the values ​​of one or more parameters of the impedance matching circuit are CV1 and CV2. Further, when the value of one or more parameters of the impedance matching circuit is changed from CV1 to CV3 and from CV2 to CV4, the reflected power measured during state S(nN) drops to PRF2, which is less than the value PRF1.

[0119] In step 406 of method 400, the reflected power is measured at the output of the RF generator during state S(n). For example, during a period when an RF signal generated by the RF generator has state S(n), the reflected power is measured by a sensor at the output of the RF generator. The sensor provides a value of the reflected power measured during state S(n) to the processor 116.

[0120] In step 408 of the method 400, the value of one or more parameters of the impedance matching circuit is changed by the processor 116 during state S(n) such that the reflected power measured at the output of the RF generator during both states S(n) and S(nN) is reduced. For example, when the value of one or more parameters of the impedance is controlled to change by the processor 116 from CV3 to CV5 and from CV4 to CV6 during state S(n), the reflected power drops to PRF3, which is less than the value PRF1. The value PRF3 is greater than the value PRF2. In another example, the value PRF3 is less than or equal to the value PRF2. As an example, the values ​​PRF2 and PRF3 are within a predetermined threshold of each other. The predetermined threshold is stored in the memory device 118 (FIG. 1C) for access by the processor 116. As yet another example, the values ​​PRF2 and PRF3 are both less than a predetermined level and within a predetermined threshold of each other. The predetermined level is stored in the memory device 118 for access by the processor 116. The value PR1 is greater than the predetermined level.After step 408, for states S(nN) to S(n), the values ​​of the one or more parameters of the impedance matching circuit are maintained at CV5 and CV6.

[0121] In some embodiments, after step 408, values ​​CV5 and CV6 are adjusted (e.g., increased or decreased) by processor 116 to further reduce the reflected power at the output of the RF generator during states S(nN) through S(n) when the power and / or frequency of the RF signal generated by the RF generator changes.

[0122] It should be noted that in various embodiments, where the impedance matching circuit described herein includes multiple parameter values ​​determined such that the reflected power at the output of the RF generator connected to the impedance matching circuit is reduced for states S(nN)-S(n), a multivariate analysis method is utilized by the processor 116 to determine the parameter values. For example, the processor 116 utilizes a multivariate analysis method to determine capacitance and / or inductance values ​​of the series and shunt circuits of the impedance matching circuit such that the minimum value of the reflected power at the output of the RF generator for states S(nN)-S(n) is less than a predetermined level and the minimum value of the reflected power at the output of the RF generator for state S(nN) is within a predetermined threshold value of the minimum value of the reflected power at the output of the RF generator for state state S(n).

[0123] In some embodiments, a neural network, e.g., a computer system modeled on a human brain, a network of computers modeled on a human brain, etc., determines a relationship between one or more values ​​of a parameter of an impedance matching circuit described herein and the reflected power at an output of an RF generator described herein connected to the impedance matching circuit. For example, a regression analysis is utilized by the neural network to determine the relationship based on values ​​of the one or more parameters input to the neural network and values ​​of the reflected power for states S(nN)-S(n). For example, the values ​​of the one or more parameters are inputs at input nodes of the neural network and the reflected power for states S(nN)-S(n) are outputs at output nodes of the neural network. The regression analysis is utilized to determine the relationship between the inputs and outputs. The relationship is then utilized by the processor 116 or the neural network during processing of the substrate 112 (FIGS. 1A-1C) to determine values ​​of the one or more parameters at which the reflected power at the output of the RF generator is reduced for states S(nN)-S(n).

[0124] FIG. 5A is a diagram for explaining a method for determining a capacitance Cseries of a series circuit of an impedance matching circuit described herein and a capacitance Cshunt of a shunt circuit of the impedance matching circuit described herein for reducing reflected power at the output of an RF generator described herein for states S(nN) to S(n). In some embodiments, the capacitance of the series circuit of the impedance matching circuit is a combination of multiple capacitors in the series circuit. For example, the capacitance of the series circuit is the product of the capacitances of the capacitors connected in series to each other in the series circuit divided by the sum of the capacitances. As another example, the capacitance of the series circuit of the impedance matching circuit is the sum of the capacitances of the capacitors connected in parallel to each other in the series circuit. Similarly, the capacitance of the shunt circuit of the impedance matching circuit is a combination of multiple capacitors in the shunt circuit.

[0125] A line 502 has values ​​of capacitance Cseries and another line 504 has values ​​of capacitance Cshunt. Values ​​of reflected power at the output of the RF generator are measured during states S(nN)-S(n) and plotted in graph 506 when the value of capacitance Cseries is reduced from value CS1 and the value of capacitance Cshunt is reduced from value CSH1. Graph 506 plots reflected power at the output of the RF generator versus time. Values ​​of reflected power at the output of the RF generator during state S(nN), e.g., value 510A, value 512A, etc., are shown in plot 508A and values ​​of reflected power at the output of the RF generator during state S(n), e.g., value 510B, value 512B, etc., are shown in plot 508B. For example, reflected power values ​​510A and 510B are measured when capacitance Cseries is CS(-2) and capacitance Cshunt is CSH(-2). Additionally, values ​​of reflected power 512A and 512B are measured when the capacitance Cseries is CS(-3) and the capacitance Cshunt is CSH(-3). As shown in graph 504, the value of reflected power at the output of the RF generator is greater than a predetermined level during states S(nN) to S(n) and is therefore not reduced for states S(nN) to S(n).

[0126] Additionally, values ​​of reflected power at the output of the RF generator are measured during states S(nN)-S(n) and plotted in graph 514 when the value of capacitance Cseries is decreased from value CS1 and the value of capacitance Cshunt is increased from value CSH1. Graph 514 plots reflected power at the output of the RF generator versus time. Values ​​of reflected power at the output of the RF generator during state S(nN), e.g., value 518A, value 520A, value 522A, etc., are shown in plot 516A, and values ​​of reflected power at the output of the RF generator during state S(n), e.g., value 518B, value 520B, value 522B, etc., are shown in plot 516B. For example, reflected power values ​​518A and 518B are measured when capacitance Cseries is CS(-2) and capacitance Cshunt is CSH(2). Additionally, values ​​of reflected power 520A and 520B are measured when capacitance Cseries is CS(-3) and capacitance Cshunt is CSH(3). Additionally, values ​​of reflected power 522A and 522B are measured when capacitance Cseries is CS(-4) and capacitance Cshunt is CSH(4). As shown in graph 514, values ​​of reflected power 522A and 522B at the output of the RF generator are less than a predetermined level during states S(nN) through S(n). Additionally, values ​​522A and 522B are within a predetermined threshold of each other. For example, value 522A is an absolute minimum of plot 516A and value 522B is an absolute minimum of plot 516B. In various embodiments, value 522A is a local minimum of plot 516A and value 522B is a local minimum of plot 516B. A local minimum is the minimum value of reflected power during a given period of time during which the reflected power is measured, e.g., between time t1 and time t2, whereas an absolute minimum is the minimum value of reflected power over the entire period during which the reflected power is measured, e.g., between time t1 and time t3. The capacitance values ​​CS(-4) and CSH(4) are capacitance values ​​at which the reflected power at the output of the RF generator is reduced for states S(nN) through S(n) compared to the reflected power being reduced for one of states S(nN) through S(n) but not for the other of states S(nN) through S(n).

[0127] Additionally, values ​​of reflected power at the output of the RF generator are measured during states S(nN)-S(n) and plotted in graph 524 when the value of capacitance Cseries is increased from value CS1 and the value of capacitance Cshunt is decreased from value CSH1. Graph 524 plots reflected power at the output of the RF generator versus time. Values ​​of reflected power at the output of the RF generator during state S(nN), e.g., value 528A, value 530A, etc., are shown in plot 526A, and values ​​of reflected power at the output of the RF generator during state S(n), e.g., value 528B, value 530B, etc., are shown in plot 526B. For example, reflected power values ​​526A and 526B are measured when capacitance Cseries is CS(2) and capacitance Cshunt is CSH(-2). Additionally, values ​​of reflected power 530A and 530B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(-3). As shown in graph 524, the values ​​of reflected power at the output of the RF generator are greater than a predetermined level during states S(nN) to S(n).

[0128] Additionally, values ​​of reflected power at the output of the RF generator are measured during states S(nN)-S(n) and plotted in graph 524 when the value of capacitance Cseries is increased from value CS1 and the value of capacitance Cshunt is decreased from value CSH1. Graph 524 plots reflected power at the output of the RF generator versus time. Values ​​of reflected power at the output of the RF generator during state S(nN), e.g., value 528A, value 530A, etc., are shown in plot 526A, and values ​​of reflected power at the output of the RF generator during state S(n), e.g., value 528B, value 530B, etc., are shown in plot 526B. For example, reflected power values ​​528A and 528B are measured when capacitance Cseries is CS(2) and capacitance Cshunt is CSH(-2). Additionally, values ​​of reflected power 530A and 530B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(-3). As shown in graph 524, the value of reflected power at the output of the RF generator is greater than a predetermined level during states S(nN) to S(n) and is therefore not reduced for states S(nN) to S(n).

[0129] Values ​​of reflected power at the output of the RF generator are measured during states S(nN) through S(n) and plotted in graph 532 as the value of capacitance Cseries is increased from a value CS1 and the value of capacitance Cshunt is increased from a value CSH1. Graph 532 plots reflected power at the output of the RF generator versus time. Values ​​of reflected power at the output of the RF generator during state S(nN), e.g., values ​​536A, 538A, etc., are shown in plot 534A, and values ​​of reflected power at the output of the RF generator during state S(n), e.g., values ​​536B, 538B, etc., are shown in plot 534B. For example, reflected power values ​​536A and 536B are measured when capacitance Cseries is CS(2) and capacitance Cshunt is CSH(2). Additionally, values ​​of reflected power 538A and 538B are measured when the capacitance Cseries is CS(3) and the capacitance Cshunt is CSH(3). As shown in graph 532, the value of reflected power at the output of the RF generator is greater than a predetermined level during states S(nN) to S(n) and is therefore not reduced for states S(nN) to S(n).

[0130] In some embodiments, one of the capacitances Cseries and Cshunt is altered during the method illustrated in FIG. 5A, and the other of the capacitances Cseries and Cshunt is not altered.

[0131] In various embodiments, instead of changing the capacitances Cseries and Cshunt, the method described with reference to FIG. 5A is equally applicable to changing the inductance of the series circuit of the impedance matching circuit and to changing the inductance of the shunt circuit of the impedance matching circuit. In some embodiments, instead of changing the capacitances Cseries and Cshunt, the method described with reference to FIG. 5A is equally applicable to changing the capacitance and inductance of the series circuit of the impedance matching circuit and to changing the capacitance and inductance of the shunt circuit of the impedance matching circuit.

[0132] It should be noted that the method described with reference to Figure 5A is an empirical process for achieving a minimum value of reflected power for states S(nN) to S(n). For example, the method described with reference to Figure 5A is a multivariate tuning method in which values ​​Cshunt and Cshunt are determined to achieve two objectives (e.g., a minimum value of reflected power during state S(nN) and a minimum value of reflected power during state S(n)).

[0133] Furthermore, it should be noted that the values ​​CS(-4) to CS(4) are progressive with respect to each other. For example, the value CS(-4) is smaller than the value CS(-3), which is smaller than the value CS(-2). The value CS(-2) is smaller than the value CS(-1), which is smaller than the value CS(0). The value CS(0) is smaller than the value CS(1), which is smaller than the value CS(2). The value CS(2) is smaller than the value CS(3), which is smaller than the value CS(4). To further explain, CS(-4) is a unit smaller than the value CS(-3), e.g., 0.1 picofarads, 0.2 picofarads, etc., and the value CS(-3) is a unit smaller than the value CS(-2). The value CS(-2) is one unit smaller than the value CS(-1), which is one unit smaller than the value CS(0), which is one unit smaller than the value CS(1), which is one unit smaller than the value CS(2), which is one unit smaller than the value CS(3), which is one unit smaller than the value CS(4).

[0134] Similarly, it should be noted that the values ​​CSH(-4) to CSH(4) are progressive with respect to each other. For example, the value CSH(-4) is less than the value CSH(-3), which is less than the value CSH(-2). The value CSH(-2) is less than the value CSH(-1), which is less than the value CSH(-1). The value CSH(0) is less than the value CSH(1), which is less than the value CSH(2). The value CSH(2) is less than the value CSH(3), which is less than the value CSH(4). To further explain, CSH(-4) is a unit smaller than the value CSH(-3), e.g., 0.1 picofarads, 0.2 picofarads, etc., and the value CSH(-3) is a unit smaller than the value CS(-2). The value CSH(-2) is one unit smaller than the value CSH(-1), which is one unit smaller than the value CSH(0), which is one unit smaller than the value CSH(1), which is one unit smaller than the value CSH(2), which is one unit smaller than the value CSH(3), which is one unit smaller than the value CSH(4).

[0135] FIG. 5B is an illustration of an embodiment of a graph 550 for illustrating a technical advantage of applying a tuning method to reduce reflected power in states S(nN)-S(n). Graph 550 plots reflectivity versus frequency of an RF generator. Reflectivity is a measure of power reflected back to an RF generator. Graph 550 includes plots 552, 554, 556, and 558. In some embodiments, reflectivity indicates the amount of RF signal reflected back from the plasma chamber 108 (FIG. 1C) to an RF generator, e.g., an x ​​MHz RF generator, a y MHz RF generator, or a z MHz RF generator. For example, reflectivity is equal to the ratio of the amplitude of reflected power and the amplitude of forward power. Forward power is the power provided by the RF generator to the plasma chamber 108 through an impedance matching circuit.

[0136] Plot 552 is a plot when the reflectance is zero or near zero for a frequency of operation of the RF generator of f1 MHz, which is between the frequencies of operation of the RF generator Fmin and Fmax. Additionally, plot 554 is a plot when the parameter values ​​at which the reflectance for state S(nN) is minimum are used during state S(n). For example, the capacitance values ​​of the series circuit 102 and the shunt circuit 104 (FIG. 1A) of the impedance matching circuit 106 of FIG. 1A for state S1 are CA1 and CA2. When the capacitance values ​​CA1 and CA2 are used during state S2, the reflectance at the output 136 of the x MHz RF generator is as shown in plot 554. The reflectance of plot 554 is greater than a predetermined level, as indicated by reference numeral 560. For example, the minimum value of plot 554 is greater than the predetermined level 560.

[0137] When the method described in flowchart 400, the method described in FIGS. 1A-1C, or the method described in FIG. 5A or FIG. 6 described below is applied, the reflectance at the output of the RF generator for state S(nN) is plotted as 556 and for state S(n) is plotted as 558. For example, when the parameter value of series circuit 102 is CA3 and the parameter value of shunt circuit 104 is CA4, the reflectance shown by plot 556 is achieved for state S(nN) and the reflectance shown by plot 558 is achieved for state S(n). It should be noted that plot 556 has a minimum (e.g., an absolute minimum) at a frequency f2 of the RF generator, e.g., the x MHz RF generator, and plot 558 has a minimum (e.g., an absolute minimum) at a frequency f3 of the RF generator. The minima of plots 556 and 558 are less than a predetermined limit 560 and are within a predetermined threshold 562 from each other, which is a range of reflectance values. Frequency values ​​f2 and f3 are between frequency values ​​Fmin and Fmax.

[0138] In some embodiments, instead of measuring reflected power, forward power and reflected power are measured by a sensor as described herein. The forward power and reflected power are provided by the sensor to the processor 116 to calculate the reflectance. Additionally, any of the information described above that is applicable to reflected power is applicable to the reflectance. For example, instead of a predetermined level of reflected power, a predetermined level of reflectance is utilized. As another example, instead of a predetermined threshold for reflected power, a predetermined threshold for reflectance is used. As yet another example, instead of a predetermined range of reflected power, a predetermined range of reflectance is used. As another example, instead of a predetermined limit for reflected power, a predetermined limit for reflectance is used.

[0139] 6 is a diagram of one embodiment of a machine learning network 600 for determining values ​​of one or more parameters that minimize the values ​​of variables for states S(nN) through S(n). Examples of machine learning networks 600 include computer systems modeled after the human brain, networks of computers modeled after the human brain, and the like. A value of one of the parameters of the impedance matching circuit described herein (e.g., Cseries, inductance, etc.) is received as an input via an input device (e.g., a mouse, keyboard, button, touch screen, etc.), and a value of the parameter of the impedance matching circuit, e.g., Cshunt, or another parameter, e.g., inductance, is received as another input by the machine learning network 600. The machine learning network 600 processes the value received as input to calculate a value of a variable for states S(nN) to S(n) as an output, e.g., a reflected power value. Further, the machine learning network 600 determines whether the value of the variable for states S(nN) to S(n) is a minimum value. If the value of the variable for state S(nN) is not a minimum value, the machine learning network 600 performs back propagation to change the value of the parameter received as input, and then again determines whether the value of the variable for states S(nN) to S(n) is a minimum value. The machine learning network 600 iterates until the value of the variable is a minimum, in order to find the value of one or more parameters at which the value of the variable is a minimum.

[0140] The embodiments described herein may be practiced with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units linked through a network.

[0141] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems are integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. The controller is programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, and wafer movement in and out of load locks connected or coupled with tools and other moving tools and / or systems, depending on the processing requirements and / or type of system.

[0142] In general, in various embodiments, a controller is defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions that are communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or to a system. The operational parameters, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more process steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0143] The controller, in some embodiments, is part of or connected to a computer that is integrated with, connected to, or otherwise networked with the system, or a combination thereof. For example, the controller may be in the "cloud" or may be all or part of a fab host computer system that allows remote access of wafer processing. The computer allows remote access to the system to monitor the current progress of a manufacturing operation, look at the history of past manufacturing operations, or look at trends or performance indicators from multiple manufacturing operations, to change parameters of a current process, set up processing steps according to a current process, or initiate a new process.

[0144] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the process steps to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by having one or more separate controllers that are networked and operate toward a common purpose, such as the process and control described herein. One example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (e.g., at the platform level or located as part of the remote computer) that cooperate to control the process in the chamber.

[0145] Without being limited thereto, in various embodiments, example systems include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or utilized in the fabrication and / or manufacturing of semiconductor wafers.

[0146] It should also be noted that in some embodiments, the above operations apply to several types of plasma chambers, such as inductively coupled plasma (ICP) reactors, transformer coupled plasma chambers, capacitively coupled plasma reactors, plasma chambers with conductor tools, dielectric tools, plasma chambers with electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are connected to an inductor in an ICP reactor. Examples of inductor shapes include a solenoid, a dome coil, a flat coil, etc.

[0147] In various embodiments, the RF transmission line 128 (FIGS. 1A-1C) is connected to the upper electrode 114 instead of the chuck 110, and the chuck 110 is connected to ground.

[0148] As described above, depending on the processing step or steps being performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to or from tool locations and / or load ports within a semiconductor manufacturing factory.

[0149] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the present embodiments are useful machine operations.

[0150] Some of the embodiments further relate to hardware units or devices for performing these operations. The device is specially configured for a special purpose computer. When defined as a special purpose computer, the computer can operate for a specific purpose while performing other processes, program executions or routines that are not included in the specific purpose.

[0151] In some embodiments, operations may be processed on a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0152] One or more embodiments may be manufactured as computer readable code on a non-transitory computer readable medium. The non-transitory computer readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer readable media include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium includes a computer readable tangible medium distributed over a networked computer system such that the computer readable code is stored and executed in a distributed manner.

[0153] Although the method operations described above are presented in a particular order, it should be understood that in various embodiments, other housekeeping processes are performed between operations, or the method operations are performed at slightly different times, distributed across a system that allows method operations to occur at various intervals, or arranged to be performed in an order different from that described above.

[0154] Furthermore, it should be noted that in one embodiment, one or more features of any embodiment described herein may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0155] Although the present embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. Thus, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. 1. A method for tuning to reduce reflected power in multiple states, comprising: supplying power by a radio frequency (RF) generator during a first state of a digital pulse signal to a plasma chamber through an impedance matching circuit; measuring an amount of power reflected back to an output of the RF generator during the first condition; supplying power by the RF generator during a second state of the digital pulse signal to the plasma chamber through the impedance match circuit; measuring an amount of power reflected back to the output of the RF generator during the second state; controlling parameters of the impedance matching circuit to reduce the amount of power measured during the first state to a minimum value and to reduce the amount of power measured during the second state to a minimum value; A method comprising:

2. 2. The method of claim 1 , A method according to claim 1, wherein the minimum value of the first state is less than a predetermined level and the minimum value of the second state is less than the predetermined level.

3. 3. The method of claim 2, A method, wherein the minimum value of the first state and the minimum value of the second state are within a predetermined threshold of each other.

4. 2. The method of claim 1 , the minimum value in the first state is less than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; The method, wherein the minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value.

5. 2. The method of claim 1 , the minimum value in the first state is greater than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; the minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value; the other minimum value in the first state is less than a predetermined level; a second minimum value of the second state is reached when the parameter has the first value; The method of claim 1, wherein the another minimum value for the second state is less than the predetermined level.

6. 2. The method of claim 1 , The step of controlling the parameter includes the step of controlling a capacitor or an inductor of the impedance matching circuit, The method of claim 1, wherein the minimum value for the first and second states corresponds to a constant value of the parameter for the first and second states.

7. 2. The method of claim 1 , the parameter is a parameter of a series circuit of the impedance matching circuit or a parameter of a shunt circuit of the impedance matching circuit, A method wherein the controlling step is performed using a machine learning process.

8. 1. A system for tuning to reduce reflected power in multiple states, comprising: a radio frequency (RF) generator configured to provide power during a first state of the digital pulse signal; an impedance matching circuit connected to the RF generator via an RF cable; a plasma chamber connected to the impedance matching circuit via an RF transmission line; a sensor connected to an output of the RF generator, the sensor configured to measure an amount of power reflected back to the output of the RF generator during the first condition; Equipped with the RF generator is configured to supply power to the plasma chamber through the impedance match circuit during a second state of the digital pulse signal; the sensor is configured to measure an amount of power reflected back to the output of the RF generator during the second state; The system further comprises: a processor coupled to the impedance matching circuit for controlling parameters of the impedance matching circuit; The parameters are controlled to reduce the amount of power measured during the first state to a minimum value and to reduce the amount of power measured during the second state to a minimum value.

9. 9. The system of claim 8, the minimum value in the first state is less than a predetermined level; The minimum value of the second state is less than the predetermined level.

10. 10. The system of claim 9, wherein the minimum value of the first state and the minimum value of the second state are within a predetermined threshold of each other.

11. 9. The system of claim 8, the minimum value in the first state is less than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; The minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value.

12. 9. The system of claim 8, the minimum value in the first state is greater than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; the minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value; the minimum value in the first state is less than a predetermined level; a second minimum value of the second state is reached when the parameter has the first value; The system, wherein the another minimum value for the second state is less than the predetermined level.

13. 9. The system of claim 8, The system, wherein the parameter is a parameter of a capacitor or an inductor of the impedance matching circuit.

14. 9. The system of claim 8, The system, wherein the parameter is a parameter of a series circuit of the impedance matching circuit or a parameter of a shunt circuit of the impedance matching circuit.

15. A non-transitory computer-readable medium storing a program for causing a computer to execute a method, the method comprising: supplying power by a radio frequency (RF) generator during a first state of a digital pulse signal to a plasma chamber through an impedance matching circuit; receiving a measurement of an amount of power reflected to an output of the RF generator during the first state; supplying power by the RF generator through the impedance match circuit to the plasma chamber during a second state of the digital pulse signal; receiving a measurement of an amount of power reflected to the output of the RF generator during the second state; controlling parameters of the impedance matching circuit to reduce the amount of power measured during the first state to a minimum value and to reduce the amount of power measured during the second state to a minimum value; A medium comprising:

16. 16. The non-transitory computer readable medium of claim 15, the minimum value in the first state is less than a predetermined level; The medium, wherein the minimum value of the second state is less than the predetermined level.

17. 17. The non-transitory computer readable medium of claim 16, The medium, wherein the minimum value of the first state and the minimum value of the second state are within a predetermined threshold of each other.

18. 16. The non-transitory computer readable medium of claim 15, the minimum value in the first state is less than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; The minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value.

19. 16. The non-transitory computer readable medium of claim 15, the minimum value in the first state is greater than another minimum value in the first state; the other minimum value in the first state is achieved when the parameter has a first value; the minimum value of the first state and the minimum value of the second state are achieved when the parameter has a second value; the other minimum value in the first state is less than a predetermined level; a second minimum value of the second state is reached when the parameter has the first value; The medium, wherein the another minimum value of the second state is less than the predetermined level.

20. 16. The non-transitory computer readable medium of claim 15, The step of controlling the parameter includes controlling a capacitor or an inductor of the impedance matching circuit.

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