Half-wave rectification LLC converter and control IC

Abstract

To provide a half-wave LLC converter and a control IC capable of preventing increase in a circulating current when an output current increases or when an output voltage is low and variable.SOLUTION: A half-wave LLC converter and a control IC include: a first series circuit in which a main switch QM and a resonance switch QR are connected in series; a second series circuit in which a primary winding Np and a resonance capacitor Cr are connected in series; a transformer T having the primary winding Np and a secondary winding Ns; and a control unit 100a for turning on / off the main switch QM and the resonance switch QR. The control unit 100a includes a first drive signal for turning on / off the main switch QM, a second drive signal for turning on / off the resonance switch QR, and a third drive signal for turning on / off the resonance switch QR after the second drive signal. Further, the control unit 100a turns on the second drive signal for a half of a resonance cycle from the half of the resonance cycle before a timing at which an excitation current of a transformer T becomes zero.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a half-wave rectifying LLC converter and a control IC. [Background technology]

[0002] Conventionally, a half-wave rectification LLC converter has been proposed as a power supply circuit for an isolated DC-DC converter. Patent Document 1 discloses an operation method of a power converter that controls a main switch and a resonant switch. The operation method disclosed in Patent Document 1 proposes a control that turns the resonant switch on and off twice during the off period of the main switch. The first on / off of the resonant switch is turned on during the period when a current flows through the body diode of the resonant switch after the main switch is turned off, and power is transmitted to the secondary side by the resonant current due to the resonant capacitor and leakage inductance, and the second on / off of the resonant switch is performed immediately before the main switch, thereby achieving ZVS (zero volt switching) of the main switch, thereby achieving a high-efficiency, low-noise power supply. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,089,2687 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the control method disclosed in Patent Document 1, the resonant switch is turned on when a current flows through the body diode connected in parallel to the resonant switch immediately after the main switch is turned off, as in complementary control. Only the resonant current that flows when the resonant switch is turned on is sent as power to the secondary side. Therefore, when the output current increases, the on-time of the main switch is increased and the amplitude of the excitation current is increased, the operating frequency decreases. In this case, since the time to send power to the secondary side does not change, the peak value of the current flowing through the secondary side increases more than proportionally to the increase in the output current. Therefore, the effective value of the current flowing through the secondary side also increases more than proportionally to the increase in the output current, increasing the loss of the resistance component of the secondary side circuit and decreasing the efficiency. For example, the problem becomes more pronounced when the secondary side diode is a synchronous rectifier made of a MOSFET.

[0005] The present invention has been made in consideration of the problems inherent in the conventional techniques, and an object of the present invention is to provide a half-wave rectifying LLC converter and a control IC that are capable of preventing an increase in circulating current that accompanies an increase in output current. [Means for solving the problem]

[0006] A half-wave rectifying LLC converter and control IC according to an embodiment of the present invention includes a first series circuit in which a main switch and a resonant switch are connected in series across a DC power source, a second series circuit in which a primary winding and a resonant capacitor are connected in series across the resonant switch, a transformer having a primary winding and a secondary winding electromagnetically coupled with the primary winding in opposite polarity, a control unit that turns the main switch and the resonant switch on and off, a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding, and an output voltage detection unit that detects the output voltage of the rectifying and smoothing circuit, and the control unit outputs a first drive signal that turns the main switch on and off, and a second drive signal that turns the main switch off and on when the main switch is off. The second drive signal has a flyback period in which energy stored in the transformer is released from the secondary winding after the main switch is turned on and off by the first drive signal, and the second drive signal is generated so that the second drive signal turns on the resonant switch during the flyback period, causing a resonant current to flow, and after the resonant current has stopped flowing, the second drive signal is generated so that the second drive signal turns off the resonant switch during an excitation current charging period in which the excitation current charges the resonant capacitor. Effect of the Invention

[0007] According to the present invention, it is possible to provide a half-wave rectification LLC converter and a control IC that are capable of preventing an increase in circulating current that accompanies an increase in output current. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a half-wave rectification LLC converter operated by a control IC according to this embodiment. [Diagram 2] FIG. 2 is a diagram showing operating waveforms of a half-wave rectification LLC converter as a comparative example. [Diagram 3] FIG. 3 is a diagram showing operation waveforms of the half-wave rectification LLC converter and the control IC according to the first embodiment. [Figure 4]FIG. 4 shows operational waveforms when the on-timing of the resonant switch is shifted backward in the half-wave rectification LLC converter and control IC according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing operation waveforms of the half-wave rectification LLC converter and the control IC according to the first embodiment. [Figure 6] FIG. 6 is a block diagram of the control unit according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing a configuration of the excitation current detection means according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing a configuration of an enable signal generating means according to the first embodiment. [Figure 9A] FIG. 9A is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the first embodiment. [Figure 9B] FIG. 9B is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the first embodiment. [Figure 9C] FIG. 9C is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the first embodiment. [Figure 9D] FIG. 9D is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the first embodiment. [Figure 10] FIG. 10 is a block diagram of a control unit according to the second embodiment. [Figure 11] FIG. 11 is a diagram showing a configuration of an enable signal generating means according to the second embodiment. [Figure 12] FIG. 12 is a diagram showing operational waveforms of the enable signal generating means according to the second embodiment. [Figure 13] FIG. 13 is a diagram showing characteristics of the enable signal generating means according to the second embodiment. [Figure 14A] FIG. 14A is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the second embodiment. [Figure 14B] FIG. 14B is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the second embodiment. [Figure 14C]FIG. 14C is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the second embodiment. [Figure 14D] FIG. 14D is a diagram showing operation waveforms of the half-wave rectification LLC converter according to the second embodiment. [Figure 15] FIG. 15 is a diagram showing changes in operating frequency with respect to output current in the first and second embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a half-wave LLC converter 10 and a control IC according to some embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drive circuit according to each embodiment will be denoted by the same reference numerals and the description thereof will be omitted.

[0010] (Configuration of half-wave LLC converter 10) A half-wave rectification LLC converter (hereinafter referred to as a half-wave LLC converter 10) is one of the power supply circuit topologies of an isolated DC-DC converter.

[0011] 1 is a diagram showing the configuration of a half-wave LLC converter 10. The half-wave LLC converter 10 includes a first parallel circuit in which a main switch QM and a body diode DM are connected in parallel to one end of a DC power supply Vin. The half-wave LLC converter 10 also includes a second parallel circuit in which a resonant switch QR and a body diode DR are connected in parallel to the other end of the DC power supply Vin. The first parallel circuit and the second parallel circuit are connected in series to form a half-bridge circuit.

[0012] The half-wave LLC converter 10 also includes a transformer T having a primary winding Np and a secondary winding Ns. The half-wave LLC converter 10 also includes a series resonant circuit, in which a resonant reactor Lr, a resonant capacitor Cr, and the primary winding Np are connected in series, connected across a resonant switch QR.

[0013] Moreover, the half-wave LLC converter 10 has a rectifying element, a diode Ds, and an output capacitor Co connected in series to the secondary winding Ns. The half-wave LLC converter 10 is an isolated DC-DC converter in which the polarities of the primary winding Np and secondary winding Ns of the transformer T are connected such that the voltage generated in the secondary winding Ns when the main switch QM is turned on reverse-biases the diode Ds.

[0014] The resonant reactor Lr can utilize the leakage inductance Llk of the transformer T. Also, the body diodes DM and DR are not necessary if they are semiconductor elements that can pass current in the reverse direction even when the main switch QM and resonant switch QR are off.

[0015] For example, when using MOSFETs for the main switch QM and resonant switch QR, a reverse current can flow through the body diode that is generated due to the structure. It is also known that GaN-FETs (gallium nitride) allow a reverse current to flow due to the voltage between the gate and drain even when the voltage between the gate and source is below the threshold. It is also possible to eliminate the need for these by turning on the main switch QM and resonant switch QR during the period when current flows through the diode.

[0016] First, the timing of control of the resonant switch QR to prevent an increase in circulating current when the output current increases, which is a drawback of conventional control, will be described.

[0017] Figure 2 shows an example of the operating waveforms confirmed by simulating the control of a conventional half-wave rectified LLC converter.

[0018] In the example shown in FIG. 2, it is assumed that the output voltage is 20V and the rated output current is 3A. In the example shown in FIG. 2, the higher half of the rated output current, 1.5A to 3A, is controlled by the on-time of the main switch QM, and the lower half of the rated output current, 1.5A or less, is controlled by fixing the on-time of the main switch QM and controlling the frequency. In the example shown in FIG. 2, it is assumed that the output current becomes burst mode when it is 1 / 10 or less of the rated output current. Furthermore, the example shown in FIG. 2 shows the operating waveform when the output current is changed from 0.3A to 3A when the upper limit of the operating frequency is set to 150kHz and the circuit constant is set so that the operating frequency does not become an audible frequency when the output current is 0.3A, which is 1 / 10 of the rated output current.

[0019] As shown in Figure 2, the operating waveform at 0.3A has a low frequency, so the time width is twice as long as the other operating waveforms on the horizontal axis. As can be seen from the operating waveforms shown in Figure 2, when the switch is turned on in the full load range, zero volt switching (hereafter referred to as ZVS) has been achieved, which makes the voltage across the switch zero volts.

[0020] However, in the conventional control method, as in the case of general complementary control, after the main switch is turned off, the resonant switch is turned on when a current flows through the body diode connected in parallel to the resonant switch. Then, the only power transmission to the secondary side is the resonant current Ire that flows when this resonant switch QR is turned on. General complementary control is a control that turns on the resonant switch QR to completely complement the off period of the main switch QM while having a dead time. As a result, during the period when the main switch QM is on, the difference between the voltage Vr from the DC power supply Vin to the resonant capacitor Cr is applied to the primary winding Np of the transformer T, and the excitation current increases. Also, during the period when the resonant switch QR is on due to complementary control, the reverse voltage Vr is applied to the primary winding Np of the transformer T, so the excitation current decreases.

[0021] Therefore, when the output current Io increases, the on-time of the main switch QM increases, and the amplitude ILmp of the excitation current ILm increases, the operating frequency decreases. This decrease in the operating frequency itself is not a problem, but since the time to send power to the secondary side remains unchanged at Tcrlk / 2, where Tcrlk is the resonance period, the peak value of the current flowing through the secondary side increases more than proportionally to the increase in the output current.

[0022] As a result, the effective value of the current flowing through the secondary side also increases more than proportionally to the increase in output current, increasing the loss in the resistance component of the secondary side circuit and reducing efficiency. For example, this can be a problem when the secondary side diode is a synchronous rectifier made of a MOSFET.

[0023] It can also be seen that the current flowing through the resonant switch QR increases more than proportionally to the increase in the output current.

[0024] This is because if the increase in output current is controlled by the increase in excitation current, the excitation current ILm is not output to the secondary side after the resonant current Ire has stopped flowing. This causes a circulating excitation current ILmr to flow from the source to the drain of the resonant switch QR or through the body diode of the resonant switch QR, charging the resonant capacitor Cr.

[0025] The increase in the circulating excitation current ILmr after the resonant current stops flowing causes various problems. The circulating excitation current ILmr is a circulating current that circulates on the primary side, and increases the current that flows through the resonant switch QR, the second body diode, the primary winding Np of the transformer T, and the resonant capacitor Cr, increasing the loss of each element and deteriorating efficiency.

[0026] Therefore, if the on / off timing of the resonant switch QR after the main switch is turned off is performed using the conventional complementary control timing, the circulating current increases when the output current increases, resulting in a deterioration in efficiency. This suggests that in a power supply device with a variable output voltage, the efficiency deteriorates when the output voltage is set low, as the circulating current increases because the slope of the decrease in the excitation current becomes gentle even when the output voltage drops.

[0027] (First embodiment) Fig. 3 shows operation waveforms when the control of the present invention is applied. In Fig. 3, drive signal VgsM is a drive signal for main switch QM. The drive signal VgsM corresponds to a first drive signal. Voltage VdsM is a voltage of main switch QM. Current IdM is a current of main switch QM. Excitation current ILm is a current of excitation inductance Lm of transformer T. Threshold signal Vth1 is a threshold that determines the start timing of period T4 described later.

[0028] Moreover, the drive signal VgsR is a drive signal for the resonant switch QR. The P1 signal is the first drive signal in the drive signal VgsR, and the P2 signal is the second drive signal in the drive signal VgsR. The first drive signal VgsR corresponds to the second drive signal, and the second drive signal VgsR corresponds to the third drive signal.

[0029] Furthermore, voltage VdsR is the voltage of the resonant switch QR. Furthermore, current IdR is the current of the resonant switch QR. Furthermore, voltage Vrm is the voltage of the diode Ds. Furthermore, current If is the current of the diode Ds.

[0030] In the example shown in FIG. 3, when the resonant switch QR is in the off state, there is a period T1 during which the main switch QM is turned on to increase the currents of the magnetizing inductance Lm and the leakage inductance Llk and charge the resonant capacitor Cr.

[0031] 3, after the end of the period T1, the resonant switch QR remains off, and there is a period T2 in which the main switch QM is turned off. During the period T2, part of the current of the excitation inductance Lm and the current of the leakage inductance Llk are charged to the resonant capacitor Cr, and the remaining current of the excitation inductance Lm is output to the secondary side.

[0032] 3, after the end of the period T2, there is a period T3 during which the main switch QM and the resonant switch QR remain off and the current of the excitation inductance Lm is output to the secondary side. This period is the same as the operation of a normal flyback converter, and the period T3 corresponds to the flyback period.

[0033] 3, there is a period T4 during which the main switch QM remains off and the resonant switch QR is turned on during the period T3. This period T4 is the period during which the voltage of the resonant capacitor Cr is applied to the primary winding Np, a resonant current flows through the resonant capacitor Cr and the leakage inductance Llk, and the half-cycle current of the resonant current finishes flowing.

[0034] 3, after the end of the period T4, the excitation current is charged to the resonant capacitor Cr, and while the resonant capacitor Cr is being charged, the main switch QM remains off, the resonant switch QR is turned off, and there is a period T5 in which the excitation current ends at zero. The period T5 corresponds to the excitation current charging period.

[0035] In the example shown in FIG. 3, after the end of period T5, there is a period T6 during which resonant operation occurs between the capacitance component of the resonant capacitor Cv equivalently connected between the output of the half bridge and GND and the inductance component (Lm+Llk) of the primary winding Np.

[0036] In the example shown in FIG. 3, there is a period T7 in the middle of the period T6 during which the resonant switch QR is turned on while the main switch QM remains off, and the excitation current is increased in the opposite direction to that in the period T1.

[0037] Furthermore, in the example shown in FIG. 3, after the end of the period T7, there is a period T8 in which the main switch QM remains off and the resonant switch QR is turned off to reduce the voltage of the main switch QM.

[0038] The control method for the half-wave LLC converter 10 according to the first embodiment is characterized in that the timing of the period T4 is controlled so that the duration of the period T5 is equal to or shorter than the resonance period Tcrlk.

[0039] The control method according to the present embodiment shown in Fig. 3 is characterized in that it newly includes a flyback period, period T3, compared with the conventional control method shown in Fig. 2. Therefore, while the period T5 becomes longer in the conventional example (comparative example) as the load current increases, the control method of the present invention is characterized in that the period T3, which is the flyback period, becomes longer.

[0040] In the above-described conventional control, the circulating current increases with an increase in the load current, whereas in the control of this embodiment, the circulating current does not increase. This will be described with reference to FIG.

[0041] Figure 4(a) shows the same timing as Figure 2(f). Figures 4(b) to (f) show operating waveforms from a simulation using the same circuit constants as Figure 4(a) when the timing at which the resonant switch QR is turned on by the P1 signal is changed between times t2 and t6, when the excitation current decreases after the main switch QM is turned off by the P0 signal (see Figure 6).

[0042] Fig. 4(a) shows the operation waveform when operating under conventional control, where the period T5 is 1.2 x Tcrlk. Also, Fig. 4(b) shows the operation waveform when the timing of the P1 signal is delayed backward and the period T5 is Tcrlk.

[0043] Fig. 4(c) shows the operation waveforms when the timing of the P1 signal is further delayed to set the duration of period T5 to 0.7 x Tcrlk. Fig. 4(d) shows the operation waveforms when the timing of the P1 signal is further delayed to set the duration of period T5 to 0.4 x Tcrlk. Fig. 4(e) shows the operation waveforms when the timing of the P1 signal is further delayed to set the duration of period T5 to 0.1 x Tcrlk.

[0044] In the example shown in FIG. 4, it can be seen that the waveform of the current IdM of the main switch QM does not change, but the current IdR of the resonant switch QR and the current If of the secondary side diode Ds change significantly.

[0045] From the simulation data, the average current and effective current of the current IdR of the resonant switch QR are as follows:

[0046] In FIG. 4(a), the average current is 210mAave and the effective current is 1192Arms. In FIG. 4(b), the average current is 209mAave and the effective current is 1061Arms. In FIG. 4(c), the average current is 207mAave and the effective current is 846Arms. In FIG. 4(d), the average current is 206mAave and the effective current is 712mArms. In FIG. 4(e), the average current is 205mAave and the effective current is 657mArms.

[0047] Moreover, the average current and effective current of the current If of the diode Ds are as follows:

[0048] In FIG. 4(a), the average current is 3.0 Aave and the effective current is 8.00 Arms. In FIG. 4(b), the average current is 3.0 Aave and the effective current is 7.33 Arms. In FIG. 4(c), the average current is 3.0 Aave and the effective current is 6.12 Arms. In FIG. 4(d), the average current is 3.0 Aave and the effective current is 5.35 Arms. In FIG. 4(e), the average current is 3.0 Aave and the effective current is 4.80 Arms.

[0049] Because the average current IdR of the resonant switch QR is equal to the average current of the main switch QM, it can be seen in Fig. 4 that the input current decreases from (a) to (e). This means that the effective current flowing through the resonant switch QR and the transformer T decreases, reducing losses due to the on-resistance of the resonant switch QR and the resistance component of the transformer T, improving efficiency.

[0050] This also indicates that the further back the P1 signal is delayed, the less the period T5 during which the energy of the excitation inductance Lm stored in the period T1 cannot be output to the secondary side and the resonant capacitor Cr is charged and the circulating current increases. In other words, this appears as the effect of providing a new period T3 during which the energy of the excitation inductance Lm stored in the period T1 can be output to the secondary side.

[0051] In addition, the further back the P1 signal is delayed, the wider the period T3 becomes, making it possible to directly output the stored excitation energy to the secondary side, and the narrower the period T5 becomes, thereby reducing the circulating current.

[0052] Therefore, loss will be minimized if the pulse width of the P1 signal is Tcrlk / 2 and the off timing of P1 is set to the time when the excitation current becomes zero.

[0053] Therefore, the on-width of the P1 signal should be Tcrlk / 2, and the on-timing should be Tcrlk / 2 before the timing when the excitation current becomes zero. However, when commercializing, a margin is required, so with reference to the waveform in Figure 4, it is sufficient to set the period T3 to be provided, for example, as shown in Figure 4(b), so that the period T5 is less than the resonance period Tcrlk.

[0054] Figure 5 shows the operating waveforms of a model-based simulation performed when the control method of the present invention is applied. In the example shown in Figure 5, the peak values ​​of the current IdR of the resonant switch QR and the current If of the diode Ds, which is the secondary side rectifier element, are lower than in the example shown in Figure 2, and it can be seen that the effective current is lower.

[0055] (Configuration of half-wave LLC converter 10) The half-wave LLC converter 10 according to this embodiment relates to a control method for a main switch QM and a resonant switch QR, and a control IC that controls the main switch QM and the resonant switch QR. In the first embodiment, the control IC corresponds to the control unit 100a. Details of the circuit of the half-wave LLC converter 10 are as shown in the description of FIG. 1 above.

[0056] The key to control in this embodiment is to make the period T5 as short as possible and the period T3 as long as possible. Also, the off-timing of the resonant switch QR is preferably the period T5 that allows ZVS, and considering the variations in the on-timing and on-width, the period T5 is preferably equal to or less than Tcrlk with a margin. Also, the period T4 is 1 / 2 of the resonant period. Therefore, if the time when the excitation current becomes zero is tz, the on-time of the P1 signal is set to tz-1.5×Tcrlk to tz-Tcrlk / 2, the on-width is set to Tcrlk / 2 or more, and the off-time is set to before tz.

[0057] In addition, the on timing of the P1 signal can be determined by detecting the excitation current, turning it on at time t4 when it coincides with the value of a predetermined threshold signal Vth1, and setting the value of the threshold signal Vth1 and the pulse width of P1 so that it is turned off during period T5 after Tcrlk / 2 has elapsed.

[0058] (Configuration of half-wave LLC converter 10 and control IC) A half-wave LLC converter 10 and a control IC according to a first embodiment will be described with reference to FIGS.

[0059] As shown in FIG. 1, the half-wave LLC converter 10 includes a first series circuit in which a main switch QM and a resonant switch QR are connected in series across a DC power supply Vin, and a second series circuit in which a primary winding Np and a resonant capacitor Cr are connected in series across the resonant switch QR.

[0060] The main switch QM and the resonant switch QR are each made of a metal oxide semiconductor field effect transistor (MOSFET), and each has a body diode DM and DR between the drain and source.

[0061] In addition, the MOSFET has an output capacitance Coss between the drain and source. The capacitance of this output capacitance Coss appears in the resonant operation, and in order to simplify the explanation of the operation, in Figure 1 it is connected to both ends of the resonant switch QR as a resonant capacitor Cv, but it is not necessary to attach a capacitor other than the output capacitance Coss of the MOSFET.

[0062] Furthermore, the main switch QM and the resonant switch QR may be switch elements made of compound semiconductors such as GaN (gallium nitride) and SiC (silicon carbide). The main switch QM and the resonant switch QR may be configured with an IGBT (insulated gate bipolar transistor). If the element structure does not include a body diode, it can be replaced by separately adding body diodes DM and DR. For convenience of explanation, the main switch QM and the resonant switch QR are described in this specification as MOSFETs.

[0063] Furthermore, the half-wave LLC converter 10 includes a transformer T having a secondary winding Ns electromagnetically coupled with the primary winding Np in reverse polarity. The transformer T is configured such that the primary winding Np has an excitation inductance Lm, and the coupling coefficient between the primary winding Np and the secondary winding Ns is less than 1 so that the primary winding Np has a leakage inductance Llk. In addition, a first rectifier circuit that rectifies and smoothes the voltage on the secondary side is connected to both ends of the secondary winding Ns of the transformer T, in which a diode Ds as a rectifier element and an output capacitor Co are connected in series. The first rectifier circuit corresponds to a rectifier smoothing circuit.

[0064] Furthermore, the transformer T has an auxiliary winding Na, and both ends of the auxiliary winding Na are connected to a second rectifier circuit in which a rectifier element Da and an output capacitor Ca are connected in series.

[0065] Furthermore, the half-wave LLC converter 10 includes an output voltage detection unit 200 that detects the output voltage Vo, a winding voltage detection means that detects the winding voltage, and an IdM detection means that detects the current IdM of the main switch QM.

[0066] Here, the current detection means (IdM detection means) of the main switch QM is configured by connecting a series circuit of a capacitor Cs and a resistor Rs across the resonant capacitor Cr as shown in Fig. 1, and setting the capacitance of the capacitor Cs to 1 / 10 or less of the capacitance of the resonant capacitor Cr. Although a detection resistor may be connected in series to the resonant capacitor as in the conventional technology, the configuration shown in Fig. 1 reduces the power consumed by the resistor Rs to 1 / 10 or less. In addition, the current detection means (IdM detection means) is also capable of detecting the current of the resonant switch QR.

[0067] The control unit 100a turns the main switch QM on and off based on the output signals of the output voltage detection unit 200 and the IdM detection means. In addition, the control unit 100a turns the resonant switch QR on and off twice during the off period of the main switch QM using a P1 signal which is a first pulse signal and a P2 signal which is a second pulse signal.

[0068] 6, the control unit 100a has a current source Icc. The control unit 100a also generates a Vfb signal indicating a feedback voltage based on an output signal from the output voltage detection unit 200. The control unit 100a further includes a comparator 114 that compares the Isense signal with the Vfb signal.

[0069] The comparator 114 is connected so that the Isense signal goes High when the value of the Vfb signal exceeds the value of the Vfb signal, and outputs the signal to an R terminal of an SR-FF 115 (SR flip-flop). A P0S signal is input to an S terminal of the SR-FF 115, and the comparator 114 outputs a P0 signal that sets the output of the SR-FF 115 to High at the falling edge of the P0S signal and sets the output of the SR-FF 115 to Low.

[0070] The control unit 100a also includes a first driving means 151 that receives the P0 signal and generates a signal to drive the main switch QM of the half-wave LLC converter 10. The first driving means 151 controls the ON width of a driving signal VgsM for the main switch QM to control the output voltage to a constant voltage. The driving signal VgsM corresponds to the first driving signal.

[0071] Furthermore, the control unit 100a has an output voltage detection means 111 that receives the auxiliary winding voltage Vna, generates a VoD signal indicating a voltage proportional to the output voltage, and outputs the VoD signal to the P1 threshold generation means 144. The VoD signal corresponds to a second voltage signal.

[0072] The control unit 100a also includes a zero-cross detection means 112 that receives the auxiliary winding voltage Vna and outputs a ZCD signal, which is a pulse signal that detects a zero voltage at which the voltage of the auxiliary winding Na changes from a negative voltage to a positive voltage, to the P2 delay means 143. The ZCD signal corresponds to a zero-cross signal. The P2 delay means 143 corresponds to a second pulse delay means.

[0073] Furthermore, the control unit 100a has an excitation current detection means 113 that receives the auxiliary winding voltage Vna, generates an LmC signal indicating a voltage proportional to the excitation current, and outputs the LmC signal to the P1 generation means 121. The LmC signal corresponds to a first voltage signal.

[0074] The P1 threshold generating means 144 generates a threshold signal Vth1 by multiplying the VoD signal, which is the output of the output voltage detecting means 111, by a preset ratio so that the threshold becomes a value indicated by a threshold signal Vth1 described later, and outputs the generated signal to the P1 generating means 121. That is, when the value of the VoD signal increases or decreases, the value of the threshold signal Vth1 also increases or decreases proportionally. The P1 threshold generating means 144 corresponds to a first pulse threshold generating means.

[0075] The P1 generating means 121 sets the P1 signal to High based on the LmC signal of the excitation current detecting means 113 and the threshold signal Vth1 of the P1 threshold generating means 144, and sends out a signal with a preset pulse width. The P1 generating means 121 corresponds to a first pulse generating means.

[0076] Here, the preset ratio in the P1 threshold generating means 144 and the preset pulse width in the P1 generating means 121 are determined as follows: The time when the excitation current becomes zero is defined as time tz.

[0077] The timing at which the P1 signal generated by the P1 generating means 121 becomes High is 0.5×Tcrlk to 1.5×Tcrlk before the time tz. In this embodiment, Tcrlk indicates a resonance period. The P1 signal corresponds to a first pulse signal.

[0078] The timing at which the P1 signal goes low is set to be earlier than time tz. Furthermore, the pulse width of the P1 signal is set to 0.5×Tcrlk or more. The threshold signal Vth1 of the P1 threshold generating means 144 and the pulse width of the P1 generating means 121 are determined so that a P1 signal with such a pulse width is generated.

[0079] By performing the above-mentioned settings, even if the output voltage changes, the timing when the P1 signal goes High is before 0.5×Tcrlk to 1.5×Tcrlk described above, and the timing when the P1 signal goes Low is before the time tz when the excitation current becomes zero. If the output voltage does not change, the threshold signal Vth1 may be a threshold voltage that is predetermined to have the timing described above. The predetermined threshold voltage corresponds to the third voltage signal.

[0080] The control unit 100 a further includes an enable signal generating means 130 a that receives the P 1 signal, the P 0S signal, and the Vfb signal, and outputs the Enb signal, which is a pulse signal based on the voltage of the Vfb signal, to the P 2 delay means 143 .

[0081] The control unit 100a also has a P2 delay means 143. The P2 delay means 143 receives the Enb signal and the ZCD signal, and outputs a P2Dy signal to the P2 generation means 122 to turn on the resonant switch QR after a predetermined delay time has elapsed, using the ZCD signal when the Enb signal is High as a trigger.

[0082] The control unit 100a also includes a P2 generating means 122 that receives a P2Dy signal, outputs a P2 signal having a preset pulse width, and outputs the P2 signal to the second driving means 152. The P2 generating means 122 corresponds to a second pulse generating means. The P2 signal corresponds to a second pulse signal.

[0083] The control unit 100a further includes a P0 timing generating means 141 that outputs a P0S signal, which is a preset pulse signal, from an edge of the P2 signal. The control unit 100a further includes a second driving means 152 that receives the P1 signal and the P2 signal and outputs a driving signal VgsR that drives the resonant switch QR of the half-wave LLC converter 10.

[0084] Fig. 7 is a diagram showing the excitation current detection means 113 configured with an operational amplifier. If configured with an integrating circuit as shown in Fig. 7, the auxiliary winding voltage Vna is integrated, and the excitation current detection means 113 outputs an LmC signal indicating a voltage proportional to the excitation current.

[0085] 8 is a diagram showing a configuration of an enable signal generating means 130a of a control unit 100a according to a first embodiment of the present invention. The enable signal generating means 130a includes a reference voltage Vfbmin and an amplifier OP-Amp that outputs a voltage VT obtained by amplifying a voltage difference between a Vfb signal indicating a feedback voltage and the reference voltage Vfbmin. The enable signal generating means 130a also includes a VRamp circuit. In the VRamp circuit, a reference current Iosc, a capacitor Cosc that charges the reference current Iosc, and a switch Sosc that resets the capacitor Cosc are connected in parallel. In the VRamp circuit, the switch Sosc is turned on by a P0S signal and turned off by an edge of a P1 signal, and the reference current Iosc charges Cosc to generate a ramp voltage VR.

[0086] The enable signal generating means 130a also includes a comparator COMosc having a negative terminal connected to the voltage VT and a positive terminal connected to the lamp voltage VR, and outputs an Enb signal, which is a pulse signal that becomes High when the lamp voltage VR exceeds the voltage VT.

[0087] 9A to 9D show operational waveforms of the half-wave LLC converter 10 to which the control by the control unit 100a of the half-wave LLC converter 10 according to the first embodiment is applied.

[0088] 9A to 9D, (a) to (e) are operational waveforms when the output current decreases from (a) to (e). Due to the configuration of output voltage detection unit 200 and control unit 100a, the voltage of the Vfb signal decreases as the output current decreases.

[0089] FIG. 9A(a) shows the waveform when the output current is large, and is an operational waveform when the Vfb signal is higher than the reference voltage Vfbmin.

[0090] In the period T1, at time t1, the P0S signal goes High, the SR-FF 115 is set, and the P0 signal goes High. In addition, when the drive signal VgsM goes High and the main switch QM is turned on, the current of the main switch QM increases and the voltage of the Isense signal rises.

[0091] When the voltage of the Isense signal reaches the voltage of the Vfb signal at time t2, the comparator output goes High, the SR-FF 115 is reset, and the P0 signal goes Low. In addition, the drive signal VgsM goes Low, and the main switch QM turns off.

[0092] During period T1, if the voltage of the resonant capacitor Cr is Vcr, the difference between the voltage of the DC power supply Vin and Vcr is applied to the leakage inductance Llk and the excitation inductance Lm. Therefore, the current Itran of the primary winding Np of the transformer T is expressed by the following equation (1) and increases over time. Both the excitation inductance Lm and the leakage inductance Llk accumulate the current in Itran. In addition, the auxiliary winding voltage Vna generates a negative voltage proportional to the voltage difference between Vin and Vcr. [Number 1] Itran={(Vin-Vcr) / (Lm+Llk)}×t ···(1)

[0093] At time t2, when the main switch QM is turned off, the auxiliary winding voltage Vna crosses zero from negative to positive, but since the Enb signal is low, the output of the P2 delay means 143 remains at zero.

[0094] In period T2, when QL is turned off at time t2, the energy stored in the magnetizing inductance Lm and the leakage inductance Llk generates a back electromotive force.

[0095] Since the leakage inductance Llk is not coupled to the secondary winding Ns, it is not output from the secondary winding Ns to the first rectifier circuit, and is charged to the resonant capacitor Cr together with a portion of the energy of the excitation inductance Lm. On the other hand, the excitation inductance Lm is an inductance coupled to the secondary winding Ns. Therefore, the back electromotive force is generated in a direction that causes the diode Ds connected to the secondary winding Ns of the transformer T to conduct, and the remaining energy of the excitation inductance Lm that is charged to the resonant capacitor Cr is output to the secondary side.

[0096] Then, at time t3, when the leakage energy is completely charged into the resonant capacitor Cr, the energy of the magnetizing inductance Lm is completely output to the secondary side.

[0097] In conventional control, the resonant switch QR is turned on during the period T2, but in this embodiment, the resonant switch QR is basically not turned on during the period T2, which is different from conventional control.

[0098] However, when the load current decreases and the voltage of the Vfb signal decreases, the period T1 becomes shorter, and as a result, when the maximum value of the LmC signal approaches the value of the threshold signal Vth1, the resonant switch QR may turn on in the period T2. However, such an operation is also included in the scope of this embodiment.

[0099] In period T3, both the main switch QM and the resonant switch QR are off. At time t3, the energy stored in the leakage inductance Llk becomes zero, and the energy stored in the excitation inductance Lm is output from the secondary winding Ns to the first rectifier circuit. This period is the same as the operation of a normal flyback converter, and period T3 corresponds to the flyback period.

[0100] During periods T2 and T3, the energy stored in the excitation inductance Lm is output from the secondary winding Ns to the first rectifier circuit, so that the auxiliary winding voltage Vna is proportional to the output voltage, and the output of the excitation current detection means 113 decreases in proportion to the excitation current.

[0101] During the period T4, at time t4, the value of the LmC signal decreases, and when the value of the LmC signal becomes equal to the threshold signal Vth1, the P1 generation means 121 turns on the resonant switch QR.

[0102] Since the energy of the magnetizing inductance Lm is output to the secondary side, when the resonant switch QR is turned on, a resonant current flows between the resonant capacitor Cr and the leakage inductance Llk.

[0103] Therefore, the P1 generating means 121 has an ON width of at least 1 / 2 of the resonance period Tcrlk of the resonance capacitor Cr and the leakage inductance Llk. In addition, the P1 threshold generating means 144 sets the value of the threshold signal Vth1 and the P1 generating means 121 sets the pulse width of the P1 signal so that the OFF time of the P1 signal is between (tz-Tcrlk) and time tz, where tz is the time t6 when the excitation current becomes zero.

[0104] In the period T5, 1 / 2Tcrlk has elapsed since the resonant switch QR was turned on, and the resonant current is limited by the excitation current, and the excitation current charges the resonant capacitor Cr through the resonant switch QR. In the period T5, a current flows from the source to the drain of the resonant switch QR. The period T5 corresponds to the excitation current charging period.

[0105] Since the P1 signal is generated under the conditions described above, the P1 signal turns off during the period T5. Even if the resonant switch QR turns off during this period, the current path does not change because the current is commutated to the body diode DR after it is turned off.

[0106] Period T5 ends when the excitation current becomes zero at time t6. During period T6, the excitation current becomes zero at time t6, but because the resonant switch QR is off, the excitation current does not flow in the negative direction as in typical complementary control. As a result, resonance occurs between the resonant capacitor Cv and the excitation inductance Lm, which is the inductance of the primary winding Np of the transformer T, and the leakage inductance Llk, and the voltages of the main switch QM, the resonant switch QR, and each winding oscillate with the resonant period Tcvlm.

[0107] The enable signal generating means 130a starts increasing the ramp voltage VR at the time when the P1 signal is turned off. Since it is only necessary for the ramp voltage VR to be able to detect the first zero crossing after the excitation current becomes zero, the ramp voltage VR may be configured to start increasing at the time when the LmC signal, which is the output of the excitation current detecting means 113, becomes zero.

[0108] In (a) of FIG. 9A, since the voltage of the Vfb signal is higher than the voltage of the reference voltage Vosc, the voltage VT of the enable signal generating means 130a is zero, and the enable signal Enb signal becomes High when the P1 signal becomes Low during period T5.

[0109] The P2 delay means 143 receives the ZCD signal after the Enb signal becomes High and sends out a signal with a preset pulse width, so in (a) of Figure 9A, it outputs a signal P2Dy with a preset pulse width based on the initial ZCD signal.

[0110] The preset pulse width is Tcvlm / 4 because the ZCD signal detects the negative to positive zero crossing of the auxiliary winding voltage Vna, which oscillates with a period of Tcvlm. As a result, the time t7 of the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the resonant switch QR.

[0111] In the above example, the zero-cross detection means 112 detects the zero-crossing of the auxiliary winding voltage Vna, which changes from negative to positive, and P2Dy is described as Tcvlm / 4. Even if the zero-cross detection means 112 detects the zero-crossing of the auxiliary winding voltage Vna, which changes from positive to negative, and the pulse width of P2Dy is (3 / 4)×Tcvlm, this corresponds to time t7 of the edge of the pulse signal of the P2Dy signal, and the voltage across the resonant switch QR becomes the minimum value.

[0112] The resonant switch QR is turned on during a period T7, and a negative excitation current flows during that period. The time t7 is an edge of the P2Dy signal, and the P2 generating means 122 generates a P2 signal having a pulse width set in advance at the edge of the P2Dy signal, and outputs the P2 signal to the second driving means 152.

[0113] The preset pulse width is the energy stored by passing a negative current through the inductance of the primary winding Np of the transformer T during period T7, and is set to charge the resonant capacitor Cv and make it equal to or greater than the voltage of the DC power supply Vin, thereby setting the main switch QM to zero volts.

[0114] In the present embodiment, the second ON timing of the resonant switch QR is the same as that in the conventional non-complementary control, but no resonant current flows.

[0115] Therefore, when the voltage of the resonant capacitor Cr is Vr, the on-width Ton2 of the P2 signal, which is a pulse for making the capacitance of the resonant capacitor Cv zero, is expressed by the following equation (2).

number

[0116] The average value of the voltage Vr of the resonant capacitor Cr is the turns ratio N=Np / Ns times the output voltage Vo, so if we consider Vr=N·Vo, it can be expressed by the following equation (3).

number

[0117] Therefore, if the on-width of Ton2 at which ZVS is possible when the maximum value of the input voltage is Vinmax is Ton2max, it is expressed by the following equation (4).

number

[0118] Furthermore, the P2 generating means 122 generates a P2 signal with a preset pulse width Ton2max at the edge of the P2Dy signal and outputs it to the driving means 2, thereby enabling ZVS even if the input voltage drops.

[0119] The above is one example of the settings, and the on-width given by the above formula when the input voltage is Vintyp, which is smaller than Vinmax, may be preset as Ton2typ. In this case, when the input voltage is at its maximum value, ZVS is not used, and the on-state occurs at the minimum voltage point, but this has the advantage that the negative current can be reduced, resulting in higher efficiency when the input voltage is below Vtyp.

[0120] In addition, because the optimal Ton2 pulse width is correlated with the output voltage and input voltage, the P2 generating means 122 can achieve optimal ZVS by incorporating a means for detecting the input voltage and output voltage and correcting Ton2 with the input / output voltage. In addition, the P2 generating means 122 can achieve optimal ZVS even if the input voltage and output voltage are changed, allowing the configuration of a highly efficient power supply.

[0121] In period T8, the P0 timing generating means 141 sends out a P0S signal with a preset pulse width from the edge of the P2 signal. The P0 signal goes High at the edge of the P0S signal, turning on the main switch QM, and the period ends.

[0122] When the resonant switch QR is turned off at time t8, this is the period in which the resonant capacitor Cv is discharged by the negative current flowing through the inductance of the primary winding Np.

[0123] During this period T8, the inductance component of the primary winding Np and the resonant capacitor Cv resonate. In addition, during period T8, the voltage of the main switch QM drops due to voltage resonance, and the time DT from when the resonant switch QR is turned off to when the resonant voltage reaches its minimum point is expressed by the following equation (5), where Tcvlm is the resonant period.

number

[0124] The P0 timing generating means 141 outputs a P0S signal having a pulse width that is set in advance based on the above formula from the edge of the P2 signal.

[0125] In addition, since Vac=N·Vo, the time DT is expressed by the following equation (6).

number

[0126] By having the P0 timing generation means 141 detect the input voltage and output voltage and correct the pulse width of the P0S signal based on the input / output conditions, more optimal ZVS becomes possible, and the input voltage changes to configure a highly efficient power supply. Therefore, the P0 timing generation means 141 may incorporate a means for detecting the input voltage and output voltage and correcting the pulse width of the P0S signal based on the input / output conditions.

[0127] (b) in Fig. 9B shows the operating waveform when the output current is less than (a) in Fig. 9A. Because the voltage of the Vfb signal is lower than (a), the current peak IdMp is controlled to a lower value than in (a) and the period T3 is shorter, but because the value of the Vfb signal is slightly higher than the reference voltage Vfbmin, the operation from period T4 onwards is the same as (a).

[0128] 9B(c) shows the operation waveforms when the output current is further reduced and the voltage of the Vfb signal becomes equal to the reference voltage Vfbmin. As in FIG. 9B(b), IdMp is controlled to a low value and the period T3 is shortened, but since the value of the Vfb signal is equal to the reference voltage Vfbmin, the operation from the period T4 onwards is the same as FIG. 9A(a).

[0129] Figure 9C (d) shows the operating waveform when the output current is further reduced, and Vfb becomes a voltage slightly lower than Vfbmin. Also, IdMp in Figure 9C (d) is limited to approximately the same extent as Figure 9B (c). Furthermore, IdMp in Figure 9C (d) amplifies the slight potential difference between the value of the Vfb signal and the value of the reference voltage Vfbmin, increasing the voltage VT, and delaying the Enb signal, lengthening the period T6, and controlling the output voltage to a constant level.

[0130] FIG. 9D(e) shows the operating waveform when the output current is even smaller than FIG. 9C(d), where IdMp is approximately the same, and the period T6 is longer, controlling the output voltage to a constant value.

[0131] As described above, the control unit 100a of the half-wave LLC converter 10 according to the first embodiment includes an excitation current detection means 113 that detects the excitation current of the transformer T in order to generate the timing of time t4. This control IC is characterized in that it determines the timing of the period T4 based on the time when the excitation current reaches the value of a predetermined threshold signal Vth1 based on the LmC signal that is the output of the excitation current detection means 113. Also, Fig. 7 shows an example of the circuit configuration of the excitation current detection means 113, and a voltage proportional to the excitation current can be obtained by integrating the winding voltage of the transformer T.

[0132] As described above, the control unit 100a includes an excitation current detection means 113 that detects the excitation current of the transformer T and outputs a first voltage signal proportional to the excitation current, and an output voltage detection means 111 that outputs a second voltage signal proportional to the output voltage. The first voltage signal corresponds to the LmC signal. The second voltage signal corresponds to the VoD signal. The control unit 100a sets the timing of turning on the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, thereby causing a part of the excitation current to flow through the rectifying and smoothing circuit. As a result, the slope of the excitation current decrease becomes gentler as the output voltage decreases and becomes steeper as the output voltage increases, so that the value of the threshold signal Vth1 is adjusted in proportion to the output voltage.

[0133] Furthermore, the control unit 100a detects the time when the voltage across the resonant switch QR reaches a minimum value, and controls the time when the resonant switch QR is turned on, which is the start time of period T7, to the time when the voltage across the resonant switch QR reaches its minimum value. The control unit 100a includes zero-cross detection means 112 that detects the zero-cross time of the voltage of the auxiliary winding Na and sends a zero-cross signal (ZCD signal) as a method for detecting the time when the voltage across the resonant switch QR reaches its minimum value. The control unit 100a also includes P2 generation means 122 that sends a P2 signal that turns on the resonant switch QR after a predetermined delay time based on this ZCD signal.

[0134] Furthermore, the P2 generating means 122 includes a P2 delay means 143 that delays the P2Dy signal based on the signal of the enable signal generating means 130a. This enables the half-wave LLC converter 10 to lengthen the period T6 and reduce the frequency when the load current decreases.

[0135] As described above, the control unit 100a in the first embodiment has a first output voltage control means for controlling the ON width of the main switch QM as a means for controlling the output voltage. Also, a second output voltage control means for controlling the period T6 during which both the main switch QM and the resonant switch QR are OFF is provided as a means for controlling the output voltage. Therefore, compared to the conventional control method, the circulating current is reduced, and ZVS is possible over a wide range of output current, realizing a highly efficient and low-noise power supply.

[0136] Second embodiment 9A to 9D, when looking at the change in operating frequency in the first embodiment, the highest frequency occurs at the point where the first output voltage control means that controls the on-width of the main switch QM switches to the second output control means that controls the period T6. For example, in order to reduce the size of a power supply, it is necessary to increase the operating frequency when the output current is large and reduce the size of the passive components that make up the power supply, such as the transformer T and the capacitor.

[0137] In order to realize a more efficient and compact power supply device than the control of this embodiment, a method of controlling the operating frequency by coordinating the first output control means and the second output control means will be described below as a second embodiment.

[0138] FIG. 10 is a block diagram showing a control unit 100b for implementing control of the half-wave LLC converter 10 according to the second embodiment.

[0139] The control unit 100b according to the second embodiment differs from the control unit 100a according to the first embodiment in that it includes a disable signal generating means 142. The differences from the control unit 100a according to the first embodiment will be described below.

[0140] The control unit 100b has a disable signal generating means 142 that outputs to a P2 delay means 143 a disable signal Dis that goes High in response to a P0S signal and goes Low after a preset delay time has elapsed upon receipt of a P1 signal.

[0141] The control unit 100b also includes an enable signal generating means 130b that is reset by the P0S signal and outputs an Enb signal, which is a pulse signal based on the voltage of the Vfb signal, to the P2 delay means 143.

[0142] Furthermore, the control unit 100b has a P2 delay means 143 that receives the Dis signal, the Enb signal, and the ZCD signal, and outputs a P2Dy signal to the P2 generation means 122 using the ZCD signal as a trigger when the Dis signal is Low and the Enb signal is High.

[0143] FIG. 11 is a diagram showing the configuration of an enable signal generating means 130b of a control unit 100b according to the second embodiment.

[0144] The enable signal generating means 130b includes a reference voltage Vosc, a subtraction circuit that outputs a voltage VT obtained by subtracting the voltage of the Vfb signal from the reference voltage Vosc, and a reference current Iosc. The enable signal generating means 130b also includes a VRamp circuit. In the VRamp circuit, a capacitor Cosc that charges the reference current Iosc and a switch Sosc that resets the capacitor Cosc are connected in parallel, and when the P0S signal becomes L, Iosc charges Cosc to generate a ramp voltage VR. The enable signal generating means 130b also includes a comparator COMosc that connects the voltage VT to its negative terminal and the ramp voltage VR to its positive terminal, and outputs an Enb signal that is a pulse signal that becomes High when the ramp voltage VR exceeds the voltage VT.

[0145] Fig. 12 is a diagram showing the operation waveforms of the enable signal generating means 130a of Fig. 11. Fig. 12(a) to (d) show the operation waveforms when the output current increases toward the right side of the figure. Also, due to the configuration of the output voltage detection unit 200 and the control unit 100b, the voltage of the Vfb signal increases as the output current increases.

[0146] Because the reference current Iosc is a preset current source, the slope of the ramp voltage VR increases at a constant rate. As the output current increases, the value of the Vfb signal rises, and as the difference with the reference voltage Vosc becomes smaller, the voltage VT decreases, shortening the time it takes for the Enb signal to go high. When the value of the Vfb signal becomes higher than the value of the reference voltage Vosc, it goes high when the P0S signal goes low.

[0147] Fig. 13 is a diagram showing the characteristics of the enable signal generating means 130b in Fig. 11. The horizontal axis indicates the value of the Vfb signal, and the vertical axis indicates the time Enb_Delay from when Sosc is turned off until the Enb signal goes High.

[0148] The reference current Iosc is a preset current source, and the slope of the ramp voltage VR increases at a constant rate. The voltage VT is the difference between the preset reference voltage Vosc and the voltage of the Vfb signal. Therefore, as shown in FIG. 13, the time Enb_Delay from when the switch Sosc is turned off until the Enb signal becomes High is expressed by the following formula (7) as a characteristic of the enable signal generating means 130b according to the second embodiment. As shown in formula (7), the time Enb_Delay is controlled so as to be negatively proportional to the Vfb signal. Here, a=-(Cosc / Iosc) and b=Cosc×(Vosc / Iosc). [Number 7] Enb_Delay = a×Vfb + b( a<0 ,B>0)...(7)

[0149] 14A to 14D show operational waveforms of the half-wave LLC converter 10 to which the control unit 100b of the half-wave LLC converter 10 according to the second embodiment is applied.

[0150] 14A to 14D show operational waveforms when the output current decreases from (a) to (d). Due to the configuration of output voltage detection unit 200 and control unit 100b, the voltage of the Vfb signal decreases as the output current decreases.

[0151] FIG. 14A (a) shows the operational waveform when the output current is large and the voltage of the Vfb signal is higher than the voltage of the reference voltage Vosc.

[0152] The operation during the period T1 is the same as that in the first embodiment shown in FIGS. 9A to 9D.

[0153] When the main switch QM is turned off at time t2, the auxiliary winding voltage Vna crosses zero from negative to positive, but in (a) of Fig. 14A, the voltage VT of the enable signal generating means 130b is zero because the Vfb voltage is higher than the reference voltage Vosc. Also, although the enable signal Enb signal is high, the output of the P2 delay means 143 remains at zero because the disable signal Dis is high.

[0154] The operations in periods T2 to T6 are the same as those in the first embodiment shown in FIGS. 9A to 9D.

[0155] The disable signal generating means 142 is set to become Low after a preset delay time from the off time of the P1 signal. The preset delay time is set in advance so that the first zero crossing after the excitation current becomes zero can be detected, since the off time of the P1 signal is generated based on the time when the excitation current becomes zero. In the example shown in Fig. 14A to Fig. 14D, the delay time is set to be immediately after the time t6 when the excitation current becomes zero.

[0156] In FIG. 14A(a), since the voltage of the Vfb signal is higher than the voltage of the reference voltage Vosc, the voltage VT of the enable signal generating means 130b is zero, and the enable signal Enb signal is already High.

[0157] The P2 delay means 143 receives the ZCD signal after the Enb signal is High and the Dis signal has gone Low, and outputs a signal with a preset pulse width. Therefore, in (a) shown in FIG. 14A, the P2 delay means 143 outputs a signal P2Dy with a preset pulse width based on the ZCD signal after the Dis signal has gone Low.

[0158] The ZCD signal output from the zero-cross detection means 112 detects the negative to positive zero-crossing of the auxiliary winding voltage Vna, which oscillates with a resonant period Tcvlm. Therefore, by setting the pulse width of the P2Dy signal to Tcvlm / 4 in advance, the time t7 of the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the resonant switch QR.

[0159] In this example, the zero-cross detection means 112 detects the zero-crossing of the auxiliary winding voltage Vna, where the voltage changes from negative to positive. Furthermore, even if the zero-cross detection means 112 detects the zero-crossing of the voltage Vna, where the voltage changes from positive to negative, and the pulse width of the P2Dy signal is (3 / 4)×Tcvlm, the edge of the pulse signal of the P2Dy signal occurs at time t7. As a result, the P2Dy signal becomes the minimum value of the voltage across the resonant switch QR.

[0160] The operations in periods T7 and T8 are the same as those in the first embodiment shown in FIGS. 9A to 9D.

[0161] FIG. 14B (b) shows an operational waveform when the output current is smaller than that shown in FIG. 14A (a) and the Vfb voltage is lower than the reference voltage Vosc.

[0162] The voltage of the Vfb signal is lowered, and the IdM current peak IdMp is lowered, and the period T1 is shortened. Since the voltage of the Vfb signal is lower than the reference voltage Vosc, the enable signal generating means 130b outputs a voltage VT based on the difference between the values ​​of Vosc and the Vfb signal, and the Enb_Delay time is lengthened. As a result, the Enb signal becomes High after the time when the Dis signal becomes Low. Therefore, the P2Dy signal is sent based on the ZCD signal after the Enb signal becomes High, and the P2 ON signal is output, and in (b), the resonant switch QR is turned on at the minimum value of the second voltage oscillation. Therefore, the periods T1 and T3 are shortened, but the period T6 is lengthened, and the operating frequency is reduced.

[0163] (c) and (d) shown in Figures 14C and 14D are operational waveforms when the output current is even smaller than (b) shown in Figure 14B, and the voltage of the Vfb signal is even lower than the voltage of the reference voltage Vosc.

[0164] As the voltage of the Vfb signal decreases, the IdL current peak decreases further, period T1 becomes shorter, and periods T1 and T3 become shorter, but period T6 becomes longer, resulting in a further decrease in the operating frequency.

[0165] Comparing the operating frequencies of the half-wave LLC converter 10 according to the first embodiment and the half-wave LLC converter 10 according to the second embodiment, when the output current is 3A, both remain unchanged at 106kHz. When the output current is 2A, the operating frequency changes from 131kHz to 108kHz. When the output current is 1.5A, the operating frequency changes from 151kHz to 89kHz. When the output current is 1A, the operating frequency changes from 101kHz to 71kHz. When the output current is 0.5A, the operating frequency changes from 54kHz to 48kHz.

[0166] Fig. 15 is a diagram showing the operating frequency in the second embodiment. (a) in Fig. 15 shows the fluctuation of the operating frequency in the output current of the first embodiment. (b) in Fig. 15 shows the fluctuation of the operating frequency in the output current of the second embodiment.

[0167] Therefore, compared to the control method of the first embodiment, frequency fluctuations are suppressed, and a power supply with higher efficiency and lower noise can be realized within the output fluctuation range.

[0168] (Third embodiment) In the first and second embodiments, the control method of turning the resonant switch on and off twice during the off period of the main switch has been described. The first on and off of the resonant switch is characterized by being performed at a timing that reduces the circulating current and provides a highly efficient converter. The second on and off of the resonant switch is performed to achieve ZVS of the main switch and provide a highly efficient, low-noise power supply. However, depending on the input voltage, output voltage, and transformer turns ratio, the voltage oscillation in period T6 can be increased, and there are cases where the second on and off of the resonant switch does not necessarily need to be performed, and the control method of the first and second embodiments can be changed to one that does not include the second on and off of the resonant switch.

[0169] (Other embodiments) Although the embodiments have been described in detail with reference to the drawings, the present embodiments are not limited to the contents described in the above embodiments. The components described above include those that a person skilled in the art can easily imagine and those that are substantially the same. Furthermore, the configurations described above can be appropriately combined. Various omissions, substitutions, or modifications of the configurations can be made without departing from the spirit of the embodiments.

[0170] The features of the half-wave LLC converter 10 and the control IC are described below.

[0171] The half-wave LLC converter 10 and the control IC according to the first embodiment include a first series circuit in which a main switch QM and a resonant switch QR are connected in series across a DC power supply Vin. The half-wave LLC converter 10 and the control IC also include a second series circuit in which a primary winding Np and a resonant capacitor Cr are connected in series across the resonant switch QR. The half-wave LLC converter 10 and the control IC also include a transformer T having a primary winding Np and a secondary winding Ns electromagnetically coupled with the primary winding Np in reverse polarity. The half-wave LLC converter 10 and the control IC also include a control unit 100a that turns on and off the main switch QM and the resonant switch QR. The half-wave LLC converter 10 and the control IC also include a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding Ns, and an output voltage detection unit 200 that detects the output voltage of the rectifying and smoothing circuit. The control unit 100a has a first drive signal for turning on and off the main switch QM, and a second drive signal for turning on and off the resonant switch QR while the main switch QM is off. The control unit 100a generates a second drive signal such that after the main switch is turned on and off by the first drive signal, there is a flyback period during which energy stored in the transformer is released from the secondary winding, the second drive signal is used to turn on the resonant switch during the flyback period, a resonant current is caused to flow, and after the resonant current has stopped flowing, the second drive signal is used to turn off the resonant switch during an excitation current charging period during which the excitation current charges the resonant capacitor.

[0172] With this configuration, the half-wave LLC converter 10 and the control IC reduce circulating current, achieving a highly efficient power supply.

[0173] The half-wave LLC converter 10 and the control IC according to the second embodiment include a first series circuit in which a main switch QM and a resonant switch QR are connected in series across a DC power supply Vin. The half-wave LLC converter 10 and the control IC also include a second series circuit in which a primary winding Np and a resonant capacitor Cr are connected in series across the resonant switch QR. The half-wave LLC converter 10 and the control IC also include a transformer T having a primary winding Np and a secondary winding Ns electromagnetically coupled with the primary winding Np in reverse polarity. The half-wave LLC converter 10 and the control IC also include a control unit 100a that turns on and off the main switch QM and the resonant switch QR. The half-wave LLC converter 10 and the control IC also include a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding Ns, and an output voltage detection unit 200 that detects the output voltage of the rectifying and smoothing circuit. The control unit 100a has a first drive signal for turning on and off the main switch QM, a second drive signal for turning on and off the resonant switch QR while the main switch QM is off, and a third drive signal for turning on and off the resonant switch after the second drive signal. The control unit 100a is characterized in that it generates a second drive signal such that after the main switch is turned on and off by the first drive signal, there is a flyback period during which energy stored in the transformer is released from the secondary winding, the second drive signal is used to turn on the resonant switch during the flyback period, a resonant current is caused to flow, and after the resonant current has finished flowing, the second drive signal is used to turn off the resonant switch during an excitation current charging period during which the excitation current charges the resonant capacitor.

[0174] With this configuration, the half-wave LLC converter 10 and the control IC reduce circulating current, and a highly efficient, low-noise power supply can be realized.

[0175] The control unit 100a of the half-wave LLC converter 10 and the control IC according to the third embodiment may have an excitation current detection means 113 that detects the excitation current of the transformer T and outputs a first voltage signal proportional to the excitation current. The control unit 100a may also have an output voltage detection means 111 that outputs a second voltage signal proportional to the output voltage. The control unit 100a may generate a second drive signal by setting the on / off timing of the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, so that the second drive signal has a flyback period in which energy stored in the transformer is released from the secondary winding, the second drive signal is used to turn on the resonant switch during the flyback period, a resonant current is caused to flow, and after the resonant current has finished flowing, the second drive signal is used to turn off the resonant switch during an excitation current charging period in which the excitation current charges the resonant capacitor.

[0176] With this configuration, the half-wave LLC converter 10 and the control IC can maintain the same output voltage even if the output voltage changes. Circulating current is reduced, resulting in a highly efficient, low-noise power supply.

[0177] The control unit 100a of the half-wave LLC converter 10 and the control IC according to the fourth embodiment may have an excitation current detection means 113 that detects the excitation current of the transformer T and outputs a first voltage signal proportional to the excitation current. The control unit 100a may also have a preset third voltage signal. The control unit 100a may generate a second drive signal by setting the on / off timing of the second drive signal based on the first voltage signal and a threshold value set based on the third voltage signal, so as to have a flyback period in which energy stored in the transformer is released from the secondary winding, turn on the resonant switch by the second drive signal during the flyback period, flow the resonant current, and turn off the resonant switch by the second drive signal during the excitation current charging period in which the excitation current charges the resonant capacitor after the resonant current has finished flowing.

[0178] With this configuration, the half-wave LLC converter 10 and the control IC can reduce circulating current with a control unit that is simpler than that of the second embodiment, thereby achieving a highly efficient, low-noise power supply.

[0179] The half-wave LLC converter 10 and the control unit 100a of the control IC according to the fifth aspect include: The control unit 100a may further include a zero-cross detection means 112 that outputs a zero-cross signal indicating that a zero voltage has been detected, at which the voltage of the auxiliary winding Na of the transformer T changes from a negative voltage to a positive voltage or from a positive voltage to a negative voltage. The control unit 100a may further include a second pulse generation means that outputs a second pulse signal for turning on the resonant switch QR after a predetermined delay time has elapsed, based on the zero-cross signal.

[0180] With this configuration, the half-wave LLC converter 10 and the control IC are turned on at the minimum voltage of the resonant switch, making it possible to achieve high efficiency, low noise operation.

[0181] The control unit 100a of the half-wave LLC converter 10 and the control IC according to the sixth embodiment may include an enable signal generating means 130a for generating an enable signal based on the feedback voltage detected by the output voltage detecting unit 200. The control unit 100a may further include a second pulse delay means for delaying the third drive signal based on the zero-cross signal and the enable signal. The second pulse delay means may delay the third drive signal so as to reduce the frequency when the load current decreases.

[0182] This configuration allows the half-wave LLC converter 10 and control IC to reduce frequency for longer periods when the load current decreases.

[0183] The control unit 100b of the half-wave LLC converter 10 and the control IC according to the seventh embodiment may further include an enable signal generating means 130b for generating an enable signal based on the feedback voltage detected by the output voltage detecting unit 200. The control unit 100b may further include a disable signal generating means 142 for generating a disable signal based on the second drive signal. The control unit 100b may further include a second pulse delay means for delaying the third drive signal based on the zero cross signal, the enable signal, and the disable signal. The second pulse delay means may delay the third drive signal so as to reduce the frequency when the load current decreases.

[0184] With this configuration, the half-wave LLC converter 10 and the control IC can suppress frequency fluctuations, and can realize a power supply that is more efficient and less noiseful within the output fluctuation range. [Explanation of symbols]

[0185] Vin DC power supply QM Main Switch QR Resonant Switch T transformer Np primary winding Ns Secondary winding Na Auxiliary Winding Lm Excitation inductance Llk Leakage inductance Cr, Cv Resonant Capacitor DM, DR Body diode Ds Diode Ca, Co output capacitor Ra1, Ra2, Rs resistance VgsM, VgsR drive signals 10 Half-wave LLC converter 100a, 100b Control section 111 Output voltage detection means 112 Zero cross detection means 113 Excitation current detection means 114, COMosc comparator 115 SR Latch 121 P1 generation means 122 P2 generation means 130a, 130b Enable signal generating means 131 Subtraction Circuit 141 P0 timing generation means 142 Disable signal generating means 143 P2 Delay Measures 144 P1 threshold generation means 151 First driving means 152 Second driving means 200 Output voltage detection section

Claims

1. a first series circuit in which a main switch and a resonant switch are connected in series across a DC power supply; a second series circuit in which a primary winding and a resonant capacitor are connected in series to both ends of the resonant switch; a transformer having the primary winding and a secondary winding electromagnetically coupled to the primary winding with a polarity opposite to that of the primary winding; A control unit that turns on and off the main switch and the resonant switch; a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding; an output voltage detection unit that detects an output voltage of the rectifying and smoothing circuit, The control unit is a first drive signal for turning on and off the main switch, and a second drive signal for turning on and off the resonant switch while the main switch is off; a control unit that generates the second drive signal so that after the main switch is turned on and off by the first drive signal, a flyback period is generated in which energy stored in the transformer is released from a secondary winding, the control unit turns on the resonant switch by the second drive signal during the flyback period to flow a resonant current, and after the resonant current has stopped flowing, turns off the resonant switch by the second drive signal during an excitation current charging period in which the energy stored in the transformer charges the resonant capacitor.

2. a first series circuit in which a main switch and a resonant switch are connected in series across a DC power supply; a second series circuit in which a primary winding and a resonant capacitor are connected in series to both ends of the resonant switch; a transformer having the primary winding and a secondary winding electromagnetically coupled to the primary winding with a polarity opposite to that of the primary winding; A control unit that turns on and off the main switch and the resonant switch; a rectifying and smoothing circuit that rectifies and smoothes the voltage of the secondary winding; an output voltage detection unit that detects an output voltage of the rectifying and smoothing circuit, The control unit is a first drive signal for turning on and off the main switch, a second drive signal for turning on and off the resonant switch while the main switch is off, and a third drive signal for turning on and off the resonant switch after the second drive signal; a control unit that generates the second drive signal so that after the main switch is turned on and off by the first drive signal, a flyback period is generated in which energy stored in the transformer is released from a secondary winding, the control unit turns on the resonant switch by the second drive signal during the flyback period to flow a resonant current, and after the resonant current has stopped flowing, turns off the resonant switch by the second drive signal during an excitation current charging period in which the energy stored in the transformer charges the resonant capacitor.

3. the control unit includes an excitation current detection means for detecting an excitation current of the transformer and outputting a first voltage signal proportional to the excitation current, and an output voltage detection means for outputting a second voltage signal proportional to the output voltage, The half-wave rectified LLC converter and control IC of claim 1 or 2, characterized in that the control unit sets the on timing of the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, and generates the second drive signal so that the on width of the second drive signal is equal to or greater than half the resonant period of the resonant current and the off timing of the second drive signal is within the excitation current charging period.

4. the control unit includes an excitation current detection unit that detects an excitation current of the transformer and outputs a first voltage signal proportional to the excitation current, and a predetermined third voltage signal; The half-wave rectified LLC converter and control IC of claim 1 or 2, characterized in that the control unit sets the on timing of the second drive signal based on the first voltage signal and the third voltage signal, and generates the second drive signal so that the on width of the second drive signal is equal to or greater than half the resonant period of the resonant current and the off timing of the second drive signal is within the excitation current charging period.

5. The control unit is a zero-cross detection means for outputting a zero-cross signal indicating that a zero voltage is detected, where the voltage of the auxiliary winding of the transformer changes from a negative voltage to a positive voltage or from a positive voltage to a negative voltage; 3. The half-wave rectified LLC converter and control IC according to claim 2, further comprising: a second pulse generating means for transmitting a second pulse signal for turning on the resonant switch after a predetermined delay time has elapsed based on the zero-cross signal.

6. The control unit is an enable signal generating means for generating an enable signal based on the feedback voltage detected by the output voltage detecting unit; and a second pulse delay means for delaying the third drive signal based on the zero-cross signal and the enable signal, 6. The half-wave rectified LLC converter and control IC of claim 5, wherein the second pulse delay means delays the third drive signal to reduce its frequency when a load current decreases.

7. The control unit is an enable signal generating means for generating an enable signal based on the feedback voltage detected by the output voltage detecting unit; a disable signal generating means for generating a disable signal based on the second drive signal; Based on the zero cross signal, the enable signal, and the disable signal, and a second pulse delay means for delaying the third drive signal, 6. The half-wave rectified LLC converter and control IC of claim 5, wherein the second pulse delay means delays the third drive signal to reduce its frequency when a load current decreases.

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