Capacitive d / a converter and a / d converter
By configuring a correction circuit in a capacitive D/A converter, the parasitic capacitance between the capacitor and ground is solved, and the problem of parasitic capacitance affecting signal generation is achieved, achieving more accurate signal generation.
Patent Information
- Application Number
- JP2023120987
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-07-25
- Publication Date
- 2025-02-06
AI Technical Summary
In the prior art, capacitive D/A converters are difficult to generate appropriate signals due to the influence of parasitic capacitance.
Using a capacitive D/A converter, by configuring a correction circuit including multiple correction capacitors, the parasitic capacitance between the correction capacitor and ground is ensured that the correction capacitance value is greater than that of other capacitors, and the correction circuit is used to adjust the capacitance value to reduce the influence of the parasitic capacitance.
It effectively suppresses the influence of parasitic capacitance and improves the accuracy and consistency of signal generation.
Smart Images
Figure 2025017765000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to capacitive D / A and A / D converters. [Background technology]
[0002] Successive approximation A / D converters are known that convert analog input signals into digital output signals. In a successive approximation A / C converter, a comparator successively compares a sampled analog input signal with a signal output from a capacitive D / A converter, and generates a digital output signal based on the comparison result. [Prior art documents] [Patent documents]
[0003] [Patent Document 1] JP 2017-192099 A
[0004] [overview] However, the present inventors have come to recognize the following problem: When parasitic capacitance occurs in a capacitive D / A converter, the capacitive D / A converter may not be able to generate an appropriate signal due to the influence of the parasitic capacitance.
[0005] The present disclosure has been made in light of these circumstances, and one of its exemplary purposes is to provide a technique for suppressing the influence of parasitic capacitance in a capacitive D / A converter and generating a more appropriate signal.
[0006] A capacitive D / A converter according to an embodiment of the present disclosure converts an (M+N)-bit digital signal into an analog signal, where M and N are integers equal to or greater than 1. The capacitive D / A converter includes a lower-side circuit having a first capacitance array composed of a plurality of first capacitors and converting the lower M bits of the digital signal, an upper-side circuit having a second capacitance array composed of a plurality of second capacitors and converting the upper N bits of the digital signal, a capacitor provided between the upper-side circuit and the lower-side circuit, and a correction circuit having a correction capacitance array composed of a plurality of correction capacitors and connected to a common node of the plurality of second capacitors. Parasitic capacitance occurs between each of the plurality of correction capacitors and ground. The correction circuit is configured so that the capacitance value of the parasitic capacitance of a correction capacitor having a capacitance value larger than that of other correction capacitors is larger than the capacitance values of the parasitic capacitance of the other correction capacitors.
[0007] Any combination of the above components and conversion of the expressions of the present disclosure between methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a block diagram of an A / D converter according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram of a capacitive D / A converter according to the reference technology. [Diagram 3] FIG. 3 is a circuit diagram for explaining the configuration of a capacitive D / A converter according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of the correction unit according to the embodiment. [Diagram 5] FIG. 5 is a circuit diagram of a correction circuit according to a reference technique. [Figure 6] FIG. 6 is a diagram showing the relationship between the correction code and the correction amount in the correction circuit according to the reference technique. [Figure 7] FIG. 7 is a diagram showing the relationship between the slope of the correction code and the correction code in the correction circuit according to the reference technique. [Figure 8] FIG. 8 is a circuit diagram of a second correction circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the relationship between the correction code and the correction amount in the second correction circuit according to the embodiment. [Figure 10] 10 is a diagram showing the relationship between the slope of the correction amount and the correction code in the second correction circuit according to the embodiment.
[0009] (overview) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.
[0010] A capacitive D / A converter according to an embodiment converts a (M+N)-bit digital signal into an analog signal, where M and N are integers equal to or greater than 1. The capacitive D / A converter includes a lower-side circuit having a first capacitance array composed of a plurality of first capacitors and converting the lower M bits of the digital signal, an upper-side circuit having a second capacitance array composed of a plurality of second capacitors and converting the upper N bits of the digital signal, a capacitor provided between the upper-side circuit and the lower-side circuit, and a correction circuit having a correction capacitance array composed of a plurality of correction capacitors and connected to a common node of the plurality of second capacitors. Parasitic capacitance occurs between each of the plurality of correction capacitors and the ground. The correction circuit is configured so that the capacitance value of the parasitic capacitance of a correction capacitor having a capacitance value larger than that of other correction capacitors is larger than the capacitance values of the parasitic capacitance of the other correction capacitors.
[0011] According to this configuration, the combined capacitance of the compensation circuit and the parasitic capacitance between the common node and ground can be compensated for more accurately using the compensation circuit. As a result, the capacitive D / A converter can suppress the effect of the parasitic capacitance and generate a more appropriate signal.
[0012] In one embodiment, the multiple correction capacitors may include m correction capacitors, where m is an integer equal to or greater than 2. When the m correction capacitors are classified as first to m-th correction capacitors in order from the smallest capacitance value, the correction circuit defines the capacitance values of the parasitic capacitances of the first to m-th correction capacitors as Cp1 to Cp m Then, Cp1=Cp2==Cp m-1 =Cp m Except for the case above, the following formula (1) may be satisfied. Cp1≦Cp2≦...≦Cp m-1 ≦Cp m (1)
[0013] In one embodiment, the capacitance values of the first to m-th correction capacitors may be values obtained by weighting the unit capacitance value of the correction capacitor by a power of 2. The correction circuit may be configured such that, for n correction capacitors selected from the first to m-th correction capacitors in order from the one with the largest capacitance value, the capacitance values of the parasitic capacitances are values obtained by weighting the unit capacitance value of the parasitic capacitance by a power of 2, where n is an integer not less than 2 and not more than m. With this configuration, it is possible to further improve the accuracy of correction of the composite capacitance by the correction circuit.
[0014] In one embodiment, the correction circuit may be configured such that the parasitic capacitance of the correction capacitor having the largest capacitance value among the plurality of correction capacitors has the largest capacitance value among the plurality of correction capacitors. This configuration can further improve the accuracy of correction of the composite capacitance by the correction circuit.
[0015] In one embodiment, the correction circuit may further include a plurality of signal lines for switching the capacitance value of the correction circuit. Each of the plurality of signal lines may be connected to a corresponding correction capacitor. The parasitic capacitance may occur between the signal line and ground.
[0016] In one embodiment, the correction circuit may be a circuit that increases the capacitance value of a combined capacitance between the common node and ground due to the parasitic capacitance occurring between the common node and ground and the correction circuit, or a circuit that decreases the capacitance value of the combined capacitance.
[0017] An A / D converter according to one embodiment includes the above-described capacitive D / A converter.
[0018] According to this configuration, the combined capacitance of the compensation circuit and the parasitic capacitance between the common node and ground can be compensated for more accurately using the compensation circuit. As a result, the capacitive D / A converter can suppress the effect of the parasitic capacitance and generate a more appropriate signal.
[0019] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
[0020] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.
[0021] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.
[0022] 1 is a block diagram of an A / D converter 1 according to an embodiment of the present disclosure. The A / D converter 1 converts an analog input signal Ain into a digital output signal Dout. The A / D converter 1 according to this embodiment includes a capacitive D / A converter 10, a sample-and-hold circuit 20, a comparator 30, and a control circuit 40.
[0023] The capacitive D / A converter 10 generates an analog signal Vdac in response to a digital control signal Sct from the control circuit 40. The analog signal Vdac is input to a first input terminal of the comparator 30.
[0024] The sample-and-hold circuit 20 samples the analog input signal Ain and holds the sampled signal. The signal Vsh held by the sample-and-hold circuit 20 is input to a second input terminal of the comparator 30.
[0025] The comparator 30 compares the signal input to the first input terminal with the signal input to the second input terminal, and outputs a comparison signal Scom to the control circuit 40.
[0026] The control circuit 40 generates a control signal Sct based on the comparison signal Scom. The control circuit 40 sequentially changes the control signal Sct in response to the comparison signal Scom. The control circuit 40 generates a digital output signal Dout based on the sequentially generated comparison signal Scom.
[0027] 2 is a circuit diagram of a capacitive D / A converter 90 according to the reference technology. The capacitive D / A converter 90 according to the reference technology generates an analog signal Vdac9 based on a 14-bit digital signal. The capacitive D / A converter 90 according to the reference technology has a lower side circuit 100, an upper side circuit 140, and a scaling capacitor 180.
[0028] The lower side circuit 100 is responsible for converting the lower M bits (M is an integer equal to or greater than 1, and is 7 in this example) of the digital signal. The lower side circuit 100 has a common node 102, a first capacitance array 110 composed of a plurality of first capacitors 111-117, and signal lines 131-137.
[0029] One end of each of the first capacitors 111-117 is connected to the common node 102. The other end of each of the first capacitors 111-117 is connected to a corresponding one of the signal lines 131-137. The lowest 7 bit signals of a digital signal are input to the signal lines 131-137. Specifically, signals b0-b6 corresponding to 0 (low) or 1 (high) are input to each of the signal lines 131-137. The signal corresponding to 0 may be, for example, a lower reference voltage, and the signal corresponding to 1 may be an upper reference voltage.
[0030] The capacitance value of the first capacitors 111 to 117 is a value obtained by weighting the unit capacitance value [C] of the capacitor by a power of 2. x C] (x is an integer greater than or equal to 0 and less than or equal to 6). That is, the capacitance values of first capacitors 111 to 117 are [1C], [2C], [4C], [8C], [16C], [32C] and [64C], respectively.
[0031] Parasitic capacitances 121 to 127 are generated in parallel with the first capacitors 111 to 117, respectively. The parasitic capacitances 121 to 127 have capacitance values k0 to k6, respectively. A parasitic capacitance 104 having a capacitance value α is generated between the common node 102 and the ground (reference voltage).
[0032] The upper side circuit 140 is responsible for converting the most significant N bits (N is an integer equal to or greater than 1, and is 7 in this example) of the digital signal. The upper side circuit 140 has a common node 142, a second capacitance array 150 including a plurality of second capacitors 151-157, and signal lines 171-177. The analog signal Vdac9 is output from the common node 142 of the upper side circuit 140.
[0033] One end of each of the second capacitors 151 to 157 is connected to the common node 142. The other end of each of the second capacitors 151 to 157 is connected to a corresponding one of the signal lines 171 to 177. The most significant seven bits of a digital signal are input to the signal lines 171 to 177. Specifically, signals b7 to b13 corresponding to 0 or 1 are input to each of the signal lines 171 to 177.
[0034] The capacitance values of the second capacitors 151 to 157 are values obtained by weighting the unit capacitance value [C] by a power of 2. y C] (y is an integer greater than or equal to 0 and less than or equal to 6). That is, the capacitance values of second capacitors 151 to 157 are [1C], [2C], [4C], [8C], [16C], [32C] and [64C], respectively.
[0035] Parasitic capacitances 161 to 167 are generated in parallel with the second capacitors 151 to 157, respectively. The parasitic capacitances 161 to 167 have capacitance values m0 to m6, respectively. A parasitic capacitance 144 having a capacitance value β is generated between the common node 142 and the ground.
[0036] The scaling capacitor 180 is provided between the lower side circuit 100 and the upper side circuit 140. Specifically, the scaling capacitor 180 is provided such that one end is connected to the common node 102 of the lower side circuit 100 and the other end is connected to the common node 142 of the upper side circuit 140. The capacitance value of the scaling capacitor 180 is [1C]. A parasitic capacitance 182 having a capacitance value γ occurs in parallel with the scaling capacitor 180.
[0037] Assuming that the parasitic capacitances 104, 121 to 127, 144, 161 to 167, and 182 do not occur, that is, that α, β, γ, k0 to k6, and m0 to m6 are all 0, the analog signal Vdac9 is expressed by the following equation (1).
number
[0038] However, the analog signal Vdac9 is affected by the parasitic capacitances 104, 121 to 127, 144, 161 to 167, and 182. For this reason, the analog signal Vdac9 is expressed by the following equation (2).
number
[0039] In particular, it becomes difficult to appropriately generate a signal of code 127 (signals b0 to b6 are all 1, signals b7 to b13 are all 0) and a signal of code 128 (signals b0 to b6, b8 to b13 are all 0, b7 is 1). Ideally, the difference between the analog signal Vdac9 of code 127 and the analog signal Vdac9 of code 128 is 1 / 128. When the capacitance value α of the parasitic capacitance 104 satisfies the following formula (3), the difference becomes 1 / 128.
number
[0040] Fig. 3 is a circuit diagram for explaining the configuration of the capacitive D / A converter 10 according to this embodiment. In Fig. 3, the same reference numerals are used for configurations that are substantially the same as those shown in Fig. 2, and the description thereof will be omitted as appropriate. Note that in Fig. 3, the parasitic capacitances 121 to 127, 144, and 162 to 167 shown in Fig. 2 are omitted from illustration.
[0041] The capacitive D / A converter 10 according to this embodiment converts an (M+N)-bit digital signal into an analog signal Vdac1, where M and N are each an integer equal to or greater than 1. This digital signal is included in a control signal Sct from a control circuit 40. The capacitive D / A converter 10 has a lower-side circuit 101, an upper-side circuit 140, a scaling capacitor 186, a switch 190, and a correction unit 200.
[0042] The lower side circuit 101 is responsible for converting the lowest M bits (the lowest 7 bits in this embodiment) of a digital signal. The lower side circuit 101 according to this embodiment has a common node 102, a first capacitance array 110, and signal lines 131 to 137. The lower side circuit 101 according to this embodiment differs from the lower side circuit 100 according to the reference technology in that the common node 102 is connected to a correction unit 200.
[0043] 3 shows an example in which the first capacitance array 110 is composed of seven first capacitors 111 to 117, but the number of first capacitors constituting the first capacitance array 110 may be changed according to the number of bits converted by the lower side circuit 101. The number of first capacitors may be, for example, six or less, or eight or more.
[0044] The upper side circuit 140 is responsible for converting the most significant N bits (the most significant 7 bits in this embodiment) of the digital signal. The upper side circuit 140 according to this embodiment has a common node 142, a second capacitance array 150, and signal lines 171 to 177. The analog signal Vdac1 is output from the common node 142 of the upper side circuit 140.
[0045] 3 shows an example in which the second capacitance array 150 is composed of seven second capacitors 151 to 157, but the number of second capacitors constituting the second capacitance array 150 may be changed according to the number of bits converted by the upper side circuit 140. The number of second capacitors may be, for example, six or less, or eight or more.
[0046] The scaling capacitor 186 is provided between the lower side circuit 101 and the upper side circuit 140. Specifically, the scaling capacitor 186 is provided such that one end is connected to the common node 102 of the lower side circuit 101 and the other end is connected to the common node 142 of the upper side circuit 140. The capacitance value C1 of the scaling capacitor 186 may be, for example, [(1+8.75 / 127)C], taking into consideration the capacitance value of the correction unit 200 and the like. A parasitic capacitance 188 having a capacitance value γ occurs in parallel with the scaling capacitor 186.
[0047] The switch 190 is provided such that one end is connected to the common node 142 of the upper circuit 140 and the other end is supplied with the reference voltage Vref. When the switch 190 is on, the reference voltage Vref is supplied to the common node 142.
[0048] The correction unit 200 is configured to correct a capacitance occurring between the common node 102 of the lower side circuit 101 and the ground. Specifically, the correction unit 200 is configured to correct a combined capacitance between the common node 102 and the ground due to the parasitic capacitance 104 and the correction unit 200. The correction unit 200 according to this embodiment has a correction capacitance array composed of a plurality of correction capacitors, and is configured to be able to adjust the capacitance value of the correction unit 200. If the capacitance value of the correction unit 200 is C_α, then according to equation (3), when C_α satisfies the following equation (4), the difference between the analog signal Vdac1 of code 127 and the analog signal Vdac1 of code 128 becomes 1 / 128.
number
[0049] Therefore, by adjusting the capacitance value of the correction section 200 so that C_α approaches the value shown in equation (4), the difference between the analog signal Vdac1 of code 127 and the analog signal Vdac1 of code 128 can approach 1 / 128.
[0050] A voltage of the common node 142 of the upper circuit 140 is input to a first input terminal of the comparator 30. A reference voltage Vref supplied from a voltage generating circuit (not shown) when adjusting the capacitance value of the correction unit 200 is input to a second input terminal of the comparator 30.
[0051] 4 is a circuit diagram of the correction section 200 according to this embodiment. The correction section 200 according to this embodiment includes a first correction circuit 220, a second correction circuit 260, and a switch 290.
[0052] The first correction circuit 220 is a circuit that increases the capacitance value of a combined capacitance between the common node 102 and the ground, which is a result of the parasitic capacitance 104 and the correction unit 200 (specifically, the first correction circuit 220). The first correction circuit 220 has a common node 222, a correction capacitance array 230 composed of a plurality of correction capacitors 231-234, and switches 241-244.
[0053] A common node 222 of the first correction circuit 220 is common to the common node 102 of the lower side circuit 101. The common node 222 is connected to one end of a switch 290, the other end of which is connected to ground.
[0054] One end of each of the correction capacitors 231 to 234 is connected to the common node 222. In this embodiment, an example in which the number of the correction capacitors 231 to 234 is four will be described, but the number of the correction capacitors 231 to 234 may be three or less, or five or more.
[0055] The switches 241 to 244 are provided between the corresponding correction capacitors 231 to 234 and the ground. The switches 241 to 244 are switched on and off in response to a control signal Sct. The switches 241 to 243 are switched on and off in response to a 3-bit correction code (first correction code) included in the control signal Sct. The switches 241 to 243 correspond, in this order, to the first to third bits of this correction code. The switches 241 to 243 may be turned off when the corresponding bit is 0, and turned on when the corresponding bit is 1.
[0056] The capacitance values of m1 (m1 is an integer of 2 or more, and is 3 in this embodiment) correction capacitors 231 to 233 (first to third correction capacitors) included in the correction capacitance array 230 are values obtained by weighting the unit capacitance value [C] by a power of 2. Specifically, the capacitance values of the correction capacitors 231 to 233 are [2 a C] (where a is an integer greater than or equal to 0 and less than or equal to 2). That is, the capacitance values of the correction capacitors 231 to 233 are [1C], [2C], and [4C], respectively. The capacitance value of the correction capacitor 234 is [1C].
[0057] 4, before starting to adjust the capacitance value of the correction unit 200. At this time, the first correction circuit 220 does not contribute to the combined capacitance between the common node 102 and the ground. By turning on each of the switches 241 to 244, it is possible to increase the combined capacitance between the common node 102 and the ground by the capacitance value of the correction capacitors 231 to 234 connected to the switches 241 to 244 that are turned on.
[0058] The second correction circuit 260 is a circuit that reduces the capacitance value of the combined capacitance between the common node 102 and the ground, which is a result of the parasitic capacitance 104 and the correction unit 200 (specifically, the second correction circuit 260). The second correction circuit 260 has a common node 262, a correction capacitance array 270 composed of a plurality of correction capacitors 271 to 273, and switches 281 to 283. The common node 262 is common to the common node 102 of the lower-side circuit 101.
[0059] One end of each of the correction capacitors 271 to 273 is connected to the common node 262. In this embodiment, an example in which the number of the correction capacitors 271 to 273 is three will be described, but the number of the correction capacitors 271 to 273 may be two or less, or may be four or more.
[0060] The switches 281-283 are provided between the corresponding correction capacitors 271-273 and the ground, respectively. The switches 281-283 are switched on and off according to a 3-bit correction code (second correction code) included in the control signal Sct. The switches 281-283 correspond, in this order, to the first to third bits of this correction code. The switches 281-283 may be turned off when the corresponding bit is 0, and turned on when the corresponding bit is 1.
[0061] The capacitance values of m2 (m2 is an integer of 2 or more, and is 3 in this embodiment) correction capacitors 271 to 273 (first to third correction capacitors) included in the correction capacitance array 270 are values obtained by weighting the unit capacitance value [C] by a power of 2. Specifically, the capacitance values of the correction capacitors 271 to 273 are [2 b C] (b is an integer not less than 0 and not more than 2). That is, the capacitance values of the correction capacitors 271 to 273 are [1C], [2C], and [4C], respectively.
[0062] 4, before starting to adjust the capacitance value of the correction unit 200. At this time, the correction capacitors 271-273 all contribute to the combined capacitance between the common node 102 and the ground. By turning off each of the switches 281-283, it is possible to reduce the capacitance value of the combined capacitance between the common node 102 and the ground by the capacitance value of the correction capacitors 271-273 connected to the turned-off switches 281-283.
[0063] The above describes the schematic configuration of the correction unit 200. Here, an example of a flow for adjusting the capacitance value of the correction unit 200 and adjusting the combined capacitance between the common node 102 and ground will be described.
[0064] First, with the switch 190 turned on, a digital signal of code 128 is input to the signal lines 131-137 and 171-177. Next, with the switch 190 turned off, a digital signal of code 127 is input to the signal lines 131-137 and 171-177. The comparator 30 compares the analog signal Vdac1 at the code 127 with the reference voltage Vref, and outputs a comparison signal Scom to the control circuit 40. The control circuit 40 outputs a control signal Sct to the correction unit 200 of the capacitive D / A converter 10 in response to the comparison signal Scom.
[0065] The capacitance value of the correction unit 200 is adjusted in response to the control signal Sct. Specifically, the switches 241 to 244 of the first correction circuit 220 and the switches 281 to 283 of the second correction circuit 260 are switched in response to the control signal Sct. More specifically, when the capacitance value of the correction unit 200 is to be increased, the switch 243 is turned on, and when the capacitance value of the correction unit 200 is to be decreased, the switch 283 is turned off. Note that when the switches 241 to 244 and 281 to 283 are switched on and off, the switch 290 may be turned on. This suppresses feedthrough caused by the switching of the switches 241 to 244 and 281 to 283.
[0066] Thereafter, the capacitance value of the correction unit 200 is determined using a binary search method. Specifically, the capacitance value of the correction unit 200 is sequentially changed according to the comparison result of the comparator 30. For example, when the switch 243 is turned on first, the switches 241 to 243 are sequentially turned on and off, and when the switch 283 is turned off first, the switches 281 to 283 are sequentially turned on and off. After the on and off of the correction capacitor (correction capacitor 231 or correction capacitor 271) having the smallest capacitance value among the correction capacitors 231 to 233 or 271 to 273 is determined, the switch 244 is turned on, and the capacitance value [1C] of the correction capacitor 234 is added to the capacitance value of the correction unit 200. In this manner, the capacitance value C_α of the correction unit 200 approaches the value shown in equation (4), and the signal of code 127 and the signal of code 128 can be generated more appropriately.
[0067] 5 is a circuit diagram of a correction circuit 900 according to the reference technology. The correction circuit 900 is configured to increase or decrease a combined capacitance between a common node 102 and ground, which is a result of the parasitic capacitance 104 and the correction circuit 900. The correction circuit 900 according to the reference technology has a common node 902, a correction capacitance array 910 composed of a plurality of correction capacitors 911-913, switches 921-923, and signal lines 931-933.
[0068] One end of each of the correction capacitors 911 to 913 is connected to the common node 902. The other end of each of the correction capacitors 911 to 913 is connected to each of the switches 921 to 923 via corresponding signal lines 931 to 933, respectively.
[0069] The correction capacitors 911 to 913 have [1C], [2C], and [4C], respectively. Parasitic capacitances 941 to 943 occur between the signal lines 931 to 933 and the ground, respectively. Here, the capacitance values of the parasitic capacitances 941 to 943 are all assumed to be the unit capacitance value [Cp] of the parasitic capacitance.
[0070] When switches 921 to 923 are off, correction capacitors 911 to 913 connected to the off switches 921 to 923 are connected to ground via corresponding parasitic capacitances 941 to 943. As a result, even when switches 921 to 923 are off, a combined capacitance of correction capacitors 911 to 913 and parasitic capacitances 941 to 943 is generated between common node 902 and ground.
[0071] FIG. 6 is a diagram showing the relationship between correction codes and correction amounts (calculated values) in correction circuit 900 according to the related art. FIG. 6 shows the relationship between correction codes and correction amounts when the capacitance values [Cp] of parasitic capacitances 941 to 943 are Cp1, Cp2, Cp3, Cp4, and Cp5. Here, Cp1, Cp2, Cp3, Cp4, and Cp5 satisfy Cp1 < Cp2 < Cp3 < Cp4 < Cp5. In FIG. 6, the horizontal axis represents correction codes, and the vertical axis represents correction amounts (LSB: Least Significant Bit). The correction amount is the amount of change from the initial value (0 or 7.75C) of the capacitance value of correction circuit 900.
[0072] FIG. 7 is a diagram showing the relationship between the slopes (calculated values) of correction codes and correction codes in correction circuit 900 according to the related art. FIG. 7 shows the relationship between the slopes (LSB / code) of correction codes and correction amounts when the capacitance values [Cp] of parasitic capacitances 941 to 943 are Cp1, Cp2, Cp3, Cp4, and Cp5. In FIG. 7, the horizontal axis represents correction codes, and the vertical axis represents the slopes (LSB / code) of correction amounts.
[0073] As shown in FIG. 6, it can be seen that as the capacitance value [Cp] increases, the correction amount decreases, and the range of capacitance values that can be corrected by correction circuit 900 is limited. Also, as shown in FIGS. 6 and 7, it can be seen that there are steps in the change of the correction amount with respect to the correction code. Due to this step, the error in the correction amount becomes ±0.25 LSB or more.
[0074] The larger the capacitance value of the correction capacitors 911-913 of the switches 921-923 that are switched in response to a change in the correction code, the larger the step in the change in the correction amount for the correction code. In particular, the step in the change in the correction amount is the largest for correction codes 3 and 4. This step corresponds to the switching of the switch 923 of the correction capacitor 913 that has the largest capacitance value [4C] among the correction capacitors 911-913.
[0075] As described above, if the parasitic capacitances 941-943 occurring in the signal lines 931-933 all have the same capacitance value [Cp] as in the correction circuit 900 according to the reference technology, the amount of correction is limited and a step occurs in the change in the amount of correction. As a result, the error in the amount of correction increases, making it difficult to appropriately adjust the combined capacitance.
[0076] 5 occurs in parallel with each of the correction capacitors 911-913. However, the influence of this parallel parasitic capacitance on the accuracy of the capacitance value of the correction circuit 900 is smaller than that of the parasitic capacitances 941-943 occurring between the correction capacitors 911-913 and the ground.
[0077] 8 is a circuit diagram of the second correction circuit 260 according to this embodiment. As shown in FIG 8, the second correction circuit 260 further includes a plurality of signal lines 301-303 for adjusting the capacitance value of the second correction circuit 260, in addition to the common node 262, the correction capacitance array 270, and the switches 281-283.
[0078] Each of the multiple signal lines 301 to 303 is connected to a corresponding one of the correction capacitors 271 to 273. Each of the correction capacitors 271 to 273 is connected to a corresponding one of the switches 281 to 283 via a corresponding one of the signal lines 301 to 303. Parasitic capacitances 311 to 313 are generated between each of the correction capacitors 271 to 273 and the ground. Specifically, each of the parasitic capacitances 311 to 313 is generated between each of the signal lines 301 to 303 and the ground.
[0079] The second correction circuit 260 according to this embodiment is configured so that the capacitance values of the parasitic capacitances 311-313 of the correction capacitors 271-273 having larger capacitance values than the other correction capacitors 271-273 are larger than the capacitance values of the parasitic capacitances 311-313 of the other correction capacitors 271-273. The capacitance values of the parasitic capacitances 311-313 can be adjusted, for example, by appropriately changing the number and thickness of the wiring that constitutes the signal lines 301-303.
[0080] The second correction circuit 260 is configured so that the parasitic capacitance 313 of the correction capacitor 273 having the largest capacitance value among the multiple correction capacitors 271-273 has the largest capacitance value among the parasitic capacitances 311-313 of the multiple correction capacitors 271-273. For example, the number or thickness of the wiring constituting the signal line 303 connected to the correction capacitor 273 may be the largest or the thickest among the signal lines 301-303.
[0081] The second correction circuit 260 is configured so that, when the capacitance values of the parasitic capacitances 311 to 313 of the correction capacitors 271 to 273 (first to third correction capacitors) are Cp1 to Cp3, the following formula (5) is satisfied, except when Cp1=Cp2=Cp3. Cp1≦Cp2≦Cp3 (5)
[0082] The second correction circuit 260 is configured such that, when n is an integer equal to or greater than 2 and equal to or less than m2, the capacitance values of the parasitic capacitances of n correction capacitors selected in order from the first to m2th correction capacitors in order from the one with the largest capacitance value are weighted by a power of 2 times the unit capacitance value [Cp] of the parasitic capacitance. In this embodiment, n is 3 (=m2), and the capacitance values of the parasitic capacitances 311 to 313 of the correction capacitors 271 to 273 are weighted by a power of 2 times the unit capacitance value [Cp]. Specifically, the capacitance values of the parasitic capacitances 311 to 313 of the correction capacitors 271 to 273 are weighted by a power of 2 times [2 c Cp] (c is an integer not less than 0 and not more than 2). That is, the capacitance values of the parasitic capacitances 311 to 313 are [Cp], [2Cp], and [4Cp], respectively.
[0083] In this embodiment, an example in which the three parasitic capacitances 311 to 313 all have different capacitance values will be described, but some of the parasitic capacitances may have the same capacitance value. For example, the second correction circuit 260 may be configured so that the two parasitic capacitances 311 and 312 selected from the parasitic capacitances 311 to 313 in ascending order of capacitance value have the same capacitance value, and the remaining parasitic capacitance 313 has a capacitance value larger than these parasitic capacitances 311 and 312. By configuring the second correction circuit 260 so that some of the parasitic capacitances have the same capacitance value, the second correction circuit 260 can be realized more simply.
[0084] Fig. 9 is a diagram showing the relationship between the correction code (calculated value) and the correction amount in the second correction circuit 260 according to this embodiment. Fig. 9 shows the relationship between the correction code and the correction amount when the unit capacitance value [Cp] is Cp1, Cp2, Cp3, Cp4, and Cp5. In Fig. 9, the horizontal axis is the correction code, and the vertical axis is the correction amount (LSB).
[0085] Fig. 10 is a diagram showing the relationship between the slope (calculated value) of the correction amount in the second correction circuit 260 according to this embodiment and the correction code. Fig. 10 shows the relationship between the slope of the correction code and the correction amount when the unit capacitance value [Cp] is Cp1, Cp2, Cp3, Cp4, and Cp5. In Fig. 10, the horizontal axis is the correction code, and the vertical axis is the slope of the correction amount (LSB / code).
[0086] As shown in Fig. 9, the correction amount decreases more with an increase in the unit capacitance value [Cp] than in the correction circuit 900 according to the reference technology. However, as shown in Fig. 9 and Fig. 10, the step in the change in the correction amount with respect to the correction code becomes smaller. As a result, it becomes possible to adjust the capacitance value between the common node 262 of the second correction circuit 260 and the ground with higher accuracy.
[0087] The A / D converter 1 according to this embodiment has been described above. In the above embodiment, an example has been described in which the second correction circuit 260 is configured so that the capacitance values of the parasitic capacitances 311-313 of the correction capacitors 271-273 having a larger capacitance value than the other correction capacitors 271-273 are larger than the capacitance values of the parasitic capacitances 311-313 of the other correction capacitors 271-273. This is not limiting, and the first correction circuit 220 may be configured so that the capacitance values of the parasitic capacitances of the correction capacitors 231-233 having a larger capacitance value than the other correction capacitors 231-233 are larger than the capacitance values of the parasitic capacitances of the other correction capacitors 231-233. This makes it possible to more accurately adjust the capacitance value between the common node 222 of the first correction circuit 220 and the ground.
[0088] According to the A / D converter 1 of this embodiment, in the capacitive D / A converter 10, the correction circuits (first correction circuit 220 and second correction circuit 260) are configured so that the capacitance value of the parasitic capacitance of the correction capacitor having a larger capacitance value than the other correction capacitors is larger than the capacitance values of the parasitic capacitance of the other correction capacitors. This makes it possible to appropriately adjust the capacitance values of the correction circuits (first correction circuit 220 and second correction circuit 260) and appropriately correct the combined capacitance between the common node 102 and the ground, which is caused by the parasitic capacitance 104 and the correction unit 200. As a result, it is possible to suppress the influence of the parasitic capacitance 104 and generate a more appropriate analog signal Vdac1.
[0089] In the capacitive D / A converter 10 according to this embodiment, for example, the second correction circuit 260 is configured such that the capacitance values of the parasitic capacitances 311-313 for the three correction capacitors 271-273 are weighted by a power of 2 times the unit capacitance value [Cp]. The larger the capacitance value of the correction capacitor, the greater the effect on the accuracy of the adjustment of the capacitance value of the second correction circuit 260. For this reason, by appropriately designing the capacitance values of the parasitic capacitances 311-313 for the correction capacitors 271-273, the capacitance value of the second correction circuit 260 can be adjusted with higher accuracy.
[0090] In the capacitive D / A converter 10 according to this embodiment, for example, the second correction circuit 260 is configured so that the capacitance value of the parasitic capacitance 315 of the correction capacitor 273 having the largest capacitance value among the correction capacitors 271 to 273 has the largest capacitance value among the parasitic capacitances 311 to 313. The correction capacitor 273 having the largest capacitance value has the greatest effect on accuracy among the correction capacitors 271 to 273 in adjusting the capacitance value of the second correction circuit 260. For this reason, by appropriately designing the capacitance value of the parasitic capacitance 313 of the correction capacitor 273, it is possible to adjust the capacitance value of the second correction circuit 260 with higher accuracy.
[0091] (Modification) The A / D converter 1 is not limited to the above embodiment, and may be, for example, a differential A / D converter. Specifically, the A / D converter may be configured by connecting two paired capacitive D / A converters to the two input terminals of the comparator 30. In this case, in each of the capacitive D / A converters, similar to the capacitive D / A converter 10 according to the above embodiment, the correction circuit may be configured so that the capacitance value of the parasitic capacitance of the correction capacitor having a larger capacitance value than the other correction capacitors is larger than the capacitance values of the parasitic capacitance of the other correction capacitors.
[0092] In the above embodiment, an example has been described in which the accuracy of the capacitance value of the correction circuit is improved by adjusting the magnitude of the parasitic capacitance occurring between the correction capacitor and the ground in the correction circuit. However, the present invention is not limited to this. It is also possible to suppress the effect of the parasitic capacitance on the capacitance value of the correction circuit by making the magnitude of the parasitic capacitance occurring between each correction capacitor and the ground constant and adjusting the size of each correction capacitor.
[0093] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to aid in understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. In addition, not only the embodiments, but also embodiments, examples, and modified examples not described herein are included in the scope of the present invention.
[0094] (Additional Note) One aspect of the technology disclosed in this specification can be understood as follows.
[0095] (Item 1) A capacitive D / A converter that converts an (M+N)-bit digital signal into an analog signal, where M and N are integers of 1 or more, a lower-side circuit having a first capacitance array composed of a plurality of first capacitors and performing conversion of the lower M bits of the digital signal; a higher-order circuit having a second capacitance array composed of a plurality of second capacitors and performing conversion of the most significant N bits of the digital signal; a capacitor provided between the upper circuit and the lower circuit; a correction circuit having a correction capacitance array composed of a plurality of correction capacitors and connected to a common node of the plurality of second capacitors; A parasitic capacitance is generated between each of the plurality of correction capacitors and ground, the correction circuit is configured so that a capacitance value of the parasitic capacitance of a correction capacitor having a capacitance value larger than that of other correction capacitors is larger than a capacitance value of the parasitic capacitance of the other correction capacitors. Capacitive D / A converter.
[0096] (Item 2) the plurality of correction capacitors includes m correction capacitors, where m is an integer equal to or greater than 2; When the m correction capacitors are classified into first to m-th correction capacitors in order from the smallest capacitance value, the correction circuit defines the capacitance values of the parasitic capacitances of the first to m-th correction capacitors as Cp1 to Cpm Then, Cp1=Cp2==Cp m-1 =Cp m Except for the case where the following formula (1) is satisfied, Cp1≦Cp2≦...≦Cp m-1 ≦Cp m (1) Item 1. The capacitive D / A converter according to item 1.
[0097] (Item 3) The capacitance values of the first to mth correction capacitors are values obtained by weighting the unit capacitance value of the correction capacitor by a power of 2; the correction circuit is configured such that, for n correction capacitors selected from the first to m-th correction capacitors in order from the one with the largest capacitance, the capacitance value of the parasitic capacitance is a value weighted by a power of 2 times the unit capacitance value of the parasitic capacitance, where n is an integer not less than 2 and not more than m. Item 2. The capacitive D / A converter according to item 2.
[0098] (Item 4) the correction circuit is configured such that the parasitic capacitance of a correction capacitor having a maximum capacitance value among the plurality of correction capacitors has a maximum capacitance value among the parasitic capacitances of the plurality of correction capacitors. 4. The capacitive D / A converter according to any one of items 1 to 3.
[0099] (Item 5) the correction circuit further includes a plurality of signal lines for switching a capacitance value of the correction circuit; Each of the plurality of signal lines is connected to a corresponding one of the correction capacitors; The parasitic capacitance occurs between the signal line and ground. 5. The capacitive D / A converter according to any one of items 1 to 4.
[0100] (Item 6) the correction circuit is a circuit that increases a capacitance value of a combined capacitance between the common node and ground due to a parasitic capacitance occurring between the common node and ground and the correction circuit, or a circuit that decreases the capacitance value of the combined capacitance. 6. The capacitive D / A converter according to any one of items 1 to 5.
[0101] (Item 7) 7. An A / D converter comprising the capacitive D / A converter according to any one of items 1 to 6. (Explanation of symbols)
[0102] 1 A / D converter, 10 capacitive D / A converter, 20 sample and hold circuit, 30 comparator, 40 control circuit, 100 lower side circuit, 102 common node, 110 first capacitance array, 111 to 117 first capacitor, 140 upper side circuit, 142 common node, 171 to 177 second capacitor, 104, 121 to 127, 144, 161 to 167, 182, 188, 311 to 315 parasitic capacitance, 186 scaling capacitor, 200 correction unit, 220 first correction circuit, 230, 270 correction capacitance array, 231 to 236, 271 to 275 correction capacitor, 241 to 246, 281 to 285, 290 switch, 260 second correction circuit, 301 to 305 signal line.
Claims
1. A capacitive D / A converter that converts an (M+N)-bit digital signal into an analog signal, where M and N are integers of 1 or more, comprising: a lower-side circuit having a first capacitance array composed of a plurality of first capacitors and performing conversion of the lower M bits of the digital signal; a higher-order circuit having a second capacitance array composed of a plurality of second capacitors and performing conversion of the most significant N bits of the digital signal; a capacitor provided between the upper circuit and the lower circuit; a correction circuit having a correction capacitance array composed of a plurality of correction capacitors and connected to a common node of the plurality of second capacitors; A parasitic capacitance is generated between each of the plurality of correction capacitors and ground, the correction circuit is configured so that a capacitance value of the parasitic capacitance of a correction capacitor having a capacitance value larger than that of other correction capacitors is larger than a capacitance value of the parasitic capacitance of the other correction capacitors. Capacitive D / A converter.
2. the plurality of correction capacitors includes m correction capacitors, where m is an integer equal to or greater than 2; When the m correction capacitors are classified as first to m-th correction capacitors in order from the smallest capacitance value, the correction circuit defines the capacitance value of the parasitic capacitance of each of the first to m-th correction capacitors as Cp １ ~Cp ｍ Then, Cp １ = Cp ２ = ... = Cp ｍ－１ = Cp ｍ The following formula (1) is satisfied, except for the case Cp １ ≦Cp ２ ≦・・・≦Cp ｍ－１ ≦Cp ｍ ・・・(1) 2. The capacitive D / A converter according to claim 1.
3. The capacitance values of the first to m-th correction capacitors are values obtained by weighting the unit capacitance value of the correction capacitor by a power of 2; the correction circuit is configured such that, when n is an integer not less than 2 and not more than m, for n correction capacitors selected in order from the first to m-th correction capacitors having the largest capacitance value, the capacitance value of the parasitic capacitance is a value weighted by a power of 2 times the unit capacitance value of the parasitic capacitance.
3. The capacitive D / A converter according to claim 2.
4. the correction circuit is configured such that the parasitic capacitance of a correction capacitor having a maximum capacitance value among the plurality of correction capacitors has a maximum capacitance value among the parasitic capacitances of the plurality of correction capacitors.
2. The capacitive D / A converter according to claim 1.
5. the correction circuit further includes a plurality of signal lines for switching a capacitance value of the correction circuit; Each of the plurality of signal lines is connected to a corresponding one of the correction capacitors; The parasitic capacitance occurs between the signal line and ground.
2. The capacitive D / A converter according to claim 1.
6. the correction circuit is a circuit that increases a capacitance value of a combined capacitance between the common node and ground due to a parasitic capacitance occurring between the common node and ground and the correction circuit, or a circuit that decreases the capacitance value of the combined capacitance.
2. The capacitive D / A converter according to claim 1.
7. An A / D converter comprising the capacitive D / A converter according to any one of claims 1 to 6.
Citation Information
Patent Citations
Successive comparison type a-d converter
JP2017192099A