Semiconductor circuit device and switching regulator

Abstract

To provide a semiconductor circuit device that can achieve both the accuracy of output voltage and the frequency characteristics of a feedback loop.SOLUTION: A semiconductor circuit device 100 includes a differential amplifier circuit 110 and a switching signal output circuit 130. The differential amplifier circuit 110 outputs current IC on the basis of the output voltage VOUT of a switching regulator 200. The switching signal output circuit 130 outputs a switching signal CSWT of a switch element SWT on the basis of the voltage VC of an output node NVC of the differential amplifier circuit 110 and voltage according to inductor current IL flowing in an inductor 210. The differential amplifier circuit 110 includes a first output stage transistor and a second output stage transistor. The first output stage transistor is provided between a first power supply node and a first node and outputs current. The second output stage transistor is provided between the first node and the output node and receives input of first bias voltage at its gate.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor circuit device, a switching regulator, and the like. [Background technology]

[0002] Patent Document 1 discloses a step-up current-mode control switching regulator. This switching regulator includes an output voltage feedback circuit having a transconductance amplifier and a phase compensation circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0152099 Summary of the Invention [Problem to be solved by the invention]

[0004] In a switching regulator, there is a need to achieve both high accuracy of the output voltage and frequency characteristics of the feedback loop. The above-mentioned Patent Document 1 does not disclose a configuration for achieving both high accuracy of the output voltage and frequency characteristics of the feedback loop. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a semiconductor circuit device used in a switching regulator that regulates an input voltage using a switch element and an inductor, the semiconductor circuit device including: a differential amplifier circuit that outputs a current based on an output voltage of the switching regulator; and a switching signal output circuit that outputs a switching signal for the switch element based on a voltage at an output node of the differential amplifier circuit and a voltage corresponding to an inductor current flowing through the inductor, the differential amplifier circuit including a first output stage transistor that is provided between a first power supply node and a first node and outputs the current, and a second output stage transistor that is provided between the first node and the output node and has a gate to which a first bias voltage is input.

[0006] Another aspect of the present disclosure relates to a switching regulator including the above-described semiconductor circuit device and the inductor. [Brief description of the drawings]

[0007] [Figure 1] An example of a switching regulator configuration. [Diagram 2] FIG. 1 is a diagram illustrating the frequency characteristics of a switching regulator. [Diagram 3] FIG. 1 is a diagram illustrating the frequency characteristics of a switching regulator. [Figure 4] Example of frequency response when DC gain is increased. [Diagram 5] 1 shows a first detailed configuration example of a differential amplifier circuit. [Figure 6] 4 is an example of frequency characteristics when the DC gain is increased using the differential amplifier circuit of the present embodiment. [Figure 7] 4 is a diagram illustrating the relationship between the output impedance and gain frequency characteristics of a differential amplifier circuit. [Figure 8] 13 shows an example of the configuration of a semiconductor circuit device when a second detailed configuration example of a differential amplifier circuit is applied. [Figure 9] 4 shows a second detailed configuration example of a differential amplifier circuit. [Figure 10] 3 shows a detailed configuration example of a switching signal output circuit. [Figure 11] An example of a signal waveform from a switching signal output circuit. [Figure 12] A detailed configuration example of an inductance current detection circuit. [Figure 13] Example of signal waveform of inductance current detection circuit. [Figure 14] 1 shows a detailed configuration example of a slope generation circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A preferred embodiment of the present disclosure will be described in detail below. Note that the present embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the present embodiment are not necessarily essential configurations. For example, a step-down switching regulator will be described below as an example, but the method of the present embodiment can also be applied to a step-up switching regulator.

[0009] 1. Switching regulator and semiconductor circuit device 1 shows an example of the configuration of a switching regulator. The switching regulator 200 includes a semiconductor circuit device 100, an inductor 210, and a capacitor 220.

[0010] The power supply 250 is connected between a low potential side power supply node to which a low potential side power supply VSS is supplied and an input node NH of the switching regulator 200. The power supply 250 generates an input voltage VH to be applied to the switching regulator 200. The power supply 250 may be either an AC / DC converter or a DC / DC converter. Note that the connection in this embodiment includes an electrical connection. An electrical connection means a connection capable of transmitting an electrical signal, a voltage, or a current, and includes a connection that enables the transmission of information by an electrical signal. The electrical connection may be a connection via a passive element, an active element, or the like.

[0011] One end of the inductor 210 is connected to the switch node NSW, and the other end is connected to the output node NOUT of the switching regulator 200. One end of the capacitor 220 is connected to the node NOUT, and the other end is connected to the low potential side power supply node. A current IL flowing through the inductor 210 is referred to as an inductor current.

[0012] A load 290 of the switching regulator 200 is provided between the output node NOUT and the low potential side power supply node. The load 290 is a circuit that uses the output voltage VOUT of the switching regulator 200 as a power supply voltage.

[0013] The semiconductor circuit device 100 controls the switching regulator 200 so that the output voltage VOUT of the switching regulator 200 becomes a predetermined voltage. The semiconductor circuit device 100 is an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. The semiconductor circuit device 100 includes a switch element SWT, a diode 160, resistors RA1 and RA2, a reference voltage generating circuit 140, a differential amplifier circuit 110, a phase compensation circuit 120, and a switching signal output circuit 130. The switch element SWT, the diode 160, the resistors RA1 and RA2, and the reference voltage generating circuit 140 may be provided outside the semiconductor circuit device 100.

[0014] The switch element SWT is a transistor, and is controlled to be on or off by a switching signal CSWT. Although Fig. 1 shows an example in which the switch element SWT is an N-type transistor, it may be a P-type transistor. The source of the switch element SWT is connected to the switch node NSW, and the drain is connected to the input node NH. The switching signal CSWT is input to the gate of the switch element SWT.

[0015] The anode of the diode 160 is connected to the low potential side power supply node, and the cathode is connected to the switch node NSW. Note that a switch element may be provided instead of the diode 160. The switch element is off when the switch element SWT is on, and is on when the switch element SWT is off.

[0016] One end of resistor RA1 is connected to the output node NOUT, and the other end is connected to the inverting input terminal of the differential amplifier circuit 110. One end of resistor RA2 is connected to the inverting input terminal of the differential amplifier circuit 110, and the other end is connected to the low potential side power supply node. Resistors RA1 and RA2 divide the output voltage VOUT to a voltage DVOUT.

[0017] The reference voltage generating circuit 140 is connected between the non-inverting input terminal of the differential amplifier circuit 110 and a low potential side power supply node. The reference voltage generating circuit 140 generates a reference voltage VREF for setting the voltage value of the output voltage VOUT. The output voltage VOUT is controlled by feedback control performed by the semiconductor circuit device 100 so that the voltage DVOUT is equal to the reference voltage VREF.

[0018] The differential amplifier circuit 110 converts the voltage difference between the voltage DVOUT and the reference voltage VREF into a current, converts the current into a voltage VC by the output impedance of the differential amplifier circuit 110, and outputs the voltage VC to an output node NVC. The differential amplifier circuit 110 is also called a transconductance amplifier, a Gm amplifier, or an error amplifier.

[0019] The phase compensation circuit 120 is a circuit that performs phase compensation of a feedback loop. Although details will be described later, the first pole and second pole of the switching regulator 200 as a whole can be set by the output impedance of the phase compensation circuit 120 and the differential amplifier circuit 110. This makes it possible to control the bandwidth and phase margin of the switching regulator 200. The phase compensation circuit 120 includes a resistor RC, a first capacitor CC1, and a second capacitor CC2.

[0020] The resistor RC and the first capacitor CC1 are connected in series between the output node NVC of the differential amplifier circuit 110 and the low potential power supply node. One end of the resistor RC is connected to the output node NVC, and the other end is connected to one end of the first capacitor CC1. The other end of the first capacitor CC1 is connected to the low potential power supply node. One end of the second capacitor CC2 is connected to the output node NVC, and the other end is connected to the low potential power supply node.

[0021] The switching signal output circuit 130 controls the on-duty of the switching element SWT based on the voltage VC of the output node NVC of the differential amplifier circuit 110 and the inductor current IL. That is, the switching signal output circuit 130 controls the pulse width of the switching signal CSWT, which is a PWM signal, based on the voltage VC and the inductor current IL. PWM is an abbreviation for Pulse Width Modulation. The inductor current IL is converted into a voltage by the on-resistance of the switching element SWT. The switching signal output circuit 130 obtains the voltage from the potential difference between both ends of the switching element SWT and performs PWM control based on the potential difference. Note that the voltage based on the current flowing through the inductor 210 is not limited to the potential difference between both ends of the switching element SWT, and may be, for example, the potential difference between both ends of a sense resistor inserted in series with the inductor 210. The switching signal output circuit 130 is not limited to PWM control, and may perform, for example, PFM control. That is, the switching signal output circuit 130 may control the pulse frequency of the switching signal CSWT, which is a PFM signal, based on the voltage VC and the inductor current IL. PFM is an abbreviation for Pulse Frequency Modulation.

[0022] 2 and 3 are diagrams illustrating the frequency characteristics of a switching regulator.

[0023] 2, the switching regulator 200 is divided into a plant and a compensator. The compensator includes resistors RA1 and RA2, a differential amplifier circuit 110, and a phase compensation circuit 120. The remaining parts are the plant. The transfer function of the plant is Gplant, and the transfer function of the compensator is Gc.

[0024] FIG. 3 shows the frequency characteristics of the gain of the transfer function.

[0025] The transfer function Gplant of the plant shown in the upper diagram has a pole at a frequency ωpp1. The frequency ωpp1 is determined by the circuit constants of the circuit that constitutes the plant. The transfer function Gc of the compensator shown in the middle diagram has a first pole at a frequency ωpc1, a zero point at a frequency ωzc1, and a second pole at a frequency ωpc2. As shown in the formula FA, the frequency ωzc1 of the zero point is set by the resistor RC and the first capacitor CC1 of the phase compensation circuit 120. The frequency ωpc1 of the first pole is set by the output impedance RO of the differential amplifier circuit 110 and the first capacitor CC1 of the phase compensation circuit 120. The frequency ωpc2 of the second pole is set by the resistor RC and the second capacitor CC2 of the phase compensation circuit 120. These frequencies satisfy ωpc1<ωzc1<ωpc2.

[0026] The frequency ωzc1 of the zero point of the compensator is set to be approximately the same as the frequency ωpp1 of the pole of the plant. That is, the resistance value of the resistor RC and the capacitance value of the first capacitor CC1 are set so that the frequency ωzc1 is approximately the same as the frequency ωpp1. As a result, as shown in the lower diagram, the pole of the plant and the zero point of the compensator are cancelled out in the transfer function Ts of the entire switching regulator 200. That is, the transfer function Ts is a transfer function having a first pole of frequency ωpc1 and a second pole of frequency ωpc2. Since the frequencies of these poles are controlled by the compensator, the bandwidth and phase margin of the switching regulator 200 can be controlled by determining the circuit constants of the compensator.

[0027] Figure 4 shows an example of the frequency characteristics when the DC gain is increased.

[0028] In switching regulator 200, the higher the DC gain of transfer function Ts, the higher the accuracy of output voltage VOUT. For example, if the impedance of load 290 changes, there is a risk that output voltage VOUT will fluctuate. By increasing the DC gain of transfer function Ts, the fluctuation of output voltage VOUT can be reduced. For this reason, it is desirable for the DC gain of transfer function Ts of switching regulator 200 as a whole to be high.

[0029] Here, it is assumed that the DC gain of the transfer function Ts is increased by increasing the DC gain of the differential amplifier circuit 110. The DC gain of the differential amplifier circuit 110 is Gm×RO. As shown in the equation FB in Fig. 4, by increasing Gm×RO, the DC gain of the transfer function Gc of the compensator increases, and as a result, the gain of the transfer function Ts of the entire switching regulator 200 increases.

[0030] Gm of the DC gain Gm×RO is the transconductance of the differential amplifier circuit 110. The differential amplifier circuit 110 converts the differential input voltage VREF-DVOUT into a current, and when this current is IC, Gm=IC / (VREF-DVOUT). RO is the output impedance of the differential amplifier circuit 110, and RO=IC / VC.

[0031] FIG. 4 shows the change in the transfer function Ts when Gm of the DC gain Gm×RO is increased. The line A1 shown in the upper diagram shows the gain frequency characteristic before Gm is increased, and the line A2 shows the gain frequency characteristic after Gm is increased. Since the pole and zero point frequencies ωpc1, ωpc2, and ωzc1 described in FIG. 3 are not affected by Gm, as shown in the upper diagram of FIG. 4, the pole positions do not change on the lines A1 and A2, and the gain increases at all frequencies. Also, as shown in the lower diagram, the phase frequency characteristic does not change. At this time, the zero cross frequency at which the gain becomes 0 dB increases due to the increase in gain at all frequencies. If the zero cross frequency of the line A1 is ωzp1 and the zero cross frequency of the line A2 is ωzp2, then ωzp1<ωzp2. Since the phase frequency characteristic does not change, the phase margin Δph2 at the zero cross frequency ωzp2 is smaller than the phase margin Δph1 at the zero cross frequency ωzp1. That is, if the DC gain of the transfer function Ts is increased by increasing Gm, the DC gain can be increased, but the stability of the feedback loop decreases.

[0032] 2. Differential amplifier circuit 5 shows a first detailed configuration example of the differential amplifier circuit in this embodiment. The differential amplifier circuit 110 includes a first differential pair transistor TND1, a second differential pair transistor TND2, output stage transistors TNQa, TNQb, TPQa, and TPQb, P-type transistors TPD1 to TPD3, an N-type transistor TND3, and a current source circuit IBD. The power supply voltage of the differential amplifier circuit 110 is an internal power supply voltage VDD generated by a regulator 170, which will be described later with reference to FIG.

[0033] The first differential pair transistor TND1 and the second differential pair transistor TND2 are N-type transistors and form a differential pair. A voltage DVOUT is input to the gate of the first differential pair transistor TND1, and a reference voltage VREF is input to the gate of the second differential pair transistor TND2. A current source circuit IBD causes a current to flow through the differential pair. The current flowing through the first differential pair transistor TND1 is defined as In, and the current flowing through the second differential pair transistor TND2 is defined as Ip.

[0034] 5, the differential amplifier circuit 110 includes current mirror circuits MCa and MCb. The current mirror circuit MCa mirrors the current In to a current flowing through an output stage transistor TNQa. The current mirror circuit MCa includes P-type transistors TPD1 and TPD2, and an N-type transistor TND3.

[0035] The current In flows through the P-type transistor TPD2. The P-type transistors TPD1 and TPD2 form a current mirror, and the current In flows through the P-type transistor TPD1. This current In flows through the N-type transistor TND3. The N-type transistor TND3 and the output stage transistor TNQa form a current mirror, and the current In flows through the output stage transistor TNQa.

[0036] The current mirror circuit MCb mirrors the current Ip to a current flowing through the output stage transistor TPQa. The current mirror circuit MCb includes a P-type transistor TPD3.

[0037] The current Ip flows through the P-type transistor TPD3. The P-type transistor TPD3 and the output stage transistor TPQa form a current mirror, and the current Ip flows through the output stage transistor TPQa.

[0038] The output stage transistors TNQa and TNQb are N-type transistors. The output stage transistor TNQa is provided between the low potential power supply node and the node Na. The output stage transistor TNQb is provided between the node Na and the output node NVC. The connection of the output stage transistors TNQa and TNQb can be said to be a so-called cascode connection.

[0039] A bias voltage VBa is input to the gate of the output stage transistor TNQb. For example, a voltage generation circuit (not shown) generates the bias voltage VBa. When the threshold voltage of an N-type transistor is Vthn, the bias voltage VBa=Vthn+2×Vovn. Vovn is the overdrive voltage of an N-type transistor. The overdrive voltage is the source-drain voltage required to operate a transistor in the saturation region. By setting VBa=Vthn+2×Vovn, the output stage transistors TNQa and TNQb operate in the saturation region when VC≧2×Vovn. As an example, Vovn is about 0.2V.

[0040] The output stage transistors TPQa and TPQb are P-type transistors. The output stage transistor TPQa is provided between a high potential power supply node and a node Nb. The output stage transistor TPQb is provided between the node Nb and an output node NVC. The connection of the output stage transistors TPQa and TPQb can be said to be a so-called cascode connection.

[0041] A bias voltage VBb is input to the gate of the output stage transistor TNQb. For example, a voltage generation circuit (not shown) generates the bias voltage VBb. When the threshold voltage of a P-type transistor is Vthp, the bias voltage VBb=Vthp+2×Vovp. Vovp is the overdrive voltage of a P-type transistor. By setting VBb=Vthp+2×Vovp, the output stage transistors TPQa and TPQb operate in the saturation region when VC≦VDD-2×Vovp. As an example, Vovp is about 0.2V.

[0042] The differential amplifier circuit 110 may include a resistor element provided between the node Na and the output node NVC instead of the output stage transistor TNQb. The differential amplifier circuit 110 may also include a resistor element provided between the node Nb and the output node NVC instead of the output stage transistor TPQb.

[0043] The differential amplifier circuit 110 outputs a differential current IC=Ip-In between the current Ip flowing through the output stage transistors TPQa and TPQb and the current In flowing through the output stage transistors TNQa and TNQb. This differential current IC=Ip-In is converted to a voltage VC by the output impedance RO of the differential amplifier circuit 110. In other words, VC=IC×RO.

[0044] FIG. 6 shows an example of frequency characteristics when the DC gain is increased using the differential amplifier circuit of this embodiment.

[0045] As described in FIG. 5, the output stage transistors of the differential amplifier circuit 110 are cascode-connected. As a result, as shown in the formula FC in FIG. 6, the output impedance RO of the DC gain Gm×RO of the compensator increases. As described above, the first pole frequency is ωpc1=1 / (RO×CC1), and as the output impedance RO increases, ωpc1 decreases. For this reason, as shown by the line A3 in the upper diagram in FIG. 6, the DC gain of the transfer function Ts increases with an increase in RO, but as the frequency ωpc1 of the first pole decreases, the line A3 becomes the same as the line A1 at frequencies higher than the first pole. For this reason, the zero cross frequencies of the lines A1 and A3 are the same frequency ωzp1.

[0046] As shown in the lower part of Fig. 6, line B1 indicates the phase frequency characteristic corresponding to the gain line A1, and line B2 indicates the phase frequency characteristic corresponding to the gain line A3. Even if RO increases, the zero cross frequency does not change, so the phase margin Δph1 does not change either. That is, by using the differential amplifier circuit 110 of this embodiment, it is possible to increase the DC gain of the feedback loop and maintain stability.

[0047] The transconductance Gm of the differential amplifier circuit 110 can be increased relatively easily by a method such as increasing the mirror ratio of the current mirror circuit. On the other hand, in order to increase the output impedance RO, it is necessary to change the channel length L of the W / L dimension of the output stage transistor, and there is an upper limit to the increase in RO. According to this embodiment, by cascode-connecting the output stage transistors, it is possible to greatly increase RO. In addition, since it is only necessary to provide a cascode output stage transistor, the impact on the layout area is small.

[0048] FIG. 7 is a diagram illustrating the relationship between the output impedance and the gain frequency characteristic of the differential amplifier circuit.

[0049] Let Adc be the DC gain, Fbw be the bandwidth, and Fpc1 be the first pole frequency. The unit of Adc is the gain with respect to 1, which is 0 dB.

[0050] As shown in formula FD, the bandwidth Fbw is proportional to the transconductance Gm, but is not affected by the output impedance RO. If the DC gain Adc is increased by increasing the transconductance Gm, the bandwidth Fbw may widen and the loop stability may decrease. On the other hand, if the DC gain Adc is increased by increasing the output impedance RO, the bandwidth Fbw does not change, so the loop stability is not affected.

[0051] A second detailed configuration example of the differential amplifier circuit 110 will be described. Fig. 8 shows a configuration example of a semiconductor circuit device when the second detailed configuration example of the differential amplifier circuit is applied. The following mainly describes the points that differ from Fig. 1.

[0052] The semiconductor circuit device 100 includes a control circuit 180. As described below, the differential amplifier circuit 110 includes a switch. The control circuit 180 outputs control signals CTa and CTb that control the switch to be on or off. The control circuit 180 outputs a control signal that turns the switch on or off based on, for example, a register setting.

[0053] Fig. 9 shows a second detailed configuration example of the differential amplifier circuit. The following mainly describes the differences from Fig. 5. The differential amplifier circuit 110 includes switches TSa and TSb.

[0054] The switch TSa is provided between the node Na and the output node NVC. The switch TSa is an N-type transistor, and a control signal CTa is input to its gate. The switch TSb is provided between the node Nb and the output node NVC. The switch TSb is a P-type transistor, and a control signal CTb is input to its gate. In this configuration example, the cascode connection of the output stage transistors can be released. That is, when the switches TSa and TSb are on, both ends of the output stage transistor TNQb and the source-drain of the output stage transistor TPQb are shorted, and the cascode connection of the output stage transistors is released. When the switches TSa and TSb are off, the output stage transistors are cascode-connected.

[0055] In this embodiment, the semiconductor circuit device 100 is used in a switching regulator 200. The switching regulator 200 regulates an input voltage VH using a switch element SWT and an inductor 210. The semiconductor circuit device 100 includes a differential amplifier circuit 110 and a switching signal output circuit 130. The differential amplifier circuit 110 outputs a current IC based on an output voltage VOUT of the switching regulator 200. The switching signal output circuit 130 outputs a switching signal CSWT for the switch element SWT based on a voltage VC of an output node NVC of the differential amplifier circuit 110 and a voltage according to an inductor current IL flowing through the inductor 210. The differential amplifier circuit 110 includes a first output stage transistor and a second output stage transistor. The first output stage transistor is provided between a first power supply node and a first node, and outputs a current. The second output stage transistor is provided between the first node and an output node, and a first bias voltage is input to the gate of the second output stage transistor.

[0056] According to this embodiment, the first output stage transistor and the second output stage transistor are cascode-connected, thereby increasing the output impedance RO of the differential amplifier circuit 110. As described with reference to FIG. 6 and other figures, the increase in the output impedance RO increases the DC gain of the transfer function Ts of the switching regulator 200, improving the accuracy of the output voltage VOUT. Meanwhile, the phase margin Δph1 of the feedback loop is not affected, so the stability of the feedback loop is maintained. In this way, it is possible to achieve both the accuracy of the output voltage and the frequency characteristics of the feedback loop.

[0057] The first output stage transistor here may be either TNQa or TPQa in Fig. 5. When TNQa is the first output stage transistor, TNQb is the second output stage transistor, the low potential side power supply node is the first power supply node, Na is the first node, and VBa is the first bias voltage. When TPQa is the first output stage transistor, TPQb is the second output stage transistor, the high potential side power supply node is the first power supply node, Nb is the first node, and VBb is the first bias voltage.

[0058] In this embodiment, the differential amplifier circuit 110 may include a first differential pair transistor TND1, a second differential pair transistor TND2, and a current mirror circuit. A voltage DVOUT based on the output voltage VOUT of the switching regulator 200 may be input to the gate of the first differential pair transistor TND1. A reference voltage VREF may be input to the gate of the second differential pair transistor TND2. The current mirror circuit may mirror a current flowing through one of the first differential pair transistor TND1 and the second differential pair transistor TND2 as a current flowing through the first output stage transistor.

[0059] According to this embodiment, a current flows through the differential pair of transistors in response to a voltage input to the gates of the differential pair of transistors, and the current is mirrored to the output stage transistor. As a result, the differential amplifier circuit 110 outputs a current in response to the input voltage. In other words, the differential amplifier circuit 110 functions as a transconductance amplifier.

[0060] When TNQa is the first output stage transistor, MCa is a current mirror circuit. The current mirror circuit MCa mirrors the current In flowing through the first differential pair transistor TND1 as a current flowing through the output stage transistor TNQa. When TPQa is the first output stage transistor, MCb is a current mirror circuit. The current mirror circuit MCb mirrors the current Ip flowing through the second differential pair transistor TND2 as a current flowing through the output stage transistor TPQa.

[0061] In this embodiment, the differential amplifier circuit 110 may include a third output stage transistor and a fourth output stage transistor. The third output stage transistor may be provided between a second power supply node having a different potential from the first power supply node and the second node, and may output a current. The fourth output stage transistor may be provided between the second node and the output node, and a second bias voltage may be input to the gate.

[0062] According to this embodiment, the output stage transistors are cascode-connected on both the first power supply node side and the second power supply node side. The differential amplifier circuit 110 outputs the difference between the current flowing through the output stage transistor on the first power supply node side and the current flowing through the output stage transistor on the second power supply node side. In this embodiment, the impedance is high for the current on either power supply node side, so the output impedance RO of the differential amplifier circuit 110 is high.

[0063] When TNQa is the first output stage transistor, TPQa is the third output stage transistor, TPQb is the fourth output stage transistor, the high potential side power supply node is the second power supply node, Nb is the second node, and VBb is the second bias voltage. When TPQa is the first output stage transistor, TNQa is the third output stage transistor, TNQb is the fourth output stage transistor, the low potential side power supply node is the second power supply node, Na is the second node, and VBa is the second bias voltage.

[0064] In this embodiment, the differential amplifier circuit 110 may include a first differential pair transistor TND1, a second differential pair transistor TND2, a first current mirror circuit, and a second current mirror circuit. The first current mirror circuit may mirror a current flowing through one of the first differential pair transistor TND1 and the second differential pair transistor TND2 as a current flowing through a first output stage transistor. The second current mirror circuit may mirror a current flowing through the other of the first differential pair transistor TND1 and the second differential pair transistor TND2 as a current flowing through a third output stage transistor.

[0065] According to this embodiment, the difference between the current In corresponding to the voltage DVOUT input to the gate of the first differential pair transistor TND1 and the current Ip corresponding to the reference voltage VREF input to the gate of the second differential pair transistor TND2 is output to the output node NVC of the differential amplifier circuit 110. As a result, the differential amplifier circuit 110 outputs a current corresponding to the difference between the two input voltages. That is, the differential amplifier circuit 110 functions as a transconductance amplifier.

[0066] When TNQa is the first output stage transistor, MCa is the first current mirror circuit, and MCb is the second current mirror circuit. When TPQa is the first output stage transistor, MCb is the first current mirror circuit, and MCa is the second current mirror circuit.

[0067] In this embodiment, the first output stage transistor and the second output stage transistor may be MOS transistors. The size of the second output stage transistor may be the same as the size of the first output stage transistor.

[0068] Similarly, the third output stage transistor and the fourth output stage transistor may be MOS transistors. The size of the fourth output stage transistor may be the same as the size of the second output stage transistor.

[0069] According to this embodiment, the overdrive voltages of the two cascode-connected output stage transistors can be regarded as the same. This simplifies the setting of the bias voltage. As described above, as an example, the bias voltage can be set as VBa=Vthn+2×Vovn and VBb=Vthp+2×Vovp.

[0070] In this embodiment, the first power supply node may be a low-potential power supply node. The second power supply node may be a high-potential power supply node. The first output stage transistor and the second output stage transistor may be N-type MOS transistors. The third output stage transistor and the fourth output stage transistor may be P-type MOS transistors.

[0071] In this case, the first output stage transistor is TNQa, the second output stage transistor is TNQb, the third output stage transistor is TPQa, and the fourth output stage transistor is TPQb.

[0072] In this embodiment, the output impedance of the first output stage transistor and the second output stage transistor may be 1 MΩ or more.

[0073] In this embodiment, the output impedance of the first to fourth output stage transistors may be 1 MΩ or more.

[0074] According to this embodiment, a sufficiently large gain can be obtained as the DC gain of the entire switching regulator 200. For example, a sufficiently large output impedance RO, that is, a sufficiently large DC gain can be obtained, compared to the DC gain when the output stage transistor is not cascode-connected and the channel length L of the output stage transistor is changed.

[0075] In this embodiment, the semiconductor circuit device 100 may include a control circuit 180. The differential amplifier circuit 110 may include a first switch connected in parallel to the second output stage transistor. The control circuit 180 may control the first switch to be on or off.

[0076] In this embodiment, the semiconductor circuit device 100 may include a control circuit 180. The differential amplifier circuit 110 may include a first switch connected in parallel to the second output stage transistor and a second switch connected in parallel to the fourth output stage transistor. The control circuit 180 may control the first switch and the second switch to be on or off.

[0077] According to this embodiment, when the first switch is turned off, the second output stage transistor is cascode-connected to the first output stage transistor, and when the first switch is turned on, both ends of the second output stage transistor are shorted. When the second switch is turned off, the fourth output stage transistor is cascode-connected to the third output stage transistor, and when the second switch is turned on, both ends of the fourth output stage transistor are shorted. In this way, the cascode connection can be enabled or disabled.

[0078] When TNQb is the second output stage transistor, TSa is the first switch, TPb is the fourth output stage transistor, and TSb is the second switch. When TPQb is the second output stage transistor, TSb is the first switch, TPa is the fourth output stage transistor, and TSa is the second switch.

[0079] 3. Switching signal output circuit 10 shows a detailed configuration example of a switching signal output circuit. The semiconductor circuit device 100 includes a regulator 170. The switching signal output circuit 130 includes an inductance current detection circuit 131, an internal slope generation circuit 132, a comparison circuit 133, and a resistor R2.

[0080] The regulator 170 is a DC / DC converter that regulates the input voltage VH to the internal power supply voltage VDD. The regulator 170 is, for example, a linear regulator configured with an operational amplifier and a resistor, but is not limited to this.

[0081] The inductor current detection circuit 131 detects the inductor current IL based on the difference between the input voltage VH and the voltage VSW of the switch node NSW, and outputs the result as a detection current Isn.

[0082] The internal slope generating circuit 132 operates on the internal power supply voltage VDD, and generates a slope current Ise having a predetermined slope.

[0083] One end of the resistor R2 is connected to the output node of the inductance current detection circuit 131, the output node of the internal slope generation circuit 132, and the inverting input terminal of the comparison circuit 133. The other end of the resistor R2 is connected to the low potential side power supply node. The resistor R2 converts the detection current Isn and the slope current Ise into a voltage Vramp.

[0084] The voltage VC is input to a non-inverting input terminal of the comparator circuit 133 from the differential amplifier circuit 110. The comparator circuit 133 compares the voltage Vramp with the voltage VC to generate a switching signal CSWT, which is a PWM signal.

[0085] FIG. 11 shows an example of a signal waveform of a switching signal output circuit.

[0086] The comparison circuit 133 performs a comparison operation when the voltage Vramp is lower than the voltage VC at the comparison timing for each period Tp, and does not perform a comparison operation when the voltage Vramp is higher than the voltage VC at the comparison timing. That is, when the voltage Vramp is lower than the voltage VC at the comparison timing, the comparison circuit 133 resets the switching signal CSWT to a high level. When the switching signal CSWT is reset to a high level, the switch element SWT turns on from off, and the detection current Isn and the slope current Ise are output. At this time, Vramp = (Isn + Ise) × R2. When the voltage Vramp reaches the voltage VC, the comparison circuit 133 changes the switch element SWT from a high level to a low level. As a result, the switch element SWT turns off from on. When the switch element SWT turns off, the detection current Isn and the slope current Ise are no longer output. The comparison timing is generated based on, for example, a clock signal generated by an internal oscillation circuit (not shown). However, the comparison timing may be generated based on a clock signal supplied from outside the semiconductor circuit device 100, or may be generated using a counter or the like.

[0087] In FIG. 11, the voltage VC is shown as a constant voltage, but actually it is affected by the output voltage VOUT. When the load of the switching regulator 200 is large, the output voltage VOUT drops rapidly after the switch element SWT turns off. For this reason, the voltage VC is maintained at a relatively high voltage, and the time until Vramp returns to Vramp < VC is shorter than the period Tp. For this reason, Vramp < VC at each comparison timing, and a comparison operation is performed. In this case, the control of the switch element SWT becomes PWM control.

[0088] On the other hand, when the load of the switching regulator 200 is small, after the switching element SWT turns off, it takes time for the output voltage VOUT to decrease. Therefore, the voltage VC becomes a relatively low voltage, and the time until Vramp returns to VC becomes longer than the period Tp. For this reason, once the switching element SWT turns on and off, Vramp < VC occurs after one or more periods Tp, and the comparison operation is performed. In this case, the control of the switching element SWT is PFM control.

[0089] FIG. 11 shows an example of PWM control. As described above, the voltage VC fluctuates temporarily, but the voltage VC as a long-term average is controlled so that the divided voltage DVOUT of the output voltage VOUT matches the reference voltage VREF. When the voltage VC changes, the on-time Ton of the switching element SWT changes, the on-duty of the switching signal CSWT, which is a PWM signal, changes, and the output voltage VOUT changes. In this way, feedback control is performed so that the output voltage VOUT as a long-term average becomes constant.

[0090] FIG. 12 is a detailed configuration example of the inductance current detection circuit. The inductance current detection circuit 131 includes switches SW1 and SW2, resistors R1a, R1b, and R1c, P-type transistors TPE1, TPE2, and TPE3, N-type transistors TNE1 and TNE2, and a current source circuit IBE. Hereinafter, the operation of the inductance current detection circuit 131 will be described using signal waveform examples.

[0091] FIG. 13 is a signal waveform example of the inductance current detection circuit. Let the on-resistance of the switching element SWT be Ron. Assume that the resistance values of the resistors R1a, R1b, and R1c are equal, and the resistance value is R1.

[0092] As shown in Fig. 13, when the switch element SWT is on, the switch SW1 is off and the switch SW2 is on. The inductor current IL gradually increases. This inductor current IL is converted into a potential difference of the following equation (1) by the on-resistance Ron. The inductor current detection circuit 131 generates a detection current Isn from this potential difference VH-VSW. VH-VSW=IL×Ron (1)

[0093] Specifically, the current source circuit IBE passes a current Iref through the resistor R1a and the P-type transistor TPE1. The voltage of the node N1a between the resistor R1a and the P-type transistor TPE1 is Vx. The potential difference across the resistor R1a is VSW-Vx, so the current Iref is given by the following equation (2). Iref = (VSW - Vx) / R1 (2)

[0094] The P-type transistors TPE1 and TPE2 form a current mirror, and a current Iref flows through the resistor R1b and the P-type transistor TPE2. The P-type transistors TPE1 and TPE3 form a current mirror, and a current Iref flows through the resistor R1c and the P-type transistor TPE3. As a result, the voltage of the node N1b between the resistor R1b and the P-type transistor TPE2, and the voltage of the node N1c between the resistor R1c and the P-type transistor TPE3 become equal to Vx.

[0095] Since the potential difference across the resistor R1c is VH-Vx, the current Ivh flowing through the resistor R1c and the P-type transistor TPE3 is expressed by the following equation (3). Ivh = (VH - Vx) / R1 (3)

[0096] The current Iref flowing through the P-type transistor TPE2 flows through the N-type transistor TNE1. The N-type transistors TNE1 and TNE2 form a current mirror, and the current Iref flows through the N-type transistor TNE2. The inductance current detection circuit 131 outputs the difference between the current IVh flowing through the P-type transistor TPE3 and the current Iref flowing through the N-type transistor TNE2 as the detection current Isn. From the above equations (1) to (3), the detection current Isn is given by the following equation (4). Isn=Ivh-Iref=(VH-VSW) / R1=IL×Ron / R1 (4)

[0097] When the switch element SWT is off, the switch SW1 is on and the switch SW2 is off. The inductor current IL gradually decreases. Since the switch SW1 is on, Iref=Ivh and Isn=0.

[0098] 14 is a detailed configuration example of the slope generating circuit. The internal slope generating circuit 132 includes current source circuits IBF1 and IBF2, a PNP transistor TBF1, an NPN transistor TBF2, P-type transistors TPF2 and TPF3, a switch SW3, a capacitor CF, and a resistor RF. The operation of the internal slope generating circuit 132 will be described below.

[0099] When the switch element SWT is on, the switch SW3 is off. The current source circuit IBF1 supplies a current to a node NF1 at one end of the capacitor CF, causing the voltage VCF of the node NF1 to rise at a predetermined slope.

[0100] The base of PNP transistor TBF1 is connected to node NF1. Assume that the base-emitter voltage of the bipolar transistor is Vbe. The voltage of node NF2, the emitter of PNP transistor TBF1, is VCF+Vbe. The base of NPN transistor TBF2 is connected to node NF2. The voltage of node NF3, the emitter of the NPN transistor, is (VCF+Vbe)-Vbe=VCF.

[0101] Resistor RF is provided between node NF3 and the low potential power supply node. When the voltage of the low potential power supply VSS is 0V, a current VCF / RF flows through resistor RF. This current flows through P-type transistor TPF2 and NPN transistor TBF2. P-type transistors TPF2 and TPF3 form a current mirror, and current VCF / RF flows through P-type transistor TPF3. Internal slope generation circuit 132 outputs the current flowing through P-type transistor TPF3 as slope current Ise. That is, slope current Ise is expressed by the following equation (5). Ise=VCF / RF (5)

[0102] When the switch element SWT is off, the switch SW3 is on. Both ends of the capacitor CF are shorted by the switch SW3, so the voltage VCF becomes 0 V. As a result, Ise=0.

[0103] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configurations and operations of the differential amplifier circuit, phase compensation circuit, switching signal output circuit, semiconductor circuit device, and switching regulator are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0104] 100...semiconductor circuit device, 110...differential amplifier circuit, 120...phase compensation circuit, 130...switching signal output circuit, 131...inductance current detection circuit, 132...internal slope generation circuit, 133...comparison circuit, 140...reference voltage generation circuit, 160...diode, 170...regulator, 180...control circuit, 200...switching regulator, 210...inductor, 220...capacitor, 250...power supply, 290...load, MCa, MCb...current mirror circuit, SWT...switch element, TND1...first differential pair transistor, TND2...second differential pair transistor, TNQa, TNQb, TPQa, TPQb...output stage transistor, TSa, TSb...switch, VBa, VBb...bias voltage, VH...input voltage, VOUT...output voltage, VREF...reference voltage

Claims

1. A semiconductor circuit device used in a switching regulator that regulates an input voltage by using a switch element and an inductor, a differential amplifier circuit that outputs a current based on an output voltage of the switching regulator; a switching signal output circuit that outputs a switching signal for the switch element based on a voltage at an output node of the differential amplifier circuit and a voltage according to an inductor current flowing through the inductor; Including, The differential amplifier circuit includes: a first output stage transistor provided between a first power supply node and a first node, the first output stage transistor outputting the current; a second output stage transistor provided between the first node and the output node, the second output stage transistor having a gate to which a first bias voltage is input; A semiconductor circuit device comprising:

2. 2. The semiconductor circuit device according to claim 1, The differential amplifier circuit includes: a first differential pair transistor having a gate to which a voltage based on the output voltage of the switching regulator is input; a second differential pair of transistors, the gates of which receive a reference voltage; a current mirror circuit that mirrors a current flowing through one of the first differential pair transistors and the second differential pair transistors as a current flowing through the first output stage transistor; A semiconductor circuit device comprising:

3. 2. The semiconductor circuit device according to claim 1, The differential amplifier circuit includes: a third output stage transistor that is provided between a second node and a second power supply node having a potential different from that of the first power supply node, and outputs the current; a fourth output stage transistor provided between the second node and the output node, the fourth output stage transistor having a gate to which a second bias voltage is input; A semiconductor circuit device comprising:

4. 4. The semiconductor circuit device according to claim 3, The differential amplifier circuit includes: a first differential pair transistor having a gate to which a voltage based on the output voltage of the switching regulator is input; a second differential pair of transistors, the gates of which receive a reference voltage; a first current mirror circuit that mirrors a current flowing through one of the first differential pair transistors and the second differential pair transistors as a current flowing through the first output stage transistor; a second current mirror circuit that mirrors a current flowing through the other of the first differential pair transistors and the second differential pair transistors as a current flowing through the third output stage transistor; A semiconductor circuit device comprising:

5. 2. The semiconductor circuit device according to claim 1, the first output stage transistor and the second output stage transistor are MOS transistors, A semiconductor circuit device, characterized in that the size of the second output stage transistor is the same as the size of the first output stage transistor.

6. 4. The semiconductor circuit device according to claim 3, the first power supply node is a low potential power supply node, the second power supply node is a high potential power supply node, the first output stage transistor and the second output stage transistor are N-type MOS transistors, The semiconductor circuit device, wherein the third output stage transistor and the fourth output stage transistor are P-type MOS transistors.

7. 2. The semiconductor circuit device according to claim 1, An output impedance of the first output stage transistor and the second output stage transistor is 1 MΩ or more.

8. 4. The semiconductor circuit device according to claim 3, The semiconductor circuit device according to the present invention is characterized in that an output impedance of the first output stage transistor to the fourth output stage transistor is 1 MΩ or more.

9. 2. The semiconductor circuit device according to claim 1, A control circuit is included. The differential amplifier circuit includes: a first switch connected in parallel to the second output stage transistor; The control circuit includes: A semiconductor circuit device, characterized in that the first switch is controlled to be on or off.

10. 4. The semiconductor circuit device according to claim 3, A control circuit is included. The differential amplifier circuit includes: a first switch connected in parallel to the second output stage transistor; a second switch connected in parallel to the fourth output stage transistor; Including, The control circuit includes: A semiconductor circuit device, characterized in that the first switch and the second switch are controlled to be on or off.

11. 2. The semiconductor circuit device according to claim 1, a phase compensation circuit connected to the output node of the differential amplifier circuit; The phase compensation circuit includes: a resistor and a first capacitor connected in series between the output node of the differential amplifier circuit and a low potential side power supply node;

12. A semiconductor circuit device according to any one of claims 1 to 11, The inductor; A switching regulator comprising:

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