Semiconductor memory device and electronic system including the same

Abstract

To provide a semiconductor device with more improved reliability and integration degree.SOLUTION: There are provided a semiconductor memory device and an electronic system including the same. The semiconductor memory device includes: a peripheral circuit structure including a peripheral circuit; a stacked structure arranged on the peripheral circuit structure and including alternately stacked first electrode layers and first inter-electrode insulation films; a first vertical pattern penetrating the stacked structure; a first insulation film, a second electrode layer, and a second insulation film sequentially arranged on the stacked structure; a line separation pattern penetrating the second insulation film, the second electrode layer and the first insulation film; and a second vertical pattern penetrating the second insulation film, the second electrode layer, and the first insulation film and in contact with the first vertical pattern.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device and an electronic system including the same. [Background technology]

[0002] There is a demand for semiconductor devices capable of storing a large amount of data in electronic systems that require data storage. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been researched. For example, as one of the methods for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of memory cells arranged two-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 11,348,910 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device having improved reliability and integration density.

[0005] Another problem to be solved by the present invention is to provide an electronic system including a semiconductor device having improved reliability.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the above object, a semiconductor memory device according to an embodiment of the present invention includes a peripheral circuit structure including a peripheral circuit, a stacked structure disposed on the peripheral circuit structure and including a first electrode layer and a first inter-electrode insulating film alternately stacked, a first vertical pattern penetrating the stacked structure, a first insulating film, a second electrode layer, and a second insulating film disposed on the stacked structure in this order, a line separation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film, and a second vertical pattern penetrating the second insulating film, the second electrode layer, and the first insulating film and contacting the first vertical pattern.

[0008] According to an embodiment of the present invention, there is provided a semiconductor memory device including a substrate, a peripheral circuit integrated on the substrate, a peripheral circuit structure including a first bonding pad connected to the peripheral circuit, and a cell array structure including a second bonding pad bonded to the first bonding pad, the cell array structure including a stacked structure including first electrode layers and first inter-electrode insulating layers alternately stacked, a block isolation pattern penetrating the stacked structure and isolating the stacked structure into a plurality of blocks, a central isolation pattern penetrating the stacked structure and disposed at a center of each of the blocks, a first vertical pattern penetrating the stacked structure, a first insulating layer, a second electrode layer, and a second insulating layer in this order on the stacked structure, a first line isolation pattern penetrating the second insulating layer, the second electrode layer, and the first insulating layer and contacting the block isolation pattern, a second line isolation pattern penetrating the second insulating layer, the second electrode layer, and the first insulating layer and contacting the central isolation pattern, and a second vertical pattern penetrating the second insulating layer, the second electrode layer, and the first insulating layer and contacting the first vertical pattern.

[0009] According to an embodiment of the present invention, there is provided an electronic system including a semiconductor memory device including a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure, and a controller electrically connected to the semiconductor memory device through an input / output pad and controlling the semiconductor memory device, wherein the cell array structure is disposed on the peripheral circuit structure and includes a stacked structure including a first electrode layer and a first inter-electrode insulating film alternately stacked thereon, a first vertical pattern penetrating the stacked structure, a first insulating film, a second electrode layer, and a second insulating film on the stacked structure in this order, a line separation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film, and a second vertical pattern penetrating the second insulating film, the second electrode layer, and the first insulating film and contacting the first vertical pattern. Effect of the Invention

[0010] In the semiconductor memory device according to the present invention, the first and second line isolation patterns for isolating the ground selection lines are disposed on the stack structure, so that the first and second electrode layers of the stack structure can be formed flat, thereby preventing a 'seagull' shaped word line contact failure and improving the reliability of the semiconductor memory device. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram of an electronic system including a semiconductor memory device according to an exemplary embodiment of the inventive concept; [Diagram 2] 1 is a perspective view illustrating a schematic diagram of an electronic system including a semiconductor memory device according to an exemplary embodiment of the present invention; [Diagram 3] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present invention. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present invention. [Diagram 5] 1 is a plan view of a semiconductor memory device according to an exemplary embodiment of the inventive concept; [Figure 6]6 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line AA' of FIG. 5; [Figure 7] 6 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line BB' of FIG. 5; [Figure 8A] 7 is an enlarged view of 'P2' in FIG. 6 according to an embodiment of the present invention. [Figure 8B] 7 is an enlarged view of 'P2' in FIG. 6 according to an embodiment of the present invention. [Figure 8C] 7 is an enlarged view of 'P2' in FIG. 6 according to an embodiment of the present invention. [Figure 8D] 7 is an enlarged view of 'P2' in FIG. 6 according to an embodiment of the present invention. [Figure 9] 6 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line AA' of FIG. 5; [Figure 10] 6 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line BB' of FIG. 5; [Figure 11A] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11B] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11C] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11D] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11E] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11F] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11G] 7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 11H]7 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 6; [Figure 12A] 11B is an enlarged view of a portion 'P2' of FIG. 11E, sequentially illustrating a process for manufacturing a semiconductor memory device having the cross section of FIG. [Figure 12B] 11B is an enlarged view of a portion 'P2' of FIG. 11E, sequentially illustrating a process for manufacturing a semiconductor memory device having the cross section of FIG. [Figure 12C] 11B is an enlarged view of a portion 'P2' of FIG. 11E, sequentially illustrating a process for manufacturing a semiconductor memory device having the cross section of FIG. [Figure 13A] 8 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 7; [Figure 13B] 8 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 7; [Figure 13C] 8 is a diagram sequentially illustrating a process of manufacturing a semiconductor memory device having the cross section of FIG. 7; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0013] FIG. 1 is a schematic diagram of an electronic system including a semiconductor memory device according to an exemplary embodiment of the invention.

[0014] 1, an electronic system 1000 according to an exemplary embodiment of the present invention may include a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0015] The semiconductor memory device 1100 may be a non-volatile memory device, such as a NAND flash memory device. The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed beside the second structure 1100S.

[0016] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1, UL2, first and second gate lower lines LL1, LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0017] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1, LT2 adjacent to a common source line CSL, upper transistors UT1, UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1, LT2 and the upper transistors UT1, UT2. The number of the lower transistors LT1, LT2 and the number of the upper transistors UT1, UT2 may be variously modified according to the embodiment.

[0018] In an exemplary embodiment, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0019] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 or LT2 and a ground selection transistor LT2 or LT1 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 or UT2 and an upper erase control transistor UT2 or UT1 connected in series. At least one of the lower erase control transistor LT1 or LT2 and the upper erase control transistor UT2 or UT1 may be used for an erase operation that erases data stored in the memory cell transistor MCT using a Gate Induce Drain Leakage (GIDL) phenomenon.

[0020] The common source line CSL, the first and second gate lower lines LL1, LL2, the word line WL, and the first and second gate upper lines UL1, UL2 may be electrically connected to the decoder circuit 1110 through a first connecting line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connecting line 1125 extending from the first structure 1100F to the second structure 1100S.

[0021] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor memory device 1100 may communicate with the controller 1200 through an I / O pad 1101 electrically connected to the logic circuit 1130. The I / O pad 1101 may be electrically connected to the logic circuit 1130 through an I / O connection wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0022] Although not shown in the drawings, the first structure 1100F may include a voltage generator (not shown). The voltage generator may generate a program voltage, a read voltage, a pass voltage, a verify voltage, etc., required for the operation of the memory cell string CSTR. Here, the program voltage may be a relatively high voltage (e.g., 20V to 40V) compared to the read voltage, the pass voltage, and the verify voltage.

[0023] In an exemplary embodiment, the first structure 1100F may include high voltage transistors and low voltage transistors. The decoder circuit 1110 may include pass transistors connected to word lines WL of the memory cell strings CSTR. The pass transistors may include high voltage transistors capable of withstanding high voltages such as a program voltage applied to the word lines WL during a program operation. The page buffer 1120 may also include high voltage transistors capable of withstanding high voltages.

[0024] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an embodiment, the electronic system 1000 may include multiple semiconductor memory devices 1100, in which case the controller 1200 may control the multiple semiconductor memory devices 1100.

[0025] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 for processing communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written in the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. If a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0026] FIG. 2 is a schematic perspective view of an electronic system including a semiconductor memory device according to an exemplary embodiment of the invention.

[0027] 2, an electronic system 2000 according to an exemplary embodiment of the present invention may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main substrate 2001.

[0028] The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 may communicate with the external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 may operate using power supplied from the external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0029] The controller 2002 can write data to or read data from the semiconductor package 2003 , which can improve the operating speed of the electronic system 2000 .

[0030] The DRAM 2004 may be a buffer memory for mitigating the difference in speed between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory and provide space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0031] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0032] The package substrate 2100 may be a printed circuit board including an upper pad 2130. Each semiconductor chip 2200 may include an I / O pad 2210. The I / O pad 2210 may correspond to the I / O pad 1101 of FIG. 1. Each semiconductor chip 2200 may include a stacked structure 3210 and a vertical pattern 3220. Each semiconductor chip 2200 may include a semiconductor memory device according to an embodiment of the invention described below.

[0033] In an exemplary embodiment, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the upper pad 2130. Thus, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the connection structure 2400 in the bonding wire manner.

[0034] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0035] 3 and 4 are cross-sectional views each illustrating a semiconductor package according to an exemplary embodiment of the present invention, each illustrating an exemplary embodiment of the semiconductor package of FIG. 2 and conceptually showing an area of ​​the semiconductor package of FIG. 2 cut along cutting line II'.

[0036] 3, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body part 2120, an upper pad (2130 in FIG. 2) disposed on an upper surface of the package substrate body part 2120, a lower pad 2125 disposed on a lower surface of the package substrate body part 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body part 2120. The upper pad 2130 may be electrically connected to a connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main substrate 2010 of the electronic system 2000 as shown in FIG. 2 through a conductive connection part 2800.

[0037] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a source structure 3205, a stacked structure 3210 on the source structure 3205, a vertical pattern 3220 and an isolation structure penetrating the stacked structure 3210, a bit line 3240 electrically connected to the vertical pattern 3220, and a cell contact plug 3235 electrically connected to a word line (WL in FIG. 1) of the stacked structure 3210. Each of the first structure 3100 / second structure 3200 / semiconductor chip 2200 may further include an isolation structure, which will be described later.

[0038] Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may be disposed outside the stacked structure 3210, and may further be disposed to penetrate the stacked structure 3210. Each of the semiconductor chips 2200 may further include an input / output pad (2210 in FIG. 2) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0039] Referring to FIG. 4, in semiconductor package 2003A, each semiconductor chip 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 using a wafer bonding method.

[0040] The first structure 4100 may include a peripheral circuit region including a peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a source structure 4205, a stack structure 4210 between the source structure 4205 and the first structure 4100, a vertical pattern 4220 and an isolation structure penetrating the stack structure 4210, and a second junction structure 4250 electrically connected to the vertical pattern 4220 and a word line (WL in FIG. 1) of the stack structure 4210. For example, the second junction structure 4250 may be electrically connected to the vertical pattern 4220 and the word line (WL in FIG. 1) through a cell contact plug 4235 electrically connected to the bit line 4240 and the word line (WL in FIG. 1) electrically connected to the vertical pattern 4220. The first joint structure 4150 of the first structure 4100 and the second joint structure 4250 of the second structure 4200 may be joined while being in contact with each other. The joined portions of the first joint structure 4150 and the second joint structure 4250 may be made of copper (Cu).

[0041] Each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200 may further include a source structure according to an embodiment described below. Each of the semiconductor chips 2200 may further include an I / O pad (2210 in FIG. 2) electrically connected to the peripheral wiring 4110 of the first structure 4100.

[0042] The semiconductor chip 2200 of Fig. 3 or the semiconductor chip 2200 of Fig. 4 may be electrically connected to each other by a bonding wire-shaped connection structure 2400. However, in an exemplary embodiment, the semiconductor chips 2200 in one semiconductor package including the semiconductor chip 2200 of Fig. 3 or the semiconductor chip 2200 of Fig. 4 may be electrically connected to each other by a connection structure including a through-electrode TSV.

[0043] The first structure 3100 of FIG. 3 and the first structure 4100 of FIG. 4 may correspond to a peripheral circuit structure in the embodiments described below, and the second structure 3200 of FIG. 3 and the second structure 4200 of FIG. 4 may correspond to a cell array structure in the embodiments described below.

[0044] Fig. 5 is a plan view of a semiconductor memory device according to an exemplary embodiment of the present invention. Fig. 6 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line A-A' in Fig. 5. Fig. 7 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line B-B' in Fig. 5.

[0045] 5, 6 and 7, a semiconductor memory device according to an exemplary embodiment of the present invention may include a substrate 10, a peripheral circuit structure PS on the substrate 10, and a cell array structure CS on the peripheral circuit structure PS.

[0046] According to the embodiment, by combining the cell array structure CS on the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor memory device according to the present invention can be increased. Also, by manufacturing the peripheral circuit structure PS and the cell array structure CS separately and combining them, damage to the peripheral circuit PTR due to various heat treatment processes can be prevented, so that the electrical characteristics and reliability of the semiconductor memory device according to the present invention can be improved.

[0047] More specifically, the peripheral circuit structure PS is integrated on the front side of the substrate 10 and may include a peripheral circuit PTR that controls the memory cell array, peripheral contact plugs PCP, peripheral circuit wiring PLP electrically connected to the peripheral circuit PTR through the peripheral contact plugs PCP, a first bonding pad BP1 electrically connected to the peripheral circuit wiring PLP, and a lower insulating film 50 surrounding these.

[0048] The substrate 10 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate 10 may have a top surface that is parallel to a first direction D1 and a second direction D2 intersecting the first direction D1 and perpendicular to a third direction D3. The first to third directions D1, D2, and D3 may be, for example, perpendicular to each other. An isolation layer 11 may be provided in the substrate 10. The isolation layer 11 may define an active region of the substrate 10.

[0049] The peripheral circuit PTR may be the row and column decoders, page buffers, and control circuits described with reference to FIG. 1. More specifically, the peripheral circuit PTR may include NMOS and PMOS transistors. The transistors constituting the peripheral circuit PTR may be provided on an active region of the substrate 10.

[0050] For example, the peripheral contact plugs PCP may have a width in the first direction D1 or the second direction D2 that increases in the third direction D3. The peripheral contact plugs PCP and the peripheral circuit wiring PLP may include a conductive material such as a metal.

[0051] The lower insulating film 50 may include insulating films stacked in multiple layers. For example, the lower insulating film 50 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film. As an example, the lower insulating film 50 may include a first lower insulating film 51, a second lower insulating film 55, and an etch stop film 53 between the first and second lower insulating films 51, 55. The etch stop film 53 may include an insulating material different from that of the first and second lower insulating films 51, 55, and may cover an upper surface of the uppermost peripheral circuit wiring PLP. In addition, a surface insulating film 201 may be provided on a lower surface of the substrate 10.

[0052] The first bonding pad BP1 may be disposed in a top-layer lower insulating film 50. The lower insulating film 50 may not cover an upper surface of the first bonding pad BP1. An upper surface of the top-layer lower insulating film 50 may be substantially coplanar with an upper surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through a peripheral circuit wiring PLP and a peripheral contact plug PCP.

[0053] A cell array structure CS may be provided on the peripheral circuit structure PS. The cell array structure CS of the semiconductor memory device may include a cell array region CAR, a first connection region CNR1 and a second connection region CNR2 arranged side by side in a first direction D1.

[0054] The cell array structure CS may include a memory cell array including memory cells arranged three-dimensionally. The cell array structure CS may include a source conductive pattern SCP, a third electrode layer GE3, a stack structure ST, first and second vertical patterns VS1, VS2, a third vertical pattern VS3, a bit line BL, a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG. The third electrode layer GE3 may be a ground selection gate pattern GGE. The ground selection gate pattern GGE may also be referred to as a ground selection line. In the first vertical pattern VS1 and the third vertical pattern VS3, the 'vertical pattern' may also be referred to as a 'vertical semiconductor pattern' or a 'vertical channel pattern'.

[0055] The multiple laminate structures ST may extend in a first direction D1 and be spaced apart from each other in a second direction D2 in a plan view according to Fig. 5. In the following, for ease of explanation, a single laminate structure ST will be described, but the following explanation may be similarly applied to other laminate structures ST.

[0056] The stacked structure ST may include first and second electrode layers GE1, GE2 and first and second inter-electrode insulating films ILD1, ILD2 alternately stacked along a third direction D3 (i.e., a vertical direction) perpendicular to first and second directions D1, D2 that intersect with each other.

[0057] In an embodiment, the first electrode layer GE1 may include first and second erase gate patterns EGE1 and EGE2 adjacent to the third electrode layer GE3, and a plurality of cell gate patterns CGE below the second erase gate pattern EGE2. The second electrode layer GE2 may include a plurality of cell gate patterns CGE and a string select gate pattern SGE below the bottom cell gate pattern CGE.

[0058] The erase control gate patterns EGE1 and EGE2 are adjacent to the third electrode layer GE3 and can be used as a gate pattern of an erase control transistor (LT1 or LT2 in FIG. 1) that generates a gate induced drain leakage GIDL of the memory cell array to control an erase operation. The ground selection gate pattern GGE, which is the third electrode layer GE3, can be used as a gate pattern of a ground selection transistor (LT1 or LT2 in FIG. 1) that controls an electrical connection between a common source line (CSL in FIG. 1) and a vertical channel. The cell gate pattern CGE can be used as a word line (WL in FIG. 1) of a memory cell transistor (MCT in FIG. 1). The string selection gate pattern SGE of the top layer can be used as a gate pattern of a string selection transistor (UT1 or UT2 in FIG. 1) that controls an electrical connection between a bit line BL and a first vertical pattern VS1.

[0059] In another example, in the semiconductor memory device according to this example, the first electrode layer GE1 does not include the first and second erase gate patterns EGE1 and EGE2 and may be eliminated. The first electrode layer GE1 may include only the cell gate pattern CGE. A portion of the second electrode layer GE2 may serve as an erase gate.

[0060] 5 to 7, the first and second electrode layers GE1 and GE2 of the stacked structure ST may be stacked to have an inverted staircase structure in the first connection region CNR1, that is, the length of the first and second electrode layers GE1 and GE2 may increase in the first direction D1 as they move away from the peripheral circuit structure PS.

[0061] The first and second electrode layers GE1, GE2, and the third electrode layer GE3 may each include a pad portion in the first connection region CNR1. The pad portions of the first and second electrode layers GE1, GE2, and the third electrode layer GE3 may be located at different positions horizontally and vertically. Cell contact plugs CPLG may be connected to the pad portions of the first and second electrode layers GE1, GE2, and the third electrode layer GE3, respectively.

[0062] In the embodiment, the stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 on the first stacked structure ST1. The first stacked structure ST1 may include a first inter-electrode insulating film ILD1 and a first electrode layer GE1 that are alternately stacked, and the second stacked structure ST2 may include a second inter-electrode insulating film ILD2 and a second electrode layer GE2 that are alternately stacked.

[0063] The second stack structure ST2 may be disposed between the first stack structure ST1 and the peripheral circuit structure PS. More specifically, the second stack structure ST2 may be provided under the lower surface of the bottommost one of the first inter-electrode insulating films ILD1 of the first stack structure ST1. The topmost one of the second inter-electrode insulating films ILD2 of the second stack structure ST2 and the bottommost one of the first inter-electrode insulating films ILD1 of the first stack structure ST1 may contact each other, but the present invention is not limited thereto, and a single layer insulating film may be provided between the topmost one of the second electrode layers GE2 of the second stack structure ST2 and the bottommost one of the first electrode layers GE1 of the first stack structure ST1.

[0064] The bottommost one of the second electrode layers GE2 of the second laminate structure ST2 may have the shortest length in the first direction D1, and the topmost one of the first electrode layers GE1 of the first laminate structure ST1 may have the longest length in the first direction D1.

[0065] The first and second electrode layers GE1, GE2 and the third electrode layer GE3 may include at least one selected from, for example, an impurity-doped semiconductor (ex, silicon doped with impurities), a metal (ex, tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.), etc. According to one example, the first and second electrode layers GE1, GE2 may be formed of tungsten and a metal, and the third electrode layer GE3 may be formed of polysilicon doped with impurities.

[0066] The first and second inter-electrode insulating films ILD1 and ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, and / or low dielectric materials, for example, the first and second inter-electrode insulating films ILD1 and ILD2 may include high density plasma oxide (HDP oxide) or TEOS (TetraEthylOrthoSilicate).

[0067] According to an embodiment, the semiconductor memory device is a vertical NAND flash memory device, in which case the first and second electrode layers GE1, GE2 of the stack structure ST can be used as the gate lower lines LL1, LL2, word lines WL, and gate upper lines UL1, UL2 described with reference to FIG. 1.

[0068] The third electrode layer GE3 may be used as one of the gate lower lines LL1 and LL2 described with reference to FIG. 1 or as a ground selection line. The third electrode layer GE3 may protrude to the side of the first and second electrode layers GE1 and GE2. In this example, the third electrode layer GE3 is illustrated as a single layer, but is not limited thereto and may be configured as two or more layers. In addition, the role of the third electrode layer GE3 is not limited to a ground selection line and may also be involved in an erase operation.

[0069] The flat insulating film 110 may cover an end portion (i.e., a pad portion) of the laminated structure ST having a stepped structure. The flat insulating film 110 may have a substantially flat upper surface. The flat insulating film 110 may include one insulating film or a plurality of stacked insulating films. The flat insulating film 110 may have substantially flat upper and lower surfaces. The upper surface of the flat insulating film 110 may be substantially coplanar with the upper surface of the uppermost first inter-electrode insulating film ILD1 of the laminated structure ST, and the lower surface of the flat insulating film 110 may be substantially coplanar with the lower surface of the lowermost second inter-electrode insulating film ILD2 of the laminated structure ST.

[0070] A first insulating film 305 may be interposed between the stacked structure ST and the third electrode layer GE3. A first wiring BW1 may be disposed on the first insulating film 305. The third electrode layer GE3 and the first wiring BW1 may be formed of the same material and have the same thickness. The third electrode layer GE3 and the first wiring BW1 may be covered with a second insulating film 310. A source conductive pattern SCP and a second wiring BW2 may be disposed on the second insulating film 310. The source conductive pattern SCP and the second wiring BW2 may be formed of the same material and have the same thickness. For example, the source conductive pattern SCP and the second wiring BW2 may include at least one selected from a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.), etc.

[0071] The source conductive pattern SCP may have a uniform thickness and a substantially flat upper surface. The source conductive pattern SCP may extend in a first direction D1 parallel to the stacked structure ST in the cell array region CAR and the first connection region CNR1. In the first direction D1, the length of the source conductive pattern SCP may be greater than the length of the uppermost first electrode layer GE1 of the first stacked structure ST1.

[0072] The source conductive pattern SCP may include at least one selected from a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). As an example, the source conductive pattern SCP may include a metal material (e.g., tungsten). The source conductive pattern SCP may correspond to the common source line CSL of FIG. 1.

[0073] A plurality of first vertical patterns VS1 may be connected to the source conductive patterns SCP through the stack structure ST in the cell array region CAR. The first vertical patterns VS1 may be arranged in one direction or in a zigzag shape in a plan view. The first vertical patterns VS1 may include a semiconductor material such as silicon. The first vertical patterns VS1 may act as at least one channel in the memory cell transistors MCT, the upper transistors UT1 and UT2, and the lower transistors LT1 and LT2 of FIG. 1.

[0074] The second vertical pattern VS2 may penetrate the stacked structure ST in the first connection region CNR1. The second vertical pattern VS2 may penetrate ends (i.e., pad portions) of the first and second electrode layers GE1 and GE2 in the first connection region CNR1. The second vertical pattern VS2 may include the same semiconductor material as the first vertical pattern VS1, or may include an insulating material different therefrom. The second vertical pattern VS2 may act as a support during the manufacturing process of the stacked structure ST.

[0075] The planar shape and size of the second vertical pattern VS2 may be different from those of the first vertical pattern VS1. The upper surface of the second vertical pattern VS2 may have various shapes such as a circle, an ellipse, a bar shape, etc. The second vertical pattern VS2 may be disposed around each cell contact plug CPLG. If the upper surface of the second vertical pattern VS2 has an ellipse shape, the major axes of the second vertical patterns VS2 may be disposed in different directions in each pad part PAD. A plurality of second vertical patterns VS2 may be provided between adjacent cell contact plugs CPLG.

[0076] In the embodiment, each of the first vertical patterns VS1 may be provided in a vertical channel hole penetrating the stacked structure ST. In the embodiment, the vertical channel hole may include a first vertical channel hole penetrating the first stacked structure ST1 and a second vertical channel hole penetrating the second stacked structure ST2 and connected to the first vertical channel hole.

[0077] Each of the first vertical patterns VS1 may include a first vertical extension in the first vertical channel hole and a second vertical extension in the second vertical channel hole. The first vertical extension and the second vertical extension may be one structure that is continuously extended without an interface. Here, the first vertical extension may have a sidewall with a uniform gradient from its lower portion to its upper portion. Similarly, the second vertical extension may have a sidewall with a uniform gradient from its lower portion to its upper portion. In other words, each of the first and second vertical extensions may have a width in the first direction D1 or the second direction D2 that decreases as it becomes farther from the substrate 10. The first and second vertical extensions may have different diameters at a portion where they are connected to each other. A step may be formed at a portion where the first and second vertical extensions are connected to each other.

[0078] However, the present invention is not limited thereto, and each first vertical pattern VS1 may have three or more vertical extensions each having a step at two or more boundaries, as shown in the drawings. As another example, each first vertical pattern VS1 may have a flat sidewall without a step.

[0079] 5 to 7, the stacked structure ST of the cell array structure CS may be divided into (memory) blocks BLK by block separation patterns SS1. A first central separation pattern SS2 may penetrate the stacked structure ST at the center of one block BLK. A second central separation pattern SS3 may be disposed between the block separation pattern SS1 and the first central separation pattern SS2 adjacent to each other and may penetrate the stacked structure ST.

[0080] Each of the block isolation pattern SS1, the first central isolation pattern SS2, and the second central isolation pattern SS3 may have a single layer or multi-layer structure made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0081] The block isolation patterns SS1 may extend in parallel from the cell array region CAR to the first connecting region CNR1 along a first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The block isolation patterns SS1 may have a continuous line shape without any cuts in the first direction D1.

[0082] The first central isolation pattern SS2 may have a continuous line shape along the first direction D1 in the cell array region CAR. The first central isolation pattern SS2 may be extended to the first connecting region CNR1. However, the first central isolation pattern SS2 may have a discontinuous section cut off by the first connecting region CNR1. Therefore, the cell gate patterns CGE belonging to one block BLK are connected at the discontinuous section at a corresponding height and are in an equipotential state.

[0083] The second central separation pattern SS3 may have a line shape extending in the first direction D1 in the first connecting region CNR1 but may have a discontinuous section, i.e., a plurality of second central separation patterns SS3 may be provided and arranged to be spaced apart from each other in the first direction D1.

[0084] Referring to FIG. 5, a string line isolation pattern 9 is disposed between a block isolation pattern SS1 and a first central isolation pattern SS2 in the cell array region CAR. The string line isolation pattern 9 may be located at the same distance from the block isolation pattern SS1 and the first central isolation pattern SS2. The string line isolation pattern 9 may penetrate the lowest part of the second electrode layer GE2 and isolate the lowest part of the second electrode layer GE2 with a plurality of string selection gate patterns SGE. The string line isolation pattern 9 may have a single layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The string line isolation pattern 9 may have a line shape extending in a first direction D1 in the cell array region CAR. The string line isolation pattern 9 may be interposed between a portion of the first vertical pattern VS1. Or, the string line isolation pattern 9 may penetrate a portion of the first vertical pattern VS1. The first vertical pattern VS1 disposed within the string line isolation pattern 9 or penetrated by the string line isolation pattern 9 may not function as a channel of the memory cell but may become a dummy channel. The string line separation pattern 9 may be disposed parallel to the second central separation pattern SS3 in the first direction D1. The string line separation pattern 9 does not penetrate the cell gate pattern CGE.

[0085] The first line separation pattern GCT1 may be connected to the block separation pattern SS1 through the second insulating film 310, the third electrode layer GE3, and the first insulating film 305. The second line separation pattern GCT2 may be connected to the first center separation pattern SS2 through the second insulating film 310, the third electrode layer GE3, and the first insulating film 305. The first line separation pattern GCT1 and the second line separation pattern GCT2 separate the third electrode layer GE3 by a plurality of ground selection gate patterns GGE or ground selection lines GGE.

[0086] In the semiconductor memory device according to the present invention, the first and second line separation patterns GCT1 and GCT2 for separating the ground selection line GGE are disposed on the stack structure ST, so that the first and second electrode layers GE1 and GE2 of the stack structure ST can be formed flat. Therefore, a 'seagull' shaped word line contact failure can be prevented, and the reliability of the semiconductor memory device can be improved.

[0087] The first line separation pattern GCT1 and the second line separation pattern GCT2 may extend in parallel along a first direction D1 from the cell array region CAR to the first connecting region CNR1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The first line separation pattern GCT1 and the second line separation pattern GCT2 may have a continuous line shape without any cuts in the first direction D1. The first line separation pattern GCT1 and the second line separation pattern GCT2 may be coplanar with an upper surface of the second insulating film 310.

[0088] First, second, third and fourth interlayer insulating films 120, 130, 140 and 150 may be disposed between the peripheral circuit structure PS and the stack structure ST and between the peripheral circuit structure PS and the planar insulating film 110. The first to fourth interlayer insulating films 120, 130, 140 and 150 may be sequentially stacked on the planar insulating film 110. The first interlayer insulating film 120 may cover the lower surfaces of the first and second vertical patterns VS1 and VS2. The first, second, third and fourth interlayer insulating films 120, 130, 140 and 150 may include silicon oxide, silicon nitride, silicon oxynitride and / or a low dielectric material.

[0089] The bit lines BL, bottom contacts LCTa, LCTb, bottom conductive lines LCLa, LCLb, top conductive lines UCLa, UCLb, and second bonding pads BP2 may be disposed in the first, second, third, and fourth interlayer insulating films 120, 130, 140, and 150.

[0090] Although the bit lines are omitted in the plan view of FIG. 5, referring to FIG. 6 and FIG. 7, the bit lines BL may be disposed on the second interlayer insulating film 130 in the cell array region CAR and may be extended in the second direction D2 across the stack structure ST. The bit lines BL may be electrically connected to the first vertical pattern VS1 through bit line contact plugs BCT. A bit line conductive pad BPD may be formed at a lower end of the first vertical pattern VS1, and the bit line contact plug BCT may be in contact with the bit line conductive pad. The bit line conductive pad BPD may be made of an undoped semiconductor material, a doped semiconductor material, or a conductive material.

[0091] 6, the cell contact plug CPLG may be connected to the corresponding pad portions of the first and second electrode layers GE1 and GE2 through the first interlayer insulating film 120, the planar insulating film 110, and the end of the stack structure ST. The cell contact plug CPLG may be directly connected to the corresponding one of the first and second electrode layers GE1 and GE2, and a contact insulating film SW1 may be interposed between the non-corresponding first and second electrode layers GE1 and GE2 and the cell contact plug CPLG. The contact insulating film SW1 may have a single layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The cell contact plugs CPLG may have the same height (or vertical length) as each other. The outermost portion of the cell contact plug CPLG is connected to the third electrode layer GE3.

[0092] The peripheral contact plugs PPLG and the input / output contact plugs IOPLG may penetrate the first and second interlayer insulating layers 120 and 130 and the planar insulating layer 110 in the second connecting region CNR2 and be connected to the first wiring BW1 and the second wiring BW2.

[0093] Each of the cell contact plugs CPLG, the peripheral contact plugs PPLG, and the input / output contact plugs IOPLG may include a barrier metal film including a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) and a metal film including a metal (e.g., tungsten, titanium, tantalum, etc.).

[0094] The first bottom contact LCTa is located in the second interlayer insulating film 130 of the first connection region CNR1. The first bottom conductive line LCLa may be disposed under the second interlayer insulating film 130 of the first connection region CNR1 and may be connected to the cell contact plug CPLG through the first bottom contact LCTa.

[0095] The second bottom contact LCTb is located in the second interlayer insulating film 130 of the second connection region CNR2. The second bottom conductive line LCLb may be disposed under the second interlayer insulating film 130 of the second connection region CNR2 and may be connected to the peripheral and I / O contact plugs PPLG and IOPLG through the second bottom contact LCTb.

[0096] The first and second upper conductive lines UCLa and UCLb may be disposed under the third interlayer insulating film 140. The first upper conductive line UCLa may be electrically connected to the bit line BL in the cell array region CAR. The second upper conductive line UCLb may be electrically connected to the second lower conductive line LCLb in the first and second connection regions CNR1 and CNR2.

[0097] The first and second lower conductive lines LCLa, LCLb and the first and second upper conductive lines UCLa, UCLb may include at least one selected from a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), a transition metal (ex, titanium, tantalum, etc.), etc. For example, the first and second lower conductive lines LCLa, LCLb may be formed of tungsten having a relatively high electrical resistivity, and the first and second upper conductive lines UCLa, UCLb may be formed of copper having a relatively low electrical resistivity.

[0098] A second bonding pad BP2 may be provided in the uppermost interlayer insulating film 150. The second bonding pad BP2 may be electrically connected to the first and second upper conductive lines UCLa and UCLb. The second bonding pad BP2 may be made of aluminum, copper, tungsten, or the like.

[0099] The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 by a bonding method, that is, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0100] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1, and the width of the second bonding pad BP2 may be the same as or different from the width of the first bonding pad BP1.

[0101] 6, the outermost one of the cell contact plugs CPLG is connected to a pad portion of the third electrode layer GE3 by a first contact CT1 penetrating the first insulating film 305. The second contact CT2 penetrates the first insulating film 305 and can connect one of the peripheral contact plugs PPLG to the first wiring BW1. The third contact CT3 penetrates the first insulating film 305 and the second insulating film 310 and can connect the other one of the peripheral contact plugs PPLG to the source conductive pattern SCP. The fourth contact CT4 penetrates the first insulating film 305 and the second insulating film 310 and can connect one of the input / output contact plugs IOPLG to the second wiring BW2.

[0102] The source conductive pattern SCP and the second wiring BW2 may be covered with a third insulating layer 320. An I / O pad PD may be disposed on the third insulating layer 320. A passivation layer 330 may be disposed on the third insulating layer 320. Each of the first to third insulating layers 305, 310, and 320 may have a single layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The passivation layer 330 may be a polyimide-based material such as photosensitive polyimide (PSPI). The passivation layer 330 may have a pad opening OP exposing a portion of the I / O pad PD. A fifth contact CT5 may connect the second wiring BW2 to the I / O pad PD by penetrating the third insulating layer 320.

[0103] 8A to 8D are enlarged views of 'P2' in FIG. 6 according to an embodiment of the present invention.

[0104] Referring to FIG. 8A, the first vertical pattern VS1 is disposed in a vertical channel hole VH penetrating the stack structure ST. The first vertical pattern VS1 may be formed of a semiconductor film (e.g., a silicon film or a germanium film) that is doped or undoped with impurities. The first vertical pattern VS1 may have a pipe shape, a macaroni shape, or a shell shape with an open upper and / or lower end. A first impurity region IMR may be disposed on the first vertical pattern VS1. The first impurity region IMR may be doped with impurities of the same conductivity type as the impurities doped into the source conductive pattern SCP.

[0105] An upper surface or an upper end VS1_t of the first vertical pattern VS1 may be protruded above an upper surface ILD1t of the topmost first inter-electrode insulating film ILD1, that is, a second level LV2 of the upper surface or an upper end VS1_t of the first vertical pattern VS1 may be higher than a first level LV1 of an upper surface ILD1t of the topmost first inter-electrode insulating film ILD1.

[0106] The inside of the first vertical pattern VS1 may be filled with a first buried insulating pattern IL. The first buried insulating pattern IL may have a single layer or a multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0107] A first gate insulating film GO1 may be interposed between the first vertical pattern VS1 and the first and second electrode layers GE1 and GE2. The gate insulating film GO1 may include a tunnel insulating film L1, a charge storage film L2, and a blocking insulating film L3, which are interposed in this order from a sidewall of the first vertical pattern VS1 toward the first and second electrode layers GE1 and GE2. The tunnel insulating film L1 and the blocking insulating film L3 may include silicon oxide. The charge storage film L2 may include silicon nitride. Alternatively, the charge storage film L2 may be a trap insulating film, a floating gate electrode, or an insulating film including conductive nano dots.

[0108] A high dielectric layer HP may be interposed between the first and second electrode layers GE1, GE2 and the first and second inter-electrode insulating layers ILD1, ILD2. The high dielectric layer HP may include, for example, a metal oxide. The high dielectric layer HP may be extended and interposed between the first gate insulating layer GO1 and the first and second electrode layers GE1, GE2.

[0109] An upper surface of the first gate insulating film GO1 may be coplanar with an upper surface ILD1t of the uppermost first inter-electrode insulating film ILD1.

[0110] The third vertical pattern VS3 may be in contact with the first vertical pattern VS1 through the second insulating film 310, the third electrode layer GE3, and the first insulating film 305. The third vertical pattern VS3 is disposed in the upper hole UH. The third vertical pattern VS3 may be formed of a semiconductor film (e.g., a silicon film or a germanium film) that is doped or not doped with impurities. An upper end of the third vertical pattern VS3 is in contact with the source conductive pattern SCP. The width of the third vertical pattern VS3 may become narrower as it goes downward. The lower part of the third vertical pattern VS3 covers the upper sidewall of the first vertical pattern VS1 as shown in FIG. 8A.

[0111] In a plan view, the position and arrangement of the third vertical pattern VS3 may be the same as the position and arrangement of the first vertical pattern VS1 in Fig. 5, and may be overlapped with the first vertical pattern VS1. In another example, the third vertical pattern VS3 may not be overlapped with the string line separation pattern 9. The thickness of the third vertical pattern VS3 may be the same as or different from the thickness of the first vertical pattern VS1. The third vertical pattern VS3 may have a hollow macaroni, cylinder, or shell shape.

[0112] The inside of the third vertical pattern VS3 may be filled with a second buried insulating pattern 29. The second buried insulating pattern 29 may have a single layer or a multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second buried insulating pattern 29 may contact an upper surface VS1_t of the first vertical pattern VS1 as shown in FIG. 8A. The second buried insulating pattern 29 is spaced apart from the first buried insulating pattern IL. The upper portion of the first vertical pattern VS1 is interposed between the second buried insulating pattern 29 and the first buried insulating pattern IL.

[0113] A second gate insulating film GO2 may be interposed between the third vertical pattern VS3 and the third electrode layer GE3. The second gate insulating film GO2 may be formed of, for example, a single layer of silicon oxide. The thickness of the second gate insulating film GO2 may be different from the thickness of the first gate insulating film GO1. No high dielectric film HP is interposed between the third electrode layer GE3 and the first and second insulating films 305, 310.

[0114] 8B, the second buried insulating pattern 29 may penetrate the upper portion VS1_t of the first vertical pattern VS1 and contact the first buried insulating pattern IL, and the other structures may be the same / similar to those described with reference to FIG.

[0115] 8C, a lower portion of the third vertical pattern VS3 may contact an upper portion VS1_t of the first vertical pattern VS1. The lower portion of the third vertical pattern VS3 and the upper portion VS1_t of the first vertical pattern VS1 are interposed between the second buried insulating pattern 29 and the first buried insulating pattern IL. The third vertical pattern VS3 covers an upper surface VS1_t of the first vertical pattern VS1 and may have a U-shaped cross section or an H-shaped cross section.

[0116] 8D, an upper surface VS1_t of the first vertical pattern VS1 and an upper surface of the first gate insulating film GO1 may be coplanar with an upper surface ILD1t of the top first inter-electrode insulating film ILD1. The second buried insulating pattern 29 may be in contact with the first buried insulating pattern IL.

[0117] Fig. 9 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line A-A' in Fig. 5. Fig. 10 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention, taken along line B-B' in Fig. 5.

[0118] 9 and 10, in the semiconductor memory device according to the present embodiment, the first electrode layer GE1 does not include the first and second erase gate patterns EGE1 and EGE2 and can be eliminated. The first electrode layer GE1 can include only the cell gate pattern CGE. The third electrode layer GE3 can be formed of three layers. The third electrode layer GE3 can include the first and second erase gate patterns EGE1 and EGE2 and the ground selection gate pattern GGE. The ground selection gate pattern GGE and the first wiring BW1 are disposed on the first insulating film 305. The ground selection gate pattern GGE and the first wiring BW1 are covered with the fourth insulating film 306. The second erase gate pattern EGE2 is disposed on the fourth insulating film 306. The second erase gate pattern EGE2 is covered with the fifth insulating film 307. The first erase gate pattern EGE1 is disposed on the fifth insulating film 307. The first erase gate pattern EGE1 is covered with the second insulating film 310. The third electrode layer GE3 may be longer in the first direction D1 as it goes upward. An end of the third electrode layer GE3 may have an inverted staircase shape.

[0119] The sixth contact CT6 connects the pad portion of the second erase gate pattern EGE2 to one of the cell contact plugs CPLG by passing through the first and fourth insulating films 305 and 306. The seventh contact CT7 connects the pad portion of the first erase gate pattern EGE1 to another of the cell contact plugs CPLG by passing through the first, fourth and fifth insulating films 305, 306 and 307. The third contact CT3 connects the pad portion of the source conductive pattern SCP to another of the peripheral contact plugs PPLG by passing through the first, fourth, fifth and second insulating films 305, 306, 307 and 310.

[0120] The second vertical pattern VS3 penetrates the third electrode layer GE3 and contacts the first vertical pattern VS1. The first and second line separation patterns GCT1 and GCT2 penetrate the third electrode layer GE3 and contact the block separation pattern SS1 and the first central separation pattern SS2, respectively. The other configurations are the same / similar to those described above.

[0121] Figures 11A to 11H are views sequentially showing a process for manufacturing a semiconductor memory device having the cross-section of Figure 6. Figures 12A to 12C are enlarged views of a portion 'P2' of Figure 11E, sequentially showing a process for manufacturing a semiconductor memory device having the cross-section of Figure 6. Figures 13A to 13C are views sequentially showing a process for manufacturing a semiconductor memory device having the cross-section of Figure 7.

[0122] Referring to FIG. 11A, a peripheral circuit structure PS including a peripheral circuit PTR formed on a first substrate 10 may be formed.

[0123] Forming the peripheral circuit structure PS may include forming an element isolation film 11 that defines an active region in the first substrate 10, forming a peripheral circuit PTR on the active region of the first substrate 10, and forming peripheral contact plugs PCP electrically connected to the peripheral circuit PTR, peripheral circuit wiring PLP, first bonding pads BP1, and a peripheral circuit insulating film 50 covering them.

[0124] The first substrate 10 may include, for example, at least one of silicon (Si), germanium Ge, silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0125] The peripheral circuit PTR may include row and column decoders, a page buffer, and a control circuit formed on the first substrate 10. Here, the peripheral circuit PTR may include a MOS transistor using the first substrate 10 as a channel.

[0126] The peripheral circuit insulating film 50 may include one insulating film or a plurality of stacked insulating films covering the peripheral circuit PTR. As an example, the peripheral circuit insulating film 50 may include a first lower insulating film 51, a second lower insulating film 55, and an etching stop film 53 between the first and second lower insulating films 51, 55. The peripheral circuit insulating film 50 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0127] The peripheral contact plugs PCP may be formed to be connected to the peripheral circuits by penetrating a portion of the peripheral circuit insulating film 50. The peripheral circuit wiring PLP may be formed by performing a process of depositing a conductive film and a conductive film patterning process.

[0128] The first bonding pad BP1 may be formed in the uppermost second lower insulating film 55 of the peripheral circuit insulating film 50. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through a peripheral contact plug PCP and a peripheral circuit wiring PLP.

[0129] The first bonding pad BP1 may be formed using a damascene process. An upper surface of the first bonding pad BP1 may be substantially coplanar with an upper surface of the second lower insulating film 55. Hereinafter, being substantially coplanar means that a planarization process may be performed. The planarization process may be performed, for example, through a chemical mechanical polishing (CMP) process or an etch back process.

[0130] 5 and 11B, a first mold structure ML1 may be formed on a second substrate 100. As shown in FIG.

[0131] Forming the first mold structure ML1 may include forming a first thin film structure (not shown) in which first inter-electrode insulating films ILD1 and first sacrificial films SL1 are vertically alternately stacked, and repeatedly performing a patterning process on the first thin film structure. Therefore, the first mold structure ML1 may have a stepped structure in the first connection region CNR1.

[0132] The first inter-electrode insulating film ILD1 and the first sacrificial film SL1 may be deposited using a thermal chemical vapor deposition (Thermal CVD), a plasma enhanced chemical vapor deposition (Plasma Enhanced CVD), a physical chemical vapor deposition (Physical CVD), or an atomic layer deposition (ALD) process.

[0133] In the first mold structure ML1, the first sacrificial layer SL1 may be formed of a material that has etching selectivity with respect to the first inter-electrode insulating layer ILD1 and can be etched. As an example, the first sacrificial layer SL1 may be formed of a different insulating material from the first inter-electrode insulating layer ILD1. For example, the first sacrificial layer SL1 may be formed of a silicon nitride layer, and the first inter-electrode insulating layer ILD1 may be formed of a silicon oxide layer.

[0134] After forming the first mold structure ML1, a flat insulating film 110 may be formed to cover the staircase structure of the first mold structure ML1.

[0135] Subsequently, a second mold structure ML2 may be formed on the first mold structure ML1. According to some embodiments, a vertical sacrificial pattern (not shown) may be formed through the first mold structure ML1 before forming the second mold structure ML2.

[0136] Forming the second mold structure ML2 may be substantially the same as forming the first mold structure ML1 described above. That is, forming the second mold structure ML2 may include forming a second thin film structure (not shown) in which second interelectrode insulating films ILD2 and second sacrificial films SL2 are vertically alternately stacked on the first mold structure ML1, and repeatedly performing a patterning process on the second thin film structure. Therefore, the second mold structure ML2 may have a stepped structure in the first connection region CNR1.

[0137] The second sacrificial layer SL2 may be made of the same material as the first sacrificial layer SL1, and the second sacrificial layer SL2 may have substantially the same thickness as the first sacrificial layer SL1. The second sacrificial layer SL2 may be made of a different insulating material than the second inter-electrode insulating layer ILD2. The second sacrificial layer SL2 may be made of the same material as the first sacrificial layer SL1. For example, the second sacrificial layer SL2 may be made of a silicon nitride layer, and the second inter-electrode insulating layer ILD2 may be made of a silicon oxide layer.

[0138] After forming the second mold structure ML2, a flat insulating film 110 may be formed to cover the staircase structure of the second mold structure ML2.

[0139] Then, a vertical channel hole may be formed through the first and second mold structures ML1 and ML2 to expose the second substrate 100. If a vertical sacrificial pattern (not shown) is formed in the first mold structure ML1, forming the vertical channel hole may include removing the vertical sacrificial pattern to expose the second substrate 100.

[0140] When forming the vertical channel hole, a dummy channel hole penetrating the planar insulating layer 110 and a portion of the first and second mold structures ML1 and ML2 may be formed in the first connection region CNR1.

[0141] The vertical channel hole may be formed by forming a hard mask pattern on the second mold structure ML2 and anisotropically etching the first and second mold structures ML1 and ML2 using the hard mask pattern as an etching mask. In the anisotropic etching process for forming the vertical channel hole, the upper surface of the second substrate 100 may be over-etched, and therefore the upper surface of the second substrate 100 exposed to the vertical channel hole may be recessed to a predetermined depth. In addition, in the anisotropic etching process for forming the vertical channel hole, the recess depth of the second substrate 100 may vary depending on the position of the vertical channel hole.

[0142] Then, a first vertical pattern VS1 may be formed in the vertical channel hole of the cell array region CAR, and a second vertical pattern VS2 may be formed in the dummy channel hole of the first connection region CNR1.

[0143] Forming the first and second vertical patterns VS1 and VS2 may include sequentially depositing a first gate insulating film GO1 and the first vertical pattern VS1 in the vertical channel hole, and etching and planarizing the first gate insulating film GO1 and the first vertical pattern VS1.

[0144] 8A, the first gate insulating film GO1 may be deposited on the bottom and inner wall of the vertical channel hole VH to a uniform thickness using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The first gate insulating film GO1 may include a blocking insulating film L3, a charge storage film L2, and a tunnel insulating film L1, which are sequentially stacked in the vertical channel hole. The first vertical pattern VS1 may be deposited on the first gate insulating film GO1 to a uniform thickness using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. After forming the first gate insulating film GO1 and the first vertical pattern VS1, the vertical channel hole VH may be filled with a first buried insulating pattern IL.

[0145] Then, a bit line conductive pad BPD may be formed on an upper end of the first vertical pattern VS1. The bit line conductive pad BPD may be an impurity region doped with impurities or may be made of a conductive material. An upper surface of the bit line conductive pad BPD may be coplanar with an upper surface of the uppermost second inter-electrode insulating film ILD2.

[0146] 5 and 11C, a first interlayer insulating film 120 may be formed on the planar insulating film 110 to cover upper surfaces of the first and second vertical patterns VS1 and VS2.

[0147] Then, a process of replacing the first and second sacrificial layers SL1 and SL2 of the first and second mold structures ML1 and ML2 with the first and second electrode layers GE1 and GE2 may be performed. Thus, a stacked structure ST may be formed on the second substrate 100.

[0148] The process of replacing the first and second sacrificial layers SL1, SL2 with the first and second electrode layers GE1, GE2 may include isotropically etching the first and second sacrificial layers SL1, SL2 using an etching recipe having etching selectivity with respect to the first and second inter-electrode insulating layers ILD1, ILD2, the first and second vertical patterns VS1, VS2, and the second substrate 100. After forming the stacked structure ST, the block isolation pattern SS1, the first central isolation pattern SS2, and the second central isolation pattern SS3 of Figures 5, 7, and 13A may be formed.

[0149] Thereafter, a second interlayer insulating film 130 may be formed on the first interlayer insulating film 120, and a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG connected to the stack structure ST may be formed.

[0150] The peripheral contact plugs PPLG and the input / output contact plugs IOPLG may be formed by forming contact holes that expose the second substrate 100 by penetrating the first interlayer insulating film 120 and the planar insulating film 110 in the second connection region CNR2, and then filling a conductive material into the contact holes.

[0151] A second interlayer insulating film 130 may be formed on the first interlayer insulating film 120, and bit line contact plugs BCT of the cell array region CAR and connection contact plugs of the first and second connection regions CNR1 and CNR2 may be formed thereon.

[0152] The bit line contact plugs BCT may be connected to the first vertical pattern VS1 through the first and second interlayer insulating films 120 and 130. The bit line contact plugs BCT may be in contact with the bit line conductive pads. The bit line conductive pads may be made of an undoped semiconductor material, an impurity doped semiconductor material, or a conductive material.

[0153] The first connection contact plug may be connected to the cell contact plug CPLG through the second interlayer insulating film 130. The second connection contact plug may be connected to the peripheral contact plug PPLG and the I / O contact plug IOPLG through the second interlayer insulating film 130.

[0154] A bit line BL and lower conductive lines LCLa, LCLb may be formed on the second interlayer insulating film 130. The bit line BL may be connected to a bit line contact plug BCT, and the lower conductive lines LCLa, LCLb may be connected to a connecting contact plug.

[0155] 5 and 11D, third and fourth interlayer insulating layers 140 and 150 may be stacked on the second interlayer insulating layer 130, and first and second upper conductive lines UCLa and UCLb may be formed on the third interlayer insulating layer 140. The first and second upper conductive lines UCLa and UCLb may be connected to the first and second lower conductive lines LCLa and LCLb.

[0156] A second bonding pad BP2 may be formed in the fourth interlayer insulating film 150, and the second bonding pad BP2 may be connected to the first and second upper conductive lines UCLa and UCLb.

[0157] The first and second upper conductive lines UCLa, UCLb and the second bonding pad BP2 may be formed using a damascene process. An upper surface of the second bonding pad BP2 may be substantially coplanar with an upper surface of the fourth interlayer insulating film 150.

[0158] 5, 11D and 11E, the cell array structure CS formed on the second substrate 100 and the peripheral circuit structure PS formed on the first substrate 10 by the method described with reference to Fig. 10 may be bonded to each other. More specifically, the first bonding pad BP1 of the peripheral circuit structure PS and the second bonding pad BP2 of the cell array structure CS may be bonded to each other.

[0159] Therefore, the first bonding pad BP1 and the second bonding pad BP2 can be bonded to each other, and the second lower insulating film 55 on the first substrate 10 and the fourth interlayer insulating film 150 on the second substrate 100 can be bonded to each other.

[0160] By bonding the first bonding pad BP1 and the second bonding pad BP2 to each other, the cell array structure CS may be inverted upside down, i.e., the second substrate 100 of the cell array structure CS may be located at the top, and the staircase structure of the stacked structure ST may be arranged in an inverted shape.

[0161] 11E and 12A, after bonding the first bonding pad BP1 and the second bonding pad BP2 to each other, the second substrate 100 may be removed. Removing the second substrate 100 may include a grinding process, a planarization process, a dry etching process, and a wet etching process. By removing the second substrate 100, an upper surface 110t of the lowermost first inter-electrode insulating film ILD1 and an upper surface 110t of the planar insulating film 110 of the stacked structure ST may be exposed. In addition, by removing the second substrate 100, an upper portion of the first vertical pattern VS1 and the first gate insulating film GO1 covering the upper portion may be protruded onto the lowermost first inter-electrode insulating film ILD1, and the peripheral contact plugs PPLG and the input / output contact plugs IOPLG may be exposed.

[0162] Referring to FIG. 12B, an upper portion of the first gate insulating film GO1 protruding onto the lowermost first inter-electrode insulating film ILD1 may be removed to expose an upper surface VS1_t of the first vertical pattern VS1.

[0163] 12C, an ion implantation process is performed to form a first impurity region IMR on the first vertical pattern VS1, The first impurity region IMR may be doped with, for example, N-type impurities.

[0164] 11F and 13A, a first insulating film 305 may be stacked on the stacked structure ST, and a planarization process may be performed. The first insulating film 305 may contact the first vertical pattern VS1, the cell contact plug CPLG, the peripheral contact plug PPLG, and the I / O contact plug IOPLG. The first insulating film 305 is etched to form a first contact hole exposing at least one of the outermost cell contact plug CPLG and the peripheral contact plug PPLG. The first contact hole is filled with a conductive film to form first and second contacts CT1 and CT2. A conductive film is stacked on the first insulating film 305 and etched to form a third electrode layer GE3 and a first wiring BW1. The third electrode layer GE3 is formed to contact the first contact CT1. The first wiring BW1 is formed to contact the second contact CT2. A second insulating film 310 is formed to cover the third electrode layer GE3 and the first wiring BW1.

[0165] 5, 8A, 11G, and 13B, the second insulating film 310, the third electrode layer GE3, and the first insulating film 305 are etched in the cell array region CAR to form an upper hole UH exposing the first vertical pattern VS1. A second gate insulating film GO2 is conformally stacked on the second insulating film 310 and then anisotropically etched. Thus, a second gate insulating film GO2 is formed that covers the inner wall of the upper hole UH and exposes the first vertical pattern VS1. A semiconductor film is conformally stacked on the second insulating film 310 and then an anisotropic etching process is performed to form a third vertical pattern VS3 that covers the sidewall of the second gate insulating film GO2. A second buried insulating film is stacked on the second insulating film 310 to fill the upper hole UH, and an anisotropic etching process is performed to expose the upper end of the third vertical pattern VS3, and a second buried insulating pattern 29 is formed in the upper hole UH. Then, the second insulating layer 310 and the first insulating layer 305 are etched in the second connection region CNR2 to form second contact holes exposing at least one of the peripheral contact plugs PPLG and the I / O contact plug IOPLG. The second contact holes are filled with a conductive layer to form third and fourth contacts CT3 and CT4.

[0166] 5 and 13C, the second insulating film 310, the third electrode layer GE3, and the first insulating film 305 are etched in the cell array region CAR and the first connecting region CNR1 to form a first groove GR1 exposing the block isolation pattern SS1 and a second groove GR2 exposing the first central isolation pattern SS2. An insulating film is deposited on the second insulating film 310 to fill the first groove GR1 and the second groove GR2, and then an etch-back process or a polishing process is performed to form a first line isolation pattern GCT1 and a second line isolation pattern GCT2 in the first groove GR1 and the second groove GR2, respectively, and to expose an upper surface of the third vertical pattern VS3.

[0167] 11H, a conductive layer is deposited on the second insulating layer 310 and etched to form a source conductive pattern SCP and a second wiring BW2. The source conductive pattern SCP and the second wiring BW2 are formed of a conductive layer, which may be made of polysilicon doped with N-type impurities.

[0168] 6 and 7, a third insulating film 320 is formed to cover the source conductive pattern SCP and the second wiring BW2. A fifth contact CT5 is formed inside the third insulating film 320. An I / O pad PD is formed on the third insulating film 320. A passivation layer 330 is formed on the third insulating film 320. A portion of the passivation layer 330 is removed to form a pad opening OP exposing the I / O pad PD. Thus, the semiconductor memory device of FIGS. 5 to 7 can be manufactured.

[0169] Conventionally, the stacked structure ST is formed to include the ground selection line GGE and the first and second line separation patterns GCT1, GCT2, and the first and second electrode layers GE1, GE2 are formed to be bent in a 'seagull' shape by the first and second line separation patterns GCT1, GCT2. Therefore, a contact failure occurs in which parts of the first and second electrode layers GE1, GE2 are in contact with each other, or the first and second electrode layers GE1, GE2 are not spaced apart by a certain distance, resulting in an operation error.

[0170] However, in the present invention, after forming the stack structure ST, the first and second line separation patterns GCT1 and GCT2 for separating the ground selection line GGE are formed, so that the first and second electrode layers GE1 and GE2 can be formed flat, thereby preventing the word line contact failure such as a 'seagull' shape, and improving the reliability of the semiconductor memory device.

[0171] Although the embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical concept or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting. [Explanation of symbols]

[0172] 11. Element isolation film 50 Lower insulating film 120, 130, 140, 150 Interelectrode insulating film 201 Surface insulating film 305 310 Insulating film BP1, BP2 bonding pads CAR cell array area CNR1, CNR2 connection region CS Cell Array Structure CT1, CT2 1st Contact GCT1, GCT2 line separation pattern GE1, GE2, GE3 electrode layer GGE Ground Selection Line PCP peripheral contact plug PLP peripheral circuit wiring PS peripheral circuit structure PTR peripheral circuit SS1 Block Separation Pattern SS2 Center Separation Pattern ST laminated structure VS1, VS2 First vertical pattern

Claims

1. a peripheral circuit structure including a peripheral circuit; a laminated structure disposed on the peripheral circuit structure and including first electrode layers and first interelectrode insulating films alternately laminated; a first vertical pattern penetrating the laminate structure; a first insulating film, a second electrode layer, and a second insulating film on the laminated structure in this order; a line separation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film; a second insulating film, a second electrode layer, and a second vertical pattern penetrating the first insulating film and contacting the first vertical pattern.

2. 2. The semiconductor memory device of claim 1, wherein the line separation pattern is provided in a plurality of parts to separate the second electrode layer into a plurality of ground selection lines.

3. the line separation pattern includes a first line separation pattern and a second line separation pattern, The semiconductor memory device includes: a block separation pattern penetrating the laminated structure and separating the laminated structure into a plurality of blocks; a central separation pattern extending through the laminate structure and disposed at the center of each of the blocks; the block separation patterns are in contact with the first line separation patterns, 3. The semiconductor memory device of claim 2, wherein the central isolation pattern contacts the second line isolation pattern.

4. In a plan view, the stacked structure has a cell array region and a connection region, the first line separation pattern, the second line separation pattern, and the block separation pattern are all continuous in the cell array region and the connection region; 4. The semiconductor memory device of claim 3, wherein the central isolation pattern has a discontinuous section in the connection region.

5. 2. The semiconductor memory device of claim 1, wherein top surfaces of the line isolation pattern and the second vertical pattern are coplanar with an top surface of the second insulating layer.

6. 2. The semiconductor memory device of claim 1, further comprising a source layer located on the second insulating layer and in contact with the second vertical pattern.

7. At least one third electrode layer is located on the second insulating film, 2. The semiconductor memory device of claim 1, wherein the second vertical pattern penetrates the at least one third electrode layer.

8. A portion of the third electrode layer protrudes laterally from the second electrode layer, The semiconductor memory device includes: a first contact penetrating the first insulating film and electrically connecting the second electrode layer to the peripheral circuit structure; 8. The semiconductor memory device of claim 7, further comprising: a second contact penetrating the first insulating film and the second insulating film to electrically connect the third electrode layer to the peripheral circuit structure.

9. A substrate; a peripheral circuit structure including a peripheral circuit integrated on the substrate and a first bonding pad connected to the peripheral circuit; a cell array structure including a second bonding pad bonded to the first bonding pad; The cell array structure includes: a laminated structure including first electrode layers and first interelectrode insulating films alternately laminated; a block separation pattern penetrating the laminated structure and separating the laminated structure into a plurality of blocks; a central separation pattern extending through the laminate structure and disposed at the center of each of the blocks; a first vertical pattern penetrating the laminate structure; a first insulating film, a second electrode layer, and a second insulating film on the laminated structure in this order; a first line isolation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film and contacting the block isolation pattern; a second line isolation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film and contacting the central isolation pattern; a second insulating film, a second electrode layer, and a second vertical pattern penetrating the first insulating film and contacting the first vertical pattern.

10. a semiconductor memory device including a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure; a controller electrically connected to the semiconductor memory device through an input / output pad and configured to control the semiconductor memory device; The cell array structure includes: a laminated structure disposed on the peripheral circuit structure and including first electrode layers and first interelectrode insulating films alternately laminated; a first vertical pattern penetrating the laminate structure; a first insulating film, a second electrode layer, and a second insulating film on the laminated structure in this order; a line separation pattern penetrating the second insulating film, the second electrode layer, and the first insulating film; an insulating film, a second insulating layer, a second electrode layer, and a second vertical pattern that penetrates the first insulating film and contacts the first vertical pattern;

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