Semiconductor device and electronic apparatus

Abstract

To provide a semiconductor device that maintains the accuracy of determining a failure of a sound reproduction device despite a change in temperature.SOLUTION: A semiconductor device has a normal operation mode, an inspection mode, and a calibration mode, and comprises: a test signal generation circuit 60 that, in the inspection mode for determining the state of a sound reproduction device 3, modulates a test signal to generate a third modulated signal TP and a fourth modulated signal TN; an amplifier circuit 50 that outputs a third amplified signal DOXP obtained by amplifying the third modulated signal to a first output terminal 91, and outputs a fourth amplified signal DOXN obtained by amplifying the fourth modulated signal to a second output terminal 92; a peak frequency detection circuit 70 that measures the electric potential difference between the first output terminal and the second output terminal, and detects a peak frequency fpeak at which the impedance of the sound reproduction device that is a speaker or a buzzer reaches a peak; and a determination circuit 61 that determines whether the peak frequency is included in a reference frequency range determined on the basis of the frequency band of the test signal and information on the temperature of the sound reproduction device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and an electronic device. [Background technology]

[0002] Patent document 1 describes a speaker failure notification device in which a control unit measures the impedance that changes with structural changes in the speaker, determines whether the measured impedance is within a predetermined range, and if it determines that the impedance is not within that range, notifies the user that the speaker is malfunctioning. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-199854 A Summary of the Invention [Problem to be solved by the invention]

[0004] The speaker failure notification device described in Patent Document 1 determines whether the measured impedance is within a predetermined range, so if the speaker impedance changes due to a change in temperature, there is a risk that the speaker failure cannot be correctly determined. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a test signal generating circuit that, in a second operation mode, generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which the impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with.

[0006] Another aspect of the semiconductor device according to the present invention is A semiconductor device connected to a sound source reproducing circuit, the semiconductor device comprising: an input terminal; a modulation circuit that modulates a signal input to the input terminal and outputs a first modulated signal and a second modulated signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulated signal to a first terminal of a sound reproducing device, and that outputs a second amplified signal obtained by amplifying the second modulated signal to a second terminal of the sound reproducing device, a first input terminal connected to the first terminal of the sound reproducing device; a second input terminal connected to the second terminal of the sound reproducing device; an output terminal connected to the input terminal of the sound source reproducing circuit; a switch that outputs a signal based on a sound source signal to the output terminal in a first operation mode, and outputs a test signal, the frequency of which is changed within a preset frequency band, to the output terminal in a second operation mode; a test signal generating circuit that outputs the test signal to the switch in the second operation mode; a peak frequency detection circuit that measures a potential difference between the first input terminal and the second input terminal in the second operation mode and detects a peak frequency of the test signal at which an impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with.

[0007] One aspect of the electronic device according to the present invention is One aspect of the semiconductor device; The sound reproduction device; Equipped with.

[0008] Another aspect of the electronic device according to the present invention is a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that, in a first operation mode, modulates a signal based on a sound source signal to output a first modulated signal and a second modulated signal, and, in a second operation mode, modulates a test signal whose frequency is changed within a preset frequency band to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which the impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 shows an example of pulse width modulation for generating a modulated signal DOP. [Diagram 3] FIG. 2 is a diagram showing an example of pulse width modulation for generating a modulated signal DON. [Figure 4] 4 is a diagram showing an example of a difference between a modulated signal DOP and a modulated signal DON; [Diagram 5] 5 is a diagram showing an example of the relationship between the state of a speaker and impedance characteristics. [Figure 6] FIG. 2 is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and their peripheral circuits. [Figure 7] FIG. 2 is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and their peripheral circuits. [Figure 8] FIG. 13 is a diagram showing an example of the configuration of a differential low-pass filter. [Figure 9] FIG. 4 is a diagram showing an example of a relationship between a test signal and a peak frequency and a peak voltage. [Figure 10] FIG. 4 is a graph showing the temperature dependence of peak impedance and peak frequency. [Figure 11] 4 is a graph showing the temperature dependence of the waveform of the output voltage of a differential low-pass filter. [Figure 12] FIG. 4 is a flowchart showing an example of a processing procedure of the inspection circuit in a calibration mode in the first embodiment. [Figure 13] FIG. 4 is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the first embodiment. [Figure 14] 5A and 5B are diagrams showing an example of a method for calculating a peak frequency and a peak voltage in the first embodiment. [Figure 15] FIG. 13 is a graph showing the relationship between temperature and peak frequency. [Figure 16] FIG. 13 is a graph showing the relationship between temperature and peak impedance. [Figure 17] FIG. 11 is a flowchart showing an example of a processing procedure of the inspection circuit in a calibration mode in the second embodiment. [Figure 18] FIG. 11 is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the second embodiment. [Figure 19] FIG. 13 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block in the third embodiment. [Figure 20] FIG. 13 is a flowchart showing an example of a processing procedure of the inspection circuit in a calibration mode in the third embodiment. [Figure 21] FIG. 13 is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the third embodiment. [Figure 22] FIG. 13 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block in the fourth embodiment. [Diagram 23] FIG. 13 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block in the fourth embodiment. [Figure 24] FIG. 13 is a flowchart showing an example of a processing procedure of the inspection circuit in a calibration mode in the fourth embodiment. [Diagram 25] FIG. 13 is a diagram showing a configuration example of a semiconductor device according to a fifth embodiment. [Figure 26] FIG. 13 is a diagram showing another example of pulse width modulation for generating the modulated signal DON. [Figure 27] FIG. 13 is a diagram showing another example of the difference between the modulated signal DOP and the modulated signal DON. [Figure 28] FIG. 2 is a functional block diagram of the electronic device according to the embodiment. [Figure 29] FIG. 1 is a diagram showing an example of the configuration of a warning device, which is an example of an electronic device. [Diagram 30] FIG. 13 is a diagram showing a configuration example of an electronic device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0011] 1. Semiconductor Devices 1-1. First embodiment 1-1-1. Configuration of semiconductor device Fig. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment. As shown in Fig. 1, the semiconductor device 1 according to the first embodiment includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 81 and 82, a sound source reproducing circuit 100, and an inspection circuit 110. The semiconductor device 1 is connected to a sound reproducing device 3. The semiconductor device 1 may be a one-chip semiconductor integrated circuit device, or may be composed of semiconductor integrated circuit devices with multiple chips, or may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0012] The semiconductor device 1 has three operation modes: a normal operation mode, an inspection mode, and a calibration mode. The normal operation mode is an operation mode in which the sound reproducing device 3 reproduces sound. The inspection mode is an operation mode for determining the state of the sound reproducing device 3. The calibration mode is a mode for creating information required for determining the state of the sound reproducing device 3.

[0013] The memory 20 stores n pieces of sound source data 21-1 to 21-n, where n is an integer equal to or greater than 1. The memory 20 may be, for example, a flash memory. Each of the sound source data 21-1 to 21-n may be, for example, pulse code modulated audio data or adaptive differential pulse code modulated audio data. The sound source data 21-1 to 21-n may be, for example, data that is the basis of various sounds such as sounds that imitate the voice of a person speaking, mechanical warning sounds, sound effects, etc.

[0014] The communication interface circuit 10 is a circuit that performs data communication with the micro control unit 2. The communication interface circuit 10 may be, for example, an SPI interface circuit or an I2C interface circuit. SPI is an abbreviation for Serial Peripheral Interface, and I2C is an abbreviation for Inter-Integrated Circuit.

[0015] The communication interface circuit 10 receives various commands transmitted from the micro control unit 2, and generates various control signals according to the received commands. For example, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to a normal operation mode, an inspection mode, or a calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 41, 42, 81, and 82 according to the operation mode. Also, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the sound source reproduction circuit 100 as a sound source signal DI, and instructs the sound source reproduction circuit 100 to reproduce the sound source data 21-i by the sound reproduction device 3. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. Also, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100 to stop reproduction. Furthermore, for example, when the communication interface circuit 10 receives various setting commands related to sound source reproduction, the communication interface circuit 10 performs various settings on the sound source reproduction circuit 100 .

[0016] In this embodiment, the sound source signal DI input to the sound source reproduction circuit 100 is a pulse code modulated signal. When the sound source data 21-1 to 21-n are compressed audio data or adaptive differential pulse code modulated audio data, the sound source data 21-i to be reproduced is converted into the sound source signal DI, which is a pulse code modulated signal, by a decoder (not shown).

[0017] The sound source reproduction circuit 100 converts the sound source signal DI into amplified signals DOXP, DOXN, which are sound signals, and outputs them to the sound reproduction device 3. As a result, sound corresponding to the amplified signals DOXP, DOXN is output from the sound reproduction device 3. For example, the sound reproduction device 3 may be a speaker or a buzzer. Note that the sound output from the sound reproduction device 3 may be, for example, a voice that imitates the voice of a person when speaking, or various sounds such as a mechanical warning sound or sound effect.

[0018] As shown in FIG. 1, in this embodiment, the sound source reproducing circuit 100 includes a modulation circuit 30, switches 41 and 42, and an amplifier circuit 50.

[0019] The modulation circuit 30 receives the sound source signal DI, modulates a signal based on the sound source signal DI, and outputs modulated signals DOP and DON. The signal based on the sound source signal DI may be the sound source signal DI itself, or may be a signal obtained by performing some processing on the sound source signal DI. In this embodiment, the modulation circuit 30 includes a digital filter 31, a sigma-delta modulation circuit 32, and a pulse width modulation circuit 33.

[0020] The digital filter 31 is a low-pass filter that receives the sound source signal DI and outputs a signal DF in which high-frequency noise contained in the sound source signal DI has been reduced. The sigma-delta modulation circuit 32 receives the signal DF from the digital filter 31, and oversamples the signal DF at a sampling ratio of n times and performs sigma-delta modulation to output a sigma-delta modulated signal DS in which noise is biased toward a high frequency band. n is an integer of 2 or more. Therefore, when the sampling frequency of the sound source signal DI is fs, the sampling frequency of the signal DF output from the digital filter 31 is fs, and the sampling frequency of the sigma-delta modulated signal DS is n×fs. The digital filter 31 functions as an anti-aliasing filter that reduces high-frequency noise that is folded back into the signal band by the oversampling of the sigma-delta modulation circuit 32.

[0021] The pulse width modulation circuit 33 pulse-width modulates the sigma-delta modulated signal DS to output the modulated signals DOP and DON. The modulated signals DOP and DON are each 1-bit digital signals. If the sampling frequency of the sigma-delta modulated signal DS is n×fs, then the sampling frequency of the modulated signals DOP and DON is n×m×fs. Here, if the number of bits of the sigma-delta modulated signal DS is M, then m=2 M It is.

[0022] In this manner, the modulation circuit 30 performs sigma-delta modulation on the signal obtained by digitally filtering the sound source signal DI, and further performs pulse width modulation to output the modulated signals DOP and DON.

[0023] The pulse width modulation for generating the modulated signal DOP and the pulse width modulation for generating the modulated signal DON are different in type. FIG. 2 is a diagram showing an example of the pulse width modulation for generating the modulated signal DOP. FIG. 3 is a diagram showing an example of the pulse width modulation for generating the modulated signal DON. FIGS. 2 and 3 show an example in which the number of bits M of the sigma-delta modulated signal DS is 4. In FIGS. 2 and 3, the sigma-delta modulated signal DS is updated periodically with a period T, and the modulated signals DOP and DON are at a high level or a low level in each of the 16 sections T1 to T16 into which the period T is divided. That is, the length of the period T is 1 / (n×fs), and the length of each of the sections T1 to T16 is 1 / (n×m×fs).

[0024] As shown in FIG. 2, the higher the value of the sigma-delta modulated signal DS, the longer the time that the modulated signal DOP is at a high level. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DOP has one section T1 at a high level and 15 sections T2 to T16 at a low level. For example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DOP has eight sections T1 to T8 at a high level and eight sections T9 to T16 at a low level. For example, when the sigma-delta modulated signal DS is "7" in decimal, that is, "0111" in binary, the modulated signal DOP has 15 sections T1 to T15 at a high level and one section T16 at a low level.

[0025] As shown in FIG. 3, the higher the value of the sigma-delta modulated signal DS, the shorter the time that the modulated signal DON is at high level. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DON has 15 sections T1 to T15 at high level and one section T16 at low level. Also, for example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DON has 8 sections T1 to T8 at high level and 8 sections T9 to T16 at low level. Also, for example, when the sigma-delta modulated signal DS is "7" in decimal, that is, "0111" in binary, the modulated signal DON has 1 section T1 at high level and 15 sections T2 to T16 at low level.

[0026] Therefore, for example, when the sigma-delta modulated signal DS is the decimal numbers "-7", "0", and "7", the difference between the modulated signal DOP and the modulated signal DON is as shown in FIG.

[0027] 1, the switch 41 outputs either the modulated signal DOP or the modulated signal TP to the class-D amplifier 51P of the amplifier circuit 50 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 41 outputs the modulated signal DOP to the class-D amplifier 51P when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TP to the class-D amplifier 51P when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0028] Furthermore, the switch 42 outputs either the modulated signal DON or the modulated signal TN to the class D amplifier 51N of the amplifier circuit 50 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 42 outputs the modulated signal DON to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulated signal TN to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0029] In the normal operation mode, the amplifier circuit 50 receives the modulated signals DOP, DON, and outputs amplified signals DOXP, DOXN obtained by amplifying the modulated signals DOP, DON to the output terminals 91, 92 of the semiconductor device 1. In the inspection mode and the calibration mode, the amplifier circuit 50 receives the modulated signals TP, TN, and outputs amplified signals DOXP, DOXN obtained by amplifying the modulated signals TP, TN to the output terminals 91, 92 of the semiconductor device 1.

[0030] In this embodiment, the amplifier circuit 50 includes two class D amplifiers 51P and 51N. In the normal operation mode, the class D amplifier 51P outputs an amplified signal DOXP obtained by amplifying the modulated signal DOP to the output terminal 91, and in the inspection mode and calibration mode, outputs an amplified signal DOXP obtained by amplifying the modulated signal TP to the output terminal 91. In the normal operation mode, the class D amplifier 51N outputs an amplified signal DOXN obtained by amplifying the modulated signal DON to the output terminal 92, and in the inspection mode and calibration mode, outputs an amplified signal DOXN obtained by amplifying the modulated signal TN to the output terminal 92. The output terminal 91 is connected to the terminal P1 of the sound reproducing device 3, and the output terminal 92 is connected to the terminal P2 of the sound reproducing device 3. The sound reproducing device 3 reproduces a sound having a volume corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN. In the normal operation mode, the sound reproducing device 3 preferably outputs a desired sound instructed by the sound source reproducing command, and in the inspection mode and calibration mode, outputs a minute sound that is difficult for the human ear to hear. That is, the volume reproduced by the sound reproducing device 3 in the inspection mode and calibration mode is preferably smaller than the minimum volume reproduced by the sound reproducing device 3 in the normal operation mode. In other words, the voltage difference between the amplified signal DOXP and the amplified signal DOXN in the inspection mode and calibration mode is preferably smaller than the voltage difference between the amplified signal DOXP and the amplified signal DOXN when the minimum sound is output from the sound reproducing device 3 in the normal operation mode. This makes it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode or the calibration mode.

[0031] The inspection circuit 110 is a circuit for inspecting the sound reproduction device 3 .

[0032] FIG. 5 is a diagram showing an example of the relationship between the state of a speaker, which is an example of a sound reproduction device 3, and the impedance characteristics. In FIG. 5, the horizontal axis is the frequency of the input signal to the speaker, and the vertical axis is the impedance value of the speaker. G1 is an example of the impedance characteristics when the speaker is normal. The peak frequency, which is the frequency of the input signal at which the impedance of the speaker peaks, varies depending on the type of speaker, but when the speaker is normal, it is at least 20 Hz, which is the lower limit of the human audible range, and is used for a buzzer warning sound. This is included in the frequency band below 3kHz, which is the frequency at which the speaker will vibrate. G2 is an example of the impedance characteristics when the speaker's magnet has been damaged and removed. When the magnet is removed from a speaker, all that remains is the coil, so the impedance value rises slowly towards higher frequencies and the peak frequency disappears. G3 is an example of the impedance characteristics when the speaker's cone paper is torn. When the cone paper, which is the vibrating surface of the speaker, is torn, bass sounds are no longer produced and the peak frequency shifts to the higher frequency side.

[0033] In this way, the peak frequency changes depending on the state of the speaker. Therefore, in this embodiment, the inspection circuit 110 detects the peak frequency of the sound reproduction device 3 in the inspection mode, and judges the state of the sound reproduction device 3 based on the detected peak frequency. Note that, in the calibration mode, the inspection circuit 110 detects the peak frequency of the sound reproduction device 3, and creates information necessary for judging the state of the sound reproduction device 3 based on the detected peak frequency.

[0034] In this embodiment, the inspection circuit 110 includes a test signal generation circuit 60, a judgment circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generation circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. The judgment circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0035] The test signal generation circuit 60 generates the modulated signals TP and TN by modulating the test signal whose frequency has been changed in a preset frequency band. The frequency band in which the test signal generation circuit 60 changes the frequency of the test signal can be arbitrarily set by the micro control unit 2, and may be, for example, a frequency band of 10 Hz or more and 3 kHz or less. In this embodiment, the test signal generation circuit 60 pulse-width modulates the test signal to generate the modulated signals TP and TN. The method of pulse-width modulation by the test signal generation circuit 60 is the same as the method of pulse-width modulation by the pulse-width modulation circuit 33.

[0036] The peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects a peak frequency, which is the frequency of the test signal at which the impedance of the sound reproduction device 3 reaches a peak. The peak frequency detection circuit 70 also detects a peak voltage, which is a voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency. As will be described later, the peak frequency and the peak voltage change depending on the temperature of the sound reproduction device 3.

[0037] The memory 62 includes a non-volatile memory (not shown), and the non-volatile memory stores table information in which a plurality of temperatures and a plurality of peak frequencies related to the sound reproducing device 3 are associated with each other. This table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproducing device 3. The memory 62 also includes a volatile memory (not shown) that stores various types of data that have been temporarily created.

[0038] The judgment circuit 61 judges whether or not the peak frequency detected by the peak frequency detection circuit 70 is included in a reference frequency range. The reference frequency range is a frequency range determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproduction device 3. In this embodiment, the judgment circuit 61 acquires a temperature signal output from the temperature sensor 80 as temperature information, and calculates the reference frequency range based on the acquired temperature signal and table information stored in the memory 62. The judgment circuit 61 further judges whether or not the peak voltage detected by the peak frequency detection circuit 70 is included in a reference voltage range. The reference voltage range is a voltage range determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproduction device 3. The judgment circuit 61 calculates the reference frequency range based on the temperature signal output from the temperature sensor 80. The determination circuit 61 calculates a reference voltage range based on the intensity signal and table information stored in the memory 62. Furthermore, in this embodiment, the determination circuit 61 determines the state of the sound reproducing device 3, such as the presence or absence of a malfunction of the sound reproducing device 3, based on the determination result of whether or not the peak frequency is included in the reference frequency range and the determination result of whether or not the peak voltage is included in the reference voltage range. Details of the processing of the determination circuit 61 will be described later.

[0039] The temperature sensor 80 detects temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. In Fig. 1, the temperature sensor 80 is built into the semiconductor device 1 and directly detects the temperature of the semiconductor device 1, but since the temperatures of the semiconductor device 1 and the sound reproduction device 3 change similarly depending on the temperatures around the semiconductor device 1 and the sound reproduction device 3, the temperature sensor 80 indirectly detects the temperature of the sound reproduction device 3. However, the temperature sensor 80 may be provided outside the semiconductor device 1 and in the vicinity of the sound reproduction device 3 in order to directly detect the temperature of the sound reproduction device 3.

[0040] The switch 81 switches between electrically connecting and disconnecting the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 81 electrically disconnects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0041] Similarly, the switch 82 switches between electrically connecting or disconnecting the output terminal 92 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 82 electrically disconnects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 92 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0042] In this way, the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91, 92 by the switches 81, 82 in the normal operation mode, and is electrically connected to the output terminals 91, 92 in the inspection mode and calibration mode to measure the potential difference between the output terminals 91 and 92 and detect the peak frequency and peak voltage.

[0043] When the communication interface circuit 10 receives a command to read out information on the determination result by the determination circuit 61 from the micro control unit 2, it acquires the information on the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 recognizes the state of the sound reproducing device 3 based on the information on the determination result, and can perform various processes according to the state of the sound reproducing device 3.

[0044] 1-1-2.Determining the status of the sound playback device 6 and 7 are diagrams showing configuration examples of the class-D amplifiers 51P and 51N, the peak frequency detection circuit 70, and the peripheral circuits thereof. Fig. 6 shows the configuration in the normal operation mode, and Fig. 7 shows the configuration in the inspection mode and calibration.

[0045] As shown in FIGS. 6 and 7, the class-D amplifier 51P has a plurality of inverter circuits 201-1 to 201-n, and the class-D amplifier 51N has a plurality of inverter circuits 202-1 to 202-n, where n is an integer of 2 or more and may be, for example, about 10 to 100. Each of the inverter circuits 201-1 to 201-n is configured with a pair of a PMOS transistor and an NMOS transistor, and an output terminal, which is a node where the drain of the PMOS transistor and the drain of the NMOS transistor are connected, is connected to the output terminal 91. Similarly, each of the inverter circuits 202-1 to 202-n is configured with a pair of a PMOS transistor and an NMOS transistor, and an output terminal which is a node where the drain of the PMOS transistor and the drain of the NMOS transistor are connected is connected to the output terminal 92.

[0046] 6, in the normal operation mode, a modulation signal DOP is input to each input terminal of the inverter circuits 201-1 to 201-n of the class-D amplifier 51P via a switch 41, and a modulation signal DON is input to each input terminal of the inverter circuits 202-1 to 202-n of the class-D amplifier 51N via a switch 42. That is, in the normal operation mode, the inverter circuits 201-1 to 201-n of the class-D amplifier 51P are connected in parallel between the modulation circuit 30 and the output terminal 91 of the semiconductor device 1, and the inverter circuits 202-1 to 202-n of the class-D amplifier 51N are connected in parallel between the modulation circuit 30 and the output terminal 92 of the semiconductor device 1. As a result, the on-resistance R onP is 1 / n of the on-resistance of the inverter circuit 201-1, and the on-resistance R onN is 1 / n of the on-resistance of the inverter circuit 202-1.

[0047] The amplifier circuit 50 amplifies the modulated signal DOP to output an amplified signal DOXP to an output terminal 91, and amplifies the modulated signal DON to output an amplified signal DOXN to an output terminal 92. The output terminals 91 and 92 are respectively connected to terminals P1 and P2 of the sound reproducing device 3. An impedance R between the terminals P1 and P2 is sp is, for example, 4Ω to 128Ω, and in normal operation mode, the on-resistance R onP and the on-resistance R of the Class D amplifier 51N onN is the impedance R of the sound reproduction device 3 sp It is about 1 / 10 to 1 / 100 of that.

[0048] Furthermore, as shown in FIG. 6, in the normal operation mode, the switches 81 and 82 are non-conductive, and the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 of the semiconductor device 1.

[0049] On the other hand, as shown in Fig. 7, in the inspection mode and the calibration mode, the modulated signal TP is input to the input terminals of some of the inverter circuits 201-1 to 201-n included in the class-D amplifier 51P via the switch 41, and the output terminals of the other inverter circuits 201-1 to 201-n become high impedance. For example, in the inspection mode and the calibration mode, the modulated signal TP is input to the input terminal of the inverter circuit 201-1, and the output terminals of the inverter circuits 201-2 to 201-n become high impedance. Similarly, the modulated signal TN is input to the input terminals of some of the inverter circuits 202-1 to 202-n included in the class-D amplifier 51N via the switch 42, and the output terminals of the other inverter circuits 202-1 to 202-n become high impedance. For example, in the test mode and the calibration mode, the modulated signal TN is input to the input terminal of the inverter circuit 202-1, and the output terminals of the inverter circuits 202-2 to 202-n are set to high impedance. onPand the on-resistance R of the Class D amplifier 51N onN is the impedance R sp It is about the same.

[0050] As shown in FIG. 7, in the inspection mode and the calibration mode, the switches 81 and 82 are conductive, and the peak frequency detection circuit 70 is electrically connected to the output terminals 91 and 92 of the semiconductor device 1.

[0051] The peak frequency detection circuit 70 includes a differential low-pass filter 71 , an A / D conversion circuit 72 , and a peak time measurement circuit 73 .

[0052] The differential low-pass filter 71, in the inspection mode and the calibration mode, The voltages of the output terminals 91 and 92 are inputted via the switches 81 and 82. That is, the differential low-pass filter 71 receives the amplified signals DOXP and DOXN, reduces high-frequency noise components superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' according to the potential difference between the amplified signals DOXP and DOXN. The cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the test signal generation circuit 60 changes the frequency of the test signal. For example, when the test signal generation circuit 60 changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz, the cutoff frequency of the differential low-pass filter 71 is higher than 3 kHz. Since the cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components included in the frequency band are not attenuated by the differential low-pass filter 71.

[0053] Fig. 8 is a diagram showing an example of the configuration of the differential low-pass filter 71. As shown in Fig. 8, the differential low-pass filter 71 includes an operational amplifier 211, five resistors 212, 213, 214, 216, and 218, and three capacitors 215, 217, and 219.

[0054] In the inspection mode and the calibration mode, an amplified signal DOXP output to the output terminal 91 of the semiconductor device 1 is input to one end of the resistor 212. Furthermore, an amplified signal DOXN output to the output terminal 92 of the semiconductor device 1 is input to one end of the resistor 213. The other end of the resistor 212, one end of the resistor 214, and one end of the capacitor 215 are connected to the non-inverting input terminal of the operational amplifier 211. The other end of the resistor 213, one end of the resistor 216, one end of the capacitor 217, one end of the resistor 218, and one end of the capacitor 219 are connected to the inverting input terminal of the operational amplifier 211.

[0055] The other end of the resistor 214 and the other end of the capacitor 215 are connected to the output terminal of the operational amplifier 211. The other end of the resistor 216 and the other end of the capacitor 217 are grounded, and the other end of the resistor 218 and the other end of the capacitor 219 are supplied with a power supply voltage.

[0056] The differential low-pass filter 71 configured in this manner reduces high-frequency noise components superimposed on the amplified signals DOXP, DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP, DOXN, i.e., the potential difference between output terminals 91 and 92, from the output terminal of operational amplifier 211. When the power supply voltage is VDD and the ground voltage is 0V, if the potential difference between output terminals 91 and 92 in which the high-frequency noise components have been reduced is positive, voltage V' becomes higher than VDD×1 / 2, and when the potential difference between output terminals 91 and 92 in which the high-frequency noise components have been reduced is negative, voltage V' becomes lower than VDD×1 / 2.

[0057] The amplitude voltage V'(pp) of the voltage V' and the impedance R of the sound reproducing device 3 sp , the on-resistance R of the 51P class D amplifier onP and the on-resistance R of the Class D amplifier 51N onN The relationship between these is given by equation (1). From equation (1), the impedance R sp The larger the voltage V', the larger the amplitude of the impedance R sp When the voltage V' reaches its peak, the amplitude of the voltage V' is maximum.

[0058]

number

[0059] Returning to the explanation of FIG. 7, the A / D conversion circuit 72 converts the output voltage V' of the differential low-pass filter 71 into an m-bit digital signal and outputs it as m-bit data DT. m is 2 or more. This integer m is set to an appropriate value according to requirements such as the detection accuracy of the peak frequency and the size of the peak frequency detection circuit 70.

[0060] The peak time measurement circuit 73 measures the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 is maximum, based on the data DT which is the output signal of the A / D conversion circuit 72. Specifically, the peak time measurement circuit 73 measures the time when the data DT is maximum as the peak time. Furthermore, the peak time measurement circuit 73 measures the output voltage V' of the differential low-pass filter 71 at the peak time as the peak voltage. Specifically, the peak time measurement circuit 73 measures the maximum value of the data DT as the peak voltage.

[0061] As mentioned above, the impedance R of the sound reproduction device 3 sp When the impedance R of the sound reproduction device 3 is maximized, sp When the impedance R sp is the peak impedance R peak When the frequency of the test signal changes sequentially at a predetermined timing, the impedance R of the sound reproducing device 3 can be calculated from the peak time measured by the peak time measuring circuit 73. sp is the peak impedance R peakThus, in the inspection mode and the calibration mode, the peak frequency detection circuit 70 detects the peak frequency by measuring the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 is maximum. In addition, in the inspection mode and the calibration mode, the peak frequency detection circuit 70 further detects a peak voltage, which is a voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency.

[0062] Hereinafter, the peak frequency detected by the peak frequency detection circuit 70 in the inspection mode is referred to as f peak The peak frequency detected by the peak frequency detection circuit 70 in the calibration mode is F peak Similarly, the peak voltage detected by the peak frequency detection circuit 70 in the inspection mode is expressed as v peak The peak voltage detected by the peak frequency detection circuit 70 in the calibration mode is V peak This is explained as follows.

[0063] Figure 9 shows the test signal and peak frequency f peak and peak voltage v peak 9 is a diagram showing an example of the relationship between the test signal and the amplitude of the test signal. In the example of FIG. 9, the test signal generating circuit 60 continuously changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz while maintaining the amplitude of the test signal at a constant voltage V1. Then, when the sound reproducing device 3 is normal, the peak frequency f peak The output voltage V' of the differential low-pass filter 71 is the peak voltage v peak On the other hand, when the sound reproducing device 3 breaks down, the peak frequency f peak and peak voltage v peak Therefore, the determination circuit 61 determines the peak frequency f peak and peak voltage v peakBased on this, the state of the sound reproducing device 3 can be determined. Also, as shown in FIG. 9, when a disconnection fault occurs between the semiconductor device 1 and the sound reproducing device 3, the output voltage V' of the differential low-pass filter 71 is fixed to the power supply voltage. Therefore, the normal peak voltage v peak A predetermined voltage that is higher than the power supply voltage of the differential low-pass filter 71 and lower than the power supply voltage of the differential low-pass filter 71 is set as V err Then, the determination circuit 61 determines whether the output voltage V' of the differential low-pass filter 71 is equal to or smaller than the voltage V err If the data DT is higher than the voltage V err If the digital value is greater than the digital value corresponding to, it can be determined that a wire breakage has occurred.

[0064] As shown in Figure 10, the peak impedance R peak and peak frequency f peak changes with temperature. Impedance R sp is larger as the temperature of the sound reproducing device 3 is higher, and is smaller as the temperature of the sound reproducing device 3 is lower. For example, if the temperature range in which the operation of the sound reproducing device 3 is guaranteed is −40° C. to 80° C., the peak impedance R peak_High is the peak impedance R at normal temperature such as 25℃ peak_Nor Yo In addition, the peak impedance R peak_Low is the peak impedance R at normal temperature such as 25℃ peak_Nor As shown in Figure 10, the peak frequency f peak is lower as the temperature of the sound reproducing device 3 is higher, and is higher as the temperature of the sound reproducing device 3 is lower. Therefore, the peak frequency f peak_High is the peak frequency f at normal temperature such as 25°C peak_Nor Also, the peak frequency f peak_Low is the peak frequency f at normal temperature such as 25°C peak_Nor Higher than.

[0065] Peak Impedance R peak and peak frequency f peak11, the waveform of the output voltage V' of the differential low-pass filter 71 also changes with temperature. Therefore, the determination circuit 61 calculates a reference frequency range according to temperature based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62, and determines the reference frequency range according to the peak frequency f detected by the peak frequency detection circuit 70. peak The determination circuit 61 also calculates a reference voltage range according to temperature based on the temperature signal output from the temperature sensor 80 and table information stored in the memory 62, and determines whether the peak voltage v detected by the peak frequency detection circuit 70 is within the reference frequency range. peak is included in the reference voltage range.

[0066] In the calibration mode, the test signal and peak impedance R peak and peak frequency F peak and peak voltage V peak The relationship between is the same as in FIG. 9, FIG. 10, and FIG. 11, and therefore illustration and description thereof will be omitted.

[0067] 1-1-3. Calibration mode procedure In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the calibration mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the calibration mode. Then, the inspection circuit 110 executes a predetermined process in the calibration mode. In this embodiment, the semiconductor device 1 and the sound reproducing device 3 are housed in a thermostatic chamber, and the inspection circuit 110 executes the predetermined process in synchronization with the thermostatic chamber switching to a plurality of temperatures.

[0068] FIG. 12 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode.

[0069] First, in step S1, the determination circuit 61 determines whether or not table information should be created. For example, the determination circuit 61 may determine whether or not table information is stored in the memory 62, and determine that table information should be created if the table information is not stored. Also, for example, the determination circuit 61 may determine that table information should be created if the communication interface circuit 10 receives a command from the microcontroller instructing the creation of table information.

[0070] When the determination circuit 61 determines in step S1 that table information should be created, it waits until a predetermined temperature is reached in step S2. For example, the temperature of the thermostatic chamber is set to a predetermined temperature, and the determination circuit 61 detects the temperature T based on the temperature signal output from the temperature sensor 80, and determines whether the temperature has reached the predetermined temperature based on the acquired temperature T.

[0071] Next, in step S3, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept, and in step S4, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak , and obtain the temperature T.

[0072] Next, in step S5, the determination circuit 61 determines the peak frequency F pea k , peak voltage V peak , the temperature T is stored in the volatile memory of the memory 62.

[0073] Next, in step S6, the determination circuit 61 determines the peak frequency F at all the required temperatures. peak , peak voltage V peak If the temperature T has not been acquired, the process waits until the next temperature is acquired in step S7.

[0074] Then, the determination circuit 61 determines the peak frequency F at all the required temperatures. peak , peak voltage V peakThe processes in steps S3 to S7 are repeated until the temperature T is acquired. In this way, the determination circuit 61 determines the peak frequency F at a low temperature such as -40°C. peak_Low , peak voltage V peak_Low ,Temperature T Low , the peak frequency F at normal temperature such as 25°C peak_Nor , peak voltage V peak_Nor ,Temperature T Nor , Peak frequency F at high temperatures such as 80°C peak_High , peak voltage V peak_High ,Temperature T High is acquired and stored in the volatile memory of the memory 62.

[0075] Next, in step S8, the determination circuit 61 determines whether the plurality of peak frequencies F peak , peak voltage V peak ,T,T and peak frequency F peak , peak voltage V peak For example, the determination circuit 61 creates table information that associates the temperature T Low and peak frequency F peak_Low , peak voltage V peak_Low and the temperature T at room temperature such as 25°C. Nor and peak frequency F peak_Nor , peak voltage V peak_Nor and the temperature T at high temperatures such as 80°C. High and peak frequency F peak_High , peak voltage V peak_High Create table information that associates the above with the above.

[0076] When the determination circuit 61 determines in step S1 that the table information is not to be created, the process of steps S2 to S8 is not performed.

[0077] Next, in step S9, the determination circuit 61 sets α and β, and ends the process in the calibration mode. α is a constant for determining the aforementioned reference frequency range in consideration of the characteristic variation of the sound reproduction device 3, and β is a constant for determining the aforementioned reference voltage range in consideration of the characteristic variation of the sound reproduction device 3. For example, the constants α and β are stored in a non-volatile memory of the memory 62, and the determination circuit 61 reads out the constants α and β from the non-volatile memory and sets them in a predetermined internal register.

[0078] 1-1-4. Inspection mode processing procedure In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the inspection mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the inspection mode. Also, when the supply of power supply voltage to the semiconductor device 1 starts, the operation mode of the semiconductor device 1 may be automatically switched to the inspection mode. Then, the inspection circuit 110 executes a predetermined process in the inspection mode.

[0079] FIG. 13 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the inspection mode.

[0080] First, in step S11, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept. In step S12, the determination circuit 61 determines the peak frequency f peak , peak voltage v peak , and obtain the temperature t.

[0081] Next, in step S13, the determination circuit 61 determines the peak frequency F' corresponding to the temperature t obtained in step S12 from the table information stored in the nonvolatile memory of the memory 62. peak , peak voltage V' peak FIG. 14 shows the peak frequency F' peak , peak voltage V' peak 14 is a diagram showing an example of a method for calculating a temperature T Low and peak frequency Fpeak_Low , peak voltage V peak_Low and the temperature T at room temperature such as 25°C. Nor and peak frequency F peak_Nor , peak voltage V peak_Nor and the temperature T at high temperatures such as 80°C. High and peak frequency F peak_High , peak voltage V peak_High The temperature t is stored in a table that corresponds to the temperature T High and temperature T Nor Since the temperature is between the peak frequency F peak_High and peak frequency F peak_Nor and the peak frequency F' is calculated by linear interpolation. peak Similarly, the determination circuit 61 calculates, for example, the peak voltage V peak_High and peak voltage V peak_Nor and the peak voltage V' is calculated by linear interpolation. peak Calculate the temperature t as temperature T Nor and temperature T Low If the temperature is between, for example, the peak frequency F peak_Nor and peak frequency F peak_Low and the peak frequency F' is calculated by linear interpolation. peak Calculate the peak voltage V peak_Nor and peak voltage V peak_Low and the peak voltage V' is calculated by linear interpolation. peak Calculate.

[0082] Next, in step S14, the determination circuit 61 determines the peak voltage v peak is the voltage V err Determine whether the peak voltage v peak is the voltage V err If it is higher, in step S15, the decision circuit 61 decides that there is a failure, and ends the process in the inspection mode.

[0083] On the other hand, the peak voltage v peak is the voltage V err In the following cases, in step S16, the determination circuit 61 determines whether the peak frequency fpeak But F' peak -α and F' peak Determine whether the peak frequency f is included in the reference frequency range, which is a range lower than +α. peak is not included in the reference frequency range, in step S18, the determination circuit 61 determines that there is a possibility of a malfunction, and ends the processing in the inspection mode.

[0084] On the other hand, the peak frequency f peak is included in the reference frequency range, in step S17, the determination circuit 61 determines whether the peak voltage v obtained in step S12 is peak But V' peak -β is higher than V' peak +β is included in the reference voltage range. peak If the peak voltage v is not included in the reference voltage range, in step S18, the determination circuit 61 determines that there is a possibility of a malfunction, and ends the process in the inspection mode. peak If is included in the reference voltage range, in step S19, the determination circuit 61 determines that the voltage is normal, and ends the processing in the inspection mode.

[0085] The terminal P1 of the sound reproducing device 3 is an example of a "first terminal", and the terminal P2 of the sound reproducing device 3 is an example of a "second terminal". The output terminal 91 of the semiconductor device 1 is an example of a "first output terminal", and the output terminal 92 of the semiconductor device 1 is an example of a "second output terminal". The modulated signal DOP is an example of a "first modulated signal", and the modulated signal DON is an example of a "second modulated signal". The modulated signal TP is an example of a "third modulated signal", and the modulated signal TN is an example of a "fourth modulated signal". The amplified signal DOXP obtained by amplifying the modulated signal DOP is an example of a "first amplified signal", and the amplified signal DOXN obtained by amplifying the modulated signal DON is an example of a "second amplified signal". The amplified signal DOXP obtained by amplifying the modulated signal TP is an example of a "third amplified signal", and the amplified signal DOXN obtained by amplifying the modulated signal TN is an example of a "fourth amplified signal". The normal operation mode is an example of a "first operation mode", and the inspection mode is an example of a "second operation mode".

[0086] The semiconductor device 1 of the first embodiment has a structure capable of outputting sound from one sound reproducing device 3. However, the configuration may be such that a plurality of sound reproduction devices can output sound.

[0087] 1-1-5.Effects As described above, according to the semiconductor device 1 of the first embodiment, in the normal operation mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by amplifying the modulated signals DOP and DON based on the sound source signal DI to the output terminals 91 and 92, respectively, so that the sound reproducing device 3 can reproduce sound. On the other hand, in the test mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by amplifying the modulated signals TP and TN based on the test signal to the output terminals 91 and 92, respectively, so that the peak frequency detection circuit 70 measures the potential difference between the output terminals 91 and 92 and detects the peak frequency f at which the impedance of the sound reproducing device 3 becomes a peak. peak Then, the determination circuit 61 detects the peak frequency f peak Determine whether the peak frequency f is within the reference frequency range. peak is not included in the reference frequency range, it can be determined that there is a possibility that the sound reproducing device 3 is malfunctioning. This reference frequency range is determined based on the frequency band of the test signal and the temperature information of the sound reproducing device 3, and therefore changes appropriately according to the temperature of the sound reproducing device 3. Specifically, the determination circuit 61 can calculate an appropriate reference frequency range according to the temperature of the sound reproducing device 3 based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62. Therefore, according to the semiconductor device 1 of the first embodiment, the accuracy of the malfunction determination of the sound reproducing device 3 can be maintained even if the temperature changes.

[0088] In the semiconductor device 1 of the first embodiment, the amplifier circuit 50 generates the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce sound in the normal operation mode, and generates the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce sound in the test mode. peakTherefore, according to the semiconductor device 1 of the first embodiment, the signals required to detect a failure in the sound reproducing device 3 can be generated with a small-scale circuit.

[0089] In the semiconductor device 1 of the first embodiment, the determination circuit 61 determines the peak voltage v peak It is further determined whether the peak voltage v peak is not included in the reference voltage range, it can be determined that the sound reproducing device 3 may be broken. This reference voltage range is determined based on the frequency band of the test signal and the temperature information of the sound reproducing device 3, and therefore changes appropriately according to the temperature of the sound reproducing device 3. Therefore, the determination circuit 61 determines whether the peak frequency f peak Even if the reference frequency range includes the peak voltage v peak is not within the reference voltage range, it can be determined that the sound reproducing device 3 may be malfunctioning. Therefore, according to the semiconductor device 1 of the first embodiment, the risk of erroneously determining that the sound reproducing device 3 is normal is reduced when there is a possibility that the sound reproducing device 3 may be malfunctioning.

[0090] Furthermore, according to the semiconductor device 1 of the first embodiment, the impedance R sp When the potential difference between the output terminal 91 and the output terminal 92 reaches a peak, the potential difference between the output terminal 91 and the output terminal 92 also reaches a peak. Therefore, the peak frequency detection circuit 70 measures the time when the potential difference between the output terminal 91 and the output terminal 92 reaches a maximum, thereby detecting the peak frequency f peak can be detected.

[0091] Furthermore, according to the semiconductor device 1 of the first embodiment, in the peak frequency detection circuit 70, the differential low-pass filter 71 reduces the high-frequency noise components superimposed on the amplified signals DOXP, DOXN by modulating the test signal, the A / D conversion circuit 72 converts the output voltage of the differential low-pass filter 71 into data DT, and the peak time measurement circuit 73 can easily perform high-precision measurements.

[0092] Furthermore, according to the semiconductor device 1 of the first embodiment, the impedance R sp Since the voltage of the amplified signals DOXP and DOXN does not depend on the voltage of the amplified signals DOXP and DOXN, The reproduction device 3 reproduces a minute sound that is difficult for the human ear to hear, while peak and peak voltage v peak Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to make the user less aware that the semiconductor device 1 is operating in the inspection mode.

[0093] 1-2. Second embodiment Hereinafter, for the semiconductor device 1 of the second embodiment, the same reference numerals will be used for configurations similar to those of the first embodiment, and explanations of the same parts as those of the first embodiment will be omitted or simplified, with the main focus being on the differences from the first embodiment.

[0094] The configuration of the semiconductor device 1 of the second embodiment is omitted because it is the same as that of Fig. 1. In the semiconductor device 1 of the second embodiment, the processing of the determination circuit 61 is different from that of the first embodiment.

[0095] In the second embodiment, the non-volatile memory of the memory 62 stores the temperature T and the peak frequency F peak The non-volatile memory of the memory 62 stores information on the relationship between the temperature T and the peak voltage V peak The information on the relational expression is stored.

[0096] Temperature T and peak frequency F peak The relational expression may be an n-th degree polynomial with temperature T as a variable, as shown in Equation (2), where n is a predetermined integer equal to or greater than 2. For example, peak When the relationship between the peak frequency F and the frequency is expressed by three points shown in FIG. 15, as shown by the dashed line in FIG. peak The square root of is approximated by a quadratic function of temperature T. Therefore, the relationship between temperature T and peak frequency F peak The relational expression is a fourth-order polynomial with temperature T as a variable.

[0097]

number

[0098] As shown in equation (3), the temperature T and peak voltage V peak The relational expression may be an m-th degree polynomial with temperature T as a variable, where m is a predetermined integer equal to or greater than 2. For example, peak When the relationship between the peak impedance R and the load resistance R is expressed by the three points shown in FIG. 16, as shown by the dashed line in FIG. peak is approximated by a linear equation of temperature T. Peak voltage V peak is the peak impedance R peak is proportional to the temperature T and the peak voltage V peak The relational expression is a first-order polynomial with temperature T as a variable.

[0099]

number

[0100] The determination circuit 61, like the first embodiment, detects the peak frequency f peak is included in the reference frequency range. As in the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproducing device 3.

[0101] In the second embodiment, the determination circuit 61 obtains a temperature signal output from the temperature sensor 80 as temperature information, and compares the obtained temperature signal with the temperature T and peak frequency F stored in the memory 62. peak The reference frequency range is calculated based on the information of the relational expression (2). The determination circuit 61 also calculates the reference frequency range based on the temperature signal output from the temperature sensor 80 and the temperature T and peak voltage V peak Based on the information in relation to equation (3), the reference voltage Calculate the pressure range.

[0102] FIG. 17 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode in the second embodiment.

[0103] First, in step S101, the judgment circuit 61 judges whether or not the relational expressions (2) and (3) should be created. For example, the judgment circuit 61 may judge whether or not information on the relational expressions (2) and (3) is stored in the memory 62, and may judge that the relational expressions (2) and (3) should be created if the information on the relational expressions (2) and (3) is not stored. Also, for example, the judgment circuit 61 may judge that the relational expressions (2) and (3) should be created if the communication interface circuit 10 receives a command from the microcontroller instructing the creation of the relational expressions (2) and (3).

[0104] When the determination circuit 61 determines in step S101 that the relational expressions (2) and (3) should be created, the determination circuit 61 waits until a predetermined temperature is reached in step S102.

[0105] Next, in step S103, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept, and in step S104, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak , and obtain the temperature T.

[0106] Next, in step S105, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak , the temperature T is stored in the volatile memory of the memory 62.

[0107] Next, in step S106, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak If the temperature T has not been acquired, the process waits until the next temperature is acquired in step S107.

[0108] Then, the determination circuit 61 determines the peak frequency F at all the required temperatures. peak , peak voltage Vpeak The processes in steps S103 to S107 are repeated until the temperature T is acquired. In this way, the determination circuit 61 determines the peak frequency F at a low temperature such as -40°C. peak_Low , peak voltage V peak_Low ,Temperature T Low , the peak frequency F at normal temperature such as 25°C peak_Nor , peak voltage V peak_Nor ,Temperature T Nor , Peak frequency F at high temperatures such as 80°C peak_High , peak voltage V peak_High ,Temperature T High is acquired and stored in the volatile memory of the memory 62.

[0109] Next, in step S108, the determination circuit 61 determines whether the plurality of peak frequencies F peak , peak voltage V peak ,T,T and peak frequency F peak , peak voltage V peak The information on the relational expressions (2) and (3) is stored in the non-volatile memory of the memory 62. The information on the relational expression (2) is, for example, the coefficient a n Similarly, the information in relation (3) may be, for example, the coefficient b n It may also have a value of .about.b0.

[0110] When the decision circuit 61 decides in step S101 that the table information is not to be created, the process of steps S102 to S108 is not performed.

[0111] Next, in step S109, the determination circuit 61 sets α and β, and ends the process in the calibration mode. α is a constant for determining the aforementioned reference frequency range in consideration of the characteristic variation of the sound reproduction device 3, and β is a constant for determining the aforementioned reference voltage range in consideration of the characteristic variation of the sound reproduction device 3. For example, the constants α and β are set as The constants α and β are stored in a non-volatile memory, and the determination circuit 61 reads the constants α and β from the non-volatile memory and sets them in a predetermined internal register.

[0112] FIG. 18 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the inspection mode in the second embodiment.

[0113] First, in step S111, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept. In step S112, the determination circuit 61 determines the peak frequency f peak , peak voltage v peak , and obtain the temperature t.

[0114] Next, in step S113, the determination circuit 61 determines the peak frequency F' corresponding to the temperature t obtained in step S112 from the relational expressions (2) and (3) stored in the nonvolatile memory of the memory 62. peak , peak voltage V' peak That is, the determination circuit 61 substitutes the temperature t for the temperature T, which is a variable in the relational expression (2), to calculate the peak frequency F peak Calculate the peak frequency F peak The peak frequency F' peak Similarly, the determination circuit 61 substitutes the temperature t for the variable T in the relational expression (3) to obtain the peak voltage V peak Calculate the peak voltage V peak Peak voltage V' peak Let us assume that.

[0115] Next, in step S114, the determination circuit 61 determines the peak voltage v peak is the voltage V err Determine whether the peak voltage v peak is the voltage V err If it is higher, in step S115, the determination circuit 61 determines that there is a failure, and ends the process in the inspection mode.

[0116] On the other hand, the peak voltage v peak is the voltage V err In the following cases, in step S116, the determination circuit 61 determines whether the peak frequency f peak But F' peak-α and F' peak Determine whether the peak frequency f is included in the reference frequency range, which is a range lower than +α. peak is not included in the reference frequency range, in step S118, the determination circuit 61 determines that there is a possibility of a malfunction, and ends the processing in the inspection mode.

[0117] On the other hand, the peak frequency f peak is within the reference frequency range, in step S117, the determination circuit 61 determines whether the peak voltage v obtained in step S112 is within the reference frequency range. peak But V' peak -β is higher than V' peak +β is included in the reference voltage range. peak If the peak voltage v is not included in the reference voltage range, in step S118, the determination circuit 61 determines that there is a possibility of a malfunction, and ends the process in the inspection mode. peak If it is within the reference voltage range, in step S119, the determination circuit 61 determines that it is normal, and ends the processing in the inspection mode.

[0118] Other configurations and functions of the semiconductor device 1 of the second embodiment are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0119] Although the semiconductor device 1 of the second embodiment is configured to be capable of causing one sound reproducing device 3 to output sound, it may be configured to be capable of causing a plurality of sound reproducing devices to output sound.

[0120] According to the semiconductor device 1 of the second embodiment described above, the determination circuit 61 can calculate an appropriate reference frequency range according to the temperature of the sound reproducing device 3, based on the temperature signal output from the temperature sensor 80 and the information of the relational expression stored in the memory 62. Therefore, according to the semiconductor device 1 of the second embodiment, the accuracy of the failure determination of the sound reproducing device 3 can be maintained even if the temperature changes.

[0121] Additionally, the semiconductor device 1 of the second embodiment provides the same effects as the semiconductor device 1 of the first embodiment.

[0122] 1-3.Third embodiment Hereinafter, for the semiconductor device 1 of the third embodiment, configurations similar to those of the first or second embodiment are given the same symbols, explanations similar to those of the first or second embodiment are omitted or simplified, and mainly the differences from the first and second embodiments will be described.

[0123] The configuration of the semiconductor device 1 of the third embodiment is omitted because it is the same as that of Fig. 1. In the semiconductor device 1 of the third embodiment, the processing of the determination circuit 61 is different from those of the first and second embodiments.

[0124] In the third embodiment, information on a reference frequency block including a peak frequency corresponding to a reference temperature is stored in the non-volatile memory of the memory 62, among a plurality of frequency blocks into which a predetermined frequency range is divided. The reference temperature is, for example, a normal temperature such as 25°C.

[0125] FIG. 19 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block. In the example of FIG. 19, the predetermined frequency range is from 10 Hz to 10,000 Hz, and this frequency range is divided into six frequency blocks F1 to F6. Frequency block F1 is in the range of 10 Hz to 30 Hz. Frequency block F2 is in the range of 31 Hz to 100 Hz. Frequency block F3 is in the range of 101 Hz to 300 Hz. Frequency block F4 is in the range of 301 Hz to 1000 Hz. Frequency block F5 is in the range of 1001 Hz to 3000 Hz. Frequency block F6 is in the range of 3001 Hz to 10,000 Hz. If the temperature range in which the operation of the sound reproducing device 3 is guaranteed is −40° C. to 80° C., the reference temperature is a normal temperature such as 25° C., and the peak frequency F at normal temperature is peak_Nor In the example of FIG. 19, the frequency block F3 including the peak frequency F peak_Nor Since is close to the lower limit frequency of frequency block F3, the peak frequency Fpeak_High is included in the frequency block F2 before the frequency block F3, and is the peak frequency F at a low temperature such as -40°C. peak_Low is included in frequency block F3. Conversely, the peak frequency F peak_Nor If is close to the upper limit frequency of frequency block F3, the peak frequency F at high temperatures such as 80°C peak_High is included in frequency block F3, and is the peak frequency F at low temperatures such as -40°C. peak_Low is included in the frequency block F4 following the frequency block F3. In other words, if the state of the sound reproducing device 3 is normal, the peak frequency f peak is included in the frequency range consisting of the reference frequency block and the frequency blocks before and after the reference frequency block, regardless of the temperature t.

[0126] The determination circuit 61, like the first embodiment, detects the peak frequency f peak is included in the reference frequency range. As in the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproduction device 3. However, in the third embodiment, the temperature information is information on the temperature range in which the operation of the sound reproduction device 3 is guaranteed, and the reference frequency range is a frequency range consisting of a reference frequency block and frequency blocks before and after the reference frequency block. This reference frequency range is determined based on the peak frequency f corresponding to the temperature range in which the operation of the sound reproduction device 3 is guaranteed. peak Includes the range.

[0127] FIG. 20 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode in the third embodiment.

[0128] First, in step S201, the decision circuit 61 determines whether or not the reference frequency block should be calculated. For example, the determination circuit 61 may determine whether or not information on a reference frequency block is stored in the memory 62, and may determine that a reference frequency block should be calculated if information on a reference frequency block is not stored. Also, for example, the determination circuit 61 may determine that a reference frequency block should be calculated if the communication interface circuit 10 receives a command from the microcontroller instructing calculation of a reference frequency block.

[0129] When the decision circuit 61 decides in step S201 that the reference frequency block should be calculated, the decision circuit 61 waits until a predetermined temperature is reached in step S202.

[0130] Next, in step S203, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept, and in step S204, the determination circuit 61 determines the peak frequency F peak Get the.

[0131] Next, in step S205, the determination circuit 61 determines the peak frequency F obtained in step S204 from among the multiple frequency blocks into which the predetermined frequency range is divided. peak The frequency block including this is determined as the reference frequency block, and information about the reference frequency block is stored in the non-volatile memory of the memory 62, and the process in the calibration mode is terminated.

[0132] FIG. 21 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the inspection mode in the third embodiment.

[0133] First, in step S211, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept. In step S212, the determination circuit 61 determines the peak frequency f peak , peak voltage v peak Get the.

[0134] Next, in step S213, the determination circuit 61 determines whether the peak voltage v peak is the voltage V errDetermine whether the peak voltage v peak is the voltage V err If it is higher, in step S214, the decision circuit 61 decides that there is a failure, and ends the process in the inspection mode.

[0135] On the other hand, the peak voltage v peak is the voltage V err In the following cases, in step S215, the determination circuit 61 determines whether the peak frequency f peak It is judged whether the peak frequency f is included in the reference frequency range consisting of the reference frequency block or the frequency blocks before and after the reference frequency block. peak is not included in the reference frequency range, in step S216, the determination circuit 61 determines that there is a possibility of a malfunction, and ends the processing in the inspection mode.

[0136] On the other hand, the peak frequency f peak If is included in the reference frequency range, in step S217, the determination circuit 61 determines that it is normal, and ends the processing in the inspection mode.

[0137] Other configurations and functions of the semiconductor device 1 of the third embodiment are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0138] Although the semiconductor device 1 of the third embodiment is configured to be capable of causing one sound reproducing device 3 to output sound, it may be configured to be capable of causing a plurality of sound reproducing devices to output sound.

[0139] In the semiconductor device 1 of the third embodiment described above, the reference frequency range is a frequency range including a peak frequency range corresponding to a temperature range in which the operation of the sound reproducing device 3 is guaranteed, which is made up of a reference frequency block including a peak frequency corresponding to the reference temperature and frequency blocks before and after the reference frequency block. Therefore, even if the peak frequency changes due to a change in the temperature of the sound reproducing device 3, the change is not detected. The peak frequency f peakis included in the reference frequency range. Therefore, according to the semiconductor device 1 of the third embodiment, the risk of erroneously determining that the sound reproducing device 3 is malfunctioning when it is actually normal is reduced.

[0140] In addition, the semiconductor device 1 of the third embodiment has the same effects as the semiconductor device 1 of the first embodiment.

[0141] 1-4. Fourth embodiment Hereinafter, for the semiconductor device 1 of the fourth embodiment, configurations similar to those of any of the first to third embodiments are given the same symbols, descriptions similar to those of any of the first to third embodiments are omitted or simplified, and mainly the contents different from any of the first to third embodiments are described.

[0142] In the fourth embodiment, the non-volatile memory of the memory 62 stores information on a reference frequency block, among a plurality of frequency blocks into which a predetermined frequency range is divided, that includes a peak frequency range corresponding to a temperature range in which operation of the sound reproduction device 3 is guaranteed.

[0143] FIG. 22 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block. In the example of FIG. 22, the predetermined frequency range is from 10 Hz to 10,000 Hz, and this frequency range is divided into six frequency blocks F1 to F6. Frequency block F1 is in the range of 10 Hz to 30 Hz. Frequency block F2 is in the range of 31 Hz to 50 Hz. Frequency block F3 is in the range of 51 Hz to 300 Hz. Frequency block F4 is in the range of 301 Hz to 1000 Hz. Frequency block F5 is in the range of 1001 Hz to 3000 Hz. Frequency block F6 is in the range of 3001 Hz to 10,000 Hz. If the temperature range in which the operation of the sound reproducing device 3 is guaranteed is -40°C to 80°C, the peak frequency F at the maximum temperature of 80°C is 100 Hz to 10000 Hz. peak_High , the peak frequency F at room temperature (25°C) peak_Nor , the peak frequency F at the lowest temperature of -40°C peak_Loware all included in one frequency block F3. This frequency block F3 is the reference frequency block. In other words, if the state of the sound reproducing device 3 is normal, the peak frequency f peak is included in the reference frequency block regardless of the temperature t.

[0144] The determination circuit 61, like the first embodiment, detects the peak frequency f peak is included in the reference frequency range. As in the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproduction device 3. However, in the fourth embodiment, the temperature information is information on the temperature range in which the operation of the sound reproduction device 3 is guaranteed, and the reference frequency range is the frequency range of the reference frequency block. This reference frequency range is determined based on the peak frequency f corresponding to the temperature range in which the operation of the sound reproduction device 3 is guaranteed. peak Includes the range.

[0145] FIG. 23 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode in the fourth embodiment.

[0146] First, in step S301, the judgment circuit 61 judges whether or not the reference frequency block should be calculated. For example, the judgment circuit 61 may judge whether or not information on the reference frequency block is stored in the memory 62, and may judge that the reference frequency block should be calculated if the information on the reference frequency block is not stored. Also, for example, the judgment circuit 61 may judge that the reference frequency block should be calculated if the communication interface circuit 10 receives a command from the microcontroller instructing calculation of the reference frequency block.

[0147] When the decision circuit 61 decides in step S301 that the reference frequency block should be calculated, the decision circuit 61 waits until a predetermined temperature is reached in step S302.

[0148] Next, in step S303, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept, and in step S304, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak , and obtain the temperature T.

[0149] Next, in step S305, the determination circuit 61 determines the peak frequency F peak , peak voltage V peak , the temperature T is stored in the volatile memory of the memory 62.

[0150] Next, in step S306, the determination circuit 61 determines the peak frequency F at all the required temperatures. peak , peak voltage V peak If the temperature T has not been acquired, the process waits until the next temperature is acquired in step S307.

[0151] Then, the determination circuit 61 determines the peak frequency F at all the required temperatures. peak , peak voltage V peak The processes in steps S303 to S307 are repeated until the temperature T is acquired. In this way, the determination circuit 61 determines, for example, the peak frequency F at the lowest temperature of −40° C. peak_Low , peak voltage V peak_Low ,Temperature T Low , the peak frequency F at room temperature (25°C) peak_Nor , peak voltage V peak_Nor ,Temperature T Nor , the peak frequency F at the highest temperature of 80°C peak_High , peak voltage V peak_High ,Temperature T High is acquired and stored in the volatile memory of the memory 62.

[0152] Next, in step S308, the determination circuit 61 determines the peak frequency F at the maximum temperature stored in the volatile memory of the memory 62 in step S305. peak_High and the peak frequency at the lowest temperature F peak_Low is included in the same frequency block among a plurality of frequency blocks obtained by dividing a predetermined frequency range.

[0153] Peak frequency F peak_High and peak frequency F peak_Low are not included in the same frequency block, in step S309, the determination circuit 61 peak_High and peak frequency F peak_Low For example, as shown in FIG. 19, the peak frequency F peak_High is included in frequency block F2, and the peak frequency F peak_Low is included in frequency block F3, the frequency at the boundary between frequency block F2 and frequency block F3 is lowered to reduce the peak frequency F peak_High and peak frequency F peak_Low In this case, the lower limit frequency and the peak frequency F peak_High The difference between the upper limit frequency and the peak frequency F peak_Low It is preferable to perform the correction so that the difference between the

[0154] The determination circuit 61 detects the peak frequency F peak_High and peak frequency F peak_Low The processes in steps S302 to S309 are repeated until the frequency components are included in the same frequency block.

[0155] Then, the determination circuit 61 detects the peak frequency F peak_High and peak frequency F peak_Low are included in the same frequency block, in step S310, this frequency block is set as the reference frequency block, and information on the reference frequency block is stored in the non-volatile memory of the memory 62.

[0156] Finally, in step S311, the determination circuit 61 calculates the ratio B between the peak impedance and the steady-state impedance at room temperature, stores it in the memory 62, and ends the process in the calibration mode. spFor example, the determination circuit 61 determines the ratio B of the peak impedance to the steady-state impedance at room temperature as the peak voltage V peak_Nor and the minimum value of the output voltage V′ of the differential low-pass filter 71 is calculated.

[0157] FIG. 24 is a flow chart showing an example of a processing procedure of the inspection circuit 110 in the inspection mode in the fourth embodiment.

[0158] First, in step S321, the test signal generating circuit 60 starts outputting a test signal whose frequency has been swept. In step S322, the determination circuit 61 determines whether the peak voltage v peak and obtain the maximum value of voltage V' for each frequency block.

[0159] Next, in step S323, the determination circuit 61 calculates the ratio B' between the maximum impedance value and the steady-state impedance for each frequency block, and stores the ratio B' in the memory 62. For example, the determination circuit 61 calculates the ratio between the maximum voltage V' of each frequency block and the minimum voltage V' value in the entire frequency range as the ratio B' between the maximum impedance value and the steady-state impedance of each frequency block.

[0160] Next, in step S324, the determination circuit 61 determines the peak voltage v peak is the voltage V err Determine whether the peak voltage v peak is the voltage V err If it is higher, in step S325, the decision circuit 61 decides that there is a failure, and ends the process in the inspection mode.

[0161] On the other hand, the peak voltage v peak is the voltage V errIn the following cases, in step S326, the judgment circuit 61 judges whether or not the frequency block with the maximum ratio B' calculated in step S323 matches the reference frequency block. If the frequency block with the maximum ratio B' does not match the reference frequency block, in step S328, the judgment circuit 61 judges that there is a possibility of a failure, and ends the processing in the inspection mode.

[0162] On the other hand, if the frequency block with the maximum ratio B' coincides with the reference frequency block, in step S327, the judgment circuit 61 judges whether or not the maximum value of the ratio B' is included in a lower range greater than B-γ and smaller than B+γ, with respect to the ratio B stored in the memory 62. γ is a constant for determining the possible range of the ratio B' in consideration of the characteristic variation of the sound reproduction device 3. If the maximum value of the ratio B' is not included in the range, in step S328, the judgment circuit 61 judges that there is a possibility of a malfunction, and ends the processing in the inspection mode. On the other hand, if the maximum value of the ratio B' is included in the range, in step S329, the judgment circuit 61 judges that it is normal, and ends the processing in the inspection mode.

[0163] Other configurations and functions of the semiconductor device 1 of the fourth embodiment are similar to those of the first embodiment, and therefore description thereof will be omitted.

[0164] Although the semiconductor device 1 of the fourth embodiment is configured to be capable of causing one sound reproducing device 3 to output sound, it may be configured to be capable of causing a plurality of sound reproducing devices to output sound.

[0165] In the semiconductor device 1 of the fourth embodiment described above, the reference frequency range is the frequency range of the reference frequency block including the range of peak frequencies corresponding to the temperature range in which the operation of the sound reproduction device 3 is guaranteed. Therefore, even if the peak frequency changes due to a change in the temperature of the sound reproduction device 3, the detected peak frequency f peak is included in the reference frequency range. Therefore, According to the semiconductor device 1 of the fourth embodiment, the risk of erroneously determining that the sound reproducing device 3 is malfunctioning when it is actually normal is reduced.

[0166] In addition, the semiconductor device 1 of the fourth embodiment has the same effects as the semiconductor device 1 of the first embodiment.

[0167] Fifth embodiment Hereinafter, for the semiconductor device 1 of the fifth embodiment, configurations similar to those of any of the first to fourth embodiments are given the same symbols, descriptions similar to those of any of the first to fourth embodiments are omitted or simplified, and mainly the contents different from any of the first to fourth embodiments are described.

[0168] Fig. 25 is a diagram showing a configuration example of a semiconductor device according to the fifth embodiment. As shown in Fig. 25, the semiconductor device 1 according to the fifth embodiment is connected to a sound source reproducing circuit 100a and a sound reproducing device 3a. Specifically, the output terminal 95 of the semiconductor device 1 is connected to the input terminal 103 of the sound source reproducing circuit 100a, the input terminal 93 of the semiconductor device 1 is connected to the output terminal 101 of the sound source reproducing circuit 100a and the terminal P1a of the sound reproducing device 3a, and the input terminal 94 of the semiconductor device 1 is connected to the output terminal 102 of the sound source reproducing circuit 100a and the terminal P2a of the sound reproducing device 3a.

[0169] The semiconductor device 1 of the fifth embodiment includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 83, 84, 85, and an inspection circuit 110. The semiconductor device 1 may be a one-chip semiconductor integrated circuit device, or may be composed of semiconductor integrated circuit devices on multiple chips, or may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0170] When the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to a normal operation mode, an inspection mode, or a calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 83, 84, and 85 according to the operation mode. Also, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it as a sound source signal DIa to the input terminal 103 of the sound source reproduction circuit 100a via the switch 85 and the output terminal 95, and instructs the sound source reproduction circuit 100a to reproduce the sound source data 21-i by the sound reproduction device 3a. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. Also, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100a to stop reproduction. Furthermore, for example, when the communication interface circuit 10 receives various setting commands related to sound source reproduction, it performs various settings on the sound source reproduction circuit 100a.

[0171] The switch 85 outputs either a signal based on the sound source signal DIa or a test signal TST to the output terminal 95 in response to a control signal output from the communication interface circuit 10. Specifically, in the normal operation mode, the switch 85 outputs a signal based on the sound source signal DIa to the output terminal 95, and in the inspection mode or calibration mode, the switch 85 outputs the test signal TST to the output terminal 95. The signal based on the sound source signal DIa may be the sound source signal DIa itself, or may be a signal obtained by performing some processing on the sound source signal DIa.

[0172] The sound source reproduction circuit 100a converts the signal input from the input terminal 103 into amplified signals DOXPa and DOXNa, and outputs the amplified signals DOXPa and DOXNa to the output terminals 101 and 102, respectively. The signal input from the input terminal 103 is a signal based on the sound source signal DIa. When the signal input from the input terminal 103 is a test signal TST, the sound source reproduction circuit 100a converts the signal based on the sound source signal DIa into amplified signals DOXPa and DOXNa, which are sound signals, and outputs them to the output terminals 101 and 102, respectively. As a result, sounds corresponding to the amplified signals DOXPa and DOXNa are output from the sound reproduction device 3a. When the signal input from the input terminal 103 is a test signal TST, the test signal TST is converted into amplified signals DOXPa and DOXNa, and outputted to the output terminals 101 and 102, respectively.

[0173] For example, the sound reproducing device 3a may be a speaker or a buzzer. The sound output from the sound reproducing device 3a may be, for example, a voice that imitates a human voice when speaking, or may be various sounds such as a mechanical warning sound or sound effect.

[0174] 25, in this embodiment, the sound source reproducing circuit 100a includes a modulation circuit 30a and an amplifier circuit 50a. The sound source reproducing circuit 100a may be a one-chip semiconductor integrated circuit device, may be composed of semiconductor integrated circuit devices on multiple chips, or may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0175] The modulation circuit 30a modulates the signal input to the input terminal 103 and outputs the modulated signals DOPa and DONa. Specifically, the modulation circuit 30a includes a digital filter 31a, a sigma-delta modulation circuit 32a, and a pulse width modulation circuit 33a, and the digital filter 31a digitally filters the signal input to the input terminal 103 to produce a signal DFa, which the sigma-delta modulation circuit 32a sigma-delta modulates to output a sigma-delta modulated signal DSa, and the pulse width modulation circuit 33a further pulse-width modulates to output the modulated signals DOPa and DONa. When the signal input from the input terminal 103 is a signal based on the sound source signal DIa, the modulation circuit 30a modulates the signal based on the sound source signal DIa to output the modulated signals DOPa and DONa, and when the signal input from the input terminal 103 is a test signal TST, the modulation circuit 30a modulates the test signal TST to output the modulated signals DOPa and DONa. Note that the detailed processing of the digital filter 31a, the sigma-delta modulation circuit 32a, and the pulse-width modulation circuit 33a is similar to the processing of the digital filter 31, the sigma-delta modulation circuit 32, and the pulse-width modulation circuit 33 in any of the first to fourth embodiments, and therefore the description thereof will be omitted.

[0176] The amplifier circuit 50a outputs an amplified signal DOXPa obtained by amplifying the modulated signal DOPa to an output terminal 101, and outputs an amplified signal DOXNa obtained by amplifying the modulated signal DONa to an output terminal 102. Specifically, the amplifier circuit 50a includes two class-D amplifiers 51Pa and 51Na, and the class-D amplifier 51Pa outputs an amplified signal DOXPa obtained by amplifying the modulated signal DOPa to the output terminal 101, and the class-D amplifier 51Na outputs an amplified signal DOXNa obtained by amplifying the modulated signal DONa to the output terminal 102. Since the output terminal 101 is connected to the terminal P1a of the sound reproducing device 3a and the output terminal 102 is connected to the terminal P2a of the sound reproducing device 3a, the sound reproducing device 3a reproduces a sound having a volume corresponding to the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa.

[0177] Therefore, when the semiconductor device 1 inputs a signal based on the sound source signal DIa to the input terminal 103 of the sound source reproducing circuit 100a, the sound reproducing device 3a outputs a desired sound instructed by the sound source reproducing command. Also, when the semiconductor device 1 inputs a test signal TST to the input terminal 103 of the sound source reproducing circuit 100a, it is preferable that the sound reproducing device 3a outputs a weak sound that is difficult for the human ear to hear.

[0178] In the test mode, the test circuit 110 of the semiconductor device 1 detects a peak frequency f peak Detect the peak frequency f peak In the calibration mode, the inspection circuit 110 judges the state of the sound reproduction device 3a based on the peak frequency F peak Detect the peak frequency F peak Based on this, information required for determining the state of the sound reproducing device 3a is created.

[0179] The inspection circuit 110 includes a test signal generation circuit 60, a judgment circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generation circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. The judgment circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0180] The test signal generating circuit 60 generates a test signal TST whose frequency is changed in a preset frequency band. The frequency band in which the test signal generating circuit 60 changes the frequency of the test signal TST can be arbitrarily set by the micro control unit 2, and may be, for example, a frequency band of 10 Hz or more and 3 kHz or less.

[0181] The peak frequency detection circuit 70 measures the potential difference between the input terminal 93 and the input terminal 94, and detects a peak frequency f peak or peak frequency Fpeak The peak frequency detection circuit 70 detects whether the frequency of the test signal TST is a peak frequency f peak or peak frequency F peak The peak voltage v is the amplified voltage of the potential difference between input terminal 93 and input terminal 94 at peak or peak voltage V peak As mentioned above, the peak frequency f peak ,F peak and peak voltage v peak ,V peak varies depending on the temperature of the sound reproducing device 3a.

[0182] The memory 62 includes a non-volatile memory (not shown), and the non-volatile memory stores table information in which a plurality of temperatures and a plurality of peak frequencies related to the sound reproducing device 3a are associated with each other. The table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproducing device 3a. The memory 62 also includes a volatile memory (not shown) that stores various types of data that are temporarily created.

[0183] The determination circuit 61 detects the peak frequency f peak is included in the reference frequency range. The reference frequency range is a frequency range determined based on the frequency band of the test signal TST and temperature information, which is information related to the temperature of the sound reproduction device 3a. In this embodiment, the determination circuit 61 obtains a temperature signal output from the temperature sensor 80 as the temperature information, and calculates the reference frequency range based on the obtained temperature signal and table information stored in the memory 62. The determination circuit 61 also determines whether the peak voltage v detected by the peak frequency detection circuit 70 is included in the reference frequency range. peak is included in a reference voltage range. The reference voltage range is a voltage range determined based on the frequency band of the test signal TST and temperature information, which is information related to the temperature of the sound reproduction device 3a. The determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and table information stored in the memory 62. Furthermore, in this embodiment, the determination circuit 61 determines whether the peak frequency fpeak The result of judging whether or not the reference frequency range is included and the peak voltage v peak is within the reference voltage range, the state of the sound reproducing device 3a, such as the presence or absence of a malfunction of the sound reproducing device 3a, is determined.

[0184] The temperature sensor 80 detects temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. In FIG. 25, the temperature sensor 80 is built into the semiconductor device 1 and directly detects the temperature of the semiconductor device 1, but since the temperature of the semiconductor device 1 and the temperature of the sound reproduction device 3a change similarly depending on the temperature around the semiconductor device 1 and the sound reproduction device 3a, the temperature sensor 80 indirectly detects the temperature of the sound reproduction device 3a. However, the temperature sensor 80 may be provided inside the sound source reproduction circuit 100a to directly detect the temperature of the sound reproduction device 3a, or may be provided outside the semiconductor device 1 near the sound reproduction device 3a.

[0185] The configurations and processing details of the test signal generating circuit 60, the determining circuit 61, and the peak frequency detecting circuit 70 are similar to those of any of the first to fourth embodiments, and therefore a description thereof will be omitted.

[0186] The switch 83 switches between electrically connecting or disconnecting the input terminal 93 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 83 electrically disconnects the input terminal 93 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the input terminal 93 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0187] Similarly, the switch 84 switches between electrically connecting or disconnecting the input terminal 94 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 84 electrically disconnects the input terminal 94 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the input terminal 94 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0188] In this way, the peak frequency detection circuit 70 is electrically disconnected from the input terminals 93, 94 by the switches 83, 84 in the normal operation mode, and is electrically connected to the input terminals 93, 94 in the inspection mode and calibration mode, and measures the potential difference between the output terminals 101 and 102 of the sound source reproduction circuit 100a to detect the peak frequency f peak and peak voltage v peak、 Or, peak frequency F peak and peak voltage V peak Detect.

[0189] When the communication interface circuit 10 receives a command to read out information on the determination result by the determination circuit 61 from the micro control unit 2, it acquires the information on the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 recognizes the state of the sound reproducing device 3a based on the information on the determination result, and can perform various processes according to the state of the sound reproducing device 3a.

[0190] Other configurations and functions of the semiconductor device 1 of the fifth embodiment are similar to those of any of the first to fourth embodiments, and therefore description thereof will be omitted.

[0191] Although the semiconductor device 1 of the fifth embodiment is configured so that one sound reproducing device 3a can output sound, it may be configured so that a plurality of sound reproducing devices can output sound.

[0192] In the fifth embodiment, the terminal P1a of the sound reproducing device 3a is an example of a "first terminal", and the terminal P2a of the sound reproducing device 3 is an example of a "second terminal". The input terminal 93 of the semiconductor device 1 is an example of a "first input terminal", and the input terminal 94 of the semiconductor device 1 is an example of a "second input terminal". The modulated signal DOPa is an example of a "first modulated signal", and the modulated signal DONa is an example of a "second modulated signal". The amplified signal DOXPa is an example of a "first amplified signal", and the amplified signal DOXNa is an example of a "second amplified signal". The normal operation mode is an example of a "first operation mode", and the inspection mode is an example of a "second operation mode".

[0193] According to the semiconductor device 1 of the fifth embodiment described above, even if the sound source reproducing circuit 100a that causes the sound reproducing device 3a to output sound is provided outside the semiconductor device 1, it is possible to determine whether or not the sound reproducing device 3a may be malfunctioning. In addition, according to the semiconductor device 1 of the fifth embodiment, the same effects as those of the semiconductor device 1 of any one of the first to fourth embodiments can be obtained. do.

[0194] 1-6. Variations In each of the above embodiments, the memory 20 in which the sound source data 21-1 to 21-n are stored is built into the semiconductor device 1, but instead of the memory 20, an external memory in which the sound source data 21-1 to 21-n are stored may be connected to the semiconductor device 1, and the semiconductor device 1 may read out the sound source data 21-i, which is the sound source signal DI, from the external memory. Alternatively, instead of the memory 20, the micro control unit 2 may have a built-in memory in which the sound source data 21-1 to 21-n are stored, and the micro control unit 2 may read out the sound source data 21-i from the memory and transmit it to the semiconductor device 1 as the sound source signal DI.

[0195] In addition, in each of the above embodiments, the examples of the modulation method by the pulse width modulation circuit 33 are shown in FIGS. 2 to 4, but other modulation methods may be used. For example, the pulse width modulation for generating the modulated signal DOP may be the same as that shown in FIG. 2, and the pulse width modulation for generating the modulated signal DON may be the method shown in FIG. 26. In the example of FIG. 26, the modulated signal DON is a signal obtained by inverting the logical level of the modulated signal DOP shown in FIG. 2, and the higher the value of the sigma-delta modulated signal DS, the shorter the high-level time becomes. For example, when the sigma-delta modulated signal DS is "-7" in decimal, that is, "1001" in binary, the modulated signal DON has one section T1 at a low level and 15 sections T2 to T16 at a high level. Also, for example, when the sigma-delta modulated signal DS is "0" in decimal, that is, "0000" in binary, the modulated signal DON has eight sections T1 to T8 at a low level and eight sections T9 to T16 at a high level. Also, for example, when the sigma-delta modulated signal DS is a decimal number "7", that is, a binary number "0111", the modulated signal DON is at a low level for 15 intervals T1 to T15 and at a high level for one interval T16. Therefore, for example, when the sigma-delta modulated signal DS is a decimal number "-7", "0", "7", the difference between the modulated signal DOP and the modulated signal DON is as shown in FIG.

[0196] 2.Electronic equipment FIG. 28 is a functional block diagram showing an example of the configuration of an electronic device of the present embodiment using the semiconductor device 1 of the present embodiment.

[0197] 28, electronic device 300 of this embodiment includes a semiconductor device 1, m sound reproduction devices 3-1 to 3-m, a processing unit 310, an operation unit 320, a storage unit 330, and a display unit 340. Note that electronic device 300 of this embodiment may be configured such that some of the components in FIG. 28 are omitted or changed, or other components are added.

[0198] The processing unit 310 performs control processing of each unit of the electronic device 300 and various data processing. For example, the processing unit 310 transmits various commands to the semiconductor device 1 to control the operation of the semiconductor device 1. The processing unit 310 also performs various processes according to operation signals from the operation unit 320, and a process of transmitting a display signal for displaying various information on the display unit 340. For example, the processing unit 310 may be the micro control unit 2 described above.

[0199] The operation unit 320 is an input device including operation keys, button switches, and the like, and outputs to the processing unit 310 an operation signal in response to an operation by a user.

[0200] The storage unit 330 stores programs, data, and the like for performing various calculation processes and control processes by the processing unit 310. The storage unit 330 is realized by, for example, a hard disk, a flexible disk, an MO, an MT, various types of memory, a CD-ROM, a DVD-ROM, or the like.

[0201] The display unit 340 is a display device configured with an LCD or the like, and displays various information based on an input display signal. LCD is an abbreviation for Liquid Crystal Display. The display unit 340 may be provided with a touch panel that functions as the operation unit 320.

[0202] In the normal operation mode, the semiconductor device 1 generates a sound signal based on various commands transmitted from the processing unit 310 and outputs it to the sound reproduction device 3-1. As a result, a desired sound is output from the sound reproduction device 3-1. The sound reproduction device 3-1 corresponds to the above-mentioned sound reproduction device 3. In addition, in the inspection mode and calibration, the semiconductor device 1 outputs amplified signals DOXP and DOXN based on the test signal to the sound reproduction device 3-1. As a result, sound is output from the sound reproduction device 3-1, so it is preferable that a minute sound that is difficult for the human ear to hear is output. That is, it is preferable that the volume reproduced by the sound reproduction device 3-1 in the inspection mode and calibration is smaller than the minimum volume reproduced by the sound reproduction device 3-1 in the normal operation mode. This makes it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode or calibration. Then, the semiconductor device 1 may inspect the sound reproduction device 3-1 and transmit the inspection result to the processing unit 310, and the processing unit 310 may determine the presence or absence of a failure of the sound reproduction device 3-1 and the failure mode. When sound playback device 3-1 is malfunctioning, processing unit 310 may, for example, cause one of sound playback devices 3-2 to 3-m to play a sound notifying that sound playback device 3-1 is malfunctioning, or may switch the output destination of the sound signal from sound playback device 3-1 to one of sound playback devices 3-2 to 3-m.

[0203] The semiconductor device 1 can generate a signal required to detect a malfunction of the sound reproducing device 3-1, and therefore the electronic device 300 can be realized with high reliability.

[0204] Various electronic devices are conceivable as such electronic device 300, and examples thereof include warning devices, various household electrical appliances such as rice cookers, IH cooking heaters, vacuum cleaners, and washing machines, electronic watches, personal computers such as mobile, laptop, and tablet types, mobile terminals such as smartphones and mobile phones, inkjet discharge devices such as digital cameras and inkjet printers, storage area network devices such as routers and switches, local area network devices, equipment for mobile terminal base stations, televisions, video cameras, video recorders, car navigation devices, real time clock devices, pagers, electronic notebooks, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, security television monitors, electronic binoculars, POS terminals, medical devices such as electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, and electronic endoscopes, fish finders, various measuring devices, instruments for vehicles, aircraft, ships, and the like, flight simulators, head mounted displays, motion tracing, motion tracking, motion controllers, and pedestrian autonomous navigation devices.

[0205] Fig. 29 is a diagram showing a configuration example of a warning device 300A, which is an example of electronic device 300. In Fig. 29, the same components as those in Fig. 28 are given the same reference numerals. The warning device 300A shown in Fig. 29 is mounted on a vehicle 400. Sound reproducing device 3-1 is a speaker, and sound reproducing devices 3-2 to 3-5 are buzzers.

[0206] Based on signals from various sensors (not shown), the processing unit 310 transmits commands to reproduce various sounds to the semiconductor device 1. The various sounds include, for example, voices and warning sounds that imitate human voices to notify of abnormalities in the brakes, engine oil, power steering, brake override system, etc., driving with the door half-open, swaying, driving without releasing the parking brake, not fastening a seat belt, approaching a preceding vehicle, etc., and sound effects to notify of blinkers, hazards, reverse, etc.

[0207] The semiconductor device 1 generates a plurality of signals corresponding to various sounds based on a command from the processing unit 310. The semiconductor device 1 generates a sound signal based on a part of the sound source data and outputs it to the sound reproduction device 3-1. The semiconductor device 1 may also inspect the sound reproduction device 3-1 and transmit the inspection result to the processing unit 310, which may then determine whether or not the sound reproduction device 3-1 is malfunctioning and the malfunction mode. When the sound reproduction device 3-1 is malfunctioning, the processing unit 310 may, for example, cause one of the sound reproduction devices 3-2 to 3-5 to reproduce a sound notifying that the sound reproduction device 3-1 is malfunctioning, or may switch the output destination of the sound signal from the sound reproduction device 3-1 to one of the sound reproduction devices 3-2 to 3-5.

[0208] The semiconductor device 1 can generate a signal required to detect a malfunction of the sound reproducing device 3-1, and therefore can realize a highly reliable warning device 300A.

[0209] The electronic device 300 is not limited to the configuration shown in Fig. 28, and may include, for example, the semiconductor device 1 and the sound source reproducing circuit 100a of the fifth embodiment shown in Fig. 25, in which the semiconductor device 1 instructs the sound source reproducing circuit 100a to output sound to any of the sound reproducing devices 3-1 to 3-m. Alternatively, the electronic device 300 may include the semiconductor device 1 and the sound source reproducing circuit 100a shown in Fig. 30, in which the semiconductor device 1 causes the sound reproducing device 3 to output sound and instructs the sound source reproducing circuit 100a to output sound to the other sound reproducing device 3a.

[0210] In FIG. 30, the same components as those in FIG. 25 are denoted by the same reference numerals. In FIG. 30, the configuration and function of the sound source reproducing circuit 100a are the same as those of the sound source reproducing circuit 100a shown in FIG. 25, and the description thereof will be omitted. The semiconductor device 1 is connected to the sound source reproducing circuit 100a and the sound reproducing devices 3 and 3a. Specifically, the output terminal 91 of the semiconductor device 1 is connected to the terminal P1 of the sound reproducing device 3, and the output terminal 92 of the semiconductor device 1 is connected to the terminal P2 of the sound reproducing device 3. The output terminal 95 of the semiconductor device 1 is connected to the input terminal 103 of the sound source reproducing circuit 100a, the input terminal 93 of the semiconductor device 1 is connected to the output terminal 101 of the sound source reproducing circuit 100a, and the terminal P1a of the sound reproducing device 3a, and the input terminal 94 of the semiconductor device 1 is connected to the output terminal 102 of the sound source reproducing circuit 100a, and the terminal P2a of the sound reproducing device 3a.

[0211] The semiconductor device 1 includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 81, 82, 83, 84, 85, and 86, a sound source playback circuit 100, and an inspection circuit 110. The semiconductor device 1 may be a one-chip semiconductor integrated circuit device, or may be composed of semiconductor integrated circuit devices on multiple chips, or may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0212] When the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to a normal operation mode, an inspection mode, or a calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 81, 82, 83, 84, 85, and 86 according to the operation mode. Also, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the sound source reproduction circuit 100 as a sound source signal DI, and instructs the sound source reproduction circuit 100 to reproduce the sound source data by the sound reproduction device 3. Also, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the input terminal 103 of the sound source reproduction circuit 100a via the switch 85 and the output terminal 95 as a sound source signal DIa, and instructs the sound source reproduction circuit 100a to reproduce the sound source data by the sound reproduction device 3a. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. For example, when the sound reproducing device 3 receives a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100 to stop reproduction. For example, when the sound reproducing device 3a receives a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100a to stop reproduction. For example, the communication interface circuit 10 When the communication interface circuit 10 receives various setting commands related to sound source reproduction by the sound source reproduction circuit 100, it performs various settings on the sound source reproduction circuit 100. When the communication interface circuit 10 receives various setting commands related to sound source reproduction by the sound source reproduction circuit 100a, it performs various settings on the sound source reproduction circuit 100a.

[0213] The switch 85 outputs either a signal based on the sound source signal DIa or a test signal TST to the output terminal 95 in response to a control signal output from the communication interface circuit 10. Specifically, in the normal operation mode, the switch 85 outputs a signal based on the sound source signal DIa to the output terminal 95, and in the inspection mode or calibration mode, the switch 85 outputs the test signal TST to the output terminal 95. The signal based on the sound source signal DIa may be the sound source signal DIa itself, or may be a signal obtained by performing some processing on the sound source signal DIa.

[0214] The switch 86 outputs either a signal based on the sound source signal DI or a test signal TST to the sound source reproduction circuit 100 in response to a control signal output from the communication interface circuit 10. Specifically, the switch 86 outputs a signal based on the sound source signal DI to the sound source reproduction circuit 100 in a normal operation mode, and outputs the test signal TST to the sound source reproduction circuit 100 in an inspection mode or a calibration mode. The signal based on the sound source signal DI may be the sound source signal DI itself, or may be a signal obtained by performing some processing on the sound source signal DI.

[0215] In the normal operation mode, the sound source reproduction circuit 100 converts a signal based on the input sound source signal DI into amplified signals DOXP, DOXN, and outputs the amplified signals DOXP, DOXN to the output terminals 91, 92, respectively. As a result, sounds corresponding to the amplified signals DOXP, DOXN are output from the sound reproduction device 3. In addition, in the inspection mode or calibration mode, the sound source reproduction circuit 100 converts the input test signal TST into amplified signals DOXP, DOXN, and outputs them to the output terminals 91, 92, respectively.

[0216] For example, the sound reproducing devices 3 and 3a may each be a speaker or a buzzer. The sound output from each of the sound reproducing devices 3 and 3a may be, for example, a voice that imitates a human voice when speaking, or various sounds such as mechanical warning sounds and sound effects.

[0217] As shown in Fig. 30, the sound source reproducing circuit 100 includes a modulation circuit 30 and an amplifier circuit 50. The modulation circuit 30 modulates an input signal and outputs modulated signals DOP, DON. Specifically, the modulation circuit 30 includes a digital filter 31, a sigma-delta modulation circuit 32, and a pulse width modulation circuit 33. The digital filter 31 digitally filters the input signal to generate a signal DF, which the sigma-delta modulation circuit 32 sigma-delta modulates to generate a sigma-delta modulated signal DS, and the pulse width modulation circuit 33 pulse-width modulates to generate modulated signals DOP, DON. In the normal operation mode, the modulation circuit 30 modulates a signal based on the input sound source signal DI to generate modulated signals DOP, DON, and in the inspection mode or calibration mode, the modulation circuit 30 modulates the input test signal TST to generate modulated signals DOP, DON. Note that the detailed processing of the digital filter 31, the sigma-delta modulation circuit 32, and the pulse width modulation circuit 33 is similar to the processing of the digital filter 31, the sigma-delta modulation circuit 32, and the pulse width modulation circuit 33 in any of the first to fourth embodiments, and therefore the description thereof will be omitted.

[0218] The amplifier circuit 50 amplifies the modulated signal DOP to output an amplified signal DOXP to an output terminal 91, and also amplifies the modulated signal DON to output an amplified signal DOXN to an output terminal 92. Specifically, the amplifier circuit 50 includes two class D amplifiers 51P and 51N. The class-D amplifier 51A amplifies the modulated signal DOP and outputs an amplified signal DOXP to an output terminal 91, and the class-D amplifier 51N amplifies the modulated signal DON and outputs an amplified signal DOXN to an output terminal 92. Since the output terminal 91 is connected to the terminal P1 of the sound reproducing device 3 and the output terminal 92 is connected to the terminal P2 of the sound reproducing device 3, the sound reproducing device 3 reproduces a sound whose volume corresponds to the voltage difference between the amplified signal DOXP and the amplified signal DOXN.

[0219] Therefore, when a signal based on the sound source signal DI is input to the sound source reproduction circuit 100, the sound reproduction device 3 outputs a desired sound instructed by the sound source reproduction command. Also, when a test signal TST is input to the sound source reproduction circuit 100, it is preferable that the sound reproduction device 3 outputs a minute sound that is difficult for the human ear to hear.

[0220] The switch 81 switches between electrically connecting or disconnecting the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. The switch 82 switches between electrically connecting or disconnecting the output terminal 92 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. The switch 83 switches between electrically connecting or disconnecting the input terminal 93 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10. The switch 84 switches between electrically connecting or disconnecting the input terminal 94 of the semiconductor device 1 and the peak frequency detection circuit 70 in response to a control signal output from the communication interface circuit 10.

[0221] Specifically, when the operation mode of the semiconductor device 1 is the normal operation mode, the switches 81 and 82 electrically disconnect the output terminals 91 and 92 from the peak frequency detection circuit 70, and the switches 83 and 84 electrically disconnect the input terminals 93 and 94 from the peak frequency detection circuit 70. When the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode, the switches 81 and 82 electrically connect the output terminals 91 and 92 to the peak frequency detection circuit 70, and the switches 83 and 84 electrically disconnect the input terminals 93 and 94 from the peak frequency detection circuit 70, or alternatively, the switches 83 and 84 electrically connect the input terminals 93 and 94 to the peak frequency detection circuit 70, and the switches 81 and 82 electrically disconnect the output terminals 91 and 92 from the peak frequency detection circuit 70. That is, in the inspection mode or the calibration mode, the switches 81, 82 and the switches 83, 84 are exclusively turned on. When the switches 81, 82 are on, the switches 83, 84 are off, and when the switches 83, 84 are on, the switches 81, 82 are off.

[0222] In the test mode, the test circuit 110 detects the peak frequency f peak Detect the peak frequency f peak In the calibration mode, the inspection circuit 110 judges the state of the sound reproduction devices 3 and 3a based on the peak frequency F peak Detect the peak frequency F peak Based on this, information required for determining the state of the sound reproduction devices 3, 3a is created.

[0223] The inspection circuit 110 includes a test signal generation circuit 60, a judgment circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generation circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. The judgment circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0224] The test signal generating circuit 60 generates a test signal TST whose frequency is changed in a preset frequency band. The frequency band in which the test signal generating circuit 60 changes the frequency of the test signal TST can be arbitrarily set by the micro control unit 2, and may be, for example, a frequency band of 10 Hz or more and 3 kHz or less.

[0225] When the switches 81 and 82 are on, the peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects a peak frequency f peakm or peak frequency F peak The peak frequency detection circuit 70 detects whether the frequency of the test signal TST is a peak frequency f peak or peak frequency F peak The peak voltage v is the amplified voltage of the potential difference between the output terminals 91 and 92 at peak or peak voltage V peak When the switches 83 and 84 are on, the peak frequency detection circuit 70 measures the potential difference between the input terminal 93 and the input terminal 94, and detects a peak frequency f peak or peak frequency F peak When the switches 83 and 84 are on, the peak frequency detection circuit 70 detects that the frequency of the test signal TST is equal to or greater than the peak frequency f peak or peak frequency F peak The peak voltage v is the amplified voltage of the potential difference between input terminal 93 and input terminal 94 at peak or peak voltage V peak As mentioned above, the peak frequency f peak ,F peak and peak voltage v peak ,V peak varies depending on the temperature of the sound reproducing device 3a.

[0226] The memory 62 includes a non-volatile memory (not shown), and the non-volatile memory stores table information in which a plurality of temperatures and a plurality of peak frequencies related to the sound reproduction devices 3, 3a are associated with each other. The table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproduction devices 3, 3a. The memory 62 also includes a volatile memory (not shown) that stores various types of data that are temporarily created.

[0227] The determination circuit 61 detects the peak frequency f peak is included in the reference frequency range. The reference frequency range is a frequency range determined based on the frequency band of the test signal TST and temperature information, which is information related to the temperature of the sound reproduction devices 3, 3a. In this embodiment, the determination circuit 61 obtains a temperature signal output from the temperature sensor 80 as the temperature information, and calculates the reference frequency range based on the obtained temperature signal and table information stored in the memory 62. The determination circuit 61 also determines whether the peak voltage v detected by the peak frequency detection circuit 70 is included in the reference frequency range. peak is included in a reference voltage range. The reference voltage range is a voltage range determined based on the frequency band of the test signal TST and temperature information, which is information related to the temperatures of the sound reproduction devices 3, 3a. The determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and table information stored in the memory 62. Furthermore, in this embodiment, the determination circuit 61 determines whether the peak frequency f peak The result of judging whether or not the reference frequency range is included and the peak voltage v peak is within the reference voltage range, the state of the sound reproducing devices 3, 3a, such as the presence or absence of a malfunction of the sound reproducing devices 3, 3a, is determined.

[0228] The temperature sensor 80 detects the temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. In FIG. 30, the temperature sensor 80 is built in the semiconductor device 1 and directly detects the temperature of the semiconductor device 1. However, since the temperature of the semiconductor device 1 and the temperature of the sound reproducing devices 3, 3a change similarly depending on the temperature around the semiconductor device 1 and the sound reproducing devices 3, 3a, the temperature sensor 80 indirectly detects the temperatures of the sound reproducing devices 3, 3a. However, the temperature sensor 80 may be provided outside the semiconductor device 1 and near the sound reproducing device 3 in order to directly detect the temperature of the sound reproducing device 3. Also, a temperature sensor other than the temperature sensor 80 may be provided inside the sound source reproducing circuit 100a or near the sound reproducing device 3a in order to directly detect the temperature of the sound reproducing device 3a. In this case, the determination circuit 61 determines the peak frequency f detected when the switches 83, 84 are on. peak When determining whether or not the frequency is within the reference frequency range, a temperature signal output from a temperature sensor other than the temperature sensor 80 may be acquired as temperature information.

[0229] The configurations and processing details of the test signal generating circuit 60, the determining circuit 61, and the peak frequency detecting circuit 70 are similar to those of any of the first to fourth embodiments, and therefore a description thereof will be omitted.

[0230] When the communication interface circuit 10 receives a command to read out information on the determination result by the determination circuit 61 from the micro control unit 2, it acquires the information on the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 recognizes the state of the sound reproduction devices 3, 3a based on the information on the determination result, and can perform various processes according to the state of the sound reproduction devices 3, 3a.

[0231] Other configurations and functions of the semiconductor device 1 shown in FIG. 30 are similar to those of any of the first to fifth embodiments, and therefore description thereof will be omitted.

[0232] The terminal P1 of the sound reproducing device 3 is an example of a "first terminal", and the terminal P2 of the sound reproducing device 3 is an example of a "second terminal". The output terminal 91 of the semiconductor device 1 is an example of a "first output terminal", and the output terminal 92 of the semiconductor device 1 is an example of a "second output terminal". The modulated signal DOP obtained by modulating a signal based on the sound source signal DI is an example of a "first modulated signal", and the modulated signal DON obtained by modulating a signal based on the sound source signal DI is an example of a "second modulated signal". The modulated signal DOP obtained by modulating the test signal TST is an example of a "third modulated signal", and the modulated signal DON obtained by modulating the test signal TST is an example of a "fourth modulated signal". The amplified signal DOXP obtained by amplifying the modulated signal DOP obtained by modulating a signal based on the sound source signal DI is an example of a "first amplified signal", and the amplified signal DOXN obtained by amplifying the modulated signal DON obtained by modulating a signal based on the sound source signal DI is an example of a "second amplified signal". Moreover, the amplified signal DOXP obtained by amplifying the modulated signal DOP obtained by modulating the test signal TST is an example of a “third amplified signal,” and the amplified signal DOXN obtained by amplifying the modulated signal DON obtained by modulating the test signal TST is an example of a “fourth amplified signal.” Moreover, the normal operation mode is an example of a “first operation mode,” and the inspection mode is an example of a “second operation mode.”

[0233] 30, the semiconductor device 1 instructs one sound source reproducing circuit 100a to cause the sound reproducing device 3a to output sound, but may instruct multiple sound source reproducing circuits 100a to cause the multiple sound reproducing devices 3a to output sound. For example, in the warning device 300A shown in FIG 29, the semiconductor device 1 may cause at least one of the sound reproducing devices 3-1 to 3-5 to output sound, and may instruct one or multiple sound source reproducing circuits 100a to cause at least one of the sound reproducing devices 3-1 to 3-5 to output sound.

[0234] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0235] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be appropriately combined.

[0236] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0237] The following can be derived from the above-described embodiment and modified examples.

[0238] One aspect of the semiconductor device is a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a test signal generating circuit that, in a second operation mode, generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which the impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with.

[0239] According to this semiconductor device, in the first operation mode, the amplifier circuit outputs a first amplified signal obtained by amplifying a first modulated signal based on a sound source signal to the first output terminal, and outputs a second amplified signal obtained by amplifying a second modulated signal based on a sound source signal to the second output terminal, so that the sound reproducing device can reproduce sound. On the other hand, in the second operation mode, the amplifier circuit outputs a third amplified signal obtained by amplifying a third modulated signal based on a test signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying a fourth modulated signal based on the test signal to the second output terminal, so that the peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal, and can detect a peak frequency at which the impedance of the sound reproducing device becomes a peak. Then, the determination circuit determines whether the peak frequency is included in a reference frequency range, and, for example, if the peak frequency is not included in the reference frequency range, it can determine that the sound reproducing device may be broken. This reference frequency range is determined based on the frequency band of the test signal and temperature information of the sound reproducing device, so it changes appropriately according to the temperature of the sound reproducing device. Therefore, according to this semiconductor device, the accuracy of the failure determination of the sound reproducing device can be maintained even if the temperature changes.

[0240] In addition, in this semiconductor device, the amplifier circuit is used to generate the first and second amplified signals for causing the sound reproduction device to reproduce sound in the first operation mode, and to generate the third and fourth amplified signals required for detecting the peak frequency in the second operation mode. Therefore, according to this semiconductor device, the signals required for detecting a fault in the sound reproduction device can be generated by a small-scale circuit.

[0241] In one embodiment of the semiconductor device, The judgment circuit may acquire a temperature signal output from a temperature sensor as the temperature information, and calculate the reference frequency range based on the acquired temperature signal and table information in which a plurality of temperatures related to the sound playback device are associated with a plurality of the peak frequencies.

[0242] According to this semiconductor device, it is possible to calculate an appropriate reference frequency range according to the temperature of the sound reproducing device based on the temperature signal output from the temperature sensor and table information in which multiple temperatures are associated with multiple peak frequencies. Therefore, according to this semiconductor device, it is possible to maintain the accuracy of the failure determination of the sound reproducing device even if the temperature changes.

[0243] In one embodiment of the semiconductor device, The determination circuit may acquire a temperature signal output from a temperature sensor as the temperature information, and calculate the reference frequency range based on the acquired temperature signal and information on a relational expression between temperature and the peak frequency.

[0244] According to this semiconductor device, it is possible to calculate an appropriate reference frequency range according to the temperature of the sound reproducing device based on the temperature signal output from the temperature sensor and information on the relational expression between temperature and peak frequency, and therefore, according to this semiconductor device, it is possible to maintain the accuracy of the failure judgment of the sound reproducing device even if the temperature changes.

[0245] In one embodiment of the semiconductor device, the temperature information is information about a temperature range within which operation of the sound reproduction device is guaranteed, The reference frequency range may be a frequency range including the range of peak frequencies corresponding to the temperature range, consisting of a reference frequency block including the peak frequency corresponding to a reference temperature and frequency blocks before and after the reference frequency block, among a plurality of frequency blocks into which a predetermined frequency range is divided.

[0246] In this semiconductor device, the reference frequency range is a frequency range including a peak frequency range corresponding to the temperature range in which the operation of the sound reproduction device is guaranteed, which is composed of a reference frequency block including a peak frequency corresponding to the reference temperature and frequency blocks before and after the reference frequency block, so that even if the peak frequency changes due to a change in the temperature of the sound reproduction device, the detected peak frequency is included in the reference frequency range. Therefore, with this semiconductor device, the risk of erroneously determining that the sound reproduction device is malfunctioning when it is actually normal is reduced.

[0247] In one embodiment of the semiconductor device, the temperature information is information about a temperature range within which operation of the sound reproduction device is guaranteed, The reference frequency range may be a frequency range of a reference frequency block including the range of peak frequencies corresponding to the temperature range, among a plurality of frequency blocks into which a predetermined frequency range is divided.

[0248] In this semiconductor device, the reference frequency range is the frequency range of the reference frequency block including the range of peak frequencies corresponding to the temperature range in which the operation of the sound reproduction device is guaranteed, so that even if the peak frequency changes due to a change in the temperature of the sound reproduction device, the detected peak frequency is included in the reference frequency range. Therefore, with this semiconductor device, the risk of erroneously determining that the sound reproduction device is malfunctioning when it is actually normal is reduced.

[0249] In one embodiment of the semiconductor device, the peak frequency detection circuit further detects, in the second operation mode, a peak voltage that is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the peak frequency; The determination circuit may further determine, in the second operation mode, whether or not the peak voltage is included in a reference voltage range determined based on the frequency band of the test signal and the temperature information.

[0250] In this semiconductor device, the judgment circuit further judges whether the peak voltage is within a reference voltage range, and, for example, if the peak voltage is not within the reference voltage range, it can judge that the sound reproduction device may be broken. This reference voltage range is determined based on the frequency band of the test signal and temperature information of the sound reproduction device, and therefore changes appropriately according to the temperature of the sound reproduction device. Therefore, even if the peak frequency is within the reference frequency range, the judgment circuit can judge that the sound reproduction device may be broken. If the peak voltage is not within the reference voltage range, it can be determined that the sound reproduction device may be malfunctioning. Therefore, according to this semiconductor device, the risk of erroneously determining that the sound reproduction device is normal when there is a possibility that the sound reproduction device is malfunctioning is reduced.

[0251] In one embodiment of the semiconductor device, The peak frequency detection circuit may detect the peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal becomes maximum in the second operation mode.

[0252] According to this semiconductor device, when the impedance of the sound playback device reaches its peak, the potential difference between the first output terminal and the second output terminal also reaches its peak, so the peak frequency detection circuit can detect the peak frequency by measuring the time when the potential difference between the first output terminal and the second output terminal reaches its maximum.

[0253] In one embodiment of the semiconductor device, The peak frequency detection circuit includes: a differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; an A / D conversion circuit for converting an output voltage of the differential low-pass filter into a digital signal; a peak time measurement circuit that measures the time when the potential difference between the first output terminal and the second output terminal becomes maximum based on the digital signal; may include:

[0254] According to this semiconductor device, the differential low-pass filter reduces the high-frequency noise components superimposed on the third amplified signal and the fourth amplified signal by modulating the test signal, the A / D conversion circuit converts the output voltage of the differential low-pass filter into a digital signal, and the peak time measurement circuit can easily perform high-precision measurements.

[0255] In one embodiment of the semiconductor device, The cutoff frequency of the differential low pass filter may be higher than a maximum frequency of the frequency band.

[0256] According to this semiconductor device, the cutoff frequency of the differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, so that the frequency components included in that frequency band are not attenuated by the differential low-pass filter, enabling the peak time measurement circuit to perform highly accurate measurements.

[0257] Another aspect of the semiconductor device is A semiconductor device connected to a sound source reproducing circuit, the semiconductor device comprising: an input terminal; a modulation circuit that modulates a signal input to the input terminal and outputs a first modulated signal and a second modulated signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulated signal to a first terminal of a sound reproducing device, and that outputs a second amplified signal obtained by amplifying the second modulated signal to a second terminal of the sound reproducing device, a first input terminal connected to the first terminal of the sound reproducing device; a second input terminal connected to the second terminal of the sound reproducing device; an output terminal connected to the input terminal of the sound source reproducing circuit; a switch that outputs a signal based on a sound source signal to the output terminal in a first operation mode, and outputs a test signal, the frequency of which is changed within a preset frequency band, to the output terminal in a second operation mode; a test signal generator for outputting the test signal to the switch in the second operation mode; A synthesis circuit, a peak frequency detection circuit that measures a potential difference between the first input terminal and the second input terminal in the second operation mode and detects a peak frequency of the test signal at which an impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with.

[0258] According to this semiconductor device, in the first operation mode, the amplifier circuit of the sound source reproducing circuit outputs a first amplified signal obtained by amplifying a first modulated signal based on a sound source signal to the first output terminal, and outputs a second amplified signal obtained by amplifying a second modulated signal based on the sound source signal to the second output terminal, so that the sound reproducing device can reproduce sound. On the other hand, in the second operation mode, the amplifier circuit of the sound source reproducing circuit outputs a second amplified signal obtained by amplifying a first modulated signal based on a test signal to the first output terminal, and outputs a second amplified signal obtained by amplifying a second modulated signal based on the test signal to the second output terminal, so that the peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal of the sound source reproducing circuit and detects the peak frequency at which the impedance of the sound reproducing device becomes a peak. Then, the determination circuit determines whether the peak frequency is included in a reference frequency range, and, for example, if the peak frequency is not included in the reference frequency range, it can determine that the sound reproducing device may be broken. This reference frequency range is determined based on the frequency band of the test signal and temperature information of the sound reproducing device, so it changes appropriately according to the temperature of the sound reproducing device. Therefore, according to this semiconductor device, when an external sound source reproduction circuit causes the sound reproduction device to output sound, the accuracy of failure determination of the sound reproduction device can be maintained even if the temperature changes.

[0259] One aspect of the electronic device is One aspect of the semiconductor device; The sound reproduction device; Equipped with.

[0260] According to this electronic device, since it includes a semiconductor device capable of generating a signal required for detecting a malfunction of the sound reproducing device, it is possible to improve reliability.

[0261] In one aspect of the electronic device, A volume of sound reproduced by the sound reproduction device in the second operation mode may be lower than a minimum volume of sound reproduced by the sound reproduction device in the first operation mode.

[0262] According to this electronic device, the sound output from the sound playback device in the second operation mode is a very small sound that is difficult for humans to hear, making it difficult for the user to be aware that the semiconductor device is operating in the second operation mode.

[0263] Another aspect of the electronic device is a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that, in a first operation mode, modulates a signal based on a sound source signal to output a first modulated signal and a second modulated signal, and, in a second operation mode, modulates a test signal whose frequency is changed within a preset frequency band to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; In the first operation mode, the first modulated signal is amplified and output as a first amplified signal to the first output. an amplifier circuit that, in the second operation mode, outputs a first amplified signal obtained by amplifying the second modulated signal to the first output terminal and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which the impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; Equipped with.

[0264] According to this electronic device, in the first operation mode, the amplifier circuit outputs a first amplified signal obtained by amplifying a first modulated signal based on a sound source signal to the first output terminal, and outputs a second amplified signal obtained by amplifying a second modulated signal based on a sound source signal to the second output terminal, so that the sound reproducing device can reproduce sound. On the other hand, in the second operation mode, the amplifier circuit outputs a third amplified signal obtained by amplifying a third modulated signal based on a test signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying a fourth modulated signal based on the test signal to the second output terminal, so that the peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal, and can detect a peak frequency at which the impedance of the sound reproducing device becomes a peak. Then, the determination circuit determines whether the peak frequency is included in a reference frequency range, and, for example, if the peak frequency is not included in the reference frequency range, it can determine that the sound reproducing device may be broken. This reference frequency range is determined based on the frequency band of the test signal and temperature information of the sound reproducing device, and therefore changes appropriately according to the temperature of the sound reproducing device. Therefore, according to this electronic device, the accuracy of the failure determination of the sound reproducing device can be maintained even if the temperature changes.

[0265] In addition, in this electronic device, the amplifier circuit is used both to generate the first and second amplified signals for causing the sound reproduction device to reproduce sound in the first operation mode, and to generate the third and fourth amplified signals required for detecting the peak frequency in the second operation mode. Therefore, according to this electronic device, the signals required for detecting a fault in the sound reproduction device can be generated with a small-scale circuit. [Explanation of symbols]

[0266] 1...semiconductor device, 2...microcontroller unit, 3,3-1 to 3-m...sound reproduction device, 10...communication interface circuit, 20...memory, 21-1 to 21-n...sound source data, 30...modulation circuit, 31...digital filter, 32...sigma-delta modulation circuit, 33...pulse width modulation circuit, 41...switch, 42...switch, 50...amplification circuit, 51P, 51N...class D amplifier, 60...test signal generation circuit, 61...judgment circuit, 62...memory, 70...peak frequency detection circuit, 71...differential low-pass filter, 72...A / D conversion circuit, 73...peak Time measurement circuit, 80...temperature sensor, 81...switch, 82...switch, 91...output terminal, 92...output terminal, 100...sound source playback circuit, 110...inspection circuit, 201-1 to 201-n...inverter circuit, 202-1 to 202-n...inverter circuit, 211...operational amplifier, 212, 213, 214...resistor, 215...capacitor, 216...resistor, 217...capacitor, 218...resistor, 219...capacitor, 300...electronic device, 300A...warning device, 310...processing unit, 320...operation unit, 330...storage unit, 340...display unit, 400...vehicle

Claims

1. a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulated signal and a second modulated signal; a test signal generating circuit that, in a second operation mode, generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is changed within a preset frequency band; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which an impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range that is determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; A semiconductor device comprising:

2. In claim 1, The semiconductor device, wherein the judgment circuit acquires a temperature signal output from a temperature sensor as the temperature information, and calculates the reference frequency range based on the acquired temperature signal and table information in which multiple temperatures related to the sound playback device are associated with multiple peak frequencies.

3. In claim 1, The semiconductor device, wherein the judgment circuit acquires a temperature signal output from a temperature sensor as the temperature information, and calculates the reference frequency range based on the acquired temperature signal and information on a relational equation between temperature and the peak frequency.

4. In claim 1, the temperature information is information about a temperature range within which operation of the sound reproduction device is guaranteed, The semiconductor device, wherein the reference frequency range is a frequency range including the range of the peak frequency corresponding to the temperature range, the frequency range being composed of a reference frequency block including the peak frequency corresponding to a reference temperature and frequency blocks before and after the reference frequency block, among a plurality of frequency blocks into which a predetermined frequency range is divided.

5. In claim 1, the temperature information is information about a temperature range within which operation of the sound reproduction device is guaranteed, The semiconductor device, wherein the reference frequency range is a frequency range of a reference frequency block including the range of peak frequencies corresponding to the temperature range, among a plurality of frequency blocks into which a predetermined frequency range is divided.

6. In claim 1, the peak frequency detection circuit further detects, in the second operation mode, a peak voltage that is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the peak frequency; In the second operation mode, the determination circuit determines whether the peak voltage is greater than the The semiconductor device determines whether or not the frequency band is included in a reference voltage range determined based on the frequency band and the temperature information.

7. In claim 1, The semiconductor device, wherein the peak frequency detection circuit detects the peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal becomes maximum in the second operation mode.

8. In claim 7, The peak frequency detection circuit includes: a differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; an A / D conversion circuit for converting an output voltage of the differential low-pass filter into a digital signal; a peak time measurement circuit that measures the time when the potential difference between the first output terminal and the second output terminal becomes maximum based on the digital signal; 13. A semiconductor device comprising:

9. In claim 8, A semiconductor device, wherein a cutoff frequency of the differential low-pass filter is higher than a maximum frequency of the frequency band.

10. A semiconductor device connected to a sound source reproducing circuit, the semiconductor device comprising: an input terminal; a modulation circuit that modulates a signal input to the input terminal to output a first modulated signal and a second modulated signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulated signal to a first terminal of a sound reproducing device, and that outputs a second amplified signal obtained by amplifying the second modulated signal to a second terminal of the sound reproducing device, a first input terminal connected to the first terminal of the sound reproducing device; a second input terminal connected to the second terminal of the sound reproducing device; an output terminal connected to the input terminal of the sound source reproducing circuit; a switch that outputs a signal based on a sound source signal to the output terminal in a first operation mode, and outputs a test signal, the frequency of which is changed within a preset frequency band, to the output terminal in a second operation mode; a test signal generating circuit that outputs the test signal to the switch in the second operation mode; a peak frequency detection circuit that measures a potential difference between the first input terminal and the second input terminal in the second operation mode and detects a peak frequency of the test signal at which an impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range that is determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; A semiconductor device comprising:

11. A semiconductor device according to any one of claims 1 to 10, The sound reproduction device; An electronic device comprising:

12. In claim 11, An electronic device, wherein the volume of sound reproduced by the sound reproduction device in the second operation mode is lower than a minimum volume of sound reproduced by the sound reproduction device in the first operation mode.

13. a first output terminal connected to a first terminal of the sound reproducing device; a second output terminal connected to a second terminal of the sound reproducing device; a modulation circuit that, in a first operation mode, modulates a signal based on a sound source signal to output a first modulated signal and a second modulated signal, and, in a second operation mode, modulates a test signal whose frequency is changed within a preset frequency band to output a third modulated signal and a fourth modulated signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency of the test signal at which an impedance of the sound reproduction device reaches a peak; a determination circuit that determines whether or not the peak frequency is included in a reference frequency range that is determined based on the frequency band of the test signal and temperature information that is information related to a temperature of the sound reproduction device in the second operation mode; An electronic device comprising:

Images