Thin-film transistor and x-ray sensor

Abstract

To improve characteristics of a thin-film transistor used in an X-ray sensor.SOLUTION: A thin-film transistor used in an X-ray sensor includes a gate electrode, a semiconductor layer, and a gate insulation layer between the semiconductor layer and the gate electrode. The gate insulation layer includes a first region which forms an interface with the gate electrode, a second region which forms an interface with the semiconductor layer, and a third region between the first region and the second region. An electron trap level density and a hole trap level density of the first region and an electron trap level density and a hole trap level density of the second region are higher than the lower density of an electron trap level density and a hole trap level density of the third region.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present disclosure relates to the structure of thin film transistors used in X-ray sensors. [Background technology]

[0002] The technology of non-destructively inspecting the inside of a specimen using X-ray images has become indispensable in the fields of medicine and industrial non-destructive inspection. In particular, DR (Digital Radiography), which directly captures X-ray images as electronic data, has become widely used due to its speed of interpretation and the aid of interpretation through image processing. DR uses a device called FPD (Flat Panel Detector).

[0003] FPDs used in X-ray sensors are generally classified into direct conversion type and indirect conversion type. Direct conversion type FPDs directly convert X-rays into electrical signals. Indirect conversion type FPDs include an X-ray detection panel with a phosphor (scintillator) that converts X-rays into light, such as visible light or ultraviolet light, and a photoelectric conversion element array that converts the light into electrical signals. FPDs include pixels arranged in an array. Each pixel of the FPD includes a conversion element that converts X-rays or light into an electrical signal, and a switch thin-film transistor for reading out the electrical signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0344517 [Patent Document 2] US Patent Application Publication No. 2008 / 0090341 [Patent Document 3] U.S. Patent No. 10,852,447 Summary of the Invention [Problem to be solved by the invention]

[0005] According to the research of the inventors, it has been found that the switching thin-film transistors used in FPDs can exhibit large characteristic variations in response to X-rays. Specifically, it has been found that when a voltage is applied to the gate electrode in an environment where strong X-rays are irradiated, the ON / OFF characteristics of the thin-film transistor are lost. This is believed to be caused by electrons generated in the gate insulating film by X-ray irradiation flowing into the gate electrode or the semiconductor layer (active layer). [Means for solving the problem]

[0006] A thin film transistor used in an X-ray sensor of an apparatus according to an embodiment of the present disclosure includes a gate electrode, a semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The gate insulating layer includes a first region forming an interface with the gate electrode, a second region forming an interface with the semiconductor layer, and a third region between the first region and the second region. The electron trap state density and the hole trap state density in each of the first region and the second region are higher than the lower one of the electron trap state density and the hole trap state density in the third region.

[0007] A thin film transistor used in an X-ray sensor of an apparatus according to one embodiment of the present disclosure includes a gate electrode, a semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode, the gate insulating layer including a first region forming an interface with the gate electrode and a second region forming an interface with the semiconductor layer, and each of the first region and the second region has substantially the same electron trap state density and hole trap state density.

[0008] A thin film transistor used in an X-ray sensor of an apparatus according to one embodiment of the present disclosure includes a gate electrode, a semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode, the gate insulating layer including a first region forming an interface with the gate electrode, a second region forming an interface with the semiconductor layer, and a third region between the first region and the second region, the third region being made of a material different from that of the first region and the second region, the first region and the second region being made of a nitride. Effect of the Invention

[0009] According to one aspect of the present disclosure, the characteristics of a thin film transistor used in an X-ray sensor can be improved. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an example of the configuration of an X-ray sensor. [Diagram 2] FIG. 2 is a circuit diagram showing an example of an equivalent circuit configuration of a pixel. [Diagram 3] 3 shows a cross-sectional structure of a pixel. [Figure 4] 1 shows a plan view of a pixel. [Diagram 5] FIG. 1 is a cross-sectional view illustrating a thin film transistor structure according to a related art. [Figure 6A] 6 shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of +16 V to a thin film transistor having the structure shown in FIG. 5 while irradiating it with 660 Gy of X-rays. [Figure 6B] 6 shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of -8 V to a thin film transistor having the structure shown in FIG. 5 while irradiating it with 660 Gy of X-rays. [Figure 7] FIG. 1 is a cross-sectional view illustrating a thin film transistor structure according to a related art. [Figure 8A] 8 shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of +16 V to a thin film transistor having the structure shown in FIG. 7 while irradiating it with 660 Gy of X-rays. [Figure 8B] 8 shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of -8 V to a thin film transistor having the structure shown in FIG. 7 while irradiating it with 660 Gy of X-rays. [Figure 9] FIG. 5 shows a band diagram for explaining the characteristic changes described with reference to FIGS. 5-6B. [Figure 10] FIG. 7 shows a band diagram for explaining the characteristic changes described with reference to FIGS. [Figure 11]1 is a cross-sectional view showing a structural example of a switch thin-film transistor according to an embodiment of the present specification. [Figure 12] 12 shows a band diagram of a gate electrode, a gate insulating layer and a semiconductor layer in the thin film transistor structure described with reference to FIG. 11. [Figure 13] 1 is a cross-sectional view illustrating a schematic example of a structure of a switch thin-film transistor of an X-ray sensor according to an embodiment of the present specification. [Figure 14] FIG. 14 is a band diagram for explaining the movement of carriers when the thin film transistor shown in FIG. 13 is irradiated with X-rays. [Figure 15] 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a top gate structure. [Figure 16] FIG. 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. [Figure 17] FIG. 2 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a bottom gate / bottom contact structure. [Figure 18] FIG. 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. [Figure 19] FIG. 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. [Figure 20] FIG. 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. [Figure 21] FIG. 1 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. [Figure 22A] FIG. 2 is a cross-sectional view showing a schematic structure of a thin-film transistor used in an experiment. [Figure 22B] FIG. 13 is a cross-sectional view illustrating a schematic structure of another thin-film transistor used in the experiment. [Figure 22C] The X-ray irradiation conditions for the X-ray irradiation experiment performed on the switching thin-film transistor are shown below. [Figure 23A]22B shows the change in Vg-Id characteristics before and after a gate voltage Vg of +15 V is applied to a thin film transistor having the structure shown in FIG. 22A while the thin film transistor is irradiated with 1000 Gy of X-rays. [Figure 23B] FIG. 22B shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of −15 V to a thin film transistor having the structure shown in FIG. 22A while irradiating it with 1000 Gy of X-rays. [Figure 23C] FIG. 22C shows changes in Vg-Id characteristics before and after a gate voltage Vg of +15 V is applied to a thin film transistor having the structure shown in FIG. 22B while the thin film transistor is irradiated with 1000 Gy of X-rays. [Figure 23D] FIG. 22C shows changes in Vg-Id characteristics before and after applying a gate voltage Vg of −15 V to a thin film transistor having the structure shown in FIG. 22B while irradiating it with 1000 Gy of X-rays. [Figure 24] The results of tests performed by applying various Vg+ or Vg- stresses under X-ray irradiation to a thin film transistor having the structure shown in FIGS. 22A and 22B are shown. [Figure 25A] FIG. 22B is a band diagram for explaining the movement of carriers when a thin film transistor having the structure shown in FIG. 22A is irradiated with X-rays. [Figure 25B] FIG. 22B is a band diagram for explaining the movement of carriers when a thin film transistor having the structure shown in FIG. 22A is irradiated with X-rays. [Figure 26A] FIG. 22C is a band diagram for explaining the movement of carriers when a thin film transistor having the structure shown in FIG. 22B is irradiated with X-rays. [Figure 26B] FIG. 22C is a band diagram for explaining the movement of carriers when a thin film transistor having the structure shown in FIG. 22B is irradiated with X-rays. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the accompanying drawings. The embodiment is merely an example for realizing the present disclosure, and does not limit the technical scope of the present disclosure. For ease of explanation, the dimensions and shapes of the objects illustrated may be exaggerated. <First embodiment>

[0012] 1 is a block diagram showing an example of the configuration of an X-ray sensor. The X-ray sensor 10 is, for example, an image sensor used to capture an X-ray transmission image. The X-ray sensor 10 includes a pixel matrix 101, a scanning circuit 170, and a detection circuit 150. The pixel matrix 101 includes pixels 102 arranged in a matrix. The pixel matrix 101 is formed on a sensor substrate 100. The sensor substrate 100 is an insulating substrate (for example, a glass substrate).

[0013] The pixels 102 are disposed at each intersection of a plurality of signal lines 106 extending vertically and arranged horizontally in Fig. 1 and a plurality of gate lines (scanning lines) 105 extending horizontally and arranged vertically. The pixels 102 are each connected to a bias line 107 extending vertically and arranged horizontally in Fig. 1. In Fig. 1, only one pixel, one signal line, one gate line and one bias line are indicated by the reference characters 102, 106, 105 and 107, respectively.

[0014] Each of the signal lines 106 is connected to a different pixel column. Each of the gate lines 105 is connected to a different pixel row. The signal lines 106 are connected to a detection circuit 150, and the gate lines are connected to a scanning circuit 170. The bias line 107 is connected to a common bias line 108. A bias potential is applied to a pad 109 of the common bias line 108.

[0015] 2 is a circuit diagram showing an example of an equivalent circuit configuration of a pixel 102. The pixel 102 includes a photodiode 103 which is a photoelectric conversion element, and a thin film transistor (TFT) 104 which is a switching element. The gate of the thin film transistor 104 is connected to a gate line 105, one of the source / drain is connected to a signal line 106, and the other of the source / drain is connected to a cathode of the photodiode 103. In the example of FIG. 2, the anode of the photodiode 103 is connected to a bias line 107.

[0016] The thin film transistor 104 is, for example, an a-Si (amorphous silicon) thin film transistor, an oxide semiconductor thin film transistor, or a polysilicon thin film transistor. In the configuration example shown in FIG. 2, the thin film transistor 104 is of n-type conductivity. The thin film transistor may have other conductivity types. In the following, the thin film transistor 104 is assumed to be an oxide semiconductor thin film transistor. The oxide semiconductor thin film transistor exhibits excellent switching characteristics.

[0017] The X-ray sensor 10 reads out a signal by externally extracting a signal charge stored in the photodiode 103 in accordance with the amount of X-ray irradiation by turning on the thin film transistor 104 arranged in the pixel 102. Specifically, when light is incident on the photodiode 103, a signal charge is generated and accumulated in the photodiode 103.

[0018] The scanning circuit 170 sequentially selects the gate lines 105 and applies a pulse that turns on the thin film transistor 104. The anode terminal of the photodiode 103 is connected to the bias line 107, and a reference potential is applied to the signal line 106 by the detection circuit 150. Therefore, the photodiode 103 is charged with a differential voltage between the bias potential of the bias line 107 and the reference potential. This differential voltage is set to a reverse bias voltage in which the cathode potential is higher than the anode potential.

[0019] The charge required to recharge the photodiode 103 to this reverse bias voltage depends on the amount of light incident on the photodiode 103. The detection circuit 150 reads out the signal charge by integrating the current that flows as the photodiode 103 is recharged to the reverse bias.

[0020] The charge stored in the photodiode 103 inevitably decreases due to reduction in charge caused by irradiated light and due to a dark leakage current that flows even when the photodiode 103 is not irradiated with light, so that in reading out the signal charge, the voltage of the terminal of the thin film transistor 104 connected to the signal line 106 is equal to or higher than the voltage of the terminal connected to the photodiode 103. In other words, in detecting the signal charge, the terminal of the thin film transistor 104 connected to the signal line 106 is the drain, and the terminal connected to the photodiode 103 is the source.

[0021] Fig. 3 shows the cross-sectional structure of a pixel. In the following description, the side of the X-ray sensor 10 on which the measurement target is placed is called the front side. In the example of Fig. 3, the opposite side of the sensor substrate 100 from the photodiode 103 is the front side. In addition, in terms of the positional relationship of the components of the pixel, the sensor substrate 100 side is called the lower side, and the opposite side is called the upper side.

[0022] The thin film transistor 104 and the photodiode 103 included in the pixel each have a stacked structure. The thin film transistor 104 includes a gate electrode 302 formed on an insulating sensor substrate 100, a gate insulating layer 303 on the gate electrode 302, and an oxide semiconductor layer 304 on the gate insulating layer 303.

[0023] 3 has a bottom gate structure, and a gate electrode 302 is present below an oxide semiconductor layer 304. The thin film transistor 104 further includes a source / drain electrode 305 and a source / drain electrode 306 on a gate insulating layer 303. The source / drain electrodes 305 and 306 are each connected to the oxide semiconductor layer 304. The source / drain electrodes 305 and 306 are formed so as to contact the side surfaces and a part of the upper surface of the island-shaped oxide semiconductor layer 304.

[0024] Depending on the carrier flow, one of the source / drain electrodes 305 and 306 is the source electrode and the other is the drain electrode. In detecting charges in the photodiode 103, the electrode 305 is the drain electrode and the electrode 306 is the source electrode.

[0025] The gate insulating layer 303 is formed so as to cover the entire surface of the gate electrode 302. The gate insulating layer 303 is formed between the gate electrode 302 and the oxide semiconductor layer 304, and between the gate electrode 302 and each of the source / drain electrodes 305 and 306.

[0026] The first interlayer insulating layer 307 covers the entire thin film transistor 104. Specifically, the first interlayer insulating layer 307 covers the upper surface of the oxide semiconductor layer 304 and the upper surfaces of the source / drain electrodes 305 and 306.

[0027] The sensor substrate 100 is formed of, for example, glass or resin. The gate electrode 302 is a conductor and can be formed of metal or impurity-doped silicon. The gate insulating layer 303 has a single-layer or multi-layer structure. Each layer of the gate insulating layer 303 may be formed of, for example, silicon oxide (SiOx) or silicon nitride (SiNx). The gate insulating layer 303 will be described in detail later.

[0028] The oxide semiconductor constituting the oxide semiconductor layer 304 is an oxide semiconductor containing at least one of In, Ga, and Zn, and examples thereof include amorphous InGaZnO (a-InGaZnO) and microcrystalline InGaZnO. In addition, oxide semiconductors such as a-InSnZnO and a-InGaZnSnO can be used. In the examples described below, amorphous or microcrystalline InGaZnO (hereinafter, these are also referred to as IGZO) is mainly used.

[0029] The source / drain electrodes 305 and 306 are conductors and can be formed of, for example, a metal such as Mo, Ti, Al, or Cr, an alloy thereof, or a laminate thereof. The first interlayer insulating layer 307 is an inorganic or organic insulator. The thin film transistor 104 shown in FIG. 3 has a bottom gate structure, but may have a top gate structure instead.

[0030] A photodiode 103 is formed on the first interlayer insulating layer 307. An example of the photodiode 103 shown in FIG. 3 is a PIN diode. A PIN diode can detect light efficiently by forming a wide depletion layer in the film thickness direction. The photodiode 103 includes a semiconductor laminate sandwiched between a lower electrode 308 and an upper electrode 312 on the first interlayer insulating layer 307. The lower electrode 308 is connected to the source / drain electrodes 306 of the thin film transistor 104 through an interconnection portion of a via hole 321 in the first interlayer insulating layer 307.

[0031] The lower electrode 308 is a conductor and can be formed of, for example, a metal such as Cr, Mo, or Al, an alloy thereof, or a laminate thereof. The upper electrode 312 is an electrode that is transparent to the light from the scintillator 316 and is, for example, ITO.

[0032] Photodiode 103 includes an n-type amorphous silicon layer 309 on a lower electrode 308, an intrinsic amorphous silicon layer 310 on n-type amorphous silicon layer 309, and a p-type amorphous silicon layer 311 on intrinsic amorphous silicon layer 310. An upper electrode 312 is formed on p-type amorphous silicon layer 311. Light to be detected is incident on photodiode 103 from the upper electrode 312 side (p-type amorphous silicon layer 311 side).

[0033] A second interlayer insulating layer 313 is formed to cover the photodiode 103. Specifically, the second interlayer insulating layer 313 is formed on the first interlayer insulating layer 307, a part of the lower electrode 308, and the upper electrode 312. The second interlayer insulating layer 313 is an inorganic or organic insulator.

[0034] The bias line 107 is formed on the second interlayer insulating layer 313. The bias line 107 is connected to the upper electrode 312 by an interconnection formed in a via hole 322 of the second interlayer insulating layer 313. The bias line 107 is a conductor, and can be formed of, for example, a metal such as Mo, Ti, or Al, an alloy thereof, or a laminate thereof.

[0035] A passivation layer 315 is formed so as to cover the bias line 107 and the second interlayer insulating layer 313. The passivation layer 315 covers the entire area of ​​the pixel matrix 101. The passivation layer 315 is an inorganic or organic insulator. A scintillator 316 is disposed on the passivation layer 315.

[0036] The scintillator 316 covers the entire area of ​​the pixel matrix 101. The scintillator 316 emits light when excited by radiation. Specifically, the scintillator 316 converts incident X-rays into light of a wavelength that is detected by the photodiode 103. The photodiode 103 accumulates signal charges in response to the light from the scintillator 316.

[0037] 4 shows a plan view of the pixel 102. As shown in FIG. 4, the gate line 105 extends in the left-right direction in the figure, and the signal line 106 extends in the up-down direction in the figure. The gate electrode 302 is continuous with the gate line 105, and they are part of a continuous metal film. The gate electrode 302 protrudes from the gate line 105 in a direction perpendicular to the direction in which the gate line 105 extends.

[0038] The source / drain electrodes 305 of the thin film transistor are continuous with the signal line 106 and are part of a continuous metal film. The source / drain electrodes 305 protrude from the signal line 106 in a direction perpendicular to the direction in which the signal line 106 extends. The source / drain electrodes 306 are island electrodes and are spaced apart from the source / drain electrodes 305.

[0039] The oxide semiconductor layer 304 is disposed so as to overlap the gate electrode 302 in a plan view, with a source / drain electrode 305 disposed on one side and a source / drain electrode 306 disposed on the opposing side. The source / drain electrode 306 partially overlaps with a lower electrode 308 of the photodiode 103 and is connected through a via hole 321.

[0040] 4, the entire area of ​​the upper electrode 312 of the photodiode 103 is present within the area of ​​the lower electrode 308 in a plan view. The bias line 107 extends in the vertical direction of the figure. A part of the bias line 107 overlaps with the upper electrode 312 and is connected to the upper electrode 312 through a via hole 322.

[0041] 1 to 4 show a photodiode as an element that converts electromagnetic waves into an electrical signal, but other types of elements may be used. For example, an element that can directly convert X-rays into an electrical signal without using a scintillator may be used.

[0042] One of the features of an embodiment of the present specification is the structure of a switch thin-film transistor in a pixel of an X-ray sensor. The structure of a thin-film transistor according to an embodiment of the present specification will be described below. Several characteristics are required for a switch thin-film transistor used in an X-ray sensor. These include high X-ray resistance (high reliability) in addition to high current driving capability (low delay) and low leakage current characteristics (low noise).

[0043] According to the inventors' research, it has been found that the structure of the gate insulating layer of a switch thin-film transistor affects the reliability of the thin-film transistor under X-ray irradiation. It has been found that the switch thin-film transistor can exhibit large characteristic variations in response to X-rays. Specifically, it has been found that when a voltage is applied to the gate electrode in an environment where it is irradiated with strong X-rays, the ON / OFF characteristics of the thin-film transistor are lost. This is thought to be caused by electrons generated in the gate insulating film by X-ray irradiation flowing into the gate electrode or the semiconductor layer (active layer).

[0044] First, a thin film transistor structure that may show a large change in switching characteristics due to X-ray irradiation will be described. FIG. 5 is a cross-sectional view that shows a schematic diagram of a thin film transistor structure according to the related art. A switch thin film transistor 410 includes a gate electrode 412, a gate insulating layer 413 on the gate electrode 412, and an oxide semiconductor layer 414 on the gate insulating layer 413. The oxide semiconductor layer 414 is made of IGZO. An interlayer insulating layer 417 covers the entire thin film transistor 410.

[0045] In the configuration example shown in FIG. 5, the gate insulating layer 413 has a two-layer structure and is composed of a lower insulating layer 418 made of silicon oxide (SiOx) and an upper insulating layer 419 made of silicon nitride (SiNx) on the lower insulating layer 418.

[0046] The thin film transistor 410 has a bottom gate structure, and the gate electrode 412 is located below the oxide semiconductor layer 414. The thin film transistor 410 further includes a source / drain electrode 415 and a source / drain electrode 416 on the gate insulating layer 413. The source / drain electrodes 415 and 416 are connected to the oxide semiconductor layer 414, respectively.

[0047] 6A shows the change in Vg-Id characteristic before and after applying a gate voltage Vg of +16V to the thin film transistor 410 having the structure shown in FIG. 5 while irradiating it with 660Gy of X-rays. The horizontal axis of the graph shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd was 10V.

[0048] In the graph of FIG. 6A, the dashed line indicates the Vg-Id characteristic before applying the Vg+ stress to the thin film transistor 410 under X-ray irradiation. The solid line indicates the measurement result of the Vg-Id characteristic after applying the Vg+ stress to the thin film transistor 410 under X-ray irradiation. As can be seen from the characteristic change in FIG. 6A, before applying the Vg+ stress under X-ray irradiation, the thin film transistor 410 is appropriately turned ON / OFF according to the change in the gate voltage. On the other hand, when the Vg+ stress is applied to the thin film transistor 410 under X-ray irradiation, the thin film transistor 410 does not change to the OFF state.

[0049] 6B shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of -8V to the thin film transistor 410 having the structure shown in FIG. 5 while irradiating it with 660Gy of X-rays. The horizontal axis of the graph shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd was 10V.

[0050] In the graph of Fig. 6B, the dashed line indicates the Vg-Id characteristic before applying the Vg-stress to the thin film transistor 410 under the above-mentioned X-ray irradiation. The solid line indicates the Vg-Id characteristic after applying the Vg-stress to the thin film transistor 410 under the above-mentioned X-ray irradiation. As can be seen from the characteristic change in Fig. 6B, the threshold voltage changes slightly before and after applying the Vg-stress under the X-ray irradiation, but the thin film transistor 410 is appropriately turned ON / OFF in response to the change in the gate voltage.

[0051] Another example of a thin film transistor structure that may exhibit a large change in switching characteristics due to X-ray irradiation will be described. FIG. 7 is a cross-sectional view that shows a schematic diagram of a thin film transistor structure according to the related art. A switch thin film transistor 430 includes a gate electrode 432, a gate insulating layer 433 on the gate electrode 432, and an oxide semiconductor layer 434 on the gate insulating layer 433. The oxide semiconductor layer 434 is made of IGZO. An interlayer insulating layer 437 covers the entire thin film transistor 430.

[0052] In the configuration example shown in FIG. 7, the gate insulating layer 433 has a two-layer structure and is composed of a lower insulating layer 438 made of silicon nitride (SiNx) and an upper insulating layer 439 made of silicon oxide (SiOx) on the lower insulating layer 438.

[0053] The thin film transistor 430 has a bottom gate structure, and the gate electrode 432 is located below the oxide semiconductor layer 434. The thin film transistor 430 further includes a source / drain electrode 435 and a source / drain electrode 436 on the gate insulating layer 433. The source / drain electrodes 435 and 436 are connected to the oxide semiconductor layer 434, respectively.

[0054] 8A shows the change in Vg-Id characteristic before and after applying a gate voltage Vg of +16V to the thin film transistor 430 having the structure shown in FIG. 7 while irradiating it with 660Gy of X-rays. The horizontal axis of the graph shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd was 10V.

[0055] In the graph of Fig. 8A, the dashed line indicates the Vg-Id characteristic before applying the Vg+ stress to the thin film transistor 430 under the above-mentioned X-ray irradiation. The solid line indicates the Vg-Id characteristic after applying the Vg+ stress to the thin film transistor 430 under the above-mentioned X-ray irradiation. As can be seen from the characteristic change in Fig. 8A, the threshold voltage changes slightly before and after applying the Vg- stress under the X-ray irradiation, but the thin film transistor 430 is appropriately turned ON / OFF in response to the change in the gate voltage.

[0056] 8B shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of -8V to the thin film transistor 430 having the structure shown in FIG. 7 while irradiating it with 660Gy of X-rays. The horizontal axis of the graph shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd was 10V.

[0057] In the graph of FIG. 8B, the dashed line indicates the Vg-Id characteristic before applying the Vg-stress to the thin film transistor 430 under the above-mentioned X-ray irradiation. The solid line indicates the measurement result of the Vg-Id characteristic after applying the Vg-stress to the thin film transistor 430 under the above-mentioned X-ray irradiation. As can be seen from the characteristic change in FIG. 8B, before applying the Vg-stress under the X-ray irradiation, the thin film transistor 430 is appropriately turned ON / OFF according to the change in the gate voltage. On the other hand, when the Vg-stress is applied to the thin film transistor 430 under the X-ray irradiation, the thin film transistor 430 does not change to the OFF state.

[0058] From the study of the above two examples, it was found that the trap level density of electrons (e) and holes (h) (which are sometimes collectively called carriers) in the gate insulating layer is one of the major causes of the change in the switching characteristics of thin film transistors. Specifically, silicon oxide and silicon nitride have many hole trap levels (high hole trap level density). Also, silicon nitride has many electron trap levels (high electron trap level density). On the other hand, the electron trap levels of silicon oxide are very few compared to the hole trap levels or the electron trap levels of silicon nitride. Therefore, it is presumed that the above problem is caused by electrons (e) excited in silicon oxide (SiOx) flowing to the gate electrode or semiconductor active layer, which causes the charge balance in the gate insulating layer to be lost.

[0059] FIG. 9 shows a band diagram for explaining the characteristic changes described with reference to FIGS. 5-6B. The band diagram 601 shows the change in the characteristic when a positive gate voltage ( 1 shows the electron energy levels in the gate electrode 412, the gate insulating layer 413, and the oxide semiconductor layer 414 when a voltage (Vg + stress) is applied to the thin film transistor 410. Ec indicates the lower end of the conduction band level of the semiconductor layer or the insulating film, Ev indicates the upper end of the valence band level of the semiconductor layer or the insulating film, and Ef indicates the Fermi level of the metal layer. The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are shown to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0060] Electrons (e) generated in the lower silicon oxide layer 418 pass through the gate electrode 412, which has a lower energy level. Holes (h) generated in the silicon oxide layer 418 are trapped in the hole trap level in the silicon oxide layer 418.

[0061] Electrons (e) generated in the upper silicon nitride layer 419 are trapped in the electron trap level in the silicon nitride layer 419. Holes (h) generated in the silicon nitride layer 419 are trapped in the hole trap level in the silicon nitride layer 419.

[0062] As described above, since only electrons escape to the gate electrode 412, the number of positive ions in the gate insulating layer 413 becomes greater than the number of negative ions. As a result, the threshold voltage Vth of the thin film transistor 410 is significantly shifted to the negative side. As a result, the switching characteristics of the thin film transistor 410 are lost.

[0063] The band diagram 602 shows the electron energy levels in the gate electrode 412, the gate insulating layer 413, and the oxide semiconductor layer 414 when a negative gate voltage (Vg-stress) is applied to the thin film transistor 410 under X-ray irradiation as described with reference to Fig. 6B. Ec, Ev, and Ef are the same as those in 601. The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are illustrated to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0064] Electrons (e) generated in the lower silicon oxide layer 418 move to the upper silicon nitride layer 419, which has a lower energy level, and are trapped in the electron trap level in the silicon nitride layer 419. Holes (h) generated in the silicon oxide layer 418 are trapped in the hole trap level in the silicon oxide layer 418.

[0065] Electrons (e) generated in the upper silicon nitride layer 419 are trapped in the electron trap level in the silicon nitride layer 419. Holes (h) generated in the silicon nitride layer 419 are trapped in the hole trap level in the silicon nitride layer 419.

[0066] As described above, the number of positive ions and negative ions in the gate insulating layer 413 is balanced because the electrons and holes are trapped in the trap levels in the gate insulating layer 413. The threshold voltage Vth of the thin film transistor 410 is not substantially changed. In practice, a small change in the threshold voltage Vth may occur, but the proper switching characteristics of the thin film transistor 410 are maintained.

[0067] Next, the characteristic changes described with reference to Fig. 7-8B will be described. Fig. 10 shows a band diagram for explaining the characteristic changes described with reference to Fig. 7-8B. A band diagram 621 shows the electron energy levels in the gate electrode 432, the gate insulating layer 433, and the oxide semiconductor layer 434 when a positive gate voltage (Vg+stress) is applied to the thin film transistor 430 under X-ray irradiation as described with reference to Fig. 8A. Ec, Ev, and Ef are the same as 601 and 602 in Fig. 9. Also, the band gaps of silicon oxide, silicon nitride, and oxide semiconductor are illustrated to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0068] Electrons (e) generated in the upper silicon oxide layer 439 move to the lower silicon nitride layer 438, which has a lower energy level, and are trapped in the electron trap level in the silicon nitride layer 438. Holes (h) generated in the silicon oxide layer 439 are trapped in the hole trap level in the silicon oxide layer 439.

[0069] Electrons (e) generated in the lower silicon nitride layer 438 are trapped in the electron trap level in the silicon nitride layer 438. Holes (h) generated in the silicon nitride layer 438 are trapped in the hole trap level in the silicon nitride layer 438.

[0070] As described above, the number of positive ions and negative ions in the gate insulating layer 433 is balanced because the electrons and holes are trapped in the trap levels in the gate insulating layer 433. The threshold voltage Vth of the thin film transistor 430 is not substantially changed. In practice, a small change in the threshold voltage Vth may occur, but the proper switching characteristics of the thin film transistor 430 are maintained.

[0071] The band diagram 622 shows the electron energy levels in the gate electrode 432, the gate insulating layer 433, and the oxide semiconductor layer 434 when a negative gate voltage (Vg-stress) is applied to the thin film transistor 430 under X-ray irradiation as described with reference to Fig. 8B. Ec, Ev, and Ef are the same as 601 and 602 in Fig. 9 and 621 in Fig. 10. The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are illustrated to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0072] Electrons (e) generated in the upper silicon oxide layer 439 pass through the oxide semiconductor layer (active layer) 434, which has a lower energy level. Holes (h) generated in the silicon oxide layer 439 are trapped in the hole trap level in the silicon oxide layer 439.

[0073] Electrons (e) generated in the lower silicon nitride layer 438 are trapped in the electron trap level in the silicon nitride layer 438. Holes (h) generated in the silicon nitride layer 438 are trapped in the hole trap level in the silicon nitride layer 438.

[0074] As described above, since only electrons escape to the oxide semiconductor layer 434, the number of positive ions in the gate insulating layer 433 becomes greater than the number of negative ions. As a result, the threshold voltage Vth of the thin film transistor 430 is significantly shifted to the negative side. As a result, the switching characteristics of the thin film transistor 430 are lost.

[0075] From the above viewpoint, the gate insulating layer of the thin film transistor according to an embodiment of the present specification has an electron trap level and a hole trap level in both a region forming an interface with the gate electrode and a region forming an interface with the semiconductor layer (active layer), thereby preventing carriers (electrons or holes) from being released from the gate insulating layer to the gate electrode or the semiconductor layer, and reducing deterioration of the switching characteristics of the thin film transistor.

[0076] The electron trap level density and hole trap level density of each region are large enough to trap electrons and holes generated in the gate insulating layer by X-ray irradiation and prevent the electrons or holes from passing through to the gate electrode or the semiconductor layer, so that the loss of the switching characteristics of the thin film transistor can be more reliably prevented. The electron trap level density and hole trap level density are, for example, 7e11cm -2 eV -1 That's all. The inventors obtained this value from the study of silicon nitride SiNx. The trap level density value of the region of the gate insulating layer that forms an interface with the semiconductor layer or the gate electrode can be appropriately determined according to the design of the corresponding thin film transistor.

[0077] 11 is a cross-sectional view showing an example of the structure of a switch thin-film transistor according to an embodiment of the present specification. The thin-film transistor 500 includes a gate electrode 502, a gate insulating layer 503 on the gate electrode 502, and a semiconductor layer 504 on the gate insulating layer 503. The semiconductor layer 504 may be an oxide semiconductor, amorphous silicon, or polysilicon. An interlayer insulating layer 507 covers the entire thin-film transistor 500.

[0078] 11, the gate insulating layer 503 has a three-layer structure and is composed of a lower insulating layer 511, an intermediate insulating layer 512 on the lower insulating layer 511, and an upper insulating layer 513 on the intermediate insulating layer 512. These are the lower region, upper region, and intermediate region of the gate insulating layer 503. The intermediate insulating layer 512 contacts the lower insulating layer 511 and the upper insulating layer 513 to form an interface. In the gate insulating layer 503, the lower insulating layer 511 forms an interface with the gate electrode 502, and the upper insulating layer 513 forms an interface with the semiconductor layer 504.

[0079] The thin film transistor 500 has a bottom gate structure, and the gate electrode 502 is present below the semiconductor layer 504. The thin film transistor 500 further includes a source / drain electrode 505 and a source / drain electrode 506 on a gate insulating layer 503. The source / drain electrodes 505 and 506 are each connected to the semiconductor layer 504. The gate electrode 502, the source / drain electrodes 505 and 506, and the interlayer insulating layer 507 can be described with reference to FIG. 3 or 4 with respect to the components having the same names.

[0080] In the gate insulating layer 503, both the electron trap state density and the hole trap state density of the lower insulating layer 511 are higher than the lower one of the electron trap state density and the hole trap state density of the intermediate insulating layer 512. Similarly, both the electron trap state density and the hole trap state density of the upper insulating layer 513 are higher than the lower one of the electron trap state density and the hole trap state density of the intermediate insulating layer 512.

[0081] For example, the electron trap state density of the intermediate insulating layer 512 is lower than the hole trap state density. The electron trap state density and the hole trap state density of the lower insulating layer 511 and the upper insulating layer 513 are both higher than the electron trap state density of the intermediate insulating layer 512.

[0082] The lower insulating layer 511 and the upper insulating layer 513 trap, at their trap levels, the electrons and holes generated therein by X-ray irradiation, as well as the electrons or holes generated and moved in the intermediate insulating layer 512. This reduces the shift in threshold voltage Vth of the thin film transistor 500 caused by the movement of electrons and / or holes from the gate insulating layer 503 to the gate electrode 502 or the semiconductor layer 504, and prevents loss of switching characteristics.

[0083] There are various materials known for use as gate insulating layers in thin-film transistor switches for X-ray sensors, but the hole trap level density of typical gate insulating materials is large enough to trap holes generated in the material by X-ray irradiation and prevent them from moving to adjacent layers. On the other hand, some materials, such as silicon oxide SiOx, have a low electron trap level density. Therefore, the upper and lower insulating layers can be formed of materials with a higher electron trap level density than the intermediate insulating layer.

[0084] For example, the lower insulating layer 511 has a thickness of 100 nm or more, and the upper insulating layer 513 has a thickness of 20 nm or more. In other structures, the insulating layer that forms an interface with the gate electrode may have a thickness of 100 nm or more, and the insulating layer that forms an interface with the semiconductor layer may have a thickness of 20 nm or more.

[0085] FIG. 12 shows a band diagram of the gate electrode 502, the gate insulating layer 503, and the semiconductor layer 504 in the thin film transistor structure described with reference to FIG. 11. The solid arrow indicates the direction of carrier movement when a positive gate voltage is applied. The dashed arrow indicates the direction of carrier movement when a negative gate voltage is applied. Ec indicates the lower end of the conduction band level of the semiconductor layer 504, the upper insulating layer 513, the intermediate insulating layer 512, and the lower insulating layer 511, Ev indicates the upper end of the valence band level of the semiconductor layer 504, the upper insulating layer 513, the intermediate insulating layer 512, and the lower insulating layer 511, and Ef indicates the Fermi level of the gate electrode 502 (metal layer). In addition, the band gaps of silicon oxide, silicon nitride, and oxide semiconductor are illustrated to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0086] As described above, the lower insulating layer 511 and the upper insulating layer 513 have higher electron trap state density and hole trap state density than the lower carrier trap state density of the intermediate insulating layer 512. Therefore, electrons (e) and holes (h) induced by X-rays are trapped before flowing into the gate electrode 502 or the semiconductor layer 504, and the threshold voltage shift due to X-ray irradiation can be reduced.

[0087] The material of the intermediate insulating layer 512 is different from that of the lower insulating layer 511 and the upper insulating layer 513. The materials of the lower insulating layer 511 and the upper insulating layer 513 may be the same or different. There may be a plurality of intermediate insulating layers between the lower insulating layer 511 and the upper insulating layer 513. Between at least one intermediate insulating layer or each intermediate insulating layer and the lower insulating layer 511 and the upper insulating layer 513, the relationship between the intermediate insulating layer 512 and the lower insulating layer 511 and the upper insulating layer 513 is established.

[0088] 5 to 10, the electron trap state density of silicon oxide is much smaller than the hole trap state density, which may cause a large shift in the threshold voltage of the thin film transistor. The thin film transistor of the X-ray sensor according to an embodiment of the present specification has substantially the same electron trap state density and hole trap state density in the region of the gate insulating layer that forms an interface with the semiconductor layer and the region that forms an interface with the gate electrode.

[0089] For example, in a three-layer gate insulating layer, the lower insulating layer and the upper insulating layer may have substantially the same electron trap level density and hole trap level density, so that electrons and holes induced by X-rays are trapped before flowing into the gate electrode or the semiconductor layer, and the threshold voltage shift due to X-ray irradiation is reduced.

[0090] A gate insulating material having a high hydrogen concentration has a high electron trap level density and hole trap level density. In the thin film transistor of the X-ray sensor according to an embodiment of the present specification, the hydrogen concentration of the insulating layer forming an interface with the gate electrode is higher than that of the intermediate insulating layer. Similarly, the hydrogen concentration of the insulating layer forming an interface with the semiconductor layer is higher than that of the intermediate insulating layer. For example, the insulating layer forming an interface with the gate electrode or the semiconductor layer has a hydrogen concentration of 3.4e22 [atoms / cc] or more. The intermediate insulating layer has a hydrogen concentration of 1.2e21 [atoms / cc] or less.

[0091] The above-mentioned configuration of the gate insulating layer, that is, the relationship between the carrier trap level densities of the upper and lower insulating layers and the intermediate insulating layer, the relationship between the electron trap level densities and the hole trap level densities in the upper and lower insulating layers, and the relationship between the hydrogen concentrations, may be satisfied in any one, any partial combination, or all of them in the gate insulating layer. This also applies to the configuration described below.

[0092] 13 is a cross-sectional view showing a schematic structure example of a switch thin-film transistor of an X-ray sensor according to an embodiment of the present specification. The thin-film transistor 520 includes a gate electrode 522, a gate insulating layer 523 on the gate electrode 522, and a semiconductor layer 524 on the gate insulating layer 523. The semiconductor layer 524 may be an oxide semiconductor, amorphous silicon, or polysilicon. An interlayer insulating layer 527 covers the entire thin-film transistor 520.

[0093] 13, the gate insulating layer 523 has a three-layer structure, and is composed of a lower silicon nitride (SiNx) layer 531, a silicon oxide (SiOx) layer 532 on the lower silicon nitride layer 531, and an upper silicon nitride layer 533 on the silicon oxide layer 532. These are the lower region, upper region, and middle region of the gate insulating layer 523.

[0094] The silicon oxide layer 532, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 531 and the upper silicon nitride layer 533. In the gate insulating layer 523, the lower silicon nitride layer 531 forms an interface with the gate electrode 522, and the upper silicon nitride layer 533 forms an interface with the semiconductor layer 524.

[0095] The thin film transistor 520 has a bottom gate structure, and the gate electrode 522 is present below the semiconductor layer 524. The thin film transistor 520 further includes a source / drain electrode 525 and a source / drain electrode 526 on the gate insulating layer 523. The source / drain electrodes 525 and 526 are each connected to the semiconductor layer 524. The gate electrode 522, the source / drain electrodes 525 and 526, and the interlayer insulating layer 527 can be described with reference to FIG. 3 or 4 with respect to the components having the same names.

[0096] 5 to 10, the silicon nitride layer has both the electron trapping level and the hole trapping level, and can trap electrons that have moved from the silicon oxide layer in addition to electrons and holes that have been generated in the silicon nitride layer. The lower silicon nitride layer 531 and the upper silicon nitride layer 533 trap the electrons that have been generated in the silicon oxide layer 532 by X-ray irradiation and moved therefrom before they move to the semiconductor layer 524 or the gate electrode 522. This can reduce the threshold voltage Vth shift of the thin film transistor 520 and prevent the loss of switching characteristics.

[0097] FIG. 14 shows a band diagram for explaining the movement of carriers when the thin film transistor 520 shown in FIG. 13 is irradiated with X-rays. The band diagram 641 shows the electron energy levels in the gate electrode 522, the gate insulating layer 523, and the oxide semiconductor layer 524 when a positive gate voltage is applied to the thin film transistor 520 under X-ray irradiation. Ec shows the lower end of the conduction band level of the semiconductor layer 524, the upper insulating layer 533, the intermediate insulating layer 532, and the lower insulating layer 531, Ev shows the upper end of the valence band level of the semiconductor layer 524, the upper insulating layer 533, the intermediate insulating layer 532, and the lower insulating layer 531, and Ef shows the Fermi level of the gate electrode 522 (metal layer). The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are shown to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0098] Electrons (e) generated by X-rays in the lower silicon nitride layer 531 are trapped in the electron trap level in the lower silicon nitride layer 531. Holes (h) generated in the lower silicon nitride layer 531 are trapped in the hole trap level of the lower silicon nitride layer 531.

[0099] Similarly, electrons (e) generated in the upper silicon nitride layer 533 by X-rays are trapped in the electron trap level in the upper silicon nitride layer 533. Holes (h) generated in the upper silicon nitride layer 533 are trapped in the hole trap level of the upper silicon nitride layer 533.

[0100] Electrons (e) generated in the silicon oxide layer 532 by X-rays move to the lower silicon nitride layer 531, which has a lower energy level, and are trapped in the electron trap level of the lower silicon nitride layer 531. Holes (h) generated in the silicon oxide layer 532 are trapped in the hole trap level in the silicon oxide layer 532.

[0101] The band diagram 642 shows the electron energy levels in the gate electrode 522, the gate insulating layer 523, and the oxide semiconductor layer 524 when a negative gate voltage is applied to the thin film transistor 520 under X-ray irradiation. The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are shown to be approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0102] Electrons (e) generated by X-rays in the lower silicon nitride layer 531 are trapped in the electron trap level in the lower silicon nitride layer 531. Holes (h) generated in the lower silicon nitride layer 531 are trapped in the hole trap level of the lower silicon nitride layer 531.

[0103] Similarly, electrons (e) generated in the upper silicon nitride layer 533 by X-rays are trapped in the electron trap level in the upper silicon nitride layer 533. Holes (h) generated in the upper silicon nitride layer 533 are trapped in the hole trap level of the upper silicon nitride layer 533.

[0104] Electrons (e) generated in the silicon oxide layer 532 by X-rays move to the upper silicon nitride layer 533, which has a lower energy level, and are trapped in the electron trap level of the upper silicon nitride layer 533. Holes (h) generated in the silicon oxide layer 532 are trapped in the hole trap level in the silicon oxide layer 532.

[0105] As described above, since the electrons and holes are trapped in the trap levels in the gate insulating layer 523, the number of positive ions and negative ions in the gate insulating layer 523 is balanced. The threshold voltage Vth of the thin film transistor 520 is substantially unchanged. The proper switching characteristics of the thin film transistor 520 are maintained.

[0106] In the configuration example shown in FIG. 13, various insulating materials can be applied to the gate insulating layer 523. As the material of the upper insulating layer and / or the lower insulating layer, insulating nitrides such as aluminum nitride (AlNx), gallium nitride (GaNx), or indium nitride (InNx) may be used instead of silicon nitride (silicon nitride). The gate insulating layer may have a single layer structure. Also, as the material of the intermediate insulating layer, insulating oxides such as silicon oxynitride (SiON) or aluminum oxide (AlOx) may be used instead of silicon oxide (silicon oxide). In addition, as the material of the intermediate insulating layer, any insulating material applicable to the switch thin film transistor of the X-ray sensor can be used.

[0107] Other gate structure examples of the switch thin film transistor are described below. The thin film transistor in the above example has a bottom gate structure. In other examples, the thin film transistor may have a top gate structure or a dual gate structure having a top gate and a bottom gate. The description of the materials and structures of the gate insulating layer and the materials of other components described for the thin film transistor with the bottom gate structure above can be applied to thin film transistors with other gate structures.

[0108] 15 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a top gate structure. A thin-film transistor 700 includes a semiconductor layer 704, a gate insulating layer 703 on the semiconductor layer 704, and a gate electrode 702 on the gate insulating layer 703. The semiconductor layer 704 may be an oxide semiconductor, amorphous silicon, or polysilicon.

[0109] In the configuration example shown in FIG. 15, the gate insulating layer 703 has a three-layer structure, which is composed of a lower silicon nitride layer 711, a silicon oxide layer 712 on the lower silicon nitride layer 711, and an upper silicon nitride layer 713 on the silicon oxide layer 712.

[0110] The silicon oxide layer 712, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 711 and the upper silicon nitride layer 713. In the gate insulating layer 703, the lower silicon nitride layer 711 forms an interface with the semiconductor layer 704, and the upper silicon nitride layer 713 forms an interface with the gate electrode 702.

[0111] The thin film transistor 700 has a top gate structure, and the gate electrode 702 is present on the upper side of the semiconductor layer 704. The thin film transistor 700 further includes a source / drain electrode 705 and a source / drain electrode 706. The source / drain electrodes 705 and 706 are connected to the semiconductor layer 704 through an interlayer insulating layer 707 and a gate insulating layer 703, respectively. The above description with reference to the thin film transistor with a bottom gate structure can be applied to the gate insulating layer 703. In addition, the description of the gate electrode 702, the source / drain electrodes 705 and 706, and the interlayer insulating layer 707 can be applied to the components with the same names described with reference to FIG. 3 or 4.

[0112] 16 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. The thin-film transistor 720 includes a gate electrode 722, a gate insulating layer 723 on the gate electrode 722, and a semiconductor layer 724 on the gate insulating layer 723. The semiconductor layer 724 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin-film transistor 720 further includes a gate insulating layer 743 on the semiconductor layer 724, and a gate electrode 762 on the gate insulating layer 743.

[0113] In the configuration example shown in FIG. 16, the gate insulating layer 723 has a three-layer structure and is composed of a lower silicon nitride layer 731, a silicon oxide layer 732 on the lower silicon nitride layer 731, and an upper silicon nitride layer 733 on the silicon oxide layer 732.

[0114] The silicon oxide layer 732, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 731 and the upper silicon nitride layer 733. In the gate insulating layer 723, the lower silicon nitride layer 731 forms an interface with the gate electrode 722, and the upper silicon nitride layer 733 forms an interface with the semiconductor layer 724.

[0115] The gate insulating layer 743 has a three-layer structure, which is composed of a lower silicon nitride layer 751 , a silicon oxide layer 752 on the lower silicon nitride layer 751 , and an upper silicon nitride layer 753 on the silicon oxide layer 752 .

[0116] The silicon oxide layer 752, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 751 and the upper silicon nitride layer 753. In the gate insulating layer 743, the lower silicon nitride layer 751 forms an interface with the semiconductor layer 724, and the upper silicon nitride layer 753 forms an interface with the gate electrode 762.

[0117] The thin film transistor 720 has a dual gate structure, and a semiconductor layer 724 is disposed between a top gate electrode 762 and a bottom gate electrode 722. The thin film transistor 720 further includes a source / drain electrode 725 and a source / drain electrode 726. The source / drain electrodes 725 and 726 are connected to the semiconductor layer 724 through an interlayer insulating layer 727 and a gate insulating layer 743, respectively.

[0118] The above description with reference to the bottom-gate thin film transistor can be applied to the gate insulating layers 723 and 743. The gate insulating layers 723 and 743 can have the same or different configurations. In addition, the description of the gate electrodes 722 and 762, the source / drain electrodes 725 and 726, and the interlayer insulating layer 727 of the same components described with reference to FIG. 3 or 4 can be applied.

[0119] 17 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a bottom gate / bottom contact structure. The thin-film transistor 790 includes a gate electrode 791, a gate insulating layer 792 on the gate electrode 791, and a source / drain electrode 794 and a source / drain electrode 795 on the gate insulating layer 792. The thin-film transistor 790 further includes a semiconductor layer 793 that contacts the top surfaces of the source / drain electrodes 794 and 795. The semiconductor layer 793 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin-film transistor 790 further includes an interlayer insulating layer 796 on the source / drain electrodes 794 and 795 and the semiconductor layer 793.

[0120] In the configuration example shown in FIG. 17, the gate insulating layer 792 has a three-layer structure, which is composed of a lower silicon nitride layer 797, a silicon oxide layer 798 on the lower silicon nitride layer 797, and an upper silicon nitride layer 799 on the silicon oxide layer 798.

[0121] The silicon oxide layer 798, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 797 and the upper silicon nitride layer 799. In the gate insulating layer 792, the lower silicon nitride layer 797 forms an interface with the gate electrode 791, and the upper silicon nitride layer 799 forms an interface with the semiconductor layer 793.

[0122] 13 can be applied to the gate insulating layer 792. Also, the descriptions of the gate electrode 791, the source / drain electrodes 794 and 795, and the interlayer insulating layer 796 of the same names as those described with reference to FIG.

[0123] 18 is a cross-sectional view showing an example of the structure of a switch thin film transistor having a dual gate structure. The thin film transistor 800 includes a gate electrode 801, a gate insulating layer 802 on the gate electrode 801, a source / drain electrode 804 on the gate insulating layer 802, and a source / drain electrode 805 on the gate insulating layer 802. The thin film transistor 800 further includes a semiconductor layer 803 that contacts the top surfaces of the source / drain electrodes 804 and 805. The semiconductor layer 803 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin film transistor 800 further includes source / drain electrodes 804 and 805, a gate insulating layer 806 on the semiconductor layer 803, and a gate electrode 807 on the gate insulating layer 806.

[0124] In the configuration example shown in FIG. 18, the gate insulating layer 802 has a three-layer structure, which is composed of a lower silicon nitride layer 808, a silicon oxide layer 809 on the lower silicon nitride layer 808, and an upper silicon nitride layer 810 on the silicon oxide layer 809.

[0125] The silicon oxide layer 809, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 808 and the upper silicon nitride layer 810. In the gate insulating layer 809, the lower silicon nitride layer 808 forms an interface with the gate electrode 801, and the upper silicon nitride layer 810 forms an interface with the semiconductor layer 803.

[0126] The gate insulating layer 806 has a three-layer structure, which is composed of a lower silicon nitride layer 811 , a silicon oxide layer 812 on the lower silicon nitride layer 811 , and an upper silicon nitride layer 813 on the silicon oxide layer 812 .

[0127] The silicon oxide layer 812, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 811 and the upper silicon nitride layer 813. In the gate insulating layer 806, the lower silicon nitride layer 811 forms an interface with the semiconductor layer 803, and the upper silicon nitride layer 813 forms an interface with the gate electrode 807.

[0128] The above description with reference to the thin film transistor of Fig. 13 can be applied to the gate insulating layers 802 and 806. The gate insulating layers 802 and 806 can have the same or different configurations. In addition, the description of the gate electrodes 801 and 807 and the source / drain electrodes 804 and 805 of the same names as those of the components described with reference to Fig. 3 or 4 can be applied to the gate electrodes 801 and 807 and the source / drain electrodes 804 and 805.

[0129] 19 is a cross-sectional view showing a structural example of a switch thin film transistor having a dual gate structure. The thin film transistor 820 includes a gate electrode 821, a gate insulating layer 822 on the gate electrode 821, and a semiconductor layer 823 on the gate insulating layer 822. The semiconductor layer 823 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin film transistor 820 further includes source / drain electrodes 824 and 825 on the semiconductor layer 823, a gate insulating layer 826 on the source / drain electrodes 824 and 825 and the semiconductor layer 823, and a gate electrode 827 on the gate insulating layer 826.

[0130] In the configuration example shown in FIG. 19, the gate insulating layer 822 has a three-layer structure and is composed of a lower silicon nitride layer 828, a silicon oxide layer 829 on the lower silicon nitride layer 828, and an upper silicon nitride layer 830 on the silicon oxide layer 829.

[0131] The silicon oxide layer 829, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 828 and the upper silicon nitride layer 830. In the gate insulating layer 829, the lower silicon nitride layer 828 forms an interface with the gate electrode 821, and the upper silicon nitride layer 830 forms an interface with the semiconductor layer 823.

[0132] The gate insulating layer 826 has a three-layer structure, which is composed of a lower silicon nitride layer 831 , a silicon oxide layer 832 on the lower silicon nitride layer 831 , and an upper silicon nitride layer 833 on the silicon oxide layer 832 .

[0133] The silicon oxide layer 832, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 831 and the upper silicon nitride layer 833. In the gate insulating layer 826, the lower silicon nitride layer 831 forms an interface with the semiconductor layer 823, and the upper silicon nitride layer 833 forms an interface with the gate electrode 827.

[0134] The above description with reference to the thin film transistor in Fig. 13 can be applied to the gate insulating layers 822 and 826. The gate insulating layers 822 and 826 can have the same or different configurations. In addition, the description of the gate electrodes 821 and 827 and the source / drain electrodes 824 and 825 of the same names as those described with reference to Fig. 3 or 4 can be applied to the gate electrodes 821 and 827 and the source / drain electrodes 824 and 825.

[0135] 20 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. The thin-film transistor 840 includes a gate electrode 841, a gate insulating layer 842 on the gate electrode 841, and a semiconductor layer 843 on the gate insulating layer 842. The semiconductor layer 843 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin-film transistor 840 further includes a gate insulating layer 846 on the semiconductor layer 843, and a gate electrode 847 on the gate insulating layer 846.

[0136] In the configuration example shown in FIG. 20, the gate insulating layer 842 has a three-layer structure and is composed of a lower silicon nitride layer 848, a silicon oxide layer 849 on the lower silicon nitride layer 848, and an upper silicon nitride layer 850 on the silicon oxide layer 849.

[0137] The silicon oxide layer 849, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 848 and the upper silicon nitride layer 850. In the gate insulating layer 842, the lower silicon nitride layer 848 forms an interface with the gate electrode 841, and the upper silicon nitride layer 850 forms an interface with the semiconductor layer 843.

[0138] The gate insulating layer 846 has a three-layer structure, which is composed of a lower silicon nitride layer 851 , a silicon oxide layer 852 on the lower silicon nitride layer 851 , and an upper silicon nitride layer 853 on the silicon oxide layer 852 .

[0139] The silicon oxide layer 852, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 851 and the upper silicon nitride layer 853. In the gate insulating layer 846, the lower silicon nitride layer 851 forms an interface with the semiconductor layer 843, and the upper silicon nitride layer 853 forms an interface with the gate electrode 847.

[0140] The thin film transistor 840 has a dual gate structure, and a semiconductor layer 843 is disposed between a top gate electrode 847 and a bottom gate electrode 841. The thin film transistor 840 further includes a source / drain electrode 844 and a source / drain electrode 845. The source / drain electrodes 844 and 845 are formed on a lower silicon nitride layer 851 of the gate insulating layer 846, the semiconductor layer 843, and an upper silicon nitride layer 850 of the gate insulating layer 842, respectively.

[0141] The above description with reference to the thin film transistor of Fig. 13 can be applied to the gate insulating layers 842 and 846. The gate insulating layers 842 and 846 can have the same or different configurations. In addition, the description of the gate electrodes 841 and 847 and the source / drain electrodes 844 and 845 of the same names as those described with reference to Fig. 3 or 4 can be applied to the gate electrodes 841 and 847 and the source / drain electrodes 844 and 845.

[0142] 21 is a cross-sectional view showing an example of the structure of a switch thin-film transistor having a dual gate structure. The thin-film transistor 860 includes a gate electrode 861, a gate insulating layer 862 on the gate electrode 861, and a semiconductor layer 863 on the gate insulating layer 862. The semiconductor layer 863 may be an oxide semiconductor, amorphous silicon, or polysilicon. The thin-film transistor 860 further includes a gate insulating layer 866 on the semiconductor layer 863, and a gate electrode 867 on the gate insulating layer 866.

[0143] In the configuration example shown in FIG. 21, the gate insulating layer 862 has a three-layer structure and is composed of a lower silicon nitride layer 868, a silicon oxide layer 869 on the lower silicon nitride layer 868, and an upper silicon nitride layer 870 on the silicon oxide layer 869.

[0144] The silicon oxide layer 869, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 868 and the upper silicon nitride layer 870. In the gate insulating layer 862, the lower silicon nitride layer 868 forms an interface with the gate electrode 861, and the upper silicon nitride layer 870 forms an interface with the semiconductor layer 863.

[0145] The gate insulating layer 866 has a three-layer structure, which is composed of a lower silicon nitride layer 871 , a silicon oxide layer 872 on the lower silicon nitride layer 871 , and an upper silicon nitride layer 873 on the silicon oxide layer 872 .

[0146] The silicon oxide layer 872, which is an intermediate insulating layer, contacts and forms an interface with the lower silicon nitride layer 871 and the upper silicon nitride layer 873. In the gate insulating layer 866, the lower silicon nitride layer 871 forms an interface with the semiconductor layer 863, and the upper silicon nitride layer 873 forms an interface with the gate electrode 867.

[0147] The thin film transistor 860 has a dual gate structure, and a semiconductor layer 863 is disposed between a top gate electrode 867 and a bottom gate electrode 861. The thin film transistor 860 further includes a source / drain electrode 864 and a source / drain electrode 865. The source / drain electrodes 864 and 865 are formed on a silicon oxide layer 872, which is an intermediate insulating layer of a gate insulating layer 866, a semiconductor layer 863, and an upper silicon nitride layer 870 of the gate insulating layer 862, respectively.

[0148] The above description with reference to the thin film transistor in FIG. 13 can be applied to the gate insulating layers 862 and 866. The gate insulating layers 862 and 866 can have the same or different configurations. In addition, the description of the gate electrodes 861 and 867 and the source / drain electrodes 864 and 865 of the same names as those described with reference to FIG. 3 or 4 can be applied to the gate electrodes 861 and 867 and the source / drain electrodes 864 and 865. <Second embodiment>

[0149] Hereinafter, the results of experiments conducted by the inventors and embodiments based thereon will be described with reference to the attached drawings. The embodiments are merely examples for realizing the present disclosure and do not limit the technical scope of the present disclosure. For ease of understanding, the dimensions and shapes of the objects shown in the drawings may be exaggerated.

[0150] 22A is a cross-sectional view showing a schematic structure of a thin film transistor used in the experiment. The switch thin film transistor 1000 includes a gate electrode 1002 on a glass substrate 1001, a gate insulating layer 1003 on the gate electrode 1002, and an oxide semiconductor layer 1004 on the gate insulating layer 1003. The gate insulating layer 1003 is made of silicon nitride having a thickness of 420 nm, and the oxide semiconductor layer 1004 is made of IGZO. The switch thin film transistor 1000 further includes an etch stop layer 1005 on the oxide semiconductor layer 1004, and source / drain electrodes 1006 and 1007 on the gate insulating layer 1003, the oxide semiconductor layer 1004, and the etch stop layer 1005. An interlayer insulating layer 1008 covers the entire thin film transistor 1000.

[0151] FIG. 22B is a cross-sectional view showing another thin film transistor structure used in the experiment. The switch thin film transistor 1010 includes a gate electrode 1012 on a glass substrate 1011, a gate insulating layer 1013 on the gate electrode 1012, and an oxide semiconductor layer 1014 on the gate insulating layer 1013. The gate insulating layer 1013 has a three-layer structure, and is formed of a lower silicon nitride layer 1019 with a thickness of 100 nm, a silicon oxide layer 1020 with a thickness of 300 nm on the lower silicon nitride layer 1019, and an upper silicon nitride layer 1021 with a thickness of 20 nm on the silicon oxide layer 1020. The oxide semiconductor layer 1014 is formed of IGZO. The switch thin film transistor 1010 further includes an etch stop layer 1015 on the oxide semiconductor layer 1014, and source / drain electrodes 1016 and 1017 on the gate insulating layer 1013, the oxide semiconductor layer 1014, and the etch stop layer 1015. An interlayer insulating layer 1018 covers the entire thin film transistor 1010 .

[0152] Next, an X-ray irradiation experiment was performed on the switch thin-film transistors 1000 and 1010. X-ray irradiation was performed using a MediXtec MX-160 laboratory X-ray irradiation system. Table 1 in FIG. 22C shows the X-ray irradiation conditions. In addition, the gate stress voltage in Table 1 was applied during X-ray irradiation.

[0153] Fig. 23A shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of +15V to a thin-film transistor 1000 having the structure shown in Fig. 22A while irradiating it with 1000Gy of X-rays. Also, Fig. 23B shows the change in Vg-Id characteristics before and after applying a gate voltage Vg of -15V to the thin-film transistor 1000 while irradiating it with 1000Gy of X-rays. The horizontal axis of both graphs shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd is 10V.

[0154] In the graphs of Figures 23A and 23B, lines 2301 and 2311 show the Vg-Id characteristics before (Initial) applying Vg+ or Vg- stress to the thin film transistor 1000 under the above-mentioned X-ray irradiation. Lines 2302 and 2312 show the measurement results of the Vg-Id characteristics after (Stressed) applying Vg+ or Vg- stress to the thin film transistor 1000 under the above-mentioned X-ray irradiation. As can be seen from the characteristic changes in Figures 23A and 23B, the Vg-Id characteristics of the thin film transistor 1000 shift in the positive direction by applying Vg+ stress under X-ray irradiation, and the Vg-Id characteristics of the thin film transistor 1000 shift in the negative direction by applying Vg- stress under X-ray irradiation, but the thin film transistor 1000 is appropriately turned on / off according to the change in gate voltage.

[0155] FIG. 23C shows the change in Vg-Id characteristic before and after applying a gate voltage Vg of +15V to the thin film transistor 1010 having the structure shown in FIG. 22B while irradiating it with 1000Gy of X-rays. FIG. 23D shows the change in Vg-Id characteristic before and after applying a gate voltage Vg of -15V to the thin film transistor 1010 while irradiating it with 1000Gy of X-rays. The horizontal axis of both graphs shows the gate voltage Vg, and the vertical axis shows the drain current Id. The drain voltage Vd is 10V.

[0156] In the graphs of Figures 23C and 23D, lines 2321 and 2331 show the Vg-Id characteristics before (Initial) applying Vg+ or Vg- stress to the thin film transistor 1010 under the above-mentioned X-ray irradiation. Lines 2322 and 2332 show the measurement results of the Vg-Id characteristics after (Stressed) applying Vg+ or Vg- stress to the thin film transistor 1010 under the above-mentioned X-ray irradiation. As can be seen from the characteristic changes in Figures 23C and 23D, the Vg-Id characteristics of the thin film transistor 1010 are both shifted in the negative direction by applying Vg+ or Vg- stress under X-ray irradiation, but are appropriately turned ON / OFF in response to the change in gate voltage.

[0157] Furthermore, FIG. 24 shows the results of tests performed on the thin film transistors 1000 and 1010 by applying various Vg+ or Vg- stresses under X-ray irradiation. The horizontal axis of the graph is the gate stress voltage, and the vertical axis is the amount of shift ΔVth in the Vg-Id characteristics before and after the test. According to the results of FIG. 24, in the case of the thin film transistor 1000, ΔVth is within the range of −5V to +5V when stresses of Vg+15V and Vg-15V are applied, but when stresses of Vg+20V or more and Vg-20V or less are applied, ΔVth falls outside the range of −5V to +5V, and the amount of shift is large. On the other hand, in the case of the thin film transistor 1010, ΔVth is within the range of −5V to +5V even when stresses of Vg+30V and Vg-30V are applied. In other words, it is shown that the thin film transistor 1010 has higher reliability under X-ray irradiation than the thin film transistor 1000.

[0158] The results of FIG. 24 are explained with reference to FIGS. 25A, 25B, 26A, and 26B, which are further expanded versions of the band diagram of FIG. 14. FIGS. 25A and 25B show band diagrams for explaining the movement of carriers when the thin film transistor 1000 is irradiated with X-rays. The band diagram 1030 shown in FIG. 25A shows the electron energy levels in the gate electrode 1002, the gate insulating layer 1003, and the oxide semiconductor layer 1004 when a positive gate voltage is applied to the thin film transistor 1000 under X-ray irradiation. Ec shows the lower end of the conduction band level of the oxide semiconductor layer 1004 and the gate insulating layer 1003, Ev shows the upper end of the valence band level of the oxide semiconductor layer 1004 and the gate insulating layer 1003, and Ef shows the Fermi level of the gate electrode 1002 (metal layer). The band gaps of silicon nitride and oxide semiconductor are illustrated to be approximately 5.1 eV and 3.1 eV, respectively.

[0159] Electrons (e) generated in the gate insulating layer 1003 by X-rays are trapped in the electron trap level in the gate insulating layer 1003. Holes (h) generated in the gate insulating layer 1003 are trapped in the hole trap level in the gate insulating layer 1003. Therefore, the balance between electrons and holes in the gate insulating layer 1003 does not change significantly.

[0160] On the other hand, electrons (e) generated by X-rays in the oxide semiconductor layer 1004 are moved by the positive gate voltage to the vicinity of the interface between the gate insulating layer 1003 and the oxide semiconductor layer 1004 and are trapped therein. As a result, the potential of the oxide semiconductor layer 1004 changes, and the Vg-Id characteristics of the thin film transistor 1000 shift in the positive direction.

[0161] 25B shows the electron energy levels in the gate electrode 1002, the gate insulating layer 1003, and the oxide semiconductor layer 1004 when a negative gate voltage is applied to the thin film transistor 1000 under X-ray irradiation. Ec, Ev, Ef, and the band gaps of silicon nitride and oxide semiconductor are similar to those in the band diagram 1030.

[0162] Electrons (e) and holes (h) generated by X-rays in the gate insulating layer 1003 are trapped in the electron trap level and hole trap level, respectively, in the gate insulating layer 1003, as in the band diagram 1030. Therefore, the balance of electrons and holes in the gate insulating layer 1003 does not change significantly.

[0163] On the other hand, holes (h) generated by X-rays in the oxide semiconductor layer 1004 are moved by the negative gate voltage to the vicinity of the interface between the gate insulating layer 1003 and the oxide semiconductor layer 1004 and are trapped therein. As a result, the potential of the oxide semiconductor layer 1004 changes, and the Vg-Id characteristics of the thin film transistor 1000 shift in the negative direction.

[0164] 26A and 26B are band diagrams for explaining the movement of carriers when the thin film transistor 1010 is irradiated with X-rays. A band diagram 1032 shown in FIG. 26A shows the electron energy levels in the gate electrode 1012, the lower silicon nitride layer 1019, the silicon oxide layer 1020, the upper silicon nitride layer 1021, and the oxide semiconductor layer 1014 when a positive gate voltage is applied to the thin film transistor 1010 under X-ray irradiation. Ec indicates the lower end of the conduction band level of the oxide semiconductor layer 1014, the lower silicon nitride layer 1019, the silicon oxide layer 1020, and the upper silicon nitride layer 1021, Ev indicates the upper end of the valence band level of the oxide semiconductor layer 1014, the lower silicon nitride layer 1019, the silicon oxide layer 1020, and the upper silicon nitride layer 1021, and Ef indicates the Fermi level of the gate electrode 1012 (metal layer). The band gaps of silicon oxide, silicon nitride, and oxide semiconductor are illustrated as being approximately 8.8 eV, 5.1 eV, and 3.1 eV, respectively.

[0165] Electrons (e) generated by X-rays in the lower silicon nitride layer 1019 are trapped in the electron trap level in the lower silicon nitride layer 1019. Holes (h) generated in the lower silicon nitride layer 1019 are trapped in the hole trap level in the lower silicon nitride layer 1019.

[0166] Similarly, electrons (e) generated in the upper silicon nitride layer 1021 by X-rays are trapped in the electron trap level in the upper silicon nitride layer 1021. Holes (h) generated in the upper silicon nitride layer 1021 are trapped in the hole trap level in the upper silicon nitride layer 1021.

[0167] Electrons (e) generated in the silicon oxide layer 1020 by X-rays move to the lower silicon nitride layer 1019, which has a lower energy level, and are trapped in the electron trap level of the lower silicon nitride layer 1019. Holes (h) generated in the silicon oxide layer 1020 are trapped in the hole trap level in the silicon oxide layer 1020. As a result, positive charges are accumulated near the interface between the silicon oxide layer 1020 and the upper silicon nitride layer 1021.

[0168] Moreover, electrons (e) generated by X-rays in the oxide semiconductor layer 1014 are moved by a positive gate voltage to the vicinity of the interface between the upper silicon nitride layer 1021 and the oxide semiconductor layer 1014 and are trapped there. The negative charges of the trapped electrons and the positive charges accumulated near the interface between the silicon oxide layer 1020 and the upper silicon nitride layer 1021 cancel each other out, so that the change in the potential of the oxide semiconductor layer 1014 becomes small and a shift in the Vg-Id characteristics of the thin film transistor 1010 is suppressed.

[0169] 26B shows the electron energy levels in the gate electrode 1012, the lower silicon nitride layer 1019, the silicon oxide layer 1020, the upper silicon nitride layer 1021, and the oxide semiconductor layer 1014 when a negative gate voltage is applied to the thin film transistor 1010 under X-ray irradiation. The band gaps of Ec, Ev, Ef, silicon oxide, silicon nitride, and oxide semiconductor are similar to those in the band diagram 1032.

[0170] Electrons (e) and holes (h) generated by X-rays in the lower silicon nitride layer 1019 are trapped in the electron trap level and hole trap level in the lower silicon nitride layer 1019, respectively.

[0171] Similarly, electrons (e) generated in the upper silicon nitride layer 1021 by X-rays are trapped in the electron trap level in the upper silicon nitride layer 1021. Holes (h) generated in the upper silicon nitride layer 1021 are trapped in the hole trap level in the upper silicon nitride layer 1021.

[0172] Electrons (e) generated in the silicon oxide layer 1020 by X-rays move to the upper silicon nitride layer 1021, which has a lower energy level, and are trapped in the electron trap level of the upper silicon nitride layer 1021. As a result, negative charges are accumulated near the interface between the silicon oxide layer 1020 and the upper silicon nitride layer 1021. In addition, holes (h) generated in the silicon oxide layer 1020 are trapped in the hole trap level in the silicon oxide layer 1020.

[0173] Furthermore, holes (h) generated by X-rays in the oxide semiconductor layer 1014 are moved by the negative gate voltage to the vicinity of the interface between the upper silicon nitride layer 1021 and the oxide semiconductor layer 1014 and are trapped there. The positive charges of the trapped holes and the negative charges accumulated near the interface between the silicon oxide layer 1020 and the upper silicon nitride layer 1021 cancel each other out, thereby reducing the change in potential of the oxide semiconductor layer 1014 and suppressing a shift in the Vg-Id characteristics of the thin film transistor 1010.

[0174] Based on the mechanism described above, it is believed that a thin-film transistor having a three-layer gate insulating film formed of a lower silicon nitride layer, a silicon oxide layer on the lower silicon nitride layer, and an upper silicon nitride layer on the silicon oxide layer exhibits higher reliability under X-ray irradiation than a thin-film transistor whose gate insulating film is formed of a silicon nitride layer.

[0175] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0176] 10 X-ray sensor 102 pixels 103 Photodetector 104,500 Switch TFT 502 Gate electrode 503 Gate Insulation Layer 504 Semiconductor layer 511 Lower insulating layer 512 Intermediate insulation layer 513 Upper insulation layer

Claims

1. A thin film transistor for use in an X-ray sensor, comprising: A gate electrode; A semiconductor layer; a gate insulating layer between the semiconductor layer and the gate electrode; Including, The gate insulating layer is a first region forming an interface with the gate electrode, a second region forming an interface with the semiconductor layer, and a third region between the first region and the second region, the electron trap state density and the hole trap state density of each of the first region and the second region are higher than the lower one of the electron trap state density and the hole trap state density of the third region; Thin film transistor.

2. 2. The thin film transistor of claim 1 , The hydrogen concentration in each of the first region and the second region is higher than the hydrogen concentration in the third region. Thin film transistor.

3. 2. The thin film transistor of claim 1 , The electron trap state density of each of the first and second regions is 7e11 cm -2 eV -1 That's all. Thin film transistor.

4. 2. The thin film transistor of claim 1 , the first region and the second region are each a nitride region, and the third region is an oxide region; Thin film transistor.

5. 2. The thin film transistor of claim 1 , The gate insulating layer has a three-layer structure. Thin film transistor.

6. 2. The thin film transistor of claim 1 , The first region and the second region each have substantially the same electron trap state density and hole trap state density. Thin film transistor.

7. A thin film transistor for use in an X-ray sensor, comprising: A gate electrode; A semiconductor layer; a gate insulating layer between the semiconductor layer and the gate electrode; Including, The gate insulating layer is a first region forming an interface with the gate electrode and a second region forming an interface with the semiconductor layer; The first region and the second region each have substantially the same electron trap state density and hole trap state density. Thin film transistor.

8. 8. The thin film transistor of claim 7, the gate insulating layer further includes a third region between the first region and the second region; The hydrogen concentration in each of the first region and the second region is higher than the hydrogen concentration in the third region. Thin film transistor.

9. 8. The thin film transistor of claim 7, The electron trap state density of each of the first and second regions is 7e11 cm -2 eV -1 That's all. Thin film transistor.

10. 8. The thin film transistor of claim 7, the first region and the second region are each a nitride region; Thin film transistor.

11. A thin film transistor for use in an X-ray sensor, comprising: A gate electrode; A semiconductor layer; a gate insulating layer between the semiconductor layer and the gate electrode; Including, The gate insulating layer is a first region forming an interface with the gate electrode, a second region forming an interface with the semiconductor layer, and a third region between the first region and the second region, the third region being made of a material different from that of the first region and the second region; the first region and the second region are formed of a nitride; Thin film transistor.

12. 12. The thin film transistor of claim 11, The third region is formed of an oxide. Thin film transistor.

13. 13. The thin film transistor of claim 12, The hydrogen concentration in each of the first region and the second region is higher than the hydrogen concentration in the third region. Thin film transistor.

14. 13. The thin film transistor of claim 12, The electron trap state density of each of the first and second regions is 7e11 cm -2 eV -1 That's all. Thin film transistor.

15. 13. The thin film transistor of claim 12, The gate insulating layer has a three-layer structure. Thin film transistor.

16. 13. The thin film transistor of claim 12, The first region and the second region each have substantially the same electron trap state density and hole trap state density. Thin film transistor.

17. 1. An X-ray sensor comprising: A plurality of pixels and signal lines are included. Each pixel of the plurality of pixels is A conversion element that converts an electromagnetic wave into an electric signal, and the thin film transistor according to claim 1, 7 or 11, which is ON / OFF controlled between the conversion element and the signal line. X-ray sensor.

18. 12. A thin film transistor according to claim 1, 7 or 11, The gate electrode and the gate insulating layer are respectively above and below the semiconductor layer. Thin film transistor.

19. 12. A thin film transistor according to claim 4, 10 or 11, The thickness of the first region is 100 nm or more, and the thickness of the second region is 20 nm or more. Thin film transistor.

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