Manufacturing system of semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a manufacturing system of a semiconductor device which has a processing yield improved, and provide a manufacturing method of the semiconductor device.SOLUTION: A manufacturing system of a semiconductor device comprises: a wafer stage 200 which has a wafer 205 mounted onto an upper surface; a semiconductor device manufacturing device 101 that is provided with a heater control part for adjusting a plurality of heaters 201a to 201j arranged below a plurality of regions on the upper surface in an inner part of the wafer stage, and an output of a plurality of heater power supplies 202a to 202j supplied to the plurality of heaters, and performs a processing of the wafer; and a wafer temperature calculation system that determines whether or not a first output value of the plurality of heater power supplies calculated previously in order to realize a target temperature in the processing of the wafer is within an allowable range, and when the value is out of the allowable range, calculates a second output value obtained by correcting all of the first output values to a value within the allowable range.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a method for setting the wafer temperature in a semiconductor wafer processing system. [Background technology]

[0002] As semiconductor device structures become three-dimensional, there is an increasing demand every year for manufacturing technologies that can uniformly fabricate complex device structures within a wafer. In the manufacture of semiconductor devices, the desired pattern is formed over the entire surface of a wafer by repeating processes using multiple semiconductor manufacturing equipment such as exposure equipment, heat treatment equipment, dry etching equipment, wet cleaning equipment, film formation equipment, and CMP (Chemical Mechanical Polishing) equipment, to create chips.

[0003] Furthermore, to confirm that the fabricated chips are good chips that meet the desired requirements, specific physical quantities such as the dimensions of the patterns and film thickness of the multi-layered films formed on the surface of the wafer are measured using semiconductor inspection equipment such as a CD-SEM (Critical Dimension Scanning Electron Microscope), OCD (Optical Critical Dimension), STEM (Scanning Transmission Electron Microscope), TEM (Transmission Electron Microscope), optical film thickness gauge, and ellipsometer. When using these semiconductor inspection equipment, measurements are generally taken at multiple locations on the wafer rather than just one location, in order to check the number of good chips that can be obtained from the wafer surface.

[0004] The measurement results of dimensions, film thickness, etc. obtained in this way are fed back or fed forward to each semiconductor manufacturing equipment to reflect the conditions (process conditions) for processing the wafer. The operation of the semiconductor manufacturing equipment is adjusted to approach the processing conditions that can obtain the desired shape of the wafer surface after processing, thereby increasing the number of good chips that can be obtained from one wafer surface and improving the processing yield. Each such semiconductor manufacturing equipment is equipped with a control method for the equipment that performs feedback or feedforward control based on the measured data and can make the distribution of a specific physical quantity on the wafer surface the desired one.

[0005] As one method for controlling the in-plane distribution of a specific physical quantity such as a pattern dimension or a film thickness to a desired value on a wafer, it has been known to control the temperature distribution in the in-plane direction of the wafer when the wafer is processed in a semiconductor manufacturing device. An example of such a conventional technique is disclosed in Japanese Patent Laid-Open Publication No. 2006-228816 (Patent Document 1). Patent Document 1 discloses a method for controlling the in-plane temperature of a heat treatment plate which is divided into a plurality of regions and heated separately, and controlling the pattern dimension in the in-plane direction of the wafer held above the heat treatment plate in a post-exposure baking process for promoting a chemical reaction in the resist film after exposing the resist pattern in an exposure device, and a method for calculating the temperature distribution in the in-plane direction that is the target for forming a uniform pattern in the wafer from a relational expression between the temperature of the heat treatment plate and the pattern dimension obtained in advance so that the pattern dimension in the in-plane direction of the wafer is formed uniformly, and setting the temperature of each region of the heat treatment plate to achieve the temperature distribution.

[0006] Also, Japanese Patent Laid-Open Publication No. 2009-302390 (Patent Document 2) discloses a plasma etching apparatus, which is one of dry etching apparatuses, that calculates a temperature distribution within a wafer surface from the temperature of a coolant for cooling a sample stage, the power of heaters arranged in three circular and ring-shaped areas at the center, middle, and edge arranged in a dielectric film covering the upper surface of the sample stage to heat the sample stage, and the temperature of a sensor arranged on the sample stage to measure the temperature of the sample stage. Furthermore, Japanese Patent Laid-Open Publication No. 2013-513967 (Patent Document 3) discloses a technology in a plasma etching apparatus that calculates an in-plane temperature distribution in which a uniform pattern is formed within the wafer surface from a relational equation between a wafer temperature and a pattern dimension acquired in advance, and controls the output of heater power to achieve a target in-plane temperature distribution. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2006-228816 A [Patent Document 2] JP 2009-302390 A [Patent Document 3] Special Publication No. 2013-513967 Summary of the Invention [Problem to be solved by the invention]

[0008] In the above-mentioned conventional techniques, problems have arisen because the following points have not been sufficiently considered.

[0009] That is, in the above-mentioned conventional technology, a target in-plane temperature distribution where a circuit pattern of a desired semiconductor device is formed on the wafer surface is calculated from a relational expression between the wafer temperature and a pattern dimension value, for example, a CD (Critical Dimension) value, which is obtained in advance, and the heater power output is adjusted so that the target in-plane temperature distribution is obtained. However, in reality, the calculated target temperature during wafer processing or the magnitude of the heater power required to achieve this may exceed the range that the plasma processing apparatus can achieve. In this case, it has been found that the target temperature cannot be achieved, and the formed circuit pattern does not achieve the desired performance, thereby reducing the processing yield.

[0010] One of the reasons why the wafer temperature and heater output values ​​required to realize the target wafer temperature are calculated to be values ​​that exceed the range that can be realized by the apparatus is that the amount of heat required to realize the target temperature of one wafer region is physically difficult to realize with the amount of heat generated by the heater corresponding to the region due to heat transfer within the wafer. That is, the inventors' study revealed that the amount of heat generated by the heater corresponding to one region may exceed the maximum possible value due to a part of the heat generated by the heater corresponding to one region moving to another adjacent or nearby region, or conversely, the temperature of the region may exceed the target value even if the amount of heat generated is 0, making it impossible to realize the target wafer temperature distribution by adjusting the power supplied to the heaters corresponding to the multiple regions and the amount of heat generated thereby.

[0011] As described above, the conventional techniques do not take into consideration the problem that the temperature distribution of the wafer during processing cannot be made to be the initial one, and the yield of wafer processing is impaired.

[0012] An object of the present invention is to provide a semiconductor device manufacturing system and a semiconductor device manufacturing method that improves the processing yield. [Means for solving the problem]

[0013] In order to solve the above problems, the present invention provides a means for correcting a difficult-to-achieve target wafer temperature distribution to a more achievable distribution.

[0014] That is, the above objective is achieved by a wafer processing apparatus comprising a stage disposed within a processing chamber inside a vessel on whose upper surface a wafer to be processed is placed, a plurality of heaters disposed inside the stage below a plurality of regions of the upper surface of the stage, and a controller that adjusts the power supplied to the plurality of heaters, the controller adjusting the power so that a second target temperature distribution is obtained by correcting a first target temperature distribution given in advance to bring the wafer to a target temperature during processing. Effect of the Invention

[0015] According to the present invention, a target temperature distribution capable of forming a desired shape in an in-plane direction of the wafer is calculated using a relationship between a wafer temperature and a specific physical quantity obtained in advance, and then the amount of power supply to the heaters capable of realizing the target temperature distribution is calculated. Furthermore, whether the target temperature distribution can be realized is determined before the wafer is processed using the value of the amount of power supply, and as a result, when it is determined that the output value from the heater power supply cannot be realized, a second target temperature distribution capable of minimizing the objective function among the achievable heater power supply outputs and the amount of power supply to the heaters capable of realizing the second target temperature distribution are calculated.

[0016] This prevents the target temperature distribution of the wafer during processing from being not achieved, reduces the number of wafer processing stops, and prevents the wafer temperature during processing from deviating from the desired value, improving processing yield. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic diagram showing the configuration of a semiconductor device manufacturing system according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a vertical cross-sectional view that illustrates a schematic configuration of a wafer stage provided in the semiconductor device manufacturing apparatus according to the embodiment. [Diagram 3] FIG. 3 is a plan view that shows a schematic example of the arrangement of heater zones on the upper surface of the wafer stage. [Figure 4] FIG. 4 is a schematic diagram showing heater zones determined to be impossible to implement in a wafer temperature calculation system according to an embodiment, which is shown on a display connected to a semiconductor device manufacturing apparatus. [Figure 5A] FIG. 5A is a flowchart showing the operation flow of the wafer temperature calculation system according to the embodiment. [Figure 5B] FIG. 5B is a flowchart showing the flow of operations of the wafer temperature calculation system according to the embodiment. [Figure 6] FIG. 6 is a flowchart showing the flow of operations of the wafer temperature calculation system according to the embodiment. [Figure 7] FIG. 7 is a flow chart showing the flow of operations added to the present embodiment shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiment. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals. When there are multiple components having the same or similar functions, they may be described by using the same reference numerals with different subscripts, or when there is no need to distinguish between these multiple components, the subscripts may be omitted. In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0020] In this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Additionally, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-shaped member or a layer contained in the plate-shaped member is illustrated. Additionally, the "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface".

[0021] Moreover, "upper" means the vertically upward direction when the plate-like member or layer is placed horizontally. Moreover, the direction opposite to "upper" is referred to as "lower". Moreover, the term "in-plane distribution" refers to distribution in an in-plane direction. It is also called "distribution in an in-plane direction."

[0022] [Example 1] An embodiment of the present invention will be described with reference to FIGS.

[0023] 1 is a schematic diagram showing the configuration of a semiconductor device manufacturing system according to an embodiment of the present invention. In this diagram, the overall configuration of the semiconductor device manufacturing system is shown, and a semiconductor wafer processing apparatus such as an etching processing apparatus is shown, which processes the semiconductor wafer to realize a distribution of a specific physical quantity (for example, the shape or dimensions of a circuit pattern formed on the wafer surface) in an in-plane direction of the wafer.

[0024] The semiconductor device manufacturing system of this example includes a plurality of semiconductor device manufacturing apparatuses 101 (101a, 101b, etc. are shown in this figure) such as etching processing apparatuses, each of which has a sample stage (wafer stage) on the upper surface of which a wafer is placed and has a function of variably adjusting the temperature distribution in the in-plane direction of the wafer, a plurality of wafer measuring apparatuses 102 (102a to 102z) capable of measuring the distribution of a specific physical quantity in the wafer, and a wafer temperature calculation system 100 for calculating the temperature distribution in the in-plane direction of the wafer processed by the semiconductor device manufacturing apparatus 101. Furthermore, the wafer temperature calculation system 100, the plurality of semiconductor device manufacturing apparatuses 101, and the wafer measuring apparatus 102 are communicatively connected by wired or wireless communication means so as to be able to transmit and receive signals to and from each other. In order to transmit and receive data, it is preferable that the wafer temperature calculation system 100, each semiconductor device manufacturing apparatus 101, and each wafer measuring apparatus 102 are connected to a so-called network such as Ethernet and configured to be able to communicate with each other via the network, but any form capable of transmitting and receiving data to and from each other may be used. For example, data may be exchanged between devices using recording media such as floppy disks, flash memories such as USB memories and SD cards, CDs, DVDs and Blu-Ray Discs (registered trademark).

[0025] The wafer temperature calculation system 100 includes a calculator 103 such as a microprocessor, a storage device 104 in which data related to the wafer and software for driving the calculator 103 are stored in a readable and writable manner, and an interface 105 that is communicatively connected to a network and transmits and receives signals including data, and is configured to be communicative. The wafer temperature calculation system 100 may be configured such that the calculator 103, the storage device 104, and the interface 105 are built into a so-called computer such as a PC or a server, or the storage device 104 may be located in a remote location that is communicatively connected. Each semiconductor device manufacturing apparatus 101 and each wafer measuring apparatus 102 do not need to be located in the same building, and may be located in a different building or different location so as to be communicative.

[0026] Fig. 2 is a vertical cross-sectional view showing a schematic configuration of a wafer stage provided in a semiconductor device manufacturing apparatus according to an embodiment. Each of the semiconductor device manufacturing apparatuses 101 of this embodiment has a wafer stage 200 shown in Fig. 2 in a processing chamber inside a vessel. The wafer stage 200 has a disk or cylindrical shape that shares a central axis with the cylindrical processing chamber, and is equipped with a plurality of heaters 201 (201a to 201j) arranged inside along the upper surface of the metal base material, and coolant flow paths 204 arranged in multiple concentric or spiral shapes inside the base material below the heaters 201, through which a coolant for cooling the wafer flows.

[0027] By adjusting the heat generation amount of the heaters 201 and the temperature of the coolant flowing through the coolant flow passage 204, the temperature distribution in the in-plane direction of the wafer 205 is adjusted while the wafer 205 is placed and held on the dielectric film covering the upper surface of the wafer stage 200. In the wafer stage 200 of this example, the heaters 201 are arranged below each of the zones into which the upper surface of the wafer stage 200 on which the wafer 205 is placed is divided in the radial or circumferential direction, and each heater 201 constitutes a plurality of heater zones. The heater power supplies 202 (202a to 202j) electrically connected to the heaters 201 receive command signals from a heater control unit 203 communicably connected thereto, and the value of the power (current or voltage) output based on the command signal is adjusted, so that the heat generation amount and temperature of each heater zone, and thus the temperature of the region of the placed wafer 205 corresponding to the heater zone, are adjusted to values ​​within a range suitable for processing.

[0028] 2, a temperature sensor that detects the temperature of the substrate of the wafer stage 200 may be disposed inside the substrate below each heater zone in correspondence with the heater zone. Furthermore, the output from the temperature sensor may be transmitted to a heater control unit 203, and information on the detected temperature may be fed back or fed forward to adjust the output of the heater power supply 202.

[0029] The coolant circulates between the coolant flow passage 204 and a coolant temperature controller connected via a pipe (not shown), and is adjusted to a temperature within a predetermined range by the coolant temperature controller. If necessary, coolants set to different temperatures may be supplied to each of the multiple coolant flow passages 204. Furthermore, the wafer stage 200 may be configured without the coolant flow passage 204 if the temperature controllability within the wafer surface is sufficient.

[0030] 2, the coolant flow path 204 through which the coolant flows is disposed below the heater 201, but the coolant flow path 204 can also be disposed above the heater. In addition, although not shown in FIG. 2, the wafer stage 200 is provided with a holding mechanism such as a mechanical chuck, a vacuum chuck, or an electrostatic chuck that can hold the wafer 205 placed on the upper surface and suppress positional deviation.

[0031] Fig. 3 shows an example of heater zones on the upper surface of the wafer stage 200 as viewed from above. Fig. 3 is a plan view that shows a schematic example of the arrangement of heater zones on the upper surface of the wafer stage. Fig. 3(a) shows an example of a pattern in which the heater zones are divided into a lattice shape, and Fig. 3(b) shows an example of a pattern on concentric circles.

[0032] In this example, as long as the desired temperature distribution in the in-plane direction of the wafer 205 is realized by appropriately selecting the shape and position of the heater 201 or the output of the heater power supply 202, the size, arrangement, and number of the heater zones are not limited to those illustrated in FIG. 3.

[0033] In each semiconductor device manufacturing apparatus 101, a specific correlation is established between the output (heat generation amount) of the multiple heaters 201 or the output from the heater power source 202, the temperature value of the coolant, and the temperature of each zone of the wafer 205 placed on the wafer stage 200. In this example, such a correlation is set as a first correlation, and the temperature distribution in the in-plane direction of the wafer 205 can be predicted using data indicating the first correlation calculated or acquired in advance, and the set values ​​of the output of the heater power source 202 and the temperature of the coolant. Furthermore, when a temperature sensor is disposed to detect the temperature of each heater zone, the temperature data obtained from the output of the temperature sensor can be included in the first correlation, or used together with the first correlation to predict the temperature of the wafer 205, thereby improving the accuracy.

[0034] The first correlation can be expressed using a matrix to relate the plurality of heater zones to the temperatures of the locations in each of the plurality of regions of the wafer 205. The first correlation can also be expressed using simultaneous differential equations.

[0035] In this embodiment, the upper and lower limit values ​​of the output of the heater power supplies 202 provided in each semiconductor device manufacturing apparatus 101, and the upper and lower limit values ​​of the temperature of the wafer 205 obtained using the first correlation are determined from the configuration of each semiconductor device manufacturing apparatus 101, and are therefore specific to each semiconductor device manufacturing apparatus 101. Furthermore, if the output of the heater power supply 202 or the temperature of the wafer 205 during processing of any wafer 205 falls outside the allowable range determined by the above-mentioned specific values, the processing of the wafer 205 is stopped to avoid malfunction or damage of the wafer stage 200. For this reason, when processing the wafer 205, the output of the heater power supply 202 and the temperature of the wafer 205 need to be set to values ​​within the allowable range that do not exceed the above-mentioned upper and lower limits.

[0036] The wafer 205 processed in each semiconductor device manufacturing tool 101 is transferred to one of the wafer measuring tools 102 (102a to 102z), and a distribution of a specific physical quantity to be detected or evaluated is detected in an in-plane direction of the wafer 205. If necessary, the distribution of the specific physical quantity before processing in each semiconductor device manufacturing tool 101 can also be detected by one of the wafer measuring tools 102. However, it is not necessary to detect the specific physical quantity of the processed wafer 205 immediately after processing in each semiconductor device manufacturing tool 101. The wafer 205 processed in each semiconductor device manufacturing tool 101 can be transferred to another tool, and the wafer 205 after being subjected to at least one process can be transferred to the wafer measuring tool 102 to detect the distribution of the specific physical quantity in an in-plane direction of the wafer 205.

[0037] Also, the surface of a wafer 205 processed in one semiconductor device manufacturing tool 101 can be measured using a plurality of wafer measuring tools 102. That is, a wafer 205 processed in a semiconductor device manufacturing tool 101a can be transferred to a wafer measuring tool 102a and then to a wafer measuring tool 102b, and a distribution of one or more specific physical quantities on the surface of the wafer 205 can be detected in each of the tools.

[0038] Next, an operation of calculating a target temperature distribution in an in-plane direction of the wafer 205 in any one of the semiconductor device manufacturing tools 101 using the wafer temperature calculation system 100, and an operation of correcting the target temperature distribution to a realizable target temperature distribution when it is determined that the target temperature distribution cannot be realized will be described. Note that the following description will be given as an example of a case where the semiconductor device manufacturing tool 101a is used as a target for calculating the target temperature distribution, and the wafer measuring tool 102a is used as a tool for detecting a specific physical quantity, but in the embodiment of the present invention, similar operations can be performed when other semiconductor device manufacturing tools or wafer measuring tools are used.

[0039] The wafer temperature calculation system 100 has a function of storing, in each semiconductor device manufacturing apparatus 101, a first correlation between the output from each heater power supply 202 and the in-plane distribution of the temperature of the wafer 205, and data on the range in which the heater power supply 202 can output and the allowable range of the temperature of the wafer 205 in each wafer stage 200 in each semiconductor device manufacturing apparatus 101a to 101z in a readable and writable manner, and updating each data as necessary. These data are periodically transmitted and received between the wafer temperature calculation system 100 and the semiconductor device manufacturing apparatus 101a, and the same data is held by both of them. When the structure of the wafer stage 200 including the heater 201 and the heater power supply 202 of the wafer stage 200 or the temperature of the coolant is changed, information related to the change is stored and memorized in the wafer temperature calculation system 100 during the periodic data transmission and reception, and is reflected in the operation. This allows the wafer 205 to be processed with high accuracy by realizing a target temperature distribution using the data shared for any wafer 205.

[0040] Next, the wafer temperature calculation system 100 has a function of associating a process recipe for processing the wafer 205 in the semiconductor device manufacturing equipment 101a with data obtained by measuring the distribution of a specific physical quantity in an in-plane direction of the processed wafer 205 in the wafer measuring equipment 102a. Here, the process recipe includes the target in-plane temperature distribution of the wafer 205 set in the wafer stage 200, or the distribution of the temperature detected during actual processing using a temperature sensor, or data on the output value of each heater power supply 202. This makes it possible to associate the temperature distribution of the wafer 205 in the semiconductor device manufacturing equipment 101 with the distribution of a specific physical quantity in an in-plane direction of the wafer 205 measured by the wafer measuring equipment 102.

[0041] Furthermore, when a distribution of a specific physical quantity in an in-plane direction of the wafer 205 is detected before the wafer 205 is processed in the semiconductor device manufacturing equipment 101a, the wafer temperature calculation system 100 also has a function of associating the data with the processing recipe of the semiconductor device manufacturing equipment 101a. With this configuration, it is possible to associate the distribution of the specific physical quantity before and after processing in the in-plane direction of the wafer 205 in the semiconductor device manufacturing equipment 101a, and it is possible to associate the in-plane distribution of the wafer temperature set in the semiconductor device manufacturing equipment 101a with the in-plane distribution of the change in the specific physical quantity before and after processing from the difference between the in-plane distributions of the wafer before and after processing.

[0042] Furthermore, the wafer temperature calculation system 100 has a function of calculating a second correlation between a set value of the temperature distribution in an in-plane direction of the wafer 205 in the semiconductor device manufacturing equipment 101a and a distribution of a specific physical quantity in an in-plane direction of the wafer 205, and storing and memorizing this as data related to the semiconductor device manufacturing equipment 101a. The second correlation can be calculated, for example, using data obtained by processing two or more wafers 205 in the semiconductor device manufacturing equipment 101a using different temperature distribution settings and then transporting each wafer 205 to the wafer measuring equipment 102a and detecting the specific physical quantity, prior to processing the wafer 205 for manufacturing a semiconductor device.

[0043] That is, the second correlation is calculated using a result in which different temperature distribution conditions set for two or more wafers 205 are associated with detection result data of a distribution of a specific physical quantity in an in-plane direction for each wafer 205. As a method for calculating the second correlation, a least squares method using linear or polynomial approximation can be used, but other methods can also be used.

[0044] Next, the wafer temperature calculation system 100 has a function of calculating a target temperature distribution that minimizes an objective function using a specific physical quantity on the wafer stage 200 of the semiconductor device manufacturing apparatus 101a using the stored second correlation. An example of the objective function in this embodiment is a function that sets target values ​​of a specific physical quantity on a plurality of coordinates in an in-plane direction of the wafer 205, calculates the square of the difference between the target value at a specified coordinate on the surface of the wafer 205 and a predicted value at the specified coordinate calculated based on the second correlation, and sums up the squared values ​​for the plurality of specified coordinates.

[0045] The target value of a specific physical quantity used in calculating such an objective function does not necessarily have to be set to the same value in the in-plane direction of the wafer 205. A different target value may be set for each coordinate that can obtain the result of processing in the in-plane direction of the wafer 205, for example, a shape after processing, and even if the coordinate is the same on the wafer 205, the target value in the process of the processing may be different depending on the type, content, and conditions of the previous and next processing. In this way, in this embodiment, an appropriate objective function is set, and a temperature distribution in the in-plane direction of the wafer 205 that minimizes the set objective function is calculated. A target temperature distribution during processing of the wafer 205 is calculated so that a desired physical quantity distribution is achieved after processing.

[0046] Furthermore, the wafer temperature calculation system 100 has a function of calculating a predicted value of the output of the heater power source 202 connected to each heater zone to realize the calculated target temperature distribution by using the first correlation in the semiconductor device manufacturing equipment 101a. When actually processing the wafer 205, the output of the heater power source 202 is set to a value equal to or greater than 0, but the predicted value of the output calculated here may be a physically unrealizable negative value by extrapolating the first correlation. In other words, even if the target temperature distribution of the wafer 205 cannot be actually realized due to the heat transfer between the multiple heater zones via the wafer 205, the output value during processing of the multiple heater power sources 202 that can realize this distribution mathematically is calculated.

[0047] Next, the wafer temperature calculation system 100 has a function of judging whether or not the calculated target temperature distribution of the wafer stage 200 can be realized based on the upper and lower limit values ​​of the allowable range of the temperature during processing of the wafer 205 in the semiconductor device manufacturing equipment 101a and the upper and lower limit values ​​of the range in which the heater power supply 202 can output. That is, in the wafer temperature calculation system 100, the calculated target temperature value and the predicted value of the output of the heater power supply 202 are compared with the two upper and lower limit values. Here, if the already calculated target temperature during processing of the wafer 205 and the predicted value of the output of the heater power supply 202 do not exceed the respective upper and lower limit values ​​in all heater zones, the calculated target temperature distribution is recorded in the wafer temperature calculation system 100 as a target temperature distribution that can be realized.

[0048] On the other hand, if it is determined that at least one of the target temperature or the predicted value of the output of the heater power supply 202 exceeds the two upper and lower limits in one or more heater zones, it is recorded as an impossible target temperature distribution. At that time, the heater zones in which the target temperature or the predicted value of the output of the heater power supply 202 cannot be achieved are identified and recorded by the corresponding code, number, etc., so that the information can be checked when necessary.

[0049] When recording the heater zones that cannot realize the target temperature distribution, each heater zone can be given a name, a symbol, or a number, and the heater zones that cannot realize the target temperature distribution can be displayed on a display device such as a display communicatively connected to the wafer temperature calculation system 100. An example of the display is shown in FIG.

[0050] 4 is a schematic diagram showing heater zones that are determined to be impossible to realize in the wafer temperature calculation system according to the embodiment, which is shown on a display connected to a semiconductor device manufacturing apparatus. As shown by 401 in FIG. 4(a) or 4(b), the heater zones that are determined to be impossible to realize in the wafer temperature calculation system 100 are shown as hatched heater zones 401 on the figure, and the locations of the heater zones among all the heater zones on the upper surface of the wafer stage 200 are easily displayed using a GUI (Graphical User Interface).

[0051] Next, when it is determined that the target temperature distribution cannot be realized, the wafer temperature calculation system 100 calculates a second target temperature distribution that can be realized. The second target temperature distribution may be a distribution in which only the target temperature or the predicted value of the heater power supply 202 output of the heater zone in which the predicted value of the heater power supply 202 output falls outside the allowable range is changed.

[0052] On the other hand, simply changing the predicted value of the output of the heater power supply 202 of the heater 201 corresponding to the heater zone that is outside the allowable range due to heat transfer in the wafer 205 may change the temperature at an unexpected specified coordinate of the wafer 205, increasing the objective function, and may result in the target temperature distribution being significantly different from that which obtains the expected processing result. Therefore, using a first correlation that predicts the in-plane temperature distribution of the wafer 205 from the output values ​​of the multiple heater power supplies 202 and a second correlation between the set value of the in-plane temperature distribution of the wafer 205 and the distribution of a specific physical quantity in the in-plane direction of the wafer 205, a temperature distribution of the wafer 205 that can minimize the objective function among all possible temperature distributions can be calculated, and this can be calculated as a second target temperature distribution.

[0053] Furthermore, wafer temperature calculation system 100 reflects either the target temperature distribution determined to be feasible or the second target temperature distribution in the processing conditions (processing recipe) in semiconductor device manufacturing equipment 101a, and transmits the processing recipe to semiconductor device manufacturing equipment 101a. After being calculated by wafer temperature calculation system 100, semiconductor device manufacturing equipment 101a can process target wafer 205 using the processing recipe including the transmitted information on the feasible target temperature distribution.

[0054] As described above, by using a semiconductor device manufacturing system including the wafer temperature calculation system 100 of this embodiment, even if the initial target temperature distribution calculated to obtain the desired processing results is impossible to realize, a second target temperature distribution that can minimize the objective function among the possible temperature distributions is calculated, and semiconductor devices are manufactured based on this, thereby suppressing a decrease in manufacturing yield.

[0055] Next, the operation of calculating the target temperature distribution of the wafer temperature calculation system 100 according to the embodiment of Fig. 1 will be described with reference to Figs. 5A to 6. Figs. 5A to 6 are flowcharts showing the flow of the operation of the wafer temperature calculation system according to the embodiment. Note that, although an example using semiconductor device manufacturing equipment 101a and wafer measuring equipment 102a is described in this example, the same operation can be performed and the same effect can be obtained even when other semiconductor device manufacturing equipment or wafer measuring equipment is used.

[0056] 5A and 5B show a series of flow of operations for calculating the set value of the target temperature distribution by the wafer temperature calculation system 100. FIG. 6 shows in more detail the flow of operations for setting the output value of the heater power supply 202 in step 512 shown in FIG. 5B. The wafer temperature calculation system 100 of this embodiment has a function of managing, for each of the semiconductor device manufacturing apparatuses 101 connected to the semiconductor device manufacturing system via a communication means such as a network as shown in step 501, a first correlation indicating the relationship between the output value of each of the plurality of heater power supplies 202 and the temperature distribution in the in-plane direction of the wafer 205 from the temperature of the coolant flowing through the coolant flow passage 204, and the output value of the heater power supply 202 and the value (tolerance) of the allowable range of the temperature of the wafer 205 in association with each of the semiconductor device manufacturing apparatuses 101a to 101z. These data are periodically synchronized between wafer temperature calculation system 100 and each semiconductor device manufacturing apparatus, for example semiconductor device manufacturing apparatus 101a, and the same data is stored and shared between both. If any changes are made to the structure of wafer stage 200 or the set temperature of the coolant, data and information reflecting the changes are periodically transmitted to and stored in wafer temperature calculation system 100.

[0057] Next, in step 502, the semiconductor device manufacturing equipment 101a associates a process recipe for processing the wafer 205 with data on the distribution of a specific physical quantity in an in-plane direction of the wafer 205 after processing the wafer using the process recipe and detected by the wafer measuring equipment 102a. Here, the process recipe also contains data indicating the in-plane temperature distribution during processing of the wafer 205 set by the wafer stage 200 or the output value of each heater power supply 202. This associates the in-plane temperature distribution of the wafer 205 set by the semiconductor device manufacturing equipment 101 with the in-plane distribution of the specific physical quantity of the wafer 205 detected by the wafer measuring equipment 102.

[0058] Furthermore, when the wafer temperature calculation system 100 detects a distribution of a specific physical quantity in an in-plane direction of the wafer 205 in the wafer measuring device 102a before the wafer is processed in the semiconductor device manufacturing equipment 101a, the wafer temperature calculation system 100 also has a function of associating the data with the processing recipe of the semiconductor device manufacturing equipment 101a. With this configuration, the distribution of the specific physical quantity in the in-plane direction of the wafer 205 before and after the processing in the semiconductor device manufacturing equipment 101a can be associated, and the distribution of the temperature in the in-plane direction of the wafer 205 set in the semiconductor device manufacturing equipment 101a and the distribution of the change amount of the specific physical quantity in the in-plane direction before and after the processing can be associated from the distribution of the difference in the specific physical quantity in the in-plane direction before and after the processing.

[0059] Here, each heater power supply 202 is assigned a number starting from N=1, the number of heater power supplies, so that it is possible to determine which heater zone a heater power supply is connected to based on this number. Note that the heater power supplies may be named in any way as long as they can be distinguished from one another, but in this embodiment, a positive integer of N=1 or more is assigned.

[0060] Next, in step 503, wafer temperature calculation system 100 has a function of calculating a second correlation predicting a distribution of a specific physical quantity in an in-plane direction of wafer 205 from a set value of the temperature distribution in the in-plane direction of wafer 205 in semiconductor device manufacturing equipment 101a, and has a function of recording and storing the second correlation as data related to semiconductor device manufacturing equipment 101a in internal storage device 104. The second correlation is calculated using a result of correlating data of the distribution in the in-plane direction of values ​​of a specific physical quantity detected by wafer measuring equipment 102a for each wafer 205 after processing two or more wafers 205 in advance using semiconductor device manufacturing equipment 101a under conditions of different temperature distribution in the in-plane direction.

[0061] That is, the second correlation is calculated using two or more types of temperature distribution conditions in the in-plane direction of the wafer 205 and the detection result of the distribution of a specific physical quantity in the in-plane direction. The second correlation may be calculated by a least squares method using linear or polynomial approximation, or other methods may be used.

[0062] Next, wafer temperature calculation system 100 has a function of calculating a target temperature distribution in semiconductor device manufacturing equipment 101a that minimizes an objective function calculated from a specific physical quantity, using the second correlation recorded in step 504. As the objective function, for example, a target value of the specific physical quantity is set at a plurality of coordinates within the surface of wafer 205, and the difference between the target value at a specified coordinate within the surface and a predicted value at the specified coordinate calculated based on the second correlation is squared, and the sum of the squared values ​​for the plurality of specified coordinates may be set as the objective function.

[0063] The target value of the specific physical quantity used in calculating this objective function does not necessarily need to be set to the same target value within the wafer surface, but may be one that realizes the value of the specific physical quantity and its distribution that ultimately results in the desired processing result within the wafer surface, and may be one that changes the value of the target value for each coordinate depending on the processing before and after this. In this way, by setting an appropriate objective function and calculating the temperature distribution of the wafer 205 that minimizes this objective function, a target temperature distribution that ultimately achieves the value of the desired physical quantity and its distribution in the in-plane direction of the wafer 205 is calculated.

[0064] Next, in step 505, the wafer temperature calculation system 100 uses the first correlation in the semiconductor device manufacturing equipment 101a to calculate predicted values ​​of the outputs of the heater power supplies 202 connected to each heater zone for calculating the target temperature distribution. During the actual processing of the wafer 205, the output of each heater power supply 202 is set to a value equal to or greater than 0, but the predicted output value calculated here may be an unrealizable negative value by extrapolating the first correlation. As a result, even if the target temperature distribution includes a value that cannot be actually realized due to the heat transfer of the wafer 205, a set of output values ​​of the heater power supplies 202 that mathematically correspond to this can be obtained.

[0065] Next, in step 506, the wafer temperature calculation system judges whether the predicted output value of the heater power supply satisfies the limiting condition. That is, based on the result of comparing the upper and lower limits of the allowable range of the temperature of the wafer 205 in the semiconductor device manufacturing equipment 101a and the output of the heater power supply, it judges whether the target temperature distribution calculated in step 504 can be realized. Here, if the predicted values ​​of the target temperature and the output of the heater power supply 202 are within the allowable range in all heater zones, the process proceeds to the END step, and the calculated temperature distribution is reflected in the process recipe in the semiconductor device manufacturing equipment 101a as an achievable target temperature distribution and is included therein as data, and the recipe is transmitted to the semiconductor device manufacturing equipment 101a via the network 106. Also, the semiconductor device manufacturing equipment 101a can process the wafer 205 using the process recipe transmitted from the wafer temperature calculation system 100.

[0066] On the other hand, if it is determined that either the target temperature or the predicted value of the output of the heater power supply 202 is outside the allowable range in at least one heater zone, the target temperature distribution calculated in step 504 is recorded in the storage device 104 as being unrealizable, and the process proceeds to step 507. At that time, the heater zone for which it is determined that the target temperature or the predicted value of the output of the heater power supply 202 is unrealizable is recorded in the storage device 104, so that the information on the heater zone can be confirmed when necessary.

[0067] Next, in step 507, only the heater power supplies 202 corresponding to the heater zones whose predicted output values ​​are outside the allowable range are changed so that their output values ​​are within the allowable range. That is, the output values ​​of the heater power supplies whose predicted output values ​​are outside the feasible range are changed to values ​​within the feasible range. In addition, the distributions of all the heater power supplies 202 are recorded as an initial distribution. By step 507, an initial distribution that allows the outputs of all the heater power supplies to be realized can be obtained.

[0068] Next, in step 508, the current output values ​​of all the heater power supplies 202 are recorded as a C distribution. This C distribution is updated as appropriate according to the flow shown in the figure, but the output of the heater power supplies 202 calculated in step 507 is recorded as an initial distribution.

[0069] Next, in step 509, the output value of the Nth heater power supply is increased or decreased within the minimum control range. That is, the output value of each heater power supply 202 to which a positive integer is assigned in step 502 is sequentially increased or decreased by a value of a predetermined magnitude. The magnitude of this change can be arbitrarily selected in the semiconductor device manufacturing system or semiconductor device manufacturing apparatus 101a, but it is necessary to set it to a value larger than the minimum width by which the output of the heater power supply 202 can be changed. Also, depending on the configuration of the heater power supplies 202, it is possible to change the output of each heater power supply 202 even if the heater power supplies 202 are used in the same wafer stage 200. For example, when the output value of an arbitrary heater power supply 202 in the C distribution recorded in step 508 is 50 W and the minimum control range of the heater power supply 202 is 0.1 W, the output value of the heater power supply 202 increased or decreased within the minimum changeable width becomes 50.1 W and 49.9 W.

[0070] Next, in step 510, it is determined whether the output value of the heater power supply 202 satisfies the limiting condition. That is, it is determined whether the output of the heater power supply 202 or the temperature of the wafer is within the allowable range by the output value of the heater power supply 202 increased or decreased in step 509. If it is determined that the allowable range condition is satisfied, the process proceeds to step 511, where a set of output values ​​including the output value of the heater power supply 202 increased or decreased in step 509 is treated as a distribution of feasible output values. On the other hand, if it is determined that the output value is outside the allowable range, the process returns to step 509, and a positive integer N assigned to each heater power supply 202 is increased to N+1 as a distribution (set of output values) of the output of the heater power supply 202 that cannot be realized, and then the process returns to step 509, where a different heater power supply 202 is examined.

[0071] Next, in step 511, the value of the objective function is calculated using the predicted values ​​of the outputs of all heater power supplies 202 output in step 510, using a first correlation between the output value of each heater power supply 202 and the in-plane distribution of the temperature of the wafer 205, and a second correlation between a set value of the in-plane distribution of the temperature of the wafer 205 and the in-plane distribution of a specific physical quantity of the wafer 205.

[0072] In the next step 512, the output value of the heater power supply 202 is updated and set based on the value of the objective function calculated in step 511. The objective function is calculated using the C distribution obtained in step 508, and is compared with the value of the objective function calculated from the output value of the heater power supply 202 increased or decreased in steps 509 to 511, and a distribution (combination) of the output value of the heater power supply 202 is selected according to the result. A detailed operational flow of this process will be described later with reference to FIG.

[0073] Next, in step 513, the value of the positive integer N assigned to each heater power supply 202 is confirmed, and if the value of N is the same as the number of heater power supplies 202 in use and is the largest value, it is determined that all heater power supplies have been changed (adjusted at least once), and the process proceeds to the next step 514. On the other hand, if it is determined that the value of N is smaller than the number of heater power supplies 202 in use, the value of N is incremented by 1 and the process returns to step 509.

[0074] Next, in step 514, in order to determine whether the calculation of the above objective function and the distribution of the output of the heater power supplies 202 has converged, it is determined whether the distribution of the output values ​​of each heater power supply 202 set in step 512 (i.e., the current output values ​​of each heater power supply) is the same as the C distribution. If it is different from the C distribution, it means that the calculation has not converged, so the value of N is returned to 1 and the flow returns to 508. On the other hand, if it is determined that it is the same value as the C distribution, it is determined that the calculation has converged and the distribution of the second target temperature has been calculated, and the process proceeds to step 515.

[0075] In step 515, assuming that the target temperature distribution calculated in step 506 or step 514 is realizable, the calculated target temperature distribution is reflected in a process recipe for semiconductor device manufacturing equipment 101a, and data on the temperature distribution is included in the process recipe, which is then transmitted to semiconductor device manufacturing equipment 101a. Semiconductor device manufacturing equipment 101a can process wafers 205 using the process recipe calculated and transmitted by wafer temperature calculation system 100.

[0076] 5A and B, it is determined whether a target temperature distribution that minimizes a predetermined objective function can be realized, and even if it is determined that the target temperature distribution cannot be realized, a second target temperature distribution that can minimize the objective function among all the achievable temperature distributions is calculated, and the wafer 205 is processed based on a process recipe that reflects the second target temperature distribution. This realizes a distribution of a specific physical quantity in an in-plane direction that can obtain a desired processing result in the processing, and improves the processing yield of the wafer 205.

[0077] 6, the flow of the operation of step 512 shown in FIG. 5B will be described in more detail. First, in step 601, the value of the objective function calculated in step 511 is compared with the value of the objective function calculated using the value of the C distribution in step 508. If it is determined in step 602 as a result of this comparison that only one of the objective function values ​​has decreased, the process proceeds to step 604, where the distribution of the output values ​​of the heater power supply 202 whose objective function value has decreased is determined to be the distribution (set) of the output values ​​of the heater power supply 202 to be set. In other words, the output value of the heater power supply is set to the one for which the objective function has decreased. If the value of the objective function calculated in step 511 has decreased, the distribution of the output values ​​of the heater power supply 202 corresponding to the objective function is updated as a new distribution.

[0078] Also, if it is not determined in step 602 that the value of only one of the objective functions has decreased, the process proceeds to step 603, where the value of the objective function calculated from the C distribution is compared with the value of the objective function calculated in step 511, and it is determined whether the values ​​of both objective functions have decreased. If it is determined that the values ​​of both objective functions have decreased, the process proceeds to step 605, where it is determined that the distribution of the output values ​​of the heater power supply 202 corresponding to the one with the greater decrease in the value of the objective function is the distribution (set) of the output values ​​of the heater power supply 202 to be set. In other words, the output value of the heater power supply is set to the one with the greater decrease in the objective function. If the value of the objective function calculated in step 511 has decreased more significantly, the distribution of the output values ​​of the heater power supply 202 corresponding to that objective function is updated to a new distribution.

[0079] On the other hand, if it is not determined in step 603 that the values ​​of both objective functions have decreased, it is assumed that the values ​​of both objective functions have increased or not changed. In this case, the process proceeds to step 606, and the distribution of the output values ​​of the heater power supply 202 is not changed from the C distribution. By updating the distribution of the output values ​​of the heater power supply 202 based on the above determination, the distribution is changed from the C distribution to the distribution of the output values ​​of the heater power supply that can minimize the value of the objective function as a result of increasing or decreasing the output of the heater power supply 202 from the C distribution.

[0080] In the above embodiment, when it is determined in step 506 that the output value of the heater power supply 202 is outside the allowable range, a process of reallocating the positive integer N assigned to each heater power supply 202 in order to shorten the calculation time will be described with reference to Fig. 7. Fig. 7 is a flowchart showing the flow of operations added to this embodiment shown in Fig. 5. Fig. 7 describes the process performed between step 507 and step 508 in Fig. 5.

[0081] In step 507, only those heater power supplies 202 whose predicted output values ​​are outside the tolerance range are changed so that their output values ​​are within the tolerance range. In addition, the distributions of all the heater power supplies 202 are recorded as initial distributions. In this step 507, the current outputs of all the heater power supplies 202 are assumed to be feasible initial distributions.

[0082] Next, in step 1001, the wafer temperature calculation system 100 calculates and stores the coordinates of the center of the heater zone connected to the heater power source 202 whose predicted output value of the heater power source 202 is outside the allowable range. In other words, the center coordinates of the heater zone connected to the heater power source whose predicted output value of the heater power source exceeds the limit value are calculated and recorded. Next, proceeding to step 1002, the wafer temperature calculation system 100 calculates and stores the difference between the target temperature in the heater zone connected to the heater power source 202 whose predicted output value of the heater power source 202 is outside the allowable range and the temperature of the wafer 205 calculated from the output value of the heater power source 202 changed in step 507. In other words, in the heater zone connected to the heater power source whose predicted output value of the heater power source exceeds the limit value, the difference between the target temperature and the wafer temperature calculated from the output value of the heater power source changed in 507 is recorded. The temperature difference is calculated, for example, by the following (Equation 1), but is not limited to (Equation 1) as long as it is an index representing the magnitude of the difference in temperature of the wafer 205 calculated from the target temperature and the output value of the heater power supply.

[0083]

number

[0084] where e is a positive integer assigned to the heater zone connected to the heater power supply whose predicted output exceeds the limit, E e is the wafer temperature difference in heater zone e, Tt e is the target temperature in heater zone e, Tp e is the wafer temperature calculated from the output value of the heater power supply changed in 507 in the heater zone e.

[0085] Next, in step 1003, the distance D between the coordinates of the center of the zone connected to the heater power supply 202 whose predicted output value of the heater power supply 202 is outside the allowable range and the coordinates of the centers of the other heater zones is calculated. ie In other words, the distance between the center coordinates of the heater zone connected to the heater power supply whose predicted output value of the heater power supply has exceeded the limit value and the center coordinates of each heater zone is calculated, where i is a positive integer assigned to each heater zone, and e is a positive integer assigned to the heater zone connected to the heater power supply 202 whose predicted output value of the heater power supply has fallen outside the allowable range.

[0086] Next, in step 1004, the wafer temperature calculation system 100 calculates the weight for each heater zone. The weight for each heater zone is calculated, for example, by the following formula:

[0087]

number

[0088]

number

[0089] In the above formula, N e is the number of heater zones connected to the heater power supply whose predicted output exceeds the limit value, and the weight for each heater zone i can be calculated using (Equation 3).

[0090] In the next flow of 1005, the weight calculated by (Equation 3) is reassigned to a smaller value of the positive integer N assigned to the heater power supply connected to each heater zone, the larger the weight calculated by (Equation 3) is.

[0091] In the next step 508, the wafer temperature calculation system 100 records the output value of each heater power supply 202 as a C distribution using the positive integer N reassigned in 1005 to the heater power supplies 202 connected to each heater zone.

[0092] By the above operation, the heater power supply 202 with a larger difference between the target temperature and the predicted temperature is assigned a smaller positive integer N value, and the predicted output value is calculated preferentially from the heater power supply 202 with the smaller integer N, thereby shortening the calculation time for the distribution of the objective function value and the output value. Note that, although an example of using the center coordinate is described in this example, the coordinate is not limited as long as it is within the heater zone. For example, the coordinate directly above the point where the input terminal of the heater power supply 202 is connected may be used for the calculation.

[0093] According to the above embodiment, in a semiconductor device manufacturing apparatus that uses a plurality of heaters 201 inside the wafer stage 200 to adjust the temperature and distribution of a wafer 205 placed on the wafer stage 200, a first target temperature distribution that minimizes the value of an objective function related to the distribution of a specific physical quantity after processing is calculated in advance before processing the wafer 205. Furthermore, output values ​​of the heater power supplies 202 connected to the plurality of heaters 201 for realizing the target temperature distribution are calculated, and it is determined whether or not the calculated output values ​​of all the heater power supplies 202 are within an allowable range. If it is determined that the output value of at least one of the plurality of heater power supplies 202 is outside the allowable range and cannot be realized, a second target temperature distribution that can be realized using the plurality of heater power supplies 202 and that minimizes the objective function value is calculated, and the set values ​​of the temperature and its distribution of the wafer stage 200 are updated in place of the first target temperature distribution, and a temperature distribution of the wafer 205 during processing that provides a desired processing result is realized, and the processing yield is improved.

[0094] The present invention is not limited to the above-mentioned embodiment, and various modifications are included. For example, the above-mentioned embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to those having all the configurations described. It is also possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace a part of the configuration of each embodiment with another configuration. [Explanation of symbols]

[0095] 100 Wafer temperature calculation system, 101 Semiconductor device manufacturing equipment, 102 Wafer measurement device, 200...wafer stage, 201 Heater, 202 Heater power supply, 203 Heater control unit, 204... Coolant flow path, 401 Heater zone.

Claims

1. a stage disposed within a processing chamber within a vessel and on an upper surface of which a wafer to be processed is placed; a plurality of heaters disposed within the stage below a plurality of regions on the upper surface of the stage; and a controller for adjusting power supplied to the plurality of heaters; The controller adjusts the power to achieve a second target temperature distribution obtained by correcting a first target temperature distribution given in advance to make the wafer at a target temperature during the processing.

2. 2. The wafer processing apparatus of claim 1, wherein the controller adjusts the power so that the first target temperature distribution is corrected to achieve the second target temperature distribution when it is determined that the power value for achieving the first target temperature distribution is not within an acceptable range.

3. 3. The wafer processing apparatus of claim 2, wherein when any of the powers supplied to the plurality of heaters to achieve the first target temperature distribution is outside an allowable range, the controller adjusts the power so that the second target temperature distribution is achieved in which the power falls within the allowable range.

4. 3. The wafer processing apparatus according to claim 1, wherein when an output of at least one of a plurality of power supplies that supply power to the plurality of heaters is outside an allowable range, the controller adjusts the output of the at least one power supply so that the output of the at least one power supply becomes the second target temperature distribution corresponding to a second output value that is within the allowable range.

5. 4. The wafer processing apparatus according to claim 3, wherein when an output of at least one of a plurality of power supplies that supply power to the plurality of heaters is outside an allowable range, the controller adjusts the output of the at least one power supply so that the output of the at least one power supply becomes the second target temperature distribution corresponding to a second output value that is within the allowable range.

6. 3. The wafer processing apparatus according to claim 1, wherein, when an output of at least one of the plurality of heater power sources is outside an allowable range, the controller adjusts the output of the at least one heater power source so that the output of the at least one heater power source is brought within the allowable range and the second target temperature distribution is achieved which minimizes the value of a predetermined objective function.

7. 7. The wafer processing apparatus of claim 6, wherein the controller adjusts the output of the plurality of heater power sources so as to obtain the second target temperature distribution obtained corresponding to the output of the power sources obtained by sequentially increasing or decreasing the output of each of the plurality of heater power sources until the value of the objective function becomes smallest.

8. 2. The wafer processing apparatus according to claim 1, further comprising: a display that displays, when an output value of at least one of the power supplies of the plurality of heaters is outside an allowable range, an area of ​​the heater corresponding to the power supply of the at least one heater.

9. A wafer processing method in a wafer processing apparatus including a stage disposed in a processing chamber inside a vessel and having a wafer to be processed placed on an upper surface thereof, a plurality of heaters disposed inside the stage below a plurality of regions on the upper surface of the stage, and a controller for adjusting power supplied to the plurality of heaters, comprising: A wafer processing method in which the power is adjusted to achieve a second target temperature distribution obtained by correcting a first target temperature distribution given in advance to bring the wafer to a target temperature during the processing.

10. 10. The wafer processing method according to claim 9, further comprising a step of adjusting the power when it is determined that the value of the power for achieving the first target temperature distribution is not within an acceptable range so that the first target temperature distribution becomes the second target temperature distribution obtained by correcting the first target temperature distribution.

11. 11. The wafer processing method of claim 10, further comprising a step of, when any of the powers supplied to the plurality of heaters to achieve the first target temperature distribution is outside an allowable range, adjusting the power so that the second target temperature distribution is achieved with the power being a value within the allowable range.

12. 11. The wafer processing method according to claim 9, further comprising a step of, when an output of at least one of a plurality of power supplies which supply power to the plurality of heaters is outside an allowable range, adjusting an output of the plurality of heater power supplies so that the output of the at least one power supply becomes the second target temperature distribution corresponding to a second output value which is within the allowable range.

13. 12. The wafer processing method according to claim 11, further comprising a step of, when an output of at least one of a plurality of power supplies which supply power to the plurality of heaters is outside an allowable range, adjusting an output of the plurality of heater power supplies so that the output of the at least one power supply becomes the second target temperature distribution corresponding to a second output value which is within the allowable range.

14. 11. The wafer processing method according to claim 9 or 10, further comprising a step of adjusting the outputs of the plurality of heater power sources when the outputs of at least one of the plurality of heater power sources are outside an allowable range, so that the outputs of the at least one heater power sources are brought within the allowable range and the second target temperature distribution is achieved which minimizes a value of a predetermined objective function.

15. 15. The wafer processing method according to claim 14, further comprising a step of adjusting the output of the plurality of heater power sources so as to obtain the second target temperature distribution obtained corresponding to the output of the power sources obtained by sequentially increasing or decreasing the output of each of the plurality of heater power sources until the value of the objective function is smallest.

16. A wafer processing method for a wafer processing apparatus further comprising a display, comprising:

10. The wafer processing method according to claim 9, further comprising a step of displaying an area of ​​the heater corresponding to the power supplies of at least one of the plurality of heaters when the output value of the at least one power supply of the plurality of heaters is outside an allowable range.

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