Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device that is suppressed from decreasing in reliability.SOLUTION: A silicon carbide semiconductor device 1 comprises: a semiconductor substrate 10 made of silicon carbide; an epitaxial growth layer 20 provided on the semiconductor substrate and made of silicon carbide; a first electrode 30 provided on the epitaxial growth layer; a second electrode 40 provided on the reverse of the semiconductor substrate, and an oxidation suppression layer 70 provided at least on the side wall 11 of the semiconductor substrate 10.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to silicon carbide semiconductor devices and methods of manufacturing the same. [Background technology]

[0002] Non-Patent Document 1 states that for n-type SiC substrates, 1 × 10 14 cm -3 ~1×10 16 cm -3 It is disclosed that boron and aluminum are unintentionally mixed in at a concentration of 1000 nm, which form an acceptor level and release holes. In addition, Non-Patent Document 2 discloses that holes are involved in moisture to form silicon oxide. In addition, Non-Patent Document 3 discloses the oxidation rate of silicon oxide films. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] T. Kimoto, and JA Cooper Jr., “Fundamentals of Silicon Carbide Technology”, John Wiley & Sons Singapore Pte. Ltd., p.59, p.91 [Non-Patent Document 2] Gautier et al. Nanoscale Research Letters 2012, 7:367 [Non-Patent Document 3] X.Shen et al., Appl. Phys. A (2016) 122:354 DOI 10.1007 / s00339-016-9896-y Summary of the Invention [Problem to be solved by the invention]

[0004] If silicon oxide is formed thickly, it may affect the reliability of the silicon carbide semiconductor device. In view of the above-mentioned problems, the present disclosure has an object to provide a silicon carbide semiconductor device in which a decrease in reliability is suppressed, and a method for manufacturing the same. [Means for solving the problem]

[0005] In order to achieve the above object, a silicon carbide semiconductor device according to one embodiment of the present disclosure comprises a semiconductor substrate made of silicon carbide, an epitaxial growth layer provided on the semiconductor substrate and made of silicon carbide, a first electrode provided on the epitaxial growth layer, a second electrode provided under the semiconductor substrate, and an oxidation inhibition layer provided on at least a side wall of the semiconductor substrate.

[0006] In order to achieve the above object, a method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes a step of growing an epitaxial growth layer made of silicon carbide on a semiconductor substrate made of silicon carbide, and a step of forming an oxidation inhibition layer on at least a side wall of the semiconductor substrate. Effect of the Invention

[0007] Advantageous Effects of Invention According to the present disclosure, it is possible to provide a silicon carbide semiconductor device in which deterioration in reliability is suppressed, and a method for manufacturing the same. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic vertical cross-sectional view showing an example of a general configuration of a silicon carbide semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 1 is a schematic plan view showing an example of a schematic configuration of a semiconductor chip included in a silicon carbide semiconductor device according to a first embodiment of the present disclosure. [Diagram 3] 3 is a schematic vertical cross-sectional view showing an enlarged portion of the cross-sectional configuration when viewed in cross-section along the AA cutting line in FIG. 2. [Figure 4] 1A to 1C are cross-sectional views illustrating process steps in a method for manufacturing a silicon carbide semiconductor device according to a first embodiment of the present disclosure. [Diagram 5]5 is a cross-sectional view showing a process subsequent to FIG. 4. [Figure 6] 6 is a cross-sectional view showing a process subsequent to FIG. 5. [Figure 7] 7 is a cross-sectional view showing a process subsequent to FIG. 6. [Figure 8] 10 is a schematic vertical cross-sectional view showing an example of a general configuration of a silicon carbide semiconductor device according to a second embodiment of the present disclosure. FIG. [Figure 9] 5A to 5C are cross-sectional views illustrating process steps in a method for manufacturing a silicon carbide semiconductor device according to a second embodiment of the present disclosure. [Figure 10] 10 is a cross-sectional view showing a process subsequent to FIG. 9. [Figure 11] 11 is a cross-sectional view showing a process subsequent to FIG. 10. [Figure 12] 12 is a cross-sectional view showing a process subsequent to FIG. 11. [Figure 13] 13 is a cross-sectional view showing a process subsequent to FIG. 12. [Figure 14] 14 is a cross-sectional view showing a process subsequent to FIG. 13. [Figure 15] FIG. 1 is a band diagram of n-type SiC in contact with magnesium. [Figure 16] 10A to 10C are cross-sectional views illustrating process steps of a method for manufacturing a silicon carbide semiconductor device according to a first modification of the second embodiment of the present disclosure. [Figure 17] 17 is a cross-sectional view showing a process subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view showing a process subsequent to FIG. 17. [Figure 19] 13 is a schematic vertical cross-sectional view showing an example of a schematic configuration of a silicon carbide semiconductor device according to Modification 2 of the second embodiment of the present disclosure. FIG. [Figure 20] 13A to 13C are cross-sectional views illustrating process steps of a method for manufacturing a silicon carbide semiconductor device according to Modification 2 of the second embodiment of the present disclosure. [Figure 21] 11 is a schematic vertical cross-sectional view showing an example of a general configuration of a silicon carbide semiconductor device according to a third embodiment of the present disclosure. FIG. [Figure 22] 11 is a schematic vertical cross-sectional view showing an example of a general configuration of a silicon carbide semiconductor device according to a fourth embodiment of the present disclosure. FIG. [Diagram 23]13 is a schematic vertical cross-sectional view showing an example of a schematic configuration of a unit cell structure formed in an active portion of a silicon carbide semiconductor device according to a fifth embodiment of the present disclosure. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the first to fifth embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted with the same or similar reference numerals, and duplicated explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each layer, etc. may differ from the actual ones. In addition, the drawings may include parts with different dimensional relationships and ratios. In addition, the first to fifth embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0010] In this specification, the source region of a metal-oxide semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), the "one main region" can be selected as the cathode region. The drain region of a MOSFET is the "other main region (second main region)" of the semiconductor device that can be selected as the collector region in an IGBT and as the anode region in a thyristor. In this specification, when the term "main region" is used simply, it means either the first main region or the second main region that is appropriate from the technical common sense of a person skilled in the art.

[0011] In addition, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are of course read as reversed. In addition, "upper surface" may be read as "front surface" and "lower surface" may be read as "reverse surface."

[0012] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be selected in the opposite relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the semiconductor regions have the same n and n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] In addition, there are crystal polymorphs in SiC crystals, the main ones being cubic 3C, and hexagonal 4H and 6H. The band gap at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. The following explanation will be given as an example in which 4H-SiC is mainly used.

[0014] [First embodiment] The configuration of a silicon carbide semiconductor device according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 3. FIG.

[0015] <Configuration of silicon carbide semiconductor device> As shown in FIG. 1, a SiC (silicon carbide) semiconductor device 1 includes, for example, a semiconductor chip 1A, an insulating circuit board 1B, a solder layer 1C, a sealing resin 1D, and wires 1E. The semiconductor chip 1A is bonded to the upper surface of the insulating circuit board 1B via the solder layer 1C. The configuration of the semiconductor chip 1A will be described in detail later. The insulating circuit board 1B is, for example, a direct copper bonding board. The insulating circuit board 1B includes a substrate 1Ba made of an insulating material and a conductor 1Bb provided on the upper surface of the substrate 1Ba and forming a circuit pattern. The substrate 1Ba is, for example, made of aluminum oxide (Al 2 O 3The conductor 1Bb is made of a ceramic such as aluminum nitride (AlN) or silicon nitride (SiN). The conductor 1Bb is made of a conductor such as metal, for example, copper. The sealing resin 1D seals the semiconductor chip 1A. The sealing resin 1D is provided on the upper surface side of the insulating circuit board 1B and covers the upper surface of the insulating circuit board 1B and the semiconductor chip 1A. The sealing resin 1D is made of a material such as epoxy resin or silicone gel. Note that epoxy resin is a material with a higher hardness than silicone gel. In this embodiment, the sealing resin 1D is described as being epoxy resin. The sealing resin 1D is provided on the side wall 11 of the semiconductor substrate 10 via an oxidation suppression layer 70. The wire 1E electrically connects the semiconductor chip 1A to a terminal of the package of the module. The wire 1E is made of, for example, aluminum (Al).

[0016] <Semiconductor chip> The semiconductor chip 1A is a semiconductor chip including a SiC semiconductor material. In this embodiment, the semiconductor chip 1A will be described as a semiconductor chip including a Schottky barrier diode (SBD). As shown in FIG. 2, the semiconductor chip 1A includes an active portion 1Aa and a voltage withstanding structure portion 1Ab provided so as to surround the periphery of the active portion 1Aa in a plan view. The active portion 1Aa is a region through which a current flows when the Schottky barrier diode is in a conductive state. The voltage withstanding structure portion 1Ab is provided to relieve the electric field on the front surface side of the semiconductor chip 1A. The voltage withstanding structure portion 1Ab is provided with a ring-shaped electric field relief region 22 as a termination structure.

[0017] 3 is a cross-sectional view taken along the line AA in FIG. 2. As shown in FIG. 3, the semiconductor chip 1A includes a semiconductor substrate 10 made of SiC, an epitaxial growth layer 20 made of SiC provided on the upper surface of the semiconductor substrate 10, a front surface electrode 30 provided on the upper surface of the epitaxial growth layer 20, and a back surface electrode 40 provided on the lower surface of the semiconductor substrate 10. The front surface electrode 30 includes a Schottky metal layer 30a and a wiring layer 30b thereon. The semiconductor chip 1A is a vertical silicon carbide diode chip with an SBD structure in which a Schottky junction is formed between the epitaxial growth layer 20 and the Schottky metal layer 30a of the front surface electrode 30. The front surface electrode 30 is an example of a first electrode, and the back surface electrode is an example of a second electrode.

[0018] The semiconductor substrate 10 is, for example, + The semiconductor substrate 10 is a substrate made of 4H-SiC of the type. 18 cm -3 The semiconductor substrate 10 is doped with nitrogen (N) as a donor impurity at a concentration of about 100 nm. The semiconductor substrate 10 may have an off-angle of about 4° with respect to the (0001) plane. According to Non-Patent Document 1, acceptor impurities such as boron (B) and aluminum (Al) may be mixed into the semiconductor substrate 10 during the manufacturing process. The acceptor impurities mixed into the semiconductor substrate 10 form an acceptor level and emit holes.

[0019] The epitaxial growth layer 20 is, for example, - The epitaxial growth layer 20 is made of 4H-SiC of the type 10 and functions as a drift layer. 16 cm -3The epitaxial growth layer 20 includes nitrogen (N) at a concentration of about 1000 nm. The epitaxial growth layer 20 is provided on the sidewalls (sidewall surfaces) 11 as well as on the upper surface of the semiconductor substrate 10. More specifically, the epitaxial growth layer 20 is also provided on the four sidewalls 11 of the semiconductor substrate 10. The portion of the epitaxial growth layer 20 provided on the sidewalls 11 is called the epitaxial growth layer 21 in order to distinguish it from the other portions. When the epitaxial growth layer 21 is not distinguished from the other portions, it is simply called the epitaxial growth layer 20. The epitaxial growth layer 21 covers the sidewalls 11 of the semiconductor substrate 10 to prevent the sidewalls 11 from directly contacting the sealing resin 1D. The epitaxial growth layer 21 is an example of an oxidation suppression layer 70 that suppresses oxidation of the sidewalls 11 of the semiconductor substrate 10.

[0020] The concentration of the acceptor impurity contained in the epitaxial growth layer 20 is sufficiently lower than the concentration of the acceptor impurity contained in the semiconductor substrate 10. The concentration of the acceptor impurity contained in the epitaxial growth layer 20 is, for example, 1×10 14 cm -3 According to Non-Patent Document 1, when epitaxial growth is performed, the carbon (C) of the source gas propane and the silane (SiH 4 When the C / Si ratio was increased, the donor (nitrogen) density of the epitaxial layer obtained at a C / Si ratio of 2.0 was 5×10 12 cm -3 At a C / Si ratio above this, the epitaxial growth layer is inverted to p-type, so n - The acceptor impurities in the epitaxial growth layer 20 of the type are 5×10 12 cm -3 By covering the sidewall 11 with an epitaxially grown layer 21 having a sufficiently low acceptor impurity concentration, it is possible to suppress the emission of holes.

[0021] In the epitaxial growth layer 21, a depletion layer is formed that spreads from the surface side to the semiconductor substrate 10 side. When the depletion layer reaches the semiconductor substrate 10 from the surface of the epitaxial growth layer 21, the holes in the semiconductor substrate 10 are transported to the surface of the epitaxial growth layer 21. Therefore, the thickness of the epitaxial growth layer 21 is set to be larger than the thickness of the depletion layer that spreads from the surface side to the semiconductor substrate 10 side, and the transport of the holes to the surface of the epitaxial growth layer 21 is suppressed. The thickness of the epitaxial growth layer 21 required to suppress the transport of the holes is determined according to the concentration of the donor impurity contained in the epitaxial growth layer 21. For example, the thickness W of the depletion layer is calculated assuming that the epitaxial growth layer 21 is in Schottky junction with a metal instead of the sealing resin 1D. The thickness W of the depletion layer can be calculated by the following formula (1) when the Schottky barrier height is considered to be at most about 2 eV. W=sqrt(2·εs·φb / q / Nd) …(1) Here, εs = 9.7 × ε0 = 9.7 × 8.854 × 10 14 [F / cm], φb=2[eV], q=1.0602×10 19 [C], Nd is the impurity concentration [cm -3 The thickness of the depletion layer, W, is Nd = 3 × 10 16 [cm -3 ] at 0.27 [μm], Nd = 1 × 10 16 [cm -3 ] at 0.46 [μm], Nd = 5 × 10 15 [cm -3 ] at 0.66 [μm], Nd = 3 × 10 15 [cm -3 By making the thickness of the epitaxial growth layer 21 about 1 μm or more, Nd becomes 3×10 15 [cm -3 ] or more, 3×10 16 [cm -3 ] or less, the transport of holes can be suppressed.

[0022] An electric field relaxation region 22 and a stopper region 23 are provided on the upper surface side of the epitaxial growth layer 20 of the breakdown voltage structure portion 1Ab. The electric field relaxation region 22 is a structure such as a junction termination extension (JTE) structure or a field limiting ring (FLR) structure, and is a semiconductor region made of p-type SiC. The electric field relaxation region 22 faces the upper surface of the epitaxial growth layer 20 but does not face the sidewall 11, and is not in contact with the sealing resin 1D. The stopper region 23 is an n + Although not shown in the drawings, the semiconductor region 21 is provided at a distance from the electric field relaxation region 22 in a plan view and so as to surround the electric field relaxation region 22.

[0023] The semiconductor chip 1A includes an insulating film 60 provided on the upper surfaces of the electric field relaxation region 22 and the stopper region 23, and a passivation film 50 provided on the upper surface of the insulating film 60. The insulating film 60 may be, for example, a silicon oxide film (BPSG film) doped with boron (B) and phosphorus (P), a silicon oxide film (PSG film) doped with phosphorus (P), a non-doped silicon oxide film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG film) doped with boron (B), a silicon nitride film (Si 3 N 4 The passivation film 50 is made of, for example, polyimide.

[0024] The front electrode 30 is joined to the epitaxial growth layer 20 in the active portion 1Aa, and the junction side is made of a metal that forms a Schottky junction with the epitaxial growth layer 20. The front electrode 30 is made of a Schottky metal layer 30a of, for example, titanium (Ti) or molybdenum (Mo) and a wiring layer 30b made of aluminum (Al) or an aluminum alloy (for example, Al-Si, Al-Si-Cu) thereon. In addition, when the semiconductor chip 1A is a MOSFET, the front electrode 30 is formed from a silicide layer (nickel silicide (NiSi x) or the like), a barrier metal layer (titanium nitride (TiN) or titanium (Ti)), and the wiring layer 30b made of aluminum (Al) or an aluminum alloy as described above.

[0025] The back electrode 40 is provided on the entire lower surface of the semiconductor chip 1A. The back electrode 40 can be, for example, a single layer film made of gold (Au) or a metal film laminated in the order of titanium (Ti), nickel (Ni) and Au from the semiconductor substrate 10 side, and further a metal film of molybdenum (Mo), tungsten (W) or the like may be laminated on the bottom layer. Nickel silicide (NiSi x A drain contact layer such as a SiO 2 film may be provided.

[0026] <Manufacturing method of silicon carbide semiconductor device> Hereinafter, a method for manufacturing the SiC semiconductor device 1 will be described with reference to FIG. 4 to FIG. 7. In this embodiment, a method for forming the semiconductor chip 1A will be mainly described. In addition, in FIG. 4 to FIG. 7, some of the components of the semiconductor chip 1A shown in FIG. 3 are omitted from illustration. First, as shown in FIG. 4, a wafer Wf made of a silicon carbide semiconductor constituting the semiconductor substrate 10 is prepared, and a groove T is formed in the upper part of the prepared wafer Wf to partition the spaces between the plurality of semiconductor substrates 10. The groove T has a width of about 100 μm in a plan view, for example, and is provided to a depth of about 200 μm along the thickness direction of the wafer Wf. The groove T is formed, for example, by dry etching. The partitioned plurality of semiconductor substrates 10 are connected to each other at the lower part of the wafer Wf. Hereinafter, the process of forming the groove T to partition the spaces between the plurality of semiconductor substrates 10 may be referred to as a partitioning process. The partitioning process exposes the sidewall 11 of the semiconductor substrate 10 in the groove T.

[0027] Then, as shown in FIG. 5, an epitaxial growth layer 20 is grown on the upper part of the wafer Wf, that is, on the surface of the wafer Wf on which the groove T is formed. At this time, the epitaxial growth layer 20 is laminated on the upper surface of the semiconductor substrate 10, the side wall 11, and the bottom surface of the groove T. The epitaxial growth layer 21 laminated on the side wall 11 corresponds to the oxidation suppression layer 70. Then, the configuration of the upper part of the semiconductor chip 1A is completed. For example, a process of forming semiconductor regions such as an electric field relaxation region 22 and a stopper region 23 by ion-implanting impurities into the epitaxial growth layer 20 (not shown), a process of forming an insulating film 60, a front surface electrode 30, and a passivation film 50, and the like are performed to complete the configuration of the upper part of the semiconductor chip 1A. Note that the electric field relaxation region 22, which is a p-type semiconductor region, is provided at a position not exposed to the side wall 11.

[0028] Next, as shown in FIG. 6, the upper surface side of the wafer Wf is bonded to a glass substrate Y using an adhesive X. Then, as shown in FIG. 7, the lower surface side of the wafer Wf is ground. More specifically, the wafer Wf is ground from the lower surface side until the grooves T are exposed, and is diced into a plurality of semiconductor chips 1A on which epitaxial growth layers 21 are formed as oxidation suppression layers 70. The diced semiconductor chips 1A are fixed to the glass substrate Y, and therefore will not fall. The thickness of the wafer Wf after grinding is, for example, about 100 μm or more and 150 μm or less. Thereafter, although not shown, a back surface electrode 40 is formed on the lower surface side of the diced semiconductor chips 1A.

[0029] Thereafter, the semiconductor chip 1A is peeled off from the glass substrate Y, and the adhesive X is removed. This nearly completes the semiconductor chip 1A. Then, the back electrode 40 of the semiconductor chip 1A is joined to the conductor 1Bb of the insulating circuit board 1B by the solder material constituting the solder layer 1C. Then, the wire 1E is connected to the front electrode 30. Then, the semiconductor chip 1A is sealed with sealing resin 1D, and the SiC semiconductor device 1 is nearly completed.

[0030] Depending on the semiconductor chip 1A, multiple epitaxial growth layers 20 may be provided. When multiple epitaxial growth layers 20 are provided, if the thickness of the epitaxial growth layer 21 can be set to be greater than the thickness of the depletion layer, a groove T may be formed in the upper part of the wafer Wf after forming some of the multiple epitaxial growth layers 20.

[0031] <<Main Effects of the First Embodiment>> Below, the main effects of the first embodiment will be described, but before that, a reliability test of the SiC semiconductor device 1 will be described. One of the reliability tests is a THB (temperature humidity bias) test. The THB test is a high temperature and high humidity bias test in which the SiC semiconductor device 1 is placed in a high temperature and high humidity environment for a long period of time to test whether there is any change in the characteristics. As a result, under certain conditions, silicon oxide (SiO 2 As shown in the following chemical reaction formulas (2) and (3) described in Non-Patent Document 2, the silicon oxide film reacts with water to form holes (h + ) is thought to be produced by anodic oxidation involving SiC+3H 2 O+6h + →SiO 2 +CO↑+6H + …(2) SiC+4H 2 O+8h + →SiO 2 +CO 2 ↑+8H + …(3)

[0032] Non-Patent Document 3 discloses an example of the rate of progression of anodic oxidation under certain experimental conditions. More specifically, it discloses that the relationship between time t (S) and the thickness x (nm) of an oxide film formed on 4H—SiC is expressed by the following formula (4) based on experimental results. t=0.0047x 2 +0.1729x …(4)

[0033] If a thick silicon oxide film is formed on the sidewall 11 of the semiconductor substrate 10, the sealing resin 1D is subjected to stress, and a gap may occur at the interface between the sealing resin 1D and the semiconductor chip 1A. If such a gap occurs, there is a possibility that a short circuit may occur between the front surface electrode 30 and the back surface electrode 40.

[0034] In contrast, the SiC semiconductor device 1 according to the first embodiment includes a semiconductor substrate 10 made of silicon carbide, an epitaxial growth layer 20 made of silicon carbide provided on the semiconductor substrate 10, a front surface electrode 30 provided on the epitaxial growth layer 20, a back surface electrode 40 provided under the semiconductor substrate 10, and an oxidation suppression layer 70 provided on at least the side wall 11 of the semiconductor substrate 10. By covering the side wall 11 of the semiconductor substrate 10 with the oxidation suppression layer 70, it is possible to reduce holes at the interface between the side wall of the semiconductor chip 1A and the sealing resin 1D. This makes it possible to suppress the generation of a thick silicon oxide film on the side wall 11, and to suppress the deterioration of the reliability of the SiC semiconductor device 1.

[0035] In the SiC semiconductor device 1 according to the first embodiment, the oxidation inhibition layer 70 is formed of a part of the n-type epitaxial growth layer 20. The concentration of acceptor impurities contained in the epitaxial growth layer 20 constituting the oxidation inhibition layer 70 is lower than the concentration of acceptor impurities contained in the semiconductor substrate 10, and is 1×10 14 cm -3 8. Since the thickness of the sidewall 11 is smaller than that of the sidewall 11, the number of holes at the interface between the sidewall 11 and the sealing resin 1D of the semiconductor chip 1A can be reduced. This makes it possible to prevent a thick silicon oxide film from being formed on the sidewall 11, and thus to prevent a decrease in the reliability of the SiC semiconductor device 1.

[0036] Furthermore, in the SiC semiconductor device 1 according to the first embodiment, the thickness of the epitaxial growth layer 21 constituting the oxidation prevention layer 70 is set to be larger than the thickness of the depletion layer spreading from the front surface side of the epitaxial growth layer 21 to the semiconductor substrate 10. This makes it possible to prevent holes in the semiconductor substrate 10 from being transported to the interface between the sidewall of the semiconductor chip 1A and the sealing resin 1D via the depletion layer.

[0037] Moreover, the manufacturing method of the SiC semiconductor device 1 according to the first embodiment includes a step of preparing a wafer Wf made of a silicon carbide semiconductor constituting the semiconductor substrate 10, a partitioning step of forming grooves T in the upper part of the wafer Wf to partition the plurality of semiconductor substrates 10 from each other, and a step of forming an oxidation prevention layer 70 on the sidewall 11 of the semiconductor substrate 10 exposed in the grooves T. Therefore, the oxidation prevention layer 70 can be formed collectively for each wafer Wf, and a large increase in manufacturing costs can be suppressed.

[0038] Furthermore, in the manufacturing method of the SiC semiconductor device 1 according to the first embodiment, the step of forming the oxidation prevention layer 70 is performed in a step of growing the epitaxial growth layer 20, in which an n-type epitaxial growth layer 21 is formed as the oxidation prevention layer 70. Since the epitaxial growth layer 21 is formed simultaneously in the step of forming the epitaxial growth layer 20, a significant increase in the number of manufacturing steps can be suppressed.

[0039] Moreover, the manufacturing method of the SiC semiconductor device 1 according to the first embodiment includes a step of grinding the wafer Wf from the underside until the grooves T are exposed, and dicing the wafer Wf into a plurality of semiconductor chips 1A each having an oxidation prevention layer 70. Therefore, the dicing step of the semiconductor chips 1A can be omitted.

[0040] [Second embodiment] The second embodiment shown in Fig. 8 will be described below. In the SiC semiconductor device 1 according to the second embodiment, the oxidation prevention layer 70 is made of a metal material. The rest of the configuration of the SiC semiconductor device 1 is basically the same as that of the SiC semiconductor device 1 of the above-mentioned first embodiment. The same reference numerals are used for the components already described, and the description thereof will be omitted.

[0041] The oxidation suppression layer 70 is provided as a metal layer 31 provided on the sidewall 11 of the semiconductor substrate 10 and on the sidewall (sidewall surface) 20a of the epitaxial growth layer 20. The metal layer 31 is provided on the four sidewalls 11 and the four sidewalls 20a. As shown in the figure, the metal layer 31 may cover a part of the upper surface of the epitaxial growth layer 20, but is electrically separated from the front surface electrode 30. The thickness of the metal layer 31 is, for example, 100 nm or more. The thickness of the metal layer 31 may be 200 nm or more. The metal material constituting the metal layer 31 is the same material as the metal material constituting the front surface electrode 30. In this embodiment, the metal layer 31 and the front surface electrode 30 are described as being made of aluminum.

[0042] The metal layer 31 has the same potential as the back electrode 40 and the sidewall of the semiconductor chip 1A. Since the metal layer 31 has the same potential as the semiconductor substrate 10, a leakage current (holes) is unlikely to flow between the semiconductor substrate 10 and the metal layer 31. Therefore, the holes in the semiconductor substrate 10 are unlikely to be transported to the sidewall surface of the sidewall 11.

[0043] <Manufacturing method of silicon carbide semiconductor device> Hereinafter, a method for manufacturing the SiC semiconductor device 1 will be described with reference to Figs. 9 to 14. Note that in this embodiment, a method for forming the semiconductor chip 1A will be mainly described. Also, in Figs. 9 to 14, some of the components of the semiconductor chip 1A shown in Fig. 8 are omitted from illustration. Also, descriptions of the same steps as those in the first embodiment described above may be omitted.

[0044] First, as shown in FIG. 9, an epitaxial growth layer 20 is grown on the top of a prepared wafer Wf. Then, as shown in FIG. 10, a groove T is formed on the top of the prepared wafer Wf to partition the spaces between the multiple semiconductor substrates 10. In this partitioning step, the groove T is formed from the top surface of the epitaxial growth layer 20 to the top of the semiconductor substrate 10. The groove T has a width of, for example, about 100 μm in a plan view, and is provided to a depth of about 200 μm along the thickness direction of the wafer Wf. The groove T is formed, for example, by dry etching. The partitioned multiple semiconductor substrates 10 are connected to each other at the bottom of the wafer Wf. By the partitioning step, the side wall 11 of the semiconductor substrate 10 and the side wall 20a of the epitaxial growth layer 20 are exposed in the groove T.

[0045] Next, various processes are performed, such as a process of forming semiconductor regions such as the electric field relaxation region 22 and the stopper region 23, a process of forming an insulating film 60, etc., which are not shown in the figure, and then a process of forming a front surface electrode 30 is performed. The process of forming the front surface electrode 30 includes a process of forming a metal layer 31. First, as shown in Fig. 11, a metal film 30m made of aluminum is grown on the upper part of the wafer Wf, i.e., on the surface of the wafer Wf on which the groove T is formed. At that time, the metal film 30m is laminated on the upper surface of the epitaxial growth layer 20, the side walls 11 and 20a, and the bottom surface of the groove T.

[0046] 12, excess portions of the metal film 30m are removed using known lithography and etching techniques, leaving portions of the metal film 30m that correspond to the front electrode 30 and the metal layer 31. Thereafter, a process of forming a passivation film 50 and the like are performed to complete the structure of the upper portion of the semiconductor chip 1A. The passivation film 50 is provided in the area where the metal film 30m has been removed.

[0047] Next, as shown in FIG. 13, the upper surface side of the wafer Wf is bonded to the glass substrate Y using an adhesive X. Then, as shown in FIG. 14, the lower surface side of the wafer Wf is ground. More specifically, the wafer Wf is ground from the lower surface side until the grooves T are exposed, and is singulated into a plurality of semiconductor chips 1A on which the metal layer 31 is formed as the oxidation suppression layer 70. The singulated semiconductor chips 1A are fixed to the glass substrate Y, and therefore will not fall. The thickness of the wafer Wf after grinding is, for example, about 100 μm or more and 150 μm or less. Thereafter, although not shown in the drawings, a back surface electrode 40 is formed on the lower surface side of the singulated semiconductor chip 1A, and the semiconductor chip 1A is almost completed. The subsequent processing is the same as that of the first embodiment described above, and therefore will not be described.

[0048] <<Main Effects of the Second Embodiment>> The following describes the main effects of the second embodiment. The SiC semiconductor device 1 according to the second embodiment also provides the same effects as the SiC semiconductor device 1 according to the first embodiment described above.

[0049] In the SiC semiconductor device 1 according to the second embodiment, the oxidation prevention layer 70 is made of a metal material and has the same potential as the side wall of the semiconductor chip 1A. This makes it possible to prevent holes in the semiconductor substrate 10 from being transported to the side wall 11. This makes it possible to prevent a silicon oxide film from being formed thickly on the side wall 11, and thus makes it possible to prevent the reliability of the SiC semiconductor device 1 from being reduced.

[0050] Moreover, in the SiC semiconductor device 1 according to the second embodiment, since the sidewall 11 is covered with the metal layer 31, moisture is less likely to reach the sidewall 11. This makes it possible to prevent a thick silicon oxide film from being generated on the sidewall 11, and thus makes it possible to prevent a decrease in the reliability of the SiC semiconductor device 1.

[0051] In the SiC semiconductor device 1 according to the second embodiment, when the electric field relaxation region 22 faces the sidewall 20a, the metal layer 31 covers from the sidewall 20a to a part of the upper surface of the epitaxial growth layer 20, thereby preventing holes in the electric field relaxation region 22 from being transported to the sidewall 20a. This prevents a thick silicon oxide film from being generated on the sidewall 20a, and prevents the reliability of the SiC semiconductor device 1 from decreasing.

[0052] <Modification of the second embodiment> A modification of the second embodiment will be described below.

[0053] <Variation 1> In the SiC semiconductor device 1 according to the second embodiment, the metal layer 31 is made of the same metal material as the front surface electrode 30, but in the SiC semiconductor device according to Modification 1 of the second embodiment, the metal layer 31 is made of a metal material different from that of the front surface electrode 30. This modification will be described by also using FIG. 8 of the second embodiment.

[0054] In this modification, a metal having a work function smaller than the electron affinity of the semiconductor substrate 10 is used as the metal material constituting the metal layer 31. For example, when the electron affinity of SiC constituting the semiconductor substrate 10 is 3.8 eV, zinc (Zn) having a work function of 3.63 eV or magnesium (Mg) having a work function of 3.66 eV is selected as the metal material constituting the metal layer 31. FIG. 15 shows a band diagram of n-type SiC in contact with magnesium (Mg). If the work function of the metal material constituting the metal layer 31 is smaller than the electron affinity of the semiconductor substrate 10, which is n-type SiC, an energy barrier against holes is formed as shown in the figure. This makes it possible to further suppress the transport of holes in the semiconductor substrate 10 to the sidewall surface of the sidewall 11.

[0055] Hereinafter, a method for manufacturing the SiC semiconductor device 1 will be described with reference to Figs. 16 to 18. Note that in this modification, differences from the manufacturing method described in the second embodiment will be mainly described. An example in which magnesium is used as a metal having a work function smaller than the electron affinity of the semiconductor substrate 10 will be described. Also, in Figs. 16 to 18, some of the components of the semiconductor chip 1A shown in Fig. 8 are omitted from illustration. Also, the figures used in the second embodiment will be referred to as appropriate.

[0056] First, the steps up to the step shown in FIG. 10 are performed. Then, as shown in FIG. 16, a metal film 31m made of magnesium is grown on the upper part of the wafer Wf, that is, on the surface of the wafer Wf on which the groove T is formed. At this time, the metal film 31m is laminated on the upper surface of the epitaxial growth layer 20, the side walls 11, 20a, and the bottom surface of the groove T. Then, as shown in FIG. 17, the part of the metal film 31m laminated on the upper surface of the epitaxial growth layer 20 is removed by etching back. This results in the metal layer 31. Then, as shown in FIG. 18, a step of forming the upper part of the semiconductor chip 1A is performed. The front surface electrode 30 is formed of aluminum. The steps thereafter are the same as those in the second embodiment, and therefore will not be described.

[0057] Even with the SiC semiconductor device 1 according to the first modification of the second embodiment, the same effects as those of the SiC semiconductor device 1 according to the second embodiment described above can be obtained.

[0058] Furthermore, in the SiC semiconductor device 1 according to variant example 1 of the second embodiment, the work function of the metal material constituting the metal layer 31 is smaller than the electron affinity of the semiconductor substrate 10, so that an energy barrier against holes can be formed, and the transport of holes in the semiconductor substrate 10 to the side wall 11 can be further suppressed.

[0059] <Variation 2> In the SiC semiconductor device 1 according to the second modification of the second embodiment, as shown in FIG. 19, the oxidation suppression layer 70 is made of polyimide. In this modification, the passivation film 50 made of polyimide is provided on the upper surface of the epitaxial growth layer 20, the sidewall 20a of the epitaxial growth layer 20, and the sidewall 11 of the semiconductor substrate 10. In order to distinguish the portion of the passivation film 50 provided on the sidewalls 11 and 20a from the other portions, the portion is called the passivation film 51. When the passivation film 51 is not distinguished from the other portions, it is simply called the passivation film 50. The passivation film 51 is an example of the oxidation suppression layer 70. The passivation film 51 is provided on the four sidewalls 11 and the four sidewalls 20a.

[0060] Hereinafter, a method for manufacturing the SiC semiconductor device 1 will be described with reference to FIG. 20. In this modification, differences from the manufacturing method described in the second embodiment will be mainly described. In this modification, after the front surface electrode 30 is formed, a passivation film 50m is formed on the upper part of the wafer Wf, i.e., on the surface of the wafer Wf on which the grooves T are formed. Thereafter, the lower surface side of the wafer Wf is ground and divided into individual pieces in the same manner as the manufacturing method described in the second embodiment. Descriptions of subsequent steps will be omitted.

[0061] In the SiC semiconductor device 1 according to this modification, the side wall 11 is covered with the passivation film 51, so that moisture is less likely to reach the side wall 11. This makes it possible to prevent a thick silicon oxide film from being generated on the side wall 11, and to prevent a decrease in the reliability of the SiC semiconductor device 1.

[0062] [Third embodiment] The third embodiment shown in Fig. 21 will be described below. In the SiC semiconductor device 1 according to the third embodiment, the oxidation prevention layer 70 is a part of the solder layer 1C. The rest of the configuration of the SiC semiconductor device 1 is basically the same as that of the SiC semiconductor device 1 of the second embodiment described above. The same reference numerals are used for the components already described, and the description thereof will be omitted.

[0063] A part of the solder layer 1C constituting the oxidation prevention layer 70 is called the solder layer 1Ca to distinguish it from the other parts. When the solder layer 1Ca is not distinguished from the other parts, it is simply called the solder layer 1C. The solder layer 1Ca is provided on the sidewall 11 of the semiconductor substrate 10 and on the sidewall 20a of the epitaxial growth layer 20. The solder layer 1Ca is provided on the four sidewalls 11 and on the four sidewalls 20a. The solder layer 1Ca may cover a part of the upper surface of the epitaxial growth layer 20, but is electrically separated from the front surface electrode 30. The material constituting the solder layer 1C is a solder material. The solder material is a type of metallic material.

[0064] The solder layer 1Ca has the same potential as the back electrode 40 and the side wall of the semiconductor chip 1A. Since the solder layer 1Ca has the same potential as the semiconductor substrate 10, leakage current (holes) is unlikely to flow between the semiconductor substrate 10 and the solder layer 1Ca. Therefore, the holes in the semiconductor substrate 10 are unlikely to be transported to the side wall surface of the side wall 11.

[0065] <Manufacturing method of silicon carbide semiconductor device> A method for manufacturing the SiC semiconductor device 1 will be described below. The description will be made with reference to FIG. 21. First, an individual semiconductor chip 1A is formed. Then, when the semiconductor chip 1A is bonded to the insulating circuit board 1B with a solder material, the side wall 11 of the semiconductor substrate 10 and the side wall 20a of the epitaxial growth layer 20 are covered with the solder material. At that time, a large amount of solder material is used so that it spreads to the side walls 11 and 20a. In this way, the solder layer 1Ca is formed. Also, flux or the like may be used to help the solder material adhere to the side walls 11 and 20a. The description of the subsequent steps will be omitted.

[0066] <<Main Effects of the Third Embodiment>> The following describes the main effects of the third embodiment. The SiC semiconductor device 1 according to the third embodiment also provides the same effects as the SiC semiconductor device 1 according to the second embodiment described above.

[0067] Furthermore, in the SiC semiconductor device 1 of the third embodiment, when the individual semiconductor chips 1A are joined to the insulating circuit board 1B with solder material, the solder material covers the side walls 11, 20a to form the oxidation prevention layer 70, so that the oxidation prevention layer 70 can be formed without significantly changing the manufacturing process.

[0068] [Fourth embodiment] In this fourth embodiment, the first embodiment is combined with the second or third embodiment. An example of combining the first embodiment with the second embodiment will be described below with reference to Fig. 22. Components that have already been described will be given the same reference numerals and their description will be omitted.

[0069] 22, the oxidation prevention layer 70 includes a first layer 71 and a second layer 72 provided on an upper surface of the first layer 71. The first layer 71 is an epitaxial growth layer 21, and the second layer 72 is made of a metal material. In this embodiment, the second layer 72 is the metal layer 31 described in the second embodiment. The metal layer 31 is formed after the epitaxial growth layer 21 is formed. The other manufacturing steps are the same as those in the first and second embodiments, so a description thereof will be omitted.

[0070] <<Main Effects of the Fourth Embodiment>> The main effects of the fourth embodiment will be described below. The SiC semiconductor device 1 according to the fourth embodiment also provides the same effects as the SiC semiconductor device 1 according to any one of the first to third embodiments described above.

[0071] In the SiC semiconductor device 1 according to the fourth embodiment, the oxidation suppression layer 70 includes a first layer 71 and a second layer 72 provided on the upper surface of the first layer 71, the first layer 71 being a part of the n-type epitaxial growth layer 21, and the second layer 72 being made of a metal material. Therefore, the epitaxial growth layer 21 can reduce the number of holes on the sidewall 11, and the metal layer 31 can suppress the transport of the holes to the sidewall 11. This can further suppress the generation of a thick silicon oxide film on the sidewall 11, and suppress the deterioration of the reliability of the SiC semiconductor device 1. The metal layer 31 may be the solder layer 1Ca described in the third embodiment.

[0072] [Fifth embodiment] In the above-described first embodiment, a Schottky barrier diode is configured in the semiconductor chip 1A included in the SiC semiconductor device 1. In contrast, in the present fifth embodiment, an example in which a MOSFET is configured in the semiconductor chip 1A will be described.

[0073] <Structure of insulated gate semiconductor device> 23 shows a cross-sectional configuration of a unit cell structure formed in the active portion 1Aa. Although not shown, an electric field relaxation region 22 and a stopper region 23 are provided so as to surround the active portion 1Aa in a plan view. As shown in FIG. 23, the semiconductor chip 1A is a first conductivity type (n - The MISFET includes a drift layer 102 of a second conductivity type (p type) and base regions 107a, 107b, and 107c of a second conductivity type (p type) arranged on the upper surface side of the drift layer 102. The upper portions of the base regions 107a, 107b, and 107c include n-type impurity regions having a higher impurity density than the drift layer 102. +First main electrode regions (source regions) 108a, 108b, 108c, and 108d of the n-type are provided. Trenches 121a and 121b are provided penetrating the source regions 108a, 108b, 108c, and 108d and the base regions 107a, 107b, and 107c, and gate insulating films 110a and 110b are provided on the bottom and side surfaces of the trenches 121a and 121b. Gate buried electrodes 111a and 111b are buried in the trenches 121a and 121b via the gate insulating films 110a and 110b. Since the semiconductor chip 1A is a MISFET, n-type + A second main electrode region (drain region) 101 of the mold is disposed.

[0074] For convenience, two unit cell structures each including trenches 121a and 121b are shown as cross sections of the main parts in Fig. 23. However, the semiconductor chip 1A can pass a large current by periodically arranging a plurality of unit cell structures to form a multi-channel structure.

[0075] The base regions 107a, 107b, and 107c are provided at their upper portions with p-type impurity layers having a higher impurity density than the base regions 107a, 107b, and 107c so as to contact the source regions 108a, 108b, 108c, and 108d. + The upper part of the drift layer 102 is provided with n-type base contact regions 109a, 109b, and 109c. The n-type base contact regions 109a, 109b, and 109c are sandwiched between the lower part of the drift layer 102 and the base regions 107a, 107b, and 107c. + An n-type current spreading layer (CSL) 103 is provided on the drift layer 102. The current spreading layer 103 is provided by introducing an n-type impurity into the upper part of the drift layer 102, and has a function of reducing the spreading resistance of carriers. Note that the current spreading layer 103 may be omitted, and the upper surface of the drift layer 102 may be in contact with the base regions 107a, 107b, and 107c at the position of the upper surface of the current spreading layer 103.

[0076] In order to protect the gate insulating films 110a and 110b at the bottoms of the trenches 121a and 121b from a high voltage at the time of reverse bias, the bottoms of the trenches 121a and 121b are provided with p+ On the other hand, on the lower surface side of the base regions 107a, 107b, and 107c below the base contact regions 109a, 109b, and 109c, p + The mold base bottom buried regions (105a, 106a), (105b, 106b), and (105c, 106c) are disposed respectively.

[0077] In the embodiment, the drain region 101 is composed of a semiconductor substrate (SiC substrate) made of SiC, and the drift layer 102 is composed of an epitaxial layer (SiC layer) made of SiC. As the drain region 101 and the drift layer 102, in addition to SiC, semiconductor materials having a bandgap width wider than 1.1 eV of Si, such as gallium nitride (GaN), diamond, or aluminum nitride (AlN), can be used. The bandgap width at room temperature has been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, 3.02 eV for 6H-SiC, 3.4 eV for GaN, 5.5 eV for diamond, and 6.2 eV for AlN. Wide bandgap semiconductors with a bandgap width of 2.0 eV or more can be used as the drain region 101 and the drift layer 102, etc., but in LEDs and the like, a bandgap width of 2.5 eV or more is often defined as a "wide bandgap". In this embodiment, the forbidden band width of the wide band gap semiconductor will be described based on the forbidden band width of 2.23 eV of 3C-SiC at room temperature.

[0078] The bottoms of the trenches 121a and 121b that penetrate the source regions 108a, 108b, 108c, and 108d and the base regions 107a, 107b, and 107c in the depth direction reach the current spreading layer 103. Although the bottom surfaces of the trenches 121a and 121b are curved in FIG. 1, the bottom surfaces of the trenches 121a and 121b may be flat. In terms of planar pattern, the trenches 121a and 121b of each unit cell structure may be arranged in a stripe pattern, or may have a rectangular planar pattern or a polygonal planar pattern such as a hexagon.

[0079] The gate insulating films 110a and 110b are made of silicon oxide films (SiO 2 In addition to silicon oxynitride (SiON) films, SiO 2 Strontium oxide (SrO) film, which has a higher dielectric constant than silicon nitride (Si 3 N 4 ) film, aluminum oxide (Al 2 O 3 ) film, magnesium oxide (MgO) film, yttrium oxide (Y 2 O 3 ) film, hafnium oxide (HfO 2 ) film, zirconium oxide (ZrO 2 ) film, tantalum oxide (Ta 2 O 5 ) film, bismuth oxide (Bi 2 O 3 ) membrane or a composite membrane in which a plurality of these membranes are laminated can be used.

[0080] The material of the buried gate electrodes 111a and 111b may be, for example, a polysilicon layer with a high concentration of impurities (doped polysilicon layer). A first main electrode (source electrode) 116 is disposed on the buried gate electrodes 111a and 111b via interlayer insulating films 112a and 112b, separated from a gate surface electrode (not shown) located at the back of the page. The source electrode 116 is electrically connected to the source regions 108a, 108b, 108c, and 108d and the base contact regions 109a, 109b, and 109c.

[0081] The lower layer of the source electrode 116 includes first lower barrier metal layers 113a, 113b, 113c, second lower barrier metal layers 114a, 114b, and an upper barrier metal layer 115. The first lower barrier metal layers 113a, 113b, 113c are disposed so as to be metallurgically in contact with the base contact regions 109a, 109b, 109c, respectively. The second lower barrier metal layers 114a, 114b are disposed so as to be metallurgically in contact with the source regions 108a, 108b, 108c, 108d, as shown in the figure, and to cover the interlayer insulating films 112a, 112b. The upper barrier metal layer 115 is disposed so as to cover the first lower barrier metal layers 113a, 113b, 113c and the second lower barrier metal layers 114a, 114b, and the source electrode 116 is disposed so as to cover the upper barrier metal layer 115. For example, the first lower barrier metal layers 113a, 113b, and 113c are made of nickel (Ni) films, the second lower barrier metal layers 114a and 114b are made of titanium nitride (TiN) films, the upper barrier metal layer 115 is made of a titanium (Ti) / TiN / Ti laminated structure, and the source electrode 116 is made of an aluminum (Al) film. The gate surface electrode can be made of the same material as the source electrode 116.

[0082] A second main electrode (drain electrode) 117 is disposed on the lower surface side of the drift layer 102 so as to be in contact with the drift layer 102. As the drain electrode 117, for example, a single layer film made of gold (Au) or a metal film laminated in the order of Al, nickel (Ni) and Au can be used, and further a metal plate such as molybdenum (Mo) or tungsten (W) may be laminated on the bottom layer.

[0083] The drain region 101 corresponds to a semiconductor substrate, the source electrode 116 corresponds to a first electrode, the drain electrode 117 corresponds to a second electrode, and the epitaxial layer stacked on the drain region 101 corresponds to an epitaxially grown layer. The configuration of the oxidation inhibition layer 70 is the same as that of the oxidation inhibition layer 70 of the SiC semiconductor device 1 according to any of the first to fourth embodiments and their modified examples, and therefore a description thereof will be omitted.

[0084] <<Main Effects of the Fifth Embodiment>> The main effects of the fifth embodiment will be described below. If a thick silicon oxide film is formed on the sidewall of the drain region 101 in the breakdown voltage structure 1Ab, the sealing resin 1D may be subjected to stress, and a gap may be generated at the interface between the sealing resin 1D and the semiconductor chip 1A. If such a gap is generated, there is a possibility that a short circuit may occur between the source electrode 116 and the drain electrode 117. In addition, there is a possibility that a short circuit may occur between the source electrode 116 and the gate electrode. In contrast, since the SiC semiconductor device 1 according to the fifth embodiment includes the oxidation suppression layer 70, it is possible to suppress the thick silicon oxide film from being formed on the sidewall of the drain region 101, and it is possible to suppress a decrease in the reliability of the SiC semiconductor device 1. Even with the SiC semiconductor device 1 according to the fifth embodiment, the same effects as those of the SiC semiconductor device 1 according to any one of the first to fourth embodiments described above can be obtained.

[0085] <Modification of the Fifth Embodiment> A modification of the fifth embodiment will be described below.

[0086] <Variation 1> In the fifth embodiment described above, a MOSFET is configured in the semiconductor chip 1A, but in a first modification of the fifth embodiment, an example in which an insulated gate bipolar transistor (IGBT) is configured in the semiconductor chip 1A will be described. In this modification, although not shown in the drawings, the semiconductor substrate 10 (drain region) of the semiconductor chip 1A is, for example, p + The semiconductor substrate 10 is made of p-type 4H-SiC. + Even in the case of a semiconductor of this type, by providing the oxidation prevention layer 70 on the sidewall of the semiconductor substrate, it is possible to prevent a thick silicon oxide film from being formed on the sidewall, and to prevent a decrease in the reliability of the SiC semiconductor device 1. Even in the SiC semiconductor device 1 according to the first modification of the fifth embodiment, the same effects as those of the SiC semiconductor device 1 according to the fifth embodiment described above can be obtained. The configuration of the oxidation prevention layer 70 is the same as the configuration of the oxidation prevention layer 70 of the SiC semiconductor device 1 according to any of the first to fourth embodiments and their modifications.

[0087] [Other embodiments] As described above, the first to fifth embodiments of the present disclosure have been described, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operating techniques will be apparent to those skilled in the art from this disclosure.

[0088] In addition, the configurations disclosed in the first to fifth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is determined only by the invention-specifying matters related to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0089] 1A Semiconductor Chip 1B Insulated circuit board 1Ba board 1Bb conductor 1C, 1Ca solder layer 1D sealing resin 10. Semiconductor Substrate 11,20a Sidewall 20,21 Epitaxial growth layer 31 Metal layer 70 Oxidation suppression layer 71 1st layer 72 2nd layer T groove Wf wafer

Claims

1. a semiconductor substrate made of silicon carbide; an epitaxially grown layer made of silicon carbide provided on the semiconductor substrate; a first electrode provided on the epitaxially grown layer; A second electrode provided under the semiconductor substrate; an oxidation prevention layer provided on at least a side wall of the semiconductor substrate; A silicon carbide semiconductor device comprising:

2. The silicon carbide semiconductor device according to claim 1 , wherein said oxidation inhibition layer is formed of a part of said n-type epitaxial growth layer.

3. The concentration of acceptor impurities contained in the epitaxial growth layer constituting the oxidation suppression layer is 1×10 １４ cm －３ The silicon carbide semiconductor device according to claim 2 , wherein:

4. 3 . The silicon carbide semiconductor device according to claim 2 , wherein a concentration of an acceptor impurity contained in said epitaxial growth layer constituting said oxidation inhibition layer is lower than a concentration of an acceptor impurity contained in said semiconductor substrate.

5. 3 . The silicon carbide semiconductor device according to claim 2 , wherein a thickness of said epitaxially grown layer constituting said oxidation inhibition layer is greater than a thickness of a depletion layer extending from a surface side of said epitaxially grown layer to a side of said semiconductor substrate.

6. 3 . The silicon carbide semiconductor device according to claim 2 , wherein said epitaxially grown layer constituting said oxidation inhibition layer has a film thickness of not less than 1 μm.

7. The silicon carbide semiconductor device according to claim 1 , wherein said oxidation prevention layer is made of a metallic material.

8. The silicon carbide semiconductor device according to claim 7 , wherein a work function of said metal material is smaller than an electron affinity of said semiconductor substrate.

9. The silicon carbide semiconductor device according to claim 8 , wherein said metallic material is magnesium or zinc.

10. An insulating circuit board; a solder layer that bonds the second electrode and the insulating circuit board, The silicon carbide semiconductor device according to claim 1 , wherein said oxidation inhibition layer is a part of said solder layer.

11. the oxidation prevention layer includes a first layer and a second layer provided on an upper surface of the first layer, the first layer is a part of the epitaxially grown layer of n-type; The silicon carbide semiconductor device according to claim 1 , wherein said second layer is made of a metallic material.

12. The silicon carbide semiconductor device according to claim 1 , wherein said oxidation prevention layer is made of polyimide.

13. The silicon carbide semiconductor device according to claim 1 , further comprising a sealing resin provided on a side wall of said semiconductor substrate with said oxidation prevention layer interposed therebetween.

14. 13. The silicon carbide semiconductor device according to claim 7, wherein said oxidation prevention layer is also provided on a side wall of said epitaxial growth layer.

15. growing an epitaxial growth layer made of silicon carbide on a semiconductor substrate made of silicon carbide; forming an oxidation suppression layer on at least a sidewall of the semiconductor substrate; The method for manufacturing a silicon carbide semiconductor device includes:

16. preparing a wafer made of a silicon carbide semiconductor constituting the semiconductor substrate; A partitioning step of forming grooves in an upper portion of the wafer to partition the plurality of semiconductor substrates from each other, The step of forming the oxidation prevention layer includes forming the oxidation prevention layer on a side wall of the semiconductor substrate exposed in the groove. The method for manufacturing a silicon carbide semiconductor device according to claim 15 , comprising:

17. In the step of forming the oxidation inhibition layer, the epitaxial growth layer is formed as an n-type oxidation inhibition layer in the step of growing the epitaxial growth layer. The method for manufacturing a silicon carbide semiconductor device according to claim 16.

18. In the partitioning step, the groove is formed from the upper surface of the epitaxial growth layer to an upper portion of the semiconductor substrate; The step of forming the oxidation prevention layer includes forming a metal layer as the oxidation prevention layer. The method for manufacturing a silicon carbide semiconductor device according to claim 16.

19. 19. The method for manufacturing a silicon carbide semiconductor device according to claim 16, further comprising the step of grinding the wafer from a lower surface side until the grooves are exposed, to separate the wafer into a plurality of semiconductor chips each having the oxidation inhibition layer formed thereon.

20. 16. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein the step of forming the oxidation inhibition layer comprises forming the solder material as the oxidation inhibition layer on at least a side wall of the semiconductor substrate when the silicon carbide semiconductor device is joined to an insulating circuit substrate with a solder material.

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