Semiconductor device

Abstract

To improve the performance of a semiconductor device.SOLUTION: A plurality of bump electrodes included in a semiconductor chip include: first bump electrodes disposed at a position overlapping a first region; second bump electrodes disposed at a position overlapping a second region of a second insulation layer; and third bump electrodes disposed at a position overlapping a third region of the second insulation layer. In a second direction perpendicular to a first direction, the plurality of first bump electrodes are aligned at a first pitch, the plurality of second bump electrodes are aligned at a second pitch, and the plurality of third bump electrodes are aligned at a pitch different from either one of the first and second pitches.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is a semiconductor device in which a semiconductor chip is mounted on a wiring board having multiple wiring layers by a flip-chip connection method. For example, Patent Document 1 (JP 2019-75442 A) describes a structure in which a semiconductor chip and a wiring board are electrically connected via multiple protruding electrodes arranged on the surface of the semiconductor chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-75442 A Summary of the Invention [Problem to be solved by the invention]

[0004] As the functionality of semiconductor devices increases, the number of protruding electrodes on one semiconductor chip tends to increase. On the other hand, the density of the protruding electrodes is increasing due to the demand for miniaturization of semiconductor chips, so it is necessary to arrange the protruding electrodes in such a way that adjacent protruding electrodes are not electrically shorted. The inventors of the present application have found that, from the viewpoint of improving the reliability or electrical characteristics of semiconductor devices, by devising an arrangement of the protruding electrodes, it is possible to achieve improvements compared to the case where the protruding electrodes are simply arranged at a minimum pitch.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor chip of a semiconductor device according to an embodiment includes a first wiring layer formed on a semiconductor substrate, a second insulating layer arranged to cover the first wiring layer, and a plurality of protruding electrodes electrically connected to the first wiring layer. The plurality of protruding electrodes include a plurality of first protruding electrodes arranged at positions overlapping a first region of the second insulating layer, a plurality of second protruding electrodes arranged at positions overlapping a second region of the second insulating layer, and a plurality of third protruding electrodes arranged at positions overlapping a third region of the second insulating layer. The plurality of first protruding electrodes are arranged at a first pitch, the plurality of second protruding electrodes are arranged at a second pitch, and the plurality of third protruding electrodes are arranged at a pitch different from each of the first pitch and the second pitch. A component of the second pitch along the second direction is larger than a component of the first pitch along the second direction. Effect of the Invention

[0007] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a top view of a semiconductor device according to an embodiment; [Diagram 2] 2 is a bottom view of the semiconductor device shown in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] 4 is an explanatory diagram showing a configuration example of a circuit included in the semiconductor device shown in FIGS. 1 to 3. FIG. [Diagram 5] 4 is a plan view of the electrode arrangement surface side of the semiconductor chip shown in FIG. [Figure 6] FIG. 6 is an enlarged plan view of part A in FIG. 5. [Figure 7] 6 is a plan view showing an example of a layout of the plurality of protruding electrodes shown in FIG. 5; [Figure 8] 6 is a plan view showing another study example of the layout of the plurality of protruding electrodes shown in FIG. 5. FIG. [Figure 9] FIG. 7 is an enlarged cross-sectional view taken along line BB in FIG. 6. [Figure 10] FIG. 6 is an enlarged plan view of part B in FIG. 5. [Figure 11] 6 is a plan view of the electrode arrangement surface side of a semiconductor chip, which is a modified example of the semiconductor chip shown in FIG. 5. [Figure 12] FIG. 12 is an enlarged plan view of part C in FIG. [Figure 13] 13 is an enlarged plan view showing an example of the layout of the uppermost wiring layer of a wiring board on which the semiconductor chip shown in FIGS. 11 and 12 is mounted. FIG. [Figure 14] 6 is a plan view of the electrode arrangement surface side of a semiconductor chip which is another modified example of the semiconductor chip shown in FIG. 5. [Figure 15] FIG. 15 is an enlarged plan view of part D in FIG. [Figure 16] 4 is an explanatory diagram showing an example of a flow of a method for manufacturing the semiconductor device shown in FIG. [Figure 17] 17 is a plan view showing a schematic view of a direction in which air is blown in the drying step shown in FIG. 16. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (Description format, basic terms and usage in this application) In this application, the description of the embodiment is conveniently divided into multiple sections, etc., as necessary, but unless otherwise specified, these are not mutually independent and separate, and regardless of the description, each part of a single example, one is a partial detail of the other, or a partial or complete modified example, etc. In addition, as a general rule, repeated explanations of similar parts will be omitted. In addition, each component in the embodiment is not essential, unless otherwise specified, when it is theoretically limited to that number, or when it is clearly not from the context.

[0010] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X made of A," it does not exclude those containing elements other than A, unless otherwise specified or clearly indicated from the context. For example, when it comes to components, it means "X containing A as a main component." For example, when it comes to "silicon components," it goes without saying that it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys whose main component is silicon, and components containing other additives. In addition, when it comes to gold plating, Cu layer, nickel plating, etc., it includes not only pure ones, but also components whose main components are gold, Cu, nickel, etc., unless otherwise specified.

[0011] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, it may be a number greater than that specific number, or a number less than that specific number, unless it is theoretically limited to that number or unless it is clearly different from the context.

[0012] In addition, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0013] In the accompanying drawings, hatching and the like may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, the background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the explanation, etc. Furthermore, hatching or dot patterns may be added even if the drawing is not a cross section in order to clearly indicate that it is not a void or to clearly indicate the boundaries of the area.

[0014] In the following description, an electrode of a semiconductor chip means a member that functions as an external terminal of a semiconductor chip. Among electrodes, a pad that is a plate-like member with a small area is called an "electrode pad". Among electrodes, a member that is formed so as to locally protrude from the base is called a "bump electrode" or a "protruding electrode". Also, either an "electrode pad" or a "bump electrode (or protruding electrode)" may be simply called an "electrode". Also, a structure in which a bump electrode (or protruding electrode) is formed on an electrode pad may be called an "electrode".

[0015] In the following description, directions such as the X direction, the Y direction, and the Z direction may be used. For example, the X direction and the Y direction are shown in FIG. 1 described later. The X direction and the Y direction intersect with each other. In the example described below, the X direction is perpendicular to the Y direction. In the following description, the XY plane including the X direction and the Y direction is a plane parallel to the main surface of the semiconductor device and the main surface of the mounting board.

[0016] A surface that intersects with the XY plane (for example, a surface parallel to the XZ plane including the X direction and the Z direction, and a surface parallel to the YZ plane including the Y direction and the Z direction) is called a side surface. In the following description, unless otherwise specified, the term "planar view" refers to a surface parallel to the XY plane. In addition, the normal direction to the XY plane is described as the "Z direction" or thickness direction. "Thickness" and "height" refer to the length in the "Z direction" unless otherwise specified. The X direction, Y direction, and Z direction are directions that intersect with each other, and more specifically, are directions that are perpendicular to each other.

[0017] <Semiconductor device> Fig. 1 is a top view of the semiconductor device of this embodiment. Fig. 2 is a bottom view of the semiconductor device shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line AA in Fig. 1. For ease of viewing, Fig. 3 shows fewer electrodes 1PD and protruding electrodes 1BP than in a plan view of a semiconductor chip to be described later.

[0018] The semiconductor device PKG1 of this embodiment has a wiring board 20 and a semiconductor chip 10 (see FIGS. 1 and 3) mounted on the wiring board 20. The semiconductor device PKG1 also has an underfill layer (insulating layer, insulating member) UF (see FIGS. 1 and 3) that is disposed between the semiconductor chip 10 and the wiring board 20 and seals a plurality of protruding electrodes 1BP (see FIG. 3).

[0019] As shown in Fig. 3, wiring board 20 has an upper surface (surface, main surface, chip mounting surface) 20t on which semiconductor chip 10 is mounted, and a lower surface (surface, main surface, mounting surface) 20b opposite to upper surface 20t. Wiring board 20 also has a plurality of sides 20s (see Figs. 1 and 2) that form the outer edges of upper surface 20t and lower surface 20b in plan view. In this embodiment, upper surface 20t (see Fig. 1) and lower surface 20b (see Fig. 2) of wiring board 20 are each quadrilateral, and wiring board 20 has four sides 20s in plan view.

[0020] Moreover, the wiring board 20 has a plurality of wiring layers (eight layers in the example shown in FIG. 3) WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 provided between the upper surface 20t and the lower surface 20b. The plurality of wiring layers includes a wiring layer WL1 that is the layer closest to the upper surface 20t of the wiring board 20 and has a terminal (terminal 2PD) provided thereon. The plurality of wiring layers includes a wiring layer WL8 that is the layer closest to the lower surface 20b of the wiring board 20 and has a terminal (land 2LD) provided thereon.

[0021] Each wiring layer has a conductor pattern such as wiring 2D, which is a path for supplying electric signals and power. An insulating layer 2E is disposed between each wiring layer. Each wiring layer is electrically connected to each other through vias 2V, which are interlayer conductive paths penetrating the insulating layer 2E, or through-hole wiring 2THW. In this embodiment, a wiring board having eight wiring layers is illustrated as an example of the wiring board 20, but the number of wiring layers included in the wiring board 20 is not limited to eight. For example, a wiring board having seven or less wiring layers or nine or more wiring layers can be used as a modified example.

[0022] Among the multiple wiring layers, the wiring layer WL1, which is the layer (uppermost layer) closest to the top surface 20t, is covered with an insulating film SR1. The insulating film SR1 has openings, and the multiple terminals 2PD provided on the wiring layer WL1 are exposed from the insulating film SR1 at the openings.

[0023] Among the multiple wiring layers, the wiring layer WL8, which is the layer (lowest layer) closest to the lower surface 20b of the wiring substrate 20, is provided with multiple lands 2LD. The wiring layer WL8 is covered with an insulating film SR2. An opening is provided in the insulating film SR2, and the multiple lands 2LD provided on the wiring layer WL8 are exposed from the insulating film SR2 at the opening.

[0024] Each of the insulating films SR1 and SR2 is a solder resist film. The terminals 2PD provided on the wiring layer WL1 are electrically connected to the lands (land patterns) 2LD provided on the wiring layer WL8 through the conductor patterns (wires 2D and large-area conductor patterns) formed on each wiring layer of the wiring board 20, the vias 2V, and the through-hole wirings 2THW.

[0025] The wiring board 20 is formed by laminating a plurality of wiring layers on the upper surface 2Ct and the lower surface 2Cb of an insulating layer (core material, core insulating layer) 2CR made of a prepreg in which glass fibers are impregnated with resin, using a build-up method. The wiring layer WL4 on the upper surface 2Ct side of the insulating layer 2CR and the wiring layer WL5 on the lower surface 2Cb side are electrically connected via a plurality of through-hole wirings 2THW embedded in a plurality of through holes (through holes) provided so as to penetrate from one side of the upper surface 2Ct to the other side of the lower surface 2Cb.

[0026] In the example shown in Fig. 3, the wiring board 20 is a wiring board in which a plurality of wiring layers are laminated on the upper surface 2Ct side and the lower surface 2Cb side of the insulating layer 2CR, which is a core material. However, as a modification of Fig. 3, a so-called coreless board may be used, which does not have the insulating layer 2CR made of a hard material such as a prepreg material, and is formed by sequentially laminating an insulating layer 2E and a conductor pattern such as wiring 2D. When a coreless board is used, no through-hole wiring 2THW is formed, and each wiring layer is electrically connected through a via 2V.

[0027] 3, a solder ball (solder material, external terminal, electrode, external electrode) SB is connected to each of the multiple lands 2LD. The solder ball SB is a conductive member that electrically connects multiple terminals (not shown) on the motherboard side to the multiple lands 2LD when the semiconductor device PKG1 is mounted on a motherboard (not shown).

[0028] The solder ball SB is, for example, a solder material made of a Sn-Pb solder material containing lead (Pb), or a so-called lead-free solder that does not substantially contain Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), etc. Here, lead-free solder means a solder containing 0.1 wt% or less of lead (Pb), and this content is set as a standard of the RoHS (Restriction of Hazardous Substances) Directive.

[0029] As shown in Fig. 2, the multiple solder balls SB are arranged in a matrix (array). Although not shown in Fig. 2, the multiple lands 2LD (see Fig. 3) to which the multiple solder balls SB are bonded are also arranged in a matrix. A semiconductor device in which multiple external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface side of the wiring board 20 in this manner is called an area array type semiconductor device.

[0030] The area array type semiconductor device is preferable in that the mounting surface (lower surface 20b) of the wiring board 20 can be effectively used as a space for arranging external terminals, and therefore an increase in the mounting area of ​​the semiconductor device can be suppressed even if the number of external terminals increases. In other words, it is possible to mount a semiconductor device with an increasing number of external terminals in accordance with higher functionality and higher integration in a space-saving manner.

[0031] The semiconductor device PKG1 also includes a semiconductor chip 10 mounted on a wiring board 20. As shown in FIG. 3, each of the semiconductor chips 10 includes a front surface (face, main surface, upper surface) 1t and a back surface (face, main surface, back surface, lower surface) 1b opposite to the front surface 1t. The semiconductor chip 10 includes a plurality of sides 1s (see FIG. 1) that form the outer edges of the front surface 1t and the back surface 1b in a plan view. As shown in FIG. 1, the semiconductor chip 10 has a rectangular outer shape with a smaller planar area than the wiring board 20 in a plan view. Therefore, the semiconductor chip 10 has four sides 1s in a plan view. In the example shown in FIG. 1, the semiconductor chip 10 is mounted in the center of the upper surface 20t of the wiring board 20, and each of the four sides 1s of the semiconductor chip 10 extends along each of the four sides 20s of the wiring board 20.

[0032] A plurality of electrodes (pads, electrode pads, bonding pads) 1PD are formed on the front surface 1t of the semiconductor chip 10. In the example shown in Fig. 3, the semiconductor chip 10 is mounted on the wiring board 20 with the front surface 1t facing the upper surface 20t of the wiring board 20. Such a mounting method is called a face-down mounting method or a flip-chip connection method.

[0033] A plurality of semiconductor elements (circuit elements) are formed on the main surface (more specifically, a semiconductor element formation region provided on the element formation surface of a semiconductor substrate that is the base material of the semiconductor chip 10) of the semiconductor chip 10. The plurality of electrodes 1PD are electrically connected to the plurality of semiconductor elements, respectively, via wiring (not shown) formed in a wiring layer disposed inside the semiconductor chip 10 (more specifically, between the front surface 1t and the semiconductor element formation region, not shown).

[0034] The semiconductor chip 10 includes a semiconductor substrate made of, for example, silicon (Si). An insulating film covering the semiconductor substrate and wiring is formed on the front surface 1t of the semiconductor chip 10, and each of the multiple electrodes 1PD (see FIG. 3) is partially exposed from the insulating film through an opening formed in the insulating film. Each of the multiple electrodes 1PD is made of a metal film. The detailed structure of the semiconductor chip 10 will be described later.

[0035] 3, a protruding electrode 1BP is connected to each of the electrodes 1PD, and the electrodes 1PD of the semiconductor chip 10 and the terminals 2PD of the wiring board 20 are electrically connected to each other via the protruding electrodes 1BP. The protruding electrodes (bump electrodes) 1BP are metal members (conductive members) formed so as to protrude from the front surface 1t of the semiconductor chip 10.

[0036] In this embodiment, the protruding electrode 1BP is made of a solder material. The protruding electrode 1BP made of a solder material is called a solder bump. The electrode 1PD is electrically connected to the protruding electrode 1BP via an under bump metal film UBM (see FIG. 9 described later) of the protruding electrode 1BP, which is a solder bump. As the solder material constituting the protruding electrode 1BP, a lead-containing solder material or lead-free solder can be used, as in the case of the solder ball SB described above.

[0037] When mounting the semiconductor chip 10 on the wiring board 20, solder bumps are formed in advance on both the multiple electrodes 1PD and the multiple terminals 2PD, and a heat treatment (reflow treatment) is performed while the solder bumps are in contact with each other, so that the solder bumps are integrated with each other to form protruding electrodes 1BP.

[0038] 3, an underfill (insulating layer, insulating resin, insulating member) UF is disposed between the semiconductor chip 10 and the wiring board 20. The underfill layer UF is disposed so as to fill the space between the front surface 1t of the semiconductor chip 10 and the upper surface 20t of the wiring board 20. Each of the multiple protruding electrodes 1BP is sealed with the underfill layer UF. The underfill layer UF is made of an insulating (non-conductive) material (e.g., a resin material) and is disposed so as to seal the electrical connection portion (the joint portion of the multiple protruding electrodes 1BP) between the semiconductor chip 10 and the wiring board 20.

[0039] In this way, by sealing the joints between the plurality of protruding electrodes 1BP and the plurality of terminals 2PD with the underfill layer UF, it is possible to relieve stress occurring in the electrical connection portion between the semiconductor chip 10 and the wiring board 20. The underfill layer UF can relieve stress occurring in the joints between the plurality of electrodes 1PD and the plurality of protruding electrodes 1BP of the semiconductor chip 10. The underfill layer UF can protect the main surface of the semiconductor chip 10 on which the semiconductor elements (circuit elements) are formed.

[0040] There are various modified examples of the semiconductor device shown in FIG. 1 to FIG. 3. For example, in the example shown in FIG. 3, one semiconductor chip 10 is mounted on the wiring board 20. The number of semiconductor chips 10 mounted on the wiring board 20 is not limited to one, and may be two or more. In the example shown in FIG. 1 and FIG. 3, the back surface 1b of the semiconductor chip 10 is exposed. As a modified example of FIG. 1 and FIG. 3, a cover member that functions as a heat dissipation member may be attached to the back surface 1b of the semiconductor chip 10. In this case, the heat dissipation characteristics of the semiconductor device PKG1 can be improved. When the semiconductor chip 10 is covered with the cover member, the semiconductor chip 10 can be protected.

[0041] <Circuit configuration example> Next, a configuration example of the circuit included in the semiconductor device PKG1 shown in Figures 1 to 3 will be described. Figure 4 is an explanatory diagram showing a configuration example of the circuit included in the semiconductor device shown in Figures 1 to 3. Note that Figure 4 exemplarily illustrates a portion of each of the multiple circuits, multiple signal transmission paths, and multiple power supply paths included in the semiconductor device PKG1.

[0042] As shown in Fig. 4, the semiconductor chip 10 included in the semiconductor device PKG1 of the present embodiment has an input / output circuit IO1. In the example shown in Fig. 4, the semiconductor chip 10 has the input / output circuit IO1 and a core circuit CC1 electrically connected to the input / output circuit IO1.

[0043] The input / output circuit IO1 includes, for example, a SerDes circuit (Serializer Deserializer) having a function of converting parallel signals to serial signals and vice versa. In other words, the SerDes circuit included in the input / output circuit IO1 is a circuit capable of converting serial signals to parallel signals and converting parallel signals to serial signals.

[0044] 4, a signal SG1 input from the outside to the input / output circuit IO1 via the wiring board 20 is, for example, a serial signal. A signal SG2 output from the input / output circuit IO1 to the outside via the wiring board 20 is, for example, a serial signal. Meanwhile, signals SG3 and SG4 transmitted between the input / output circuit IO1 and the core circuit CC1 are, for example, parallel signals. Since the semiconductor chip 10 includes the input / output circuit IO1 including a SerDes circuit, different transmission methods can be adopted for signal transmission within the semiconductor chip 10 and signal transmission between the semiconductor chip 10 and an external device.

[0045] 4, the semiconductor chip 10 has an input / output circuit IO2. The input / output circuit IO2 and the core circuit CC1 are electrically connected. The input / output circuit IO2 is, for example, an interface circuit for a DDR (Double Data Rate) memory. A signal SG5 is input to the input / output circuit IO2 from the outside via the wiring board 20. The input / output circuit IO2 also outputs a signal SG6, and the signal SG5 is transmitted to an external memory (not shown) via the wiring board 20.

[0046] The core circuit CC1 performs data processing (e.g., arithmetic processing) on ​​the signal SG3 transmitted from the input / output circuit IO1, and outputs a signal SG4. The signal SG4 is converted to a signal SG2 in the input / output circuit IO1 and transmitted to an external device. Similarly, the core circuit CC1 performs data processing (e.g., arithmetic processing) on ​​the signal SG7 transmitted from the input / output circuit IO2, and outputs a signal SG8. The signal SG8 is transmitted to the input / output circuit IO2. Note that in FIG. 4, a distinction is made between the signal SG6 output by the input / output circuit IO2 and the signal SG8 output by the core circuit CC1. However, the signals SG6 and SG8 may be the same signal.

[0047] 4, the input / output circuit IO1 and the input / output circuit IO2 are connected to the same core circuit CC1. However, the number of core circuits CC1 included in the semiconductor chip 10 is not limited to one, and the semiconductor chip 10 may have a plurality of core circuits CC1. Also, the input / output circuit IO1 and the input / output circuit IO2 may be connected to different core circuits CC1.

[0048] The semiconductor device PKG1 has paths for supplying voltages for driving a plurality of circuits (input / output circuits IO1, IO2, and core circuit CC1) included in the semiconductor chip 10.

[0049] In detail, the semiconductor device PKG1 has a power supply potential supply path PVD1 for supplying a power supply potential VD1 to the input / output circuit IO1, and a reference potential supply path PVS1 for supplying a reference potential VS1 to the input / output circuit IO1.

[0050] The semiconductor device PKG1 has a power supply potential supply path PVD2 for supplying a power supply potential VD2 to the input / output circuit IO2, and a reference potential supply path PVS2 for supplying a reference potential VS2 to the input / output circuit IO2.

[0051] The semiconductor device PKG1 has a power supply potential supply path PVD3 for supplying a power supply potential VD3 to the core circuit CC1, and a reference potential supply path PVS3 for supplying a reference potential VS3 to the core circuit CC1.

[0052] 4 shows an example in which different potentials are supplied to the input / output circuit IO1, the input / output circuit IO2, and the core circuit CC1. However, this is not limited to the case where the potentials supplied to the multiple circuits are different. For example, some or all of the power supply potential VD1, the power supply potential VD2, and the power supply potential VD3 may be the same potential. Similarly, some or all of the reference potential VS1, the reference potential VS2, and the reference potential VS3 may be the same potential.

[0053] The reference potential VS1, the reference potential VS2, and the reference potential VS3 are different potentials from the power supply potential VD1, the power supply potential VD2, and the power supply potential VD3, respectively, and may be potentials other than the ground potential.

[0054] <Electrode layout of semiconductor chip> Next, the electrode layout of the semiconductor chip will be described. Fig. 5 is a plan view of the electrode arrangement surface side of the semiconductor chip shown in Fig. 3. Fig. 6 is an enlarged plan view of part A in Fig. 5. Figs. 7 and 8 are plan views showing an example of the layout of the multiple protruding electrodes shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view taken along line BB in Fig. 6.

[0055] Generally, the electrodes of a semiconductor chip are not arranged in the central region (region including the center) of the semiconductor chip when viewed in a plan view, but are arranged in the peripheral region around the central region. With the demand for miniaturization of semiconductor chips (reduced planar size), there is a tendency for the space for arranging the electrodes to be insufficient when the electrodes are arranged only in the peripheral region.

[0056] Therefore, an area array method is being considered in which electrodes are regularly arranged over the entirety of one main surface of a semiconductor chip, including the central and peripheral regions, as shown in Figures 5 to 8. The central region of a semiconductor chip is the area where the main circuits, such as the core circuit, are located and is called the active area. For this reason, the method of arranging electrodes using the area array method is sometimes called PAA (Pad on Active Area).

[0057] From the viewpoint of maximizing the arrangement density of the electrodes, it is preferable that all the protruding electrodes 1BP are arranged at the minimum allowable pitch, as in the semiconductor chip 10C1 shown in Fig. 7. However, due to various circumstances, it may be difficult to arrange all the protruding electrodes 1BP at the same pitch.

[0058] For example, when an element such as a coil or a capacitor is placed in a part of the semiconductor chip 10, areas may arise around the element in which it is difficult to place the protruding electrodes 1BP, and the pitch of some of the protruding electrodes 1BP may be different from the pitch of the other protruding electrodes 1BP.

[0059] Alternatively, when some of the multiple circuits (the input / output circuit IO1, the input / output circuit IO2, and the core circuit CC1 shown in FIG. 4) of the semiconductor chip 10 are standardized circuits, the layout of the protruding electrodes 1BP may be regulated by a standard. A standardized circuit is a circuit block in which the specifications of the circuit and the specifications of the circuit components that make up the circuit are standardized to increase the versatility of a circuit having a certain function. Such a circuit block may be called an IP (Intellectual Property) circuit. For example, the specifications of the input / output circuit IO1 shown in FIG. 4 are standardized, including the arrangement of the protruding electrodes.

[0060] Because the circuit scale of an integrated circuit is large, it takes a huge amount of time to design all the circuit blocks from scratch. By including standardized circuit blocks such as IP circuits as part of the integrated circuit, design efficiency can be improved.

[0061] Standardized circuits are often interface circuits that transmit signals between other circuits, such as the input / output circuit IO1 or the input / output circuit IO2. Interface circuits are often placed in the peripheral area of ​​a semiconductor chip. By placing the interface circuit in the peripheral area, the signal transmission path can be shortened.

[0062] On the other hand, in the central region, protruding electrodes 1BP for supplying a power supply potential VD3 (see FIG. 4) or a reference potential VS3 (see FIG. 4) mainly to the core circuit CC1 (see FIG. 4) are often arranged. This is because the core circuit CC1 formed in the central region transmits signals to external devices via the input / output circuit IO1 or the input / output circuit IO2.

[0063] It is difficult to arrange all the protruding electrodes 1BP at the same pitch when a standardized circuit is included, such as in the semiconductor chip 10. For example, in the case of the semiconductor chip 10C2 shown in Fig. 8, the pitch of some of the protruding electrodes 1BP arranged in the peripheral region is wider than the pitch of the protruding electrodes BP1 arranged in the central region.

[0064] <Definition of terms related to electrode arrangement> The pitch at which the multiple protruding electrodes 1BP are arranged will be described below. In this specification, the terms "staggered arrangement," "pitch," "component of the pitch along the X direction," and "component of the pitch along the Y direction" may be used. Each term is defined as follows.

[0065] First, a "staggered arrangement" is an arrangement as shown in an enlarged view in Fig. 5. In Fig. 5, if the X direction is defined as the row direction and the Y direction is defined as the column direction, the multiple protruding electrodes 1BP are arranged as follows.

[0066] That is, the plurality of protruding electrodes 1BP are arranged in a plurality of rows in the Y direction. For example, Fig. 5 shows a plurality of protruding electrodes 51 arranged in row RW1, a plurality of protruding electrodes 52 arranged in row RW2 adjacent to row RW1, a plurality of protruding electrodes 53 arranged in row RW3 adjacent to row RW2, and a plurality of protruding electrodes 54 arranged in row RW4 adjacent to row RW3.

[0067] The multiple protruding electrodes 1BP shown in Fig. 5 are arranged in a staggered manner. Therefore, in the X direction, which is the row direction, the center of each of the multiple protruding electrodes 52 is located between adjacent protruding electrodes 51 (at the middle in Fig. 5). Similarly, in the X direction, the center of each of the multiple protruding electrodes 53 is located between adjacent protruding electrodes 52 (at the middle in Fig. 5). In the X direction, the center of each of the multiple protruding electrodes 54 is located between adjacent protruding electrodes 53 (at the middle in Fig. 5).

[0068] On the other hand, in the X direction, the centers of the plurality of protruding electrodes 53 are disposed at the same positions as the centers of the plurality of protruding electrodes 51. Similarly, in the X direction, the centers of the plurality of protruding electrodes 54 are disposed at the same positions as the centers of the plurality of protruding electrodes 52.

[0069] This type of arrangement is called a "staggered arrangement." Note that an arrangement in which multiple solder balls SB are arranged in rows and columns along both the X and Y directions, such as the arrangement of multiple solder balls SB shown in Figure 2, is called a "row and matrix arrangement."

[0070] In the case of a staggered arrangement, the interval between a protruding electrode arranged in a certain row and a protruding electrode arranged in an adjacent row can be made wider than in a matrix arrangement, so that the arrangement density of the objects to be arranged can be improved. For this reason, in the present embodiment, each of the multiple protruding electrodes 1BP is arranged in a staggered manner in order to improve the arrangement density of the multiple protruding electrodes 1BP.

[0071] However, the arrangement of the plurality of protruding electrodes 1BP is not limited to the staggered arrangement, and as a modified example, some or all of the plurality of protruding electrodes 1BP may be arranged in a matrix.

[0072] The "pitch" of the protruding electrode 1BP is the center-to-center distance between one of the plurality of protruding electrodes 1BP and the protruding electrode 1BP that is disposed closest to the one protruding electrode 1BP. In the example shown in Fig. 5, the center-to-center distance between the protruding electrode 51 and the protruding electrode 52 that is disposed closest to the protruding electrode 51 is illustrated as the pitch PXY.

[0073] The "component of the pitch along the X direction" of the protruding electrode 1BP is the component of the pitch PXY along the X direction. In the example shown in Fig. 5, the component of the pitch between the protruding electrodes 51 and 52 along the X direction is illustrated as the distance PX.

[0074] The "component along the pitch Y direction" of the protruding electrode 1BP is the component of the pitch PXY along the Y direction. In the example shown in Fig. 5, the component along the pitch Y direction between the protruding electrodes 51 and 52 is illustrated as the distance PY.

[0075] <Differences between the study example and this embodiment> Next, the commonalities and differences between the semiconductor chip 10 according to the present embodiment shown in FIGS. 5 and 6 and the semiconductor chip 10C2 shown in FIG. 8 will be described.

[0076] 9, the semiconductor chip 10 has a semiconductor substrate 11, a wiring portion DP, a wiring layer RDL, an insulating layer 12, and a protruding electrode 1BP. The semiconductor substrate 11 has a surface (main surface) 11t. Semiconductor elements (not shown) such as transistors or diodes are formed on the surface 11t.

[0077] The wiring portion DP of the semiconductor chip 10 has a plurality of stacked wiring layers. Except for the plugs connected to the semiconductor elements and the uppermost wiring layer (the wiring layer located farthest from the surface 11t) of the plurality of wiring layers, the plurality of wiring layers are made of, for example, copper or a copper alloy. Inorganic insulating layers such as silicon oxide are interposed between the plurality of wiring layers. The wiring layer arranged on the uppermost layer of the wiring portion DP has a pad (not shown) made of, for example, aluminum formed thereon.

[0078] The wiring layer RDL is formed on the surface 11t of the semiconductor substrate 11 (more specifically, on the wiring portion DP disposed on the surface 11t). The wiring layer RDL is electrically connected to the semiconductor element formed on the surface 11t of the semiconductor substrate 11 via the wiring portion DP. In Fig. 9, an electrode 1PD is illustrated as an example of a conductor pattern formed on the wiring layer RDL. In addition to the electrode 1PD, a wiring pattern connected to the electrode 1PD and the like are formed on the wiring layer RDL.

[0079] When the wiring part DP and the wiring layer RDL are to be distinguished, the wiring layer RDL may be called a rewiring layer. The wiring layer RDL is made of, for example, copper or a copper alloy. The pad formed on the top layer of the wiring part DP and the electrode 1PD are electrically connected via a wire formed on the wiring layer RDL.

[0080] The insulating layer 12 has a surface 12b facing the surface 11t of the semiconductor substrate 11 and a surface 12t opposite to the surface 12b, and is disposed so as to cover the wiring layer RDL. The insulating layer 12 has a function of ensuring electrical insulation of the multiple protruding electrodes 1BP and a function as a protective film that protects the wiring layer RDL. From the viewpoint of improving the flatness of the surface 12t of the insulating layer 12, the insulating layer 12 is an organic insulating layer made of, for example, polyimide resin. However, as a modified example, the insulating layer 12 may be an inorganic insulating layer.

[0081] A plurality of openings are formed in the insulating layer 12. Each of the plurality of electrodes 1PD provided in the wiring layer RDL is disposed at a position overlapping one of the plurality of openings formed in the insulating layer 12. Each of the plurality of electrodes 1PD is exposed from the insulating layer 12 at a position overlapping the above-mentioned opening. An underbump metal film (under bump metal) UBM of the protruding electrode 1BP, which is a solder bump, is formed in the above-mentioned opening. The plurality of protruding electrodes 1BP and the plurality of electrodes 1PD are electrically connected via the underbump metal film UBM.

[0082] The structure of the semiconductor chip 10 described with reference to FIG. 9 is also the same as that of the semiconductor chip 10C2 shown in FIG.

[0083] As shown in each of Figures 5 and 8, surface 12t of insulating layer 12 has side 1s1 extending in the X direction, side 1s2 located opposite side 1s1, side 1s3 extending in the Y direction intersecting the X direction, and side 1s4 located opposite side 1s3.

[0084] In the case of the semiconductor chip 10 shown in Figure 5, the surface 12t of the insulating layer 12 includes a region R1 located between sides 1s1 and 1s2, a region R2 arranged adjacent to region R1 between side 1s1 and region R1, and a region R3 arranged adjacent to region R2 between side 1s1 and region R2.

[0085] As shown in FIG. 6, the multiple protruding electrodes 1BP include multiple protruding electrodes BP1 arranged in a position overlapping with region R1 in a planar view, multiple protruding electrodes BP2 arranged in a position overlapping with region R2 in a planar view, and multiple protruding electrodes BP3 arranged in a position overlapping with region R3 in a planar view.

[0086] Each of the multiple protruding electrodes BP3 is electrically connected to the input / output circuit IO1 of the semiconductor chip 10 shown in Fig. 4. Each of the multiple protruding electrodes BP1 and the multiple protruding electrodes BP2 shown in Fig. 6 is electrically connected to a circuit (e.g., a core circuit CC1) different from the input / output circuit IO1 shown in Fig. 4.

[0087] 6, the multiple protruding electrodes BP1 are arranged at a pitch P11. The multiple protruding electrodes BP2 are arranged at a pitch P22 that is wider than the pitch P11. The multiple protruding electrodes BP3 are arranged at a pitch different from each of the pitches P11 and P22. In the Y direction perpendicular to the X direction, the component of the pitch P22 along the Y direction (distance P2Y) is greater than the component of the pitch P11 along the Y direction (distance P1Y).

[0088] On the other hand, in the case of the semiconductor chip 10C2 shown in Fig. 8, a blank region RBL in which no protruding electrodes 1BP are arranged is provided between the region R1 and the region R3. In this respect, the semiconductor chip 10 shown in Fig. 5 differs from the semiconductor chip 10C2 shown in Fig. 8.

[0089] According to the study by the present inventors, in the case of a semiconductor device using the semiconductor chip 10C2 shown in Fig. 8, it was found that voids may be formed between the insulating layer 12 and the underfill layer UF shown in Fig. 9. It was found that the above-mentioned voids are likely to be formed in the vicinity of the blank region RBL shown in Fig. 8.

[0090] According to the inventor's investigation, the cause of the above-mentioned voids is presumed to be as follows. The manufacturing process of a semiconductor device includes a cleaning process in which, after mounting the semiconductor chip 10 on the wiring board 20, residues remaining around the plurality of protruding electrodes 1BP are cleaned with a cleaning liquid, and a drying process in which the cleaning liquid is removed. It is preferable that all moisture is removed in the drying process, but it has been found that some moisture is difficult to remove around the blank region RBL shown in FIG. 8, and cleaning residues are likely to occur. Cleaning residues are likely to occur in the gap between the protruding electrode 1BP and the insulating layer 12 shown in FIG. 9.

[0091] The above-mentioned voids are caused by this cleaning residue, and it is believed that the cleaning residue (i.e., voids) generated in the gap between the protruding electrode 1BP and the insulating layer 12 reduces the adhesion between the underfill layer UF (see FIG. 3) and the insulating layer 12t. This is because, in the blank region RBL of the semiconductor chip 10C2 shown in FIG. 8, the distance between the region R1 where the multiple protruding electrodes BP1 are arranged and the region R3 where the multiple protruding electrodes BP3 are arranged is wider than the pitch of the multiple protruding electrodes BP1 and the respective pitches of the multiple protruding electrodes BP3.

[0092] If the volume of the void is small, there is no particular problem, but if the volume of the void is large, there is a possibility that adjacent protruding electrodes 1BP may be short-circuited. Therefore, if the residual moisture that causes the above-mentioned voids can be suppressed, the reliability of the semiconductor device can be improved.

[0093] In the case of the semiconductor chip 10 according to the present embodiment shown in Fig. 6, a region R2 in which a plurality of protruding electrodes BP2 are arranged is provided between a region R1 in which a plurality of protruding electrodes BP1 are arranged and a region R3 in which a plurality of protruding electrodes BP3 are arranged. In the case of the semiconductor chip 10, by adjusting the pitch P22 of the plurality of protruding electrodes BP2 arranged in the region R2, it is possible to reduce the area of ​​the gap in which the protruding electrodes BP1BP are not arranged. Therefore, in the case of the semiconductor device PKG1 (see Fig. 3) using the semiconductor chip 10, it is possible to suppress the occurrence of voids, thereby improving reliability.

[0094] In the following description, the protruding electrode 1BP, which is arranged to reduce the wide gap that occurs between the protruding electrode BP3 arranged in region R3 and the protruding electrode BP1 arranged in region R1, such as the protruding electrode BP2, may be referred to as the protruding electrode 1BP for adjusting the arrangement.

[0095] 5 and 6, the multiple protruding electrodes BP3 arranged in the region R3 are arranged in the peripheral region of the semiconductor chip 10. In other words, among the multiple protruding electrodes 1BP, the multiple protruding electrodes BP3 include the protruding electrode 1BP arranged at the position closest to the side 1s1. Since the multiple protruding electrodes BP3 are arranged in the peripheral region of the semiconductor chip 10, even if moisture accumulates between the protruding electrodes BP3 and the insulating layer 12, the moisture is easily removed by the drying process.

[0096] The pitch P33 shown in Fig. 6 is different from the pitch P11 and the pitch P22. For example, in the example shown in Fig. 6, the pitch P33 is wider than the pitch P22. However, as a variant, the pitch P33 may be narrower than the pitch P22.

[0097] As described above, the circuit to which each of the plurality of protruding electrodes BP3 is electrically connected is the input / output circuit IO1 for electrical signals (see FIG. 4). Therefore, by arranging the plurality of protruding electrodes BP3 in the peripheral region of the semiconductor chip 10, the path length of the signal transmission path can be shortened.

[0098] In the example shown in FIG. 6, the multiple protruding electrodes BP2 are arranged in three rows in the Y direction. The number of rows of the multiple protruding electrodes BP2 in the Y direction is not limited to three rows. For example, in the case of a semiconductor chip 10A shown in FIG. 11, which will be described later as a modified example, the multiple protruding electrodes BP2 arranged in the region R2 are arranged in two rows in the Y direction. Also, the multiple protruding electrodes BP5 arranged in the region R5 are arranged in four rows in the Y direction. Although not shown in the drawings, in a further modified example, the multiple protruding electrodes BP2 or the multiple protruding electrodes BP5 may be arranged in five or more rows in the Y direction.

[0099] However, in the present embodiment, the area of ​​the gap is reduced by adjusting the Y-direction component of the pitch P22. Therefore, the number of rows of the multiple protruding electrodes BP2 in the Y direction is preferably two or more. Furthermore, if the number of rows of the multiple protruding electrodes BP2 in the Y direction becomes extremely large, the area of ​​the region R1 in which the multiple protruding electrodes BP1 are arranged will be reduced. From the viewpoint of improving the arrangement density of the protruding electrodes 1BP, it is preferable that the area of ​​the region R1 is large. Therefore, the number of rows of the multiple protruding electrodes BP2 in the Y direction is preferably, for example, five or less.

[0100] Moreover, in the present embodiment, strictly speaking, the area of ​​the gap is reduced by adjusting the Y-direction component of the pitch P22. Therefore, at least as long as the Y-direction component of the pitch P22 (distance P2Y) is longer than the Y-direction component of the pitch P11 (distance P1Y), the value of the X-direction component of the pitch P22 (distance P2X) can be set arbitrarily. In the example shown in FIG. 6, the pitch P22 is wider than the pitch P11. However, as a modified example, depending on the value of the X-direction component of the pitch P22 (distance P2X), the pitch P22 may be the same as the pitch P11 or may be narrower than the pitch P11. From the viewpoint of ease of adjustment to fill the area of ​​the gap, it is preferable that the X-direction component of the pitch P22 (distance P2X) is wider. Therefore, as shown in FIG. 6, it is easier to adjust to fill the gap when the pitch P22 is wider than the pitch P11.

[0101] 6, the plurality of protruding electrodes BP1 and the plurality of protruding electrodes BP2 are arranged in a staggered manner. From the viewpoint of improving the arrangement density of the protruding electrodes 1BP, the staggered arrangement as in the present embodiment is preferable.

[0102] 6, the component of the pitch P11 along the X direction (distance P1X) is equal to the component of the pitch P11 along the Y direction (distance P1Y). The component of the pitch P22 along the X direction (distance P2X) is equal to the component of the pitch P22 along the Y direction (distance P2Y). The component of the pitch P33 along the X direction (distance P3X) is equal to the component of the pitch P33 along the Y direction (distance P3Y).

[0103] In the example shown in FIG. 6, the shortest pitch (pitch P12min) between one of the multiple protruding electrodes BP1 and one of the multiple protruding electrodes BP2 is equal to or greater than the pitch P11. Also, the shortest pitch (pitch P23min) between one of the multiple protruding electrodes BP3 and one of the multiple protruding electrodes BP2 is equal to or greater than the pitch P11. The pitch P12min shown in FIG. 6 is the minimum value of the pitch between one of the multiple protruding electrodes BP1 and the protruding electrode BP2 located adjacent to the one protruding electrode BP1. Similarly, the pitch P23min shown in FIG. 6 is the minimum value of the pitch between one of the multiple protruding electrodes BP3 and the protruding electrode BP2 located adjacent to the one protruding electrode BP3.

[0104] In this embodiment, the pitch P11 of the plurality of protruding electrodes BP1 is set to an allowable value from the viewpoint of preventing short-circuiting between adjacent protruding electrodes BP1. Therefore, by making the pitch P12 and the pitch P23 equal to or greater than the pitch P11, it is possible to prevent short-circuiting between the protruding electrodes BP1 and BP2, or between the protruding electrodes BP3 and BP2.

[0105] In the example shown in FIG. 6, the ball diameter (maximum diameter in a plan view) of each of the plurality of protruding electrodes 1BP is about 100 μm.

[0106] The distances P1X and P1Y shown in Fig. 6 are each 92 µm. Therefore, the pitch P11 is 130 µm. The distances P2X and P2Y shown in Fig. 6 are each 104 µm. Therefore, the pitch P22 is 147 µm. Furthermore, the pitch P12min shown in Fig. 6 is equal to the pitch P11. The pitch P23min is wider than the pitch P11, being 134 µm.

[0107] On the other hand, the maximum pitch (pitch P12max in FIG. 6) between one of the plurality of protruding electrodes BP1 and the protruding electrode BP2 adjacent to the protruding electrode BP1 is preferably equal to or smaller than the pitch P22. Also, the maximum pitch (pitch P23max in FIG. 6) between one of the plurality of protruding electrodes BP3 and the protruding electrode BP2 adjacent to the protruding electrode BP3 is preferably equal to or smaller than the pitch P22.

[0108] The pitch P12max shown in Fig. 6 is 135 µm, and the pitch P23max is 144 µm. As a modification of Fig. 6, one or both of the pitch P12max and the pitch P23max may be narrower than the pitch P22. Even in this case, if the average value of the center-to-center distance between the protruding electrodes BP1 and BP2 is equal to or smaller than the pitch P22, it is possible to suppress the residual moisture.

[0109] From the viewpoint of making it easier to adjust the values ​​of pitch P12min, pitch P12max, pitch P23min, and pitch P23max, it is preferable that the value of pitch P22 is large within a range in which moisture does not remain. Therefore, by making each of pitch P12 and pitch P23 equal to or less than pitch P22, moisture can be prevented from remaining between region R1 and region R2, and between region R2 and region R3.

[0110] Incidentally, the layout of the protruding electrodes 1BP around the side 1s1 of the semiconductor chip 10 shown in Fig. 5 has been explained using Fig. 6. In the case of the semiconductor chip 10, as shown in Fig. 5, the layout around the side 1s2 of the semiconductor chip 10 is similar to that around the side 1s1. Fig. 10 is an enlarged plan view of part B in Fig. 5.

[0111] As shown in FIG. 10, the multiple protruding electrodes 1BP include multiple protruding electrodes BP1 arranged in a position overlapping with region R1 in a planar view, multiple protruding electrodes BP5 arranged in a position overlapping with region R5 in a planar view, and multiple protruding electrodes BP6 arranged in a position overlapping with region R6 in a planar view.

[0112] Each of the multiple protruding electrodes BP6 is electrically connected to the input / output circuit IO1 of the semiconductor chip 10 shown in Fig. 4. Each of the multiple protruding electrodes BP1 and the multiple protruding electrodes BP5 shown in Fig. 10 is electrically connected to a circuit (e.g., a core circuit CC1) different from the input / output circuit IO1 shown in Fig. 4.

[0113] 10, the multiple protruding electrodes BP1 are arranged at a pitch P11. The multiple protruding electrodes BP5 are arranged at a pitch P55 that is wider than the pitch P11. The multiple protruding electrodes BP6 are arranged at a pitch different from each of the pitch P11 and the pitch P55. In the Y direction perpendicular to the X direction, the component of the pitch P55 along the Y direction (distance P5Y) is greater than the component of the pitch P11 along the Y direction (distance P1Y).

[0114] As with the relationship between the pitch P11 and the pitch P22 described in FIG. 6, if the Y-direction component (distance P5Y) of the pitch P55 shown in FIG. 10 is longer than the Y-direction component (distance P1Y) of the pitch P11, the value of the X-direction component (distance P5X) of the pitch P55 can be set arbitrarily. In the example shown in FIG. 10, the pitch P55 is wider than the pitch P11. However, as a modified example, depending on the value of the X-direction component (distance P5X) of the pitch P55, the pitch P55 may be the same as the pitch P11 or may be narrower than the pitch P11. As shown in FIG. 10, it is easier to adjust the pitch P55 to fill the gap when it is wider than the pitch P11.

[0115] According to the study by the inventors of the present application, it was found that the degree of remaining moisture in the above-mentioned drying process also varies depending on the drying method. That is, in the drying process, drying may be performed by blowing air in one direction. In this case, the degree of moisture removal varies depending on the direction of the drying air.

[0116] 8, when air is blown in the Y direction from side 1s2 to side 1s1, moisture is likely to remain around blank region RBL1, which is located relatively closer to side 1s1, among the two blank regions RBL. On the other hand, moisture is unlikely to remain around blank region RBL2, which is located relatively closer to side 1s2. As a result, voids are unlikely to occur around blank region RBL2.

[0117] Considering this finding, for example, as a modification of the semiconductor chip 10 shown in Fig. 5, a case where the structure around the side 1s2 is similar to that of the semiconductor chip 10C2 shown in Fig. 8 is considered. In this case, by blowing air in the Y direction from the side 1s2 to the side 1s1 in the drying process, voids due to residual moisture are unlikely to occur even if there is a region corresponding to the blank region RBL2 shown in Fig. 8.

[0118] 5, as described above, the periphery of the side 1s2 and the periphery of the side 1s1 have similar structures. Therefore, in the case of the semiconductor chip 10, the generation of voids can be suppressed regardless of the drying method.

[0119] It is preferable that the layout of the protruding electrodes BP5 and BP6 shown in FIG. 10 is similar to the layout of the protruding electrodes BP2 and BP3 described with reference to FIG.

[0120] 5 and 10, the multiple protruding electrodes BP6 arranged in the region R6 are arranged in the peripheral region of the semiconductor chip 10. In other words, among the multiple protruding electrodes 1BP, the multiple protruding electrodes BP6 include the protruding electrode 1BP arranged at the position closest to the side 1s2.

[0121] The pitch P66 shown in Fig. 10 is different from the pitch P11 and the pitch P55. For example, in the example shown in Fig. 10, the pitch P66 is wider than the pitch P55. However, as a variant, the pitch P66 may be narrower than the pitch P55.

[0122] The circuits to which the plurality of protruding electrodes BP6 are electrically connected are input / output circuits IO1 for electrical signals (see FIG. 4). Therefore, by arranging the plurality of protruding electrodes BP6 in the peripheral region of the semiconductor chip 10, the path length of the signal transmission path can be shortened.

[0123] 10, the multiple protruding electrodes BP5 are arranged in three rows in the Y direction. The number of rows of the multiple protruding electrodes BP5 in the Y direction is not limited to three, and may be, for example, two rows, or four or more rows.

[0124] As shown in Fig. 10, the plurality of protruding electrodes BP1 and the plurality of protruding electrodes BP5 are arranged in a staggered manner. In the example shown in Fig. 10, the component of the pitch P55 along the X direction (distance P5X) is equal to the component of the pitch P55 along the Y direction (distance P5Y). The component of the pitch P66 along the X direction (distance P6X) is equal to the component of the pitch P66 along the Y direction (distance P6Y).

[0125] In the example shown in FIG. 10, the shortest pitch (pitch P15min) between one of the multiple protruding electrodes BP1 and one of the multiple protruding electrodes BP5 is equal to or greater than the pitch P11. Also, the shortest pitch (pitch P56min) between one of the multiple protruding electrodes BP6 and one of the multiple protruding electrodes BP5 is equal to or greater than the pitch P11. The pitch P15min shown in FIG. 10 is the minimum value of the pitch between one of the multiple protruding electrodes BP1 and the protruding electrode BP5 located adjacent to the one protruding electrode BP1. Similarly, the pitch P56min shown in FIG. 10 is the minimum value of the pitch between one of the multiple protruding electrodes BP6 and the protruding electrode BP5 located adjacent to the one protruding electrode BP6.

[0126] On the other hand, the maximum pitch (pitch P15max in FIG. 10) between one of the plurality of protruding electrodes BP1 and the protruding electrode BP5 adjacent to the protruding electrode BP1 is equal to or smaller than the pitch P55. Also, the maximum pitch (pitch P56max in FIG. 10) between one of the plurality of protruding electrodes BP6 and the protruding electrode BP5 adjacent to the protruding electrode BP6 is equal to or smaller than the pitch P55.

[0127] <Variation 1> Next, a description will be given of a modification of the semiconductor chip 10 shown in Fig. 5. Fig. 11 is a plan view of the electrode arrangement surface side of a semiconductor chip which is a modification of the semiconductor chip shown in Fig. 5. Fig. 12 is an enlarged plan view of part C in Fig. 11.

[0128] 11 and 12 show a semiconductor device PKG2 including a semiconductor chip 10A as a modification of the semiconductor device PKG1 including the semiconductor chip 10 shown in Fig. 5 and Fig. 6. The surface 12t of the insulating layer 12 of the semiconductor chip 10A shown in Fig. 11 and Fig. 12 includes a side 1s3 extending in the Y direction and a region R4 located between the side 1s3 and the region R1. This is the same as the semiconductor chip 10 shown in Fig. 5.

[0129] The plurality of protruding electrodes 1BP includes a protruding electrode BP4 arranged at a position overlapping with the region R4 in a plan view. Each of the plurality of protruding electrodes BP4 is electrically connected to a circuit of the semiconductor chip 10A (for example, the input / output circuit IO2 shown in FIG. 4). Each of the plurality of protruding electrodes BP1 and the plurality of protruding electrodes BP2 (see FIG. 11) is electrically connected to a circuit different from the input / output circuit IO2 (for example, the core circuit CC1 shown in FIG. 4).

[0130] The multiple protruding electrodes BP4 are arranged at a pitch P44. The value of the pitch P44 is the same as the value of the pitch P11. That is, the multiple protruding electrodes BP4 are arranged at the same pitch P11 as the multiple protruding electrodes BP1. In addition, in both the X direction and the Y direction, the multiple protruding electrodes BP4 are arranged at the same pitch as the multiple protruding electrodes BP1.

[0131] 12, each of the plurality of protruding electrodes BP4 is arranged at a pitch P44. Also, each of the plurality of protruding electrodes BP1 is arranged at a pitch P11. In the case of the semiconductor chip 10A, the distance P4X, which is the component of the pitch P44 along the X direction, is equal to the distance P1X, which is the component of the pitch P11 along the X direction, and the distance P4Y, which is the component of the pitch P44 along the Y direction, is equal to the distance P1Y, which is the component of the pitch P11 along the Y direction. Also, the pitch P14 between the adjacent protruding electrodes BP1 and BP4 is equal to the pitch P11 and the pitch P44.

[0132] As explained using Fig. 8, it is known that voids, which cause a decrease in reliability of a semiconductor device, are likely to be formed around the blank region RBL shown in Fig. 8. In the case of this modification, the multiple protruding electrodes BP4 are arranged at the same pitch as the multiple protruding electrodes BP1 in each of the X direction and the Y direction, so that it is possible to prevent the occurrence of gaps where no protruding electrodes are arranged, as in the blank region RBL shown in Fig. 8.

[0133] Incidentally, in the case of the semiconductor chip 10 shown in Fig. 5, the circuit to which the multiple protruding electrodes BP4 are connected is not, for example, an IP circuit, but a circuit in which at least the layout of the protruding electrodes 1BP has been newly designed in accordance with the specifications of the semiconductor chip 10. For this reason, even in the case of the semiconductor chip 10 shown in Fig. 5, the multiple protruding electrodes BP4 are arranged at the same pitch P1 (see Fig. 6) as the multiple protruding electrodes BP1 in each of the X and Y directions.

[0134] On the other hand, in the case of the semiconductor chip 10A shown in Figures 11 and 12, the input / output circuit IO2 (see Figure 4) to which the multiple protruding electrodes BP4 are connected is, for example, an interface circuit for a DDR memory as described above. Since memory interface circuits are often incorporated into various integrated circuits, they are often IP circuits. In the case of this modified example, the input / output circuit IO2 is a standardized IP circuit.

[0135] Therefore, in this modification, in order to arrange the plurality of protruding electrodes BP4 at the same pitch as the plurality of protruding electrodes BP1, it is necessary to align the layout of the plurality of protruding electrodes BP1 with the layout of the plurality of protruding electrodes BP4.

[0136] The semiconductor chip 10A of this modification is designed so that the layout of the plurality of protruding electrodes BP1 is the same as the layout of the plurality of protruding electrodes BP4. Therefore, unlike the case shown in FIG. 6, in this modification, the value of the distance P1X is different from the value of the distance P1Y.

[0137] 12, the component of the pitch P11 along the Y direction (distance P1Y) is longer than the component of the pitch P11 along the X direction (distance P1X). Also, the component of the pitch P44 along the Y direction (distance P4Y) is longer than the component of the pitch P44 along the X direction (distance P4X).

[0138] 12, each of the distances P1X and P4X is, for example, 75 μm, whereas each of the distances P1Y and P4Y is, for example, 110 μm.

[0139] In the case of a memory interface circuit, there are many wirings for signal transmission (hereinafter, referred to as signal wirings). Therefore, in order to secure a space for arranging a large number of signal wirings in the wiring part DP (see FIG. 9) of the semiconductor chip and the wiring layer of the wiring board 20 (see FIG. 9), one of the distance P1X and the distance P1Y may be longer than the other, as shown in FIG.

[0140] On the other hand, the multiple protruding electrodes BP1 are connected to a power supply potential supply path PVD3 for supplying a power supply potential VD3 to the core circuit CC1 shown in FIG. 4, or a reference potential supply path PVS3 for supplying a reference potential VS3 to the core circuit CC1.

[0141] Unlike the protruding electrode BP4 for signal transmission, in the case of a terminal for power supply such as the protruding electrode BP1, the value of the distance P1X is often equal to the value of the distance P1Y as shown in Fig. 6. When the value of the distance P1X is different from the value of the distance P1Y as in this modified example, there are the following advantages.

[0142] FIG. 13 is an enlarged plan view showing an example of the layout of the uppermost wiring layer of a wiring board on which the semiconductor chip shown in FIGS. 11 and 12 is mounted.

[0143] Each of the multiple protruding electrodes BP1 shown in Figures 11 and 12 is connected to either a power supply potential supply path PVD3 that supplies a power supply potential to the core circuit CC1 shown in Figure 4, or a reference potential supply path PVS3 that supplies a reference potential to the core circuit CC1.

[0144] A plurality of terminals 2PD are arranged on the wiring layer WL1 of the wiring board 20 shown in FIGS. 3 and 13, and are connected to any one of the plurality of protruding electrodes BP1, the plurality of protruding electrodes BP2, and the plurality of protruding electrodes BP3 shown in FIG.

[0145] 13, the wiring layer WL1 includes, among the terminals 2PD, a plurality of power supply potential terminals PDD electrically connected to a power supply potential supply path PVD3, and a plurality of reference potential terminals PDS electrically connected to a reference potential supply path PVS3, among the terminals 2PD. The wiring layer WL1 includes a power supply potential wiring 2DD connected to each of the power supply potential terminals PDD arranged along the X direction and extending in the X direction. The wiring layer WL1 includes a reference potential wiring 2DS connected to each of the reference potential terminals PDS arranged along the X direction and extending in the X direction.

[0146] In the Y direction, the power supply potential wirings 2DD and the reference potential wirings 2DS are alternately arranged. The power supply potential terminals PDD are electrically connected via the power supply potential wirings 2DD, so that the potential of the power supply potential supply path PVD3 can be stabilized. Similarly, the reference potential terminals PDS are electrically connected via the reference potential wirings 2DS, so that the potential of the reference potential supply path PVS3 can be stabilized.

[0147] The above configuration can also be realized when the value of the distance P1X is equal to the value of the distance P1X, as in the semiconductor chip 10 described using FIG.

[0148] However, in this modified example, as shown in Fig. 12, the value of distance P1Y is greater than the value of distance P1X, so the layout of multiple terminals 2PD in the wiring layer WL1 shown in Fig. 13 is as follows. That is, in the Y direction (column direction), the component of the pitch PPD of adjacent terminals 2PD along the Y direction (distance PPDY) is longer than the component of the pitch PPD along the X direction (distance PPDX). In the example shown in Fig. 13, the distance PPDX is, for example, 75 μm. In contrast, the distance PPDY is, for example, 110 μm.

[0149] 13 is the same as the value of the distance PPDX, the widths of the power supply potential wiring 2DD and the reference potential wiring 2DS must be designed to be narrow in order to prevent a short circuit between the power supply potential supply path VDD3 and the reference potential supply path VDS3. On the other hand, when the distance PPDY is long as in this modification, the concern of a short circuit between the power supply potential supply path VDD3 and the reference potential supply path VDS3 is reduced, so the width W2DD of the power supply potential wiring 2DD and the width W2DS of the reference potential wiring 2DS shown in FIG.

[0150] 13, the outer edge of each of the power supply potential terminals PDD is in the shape of an arc. The width W2DD of the power supply potential wiring 2DD in the Y direction is equal to or greater than the radius RPDD of the arc formed by the power supply potential terminal PDD. By increasing the width W2DD of the power supply potential wiring 2DD, the potential of the power supply potential supply path PVD3 can be further stabilized.

[0151] 13, the outer edge of each of the multiple reference potential terminals PDS forms an arc shape. The width W2DS of the reference potential wiring 2DS in the Y direction is equal to or greater than the radius RPDS of the arc formed by the reference potential terminal PDS. By widening the width W2DS of the reference potential wiring 2DS, the potential of the reference potential supply path PVS3 can be further stabilized.

[0152] In addition to the above differences, the semiconductor chip 10A shown in Fig. 11 differs from the semiconductor chip 10 shown in Fig. 5 in the following respects: the multiple protruding electrodes BP2 arranged in region R2 are arranged in two rows in the Y direction, and the multiple protruding electrodes BP5 arranged in region R5 are arranged in four rows in the Y direction.

[0153] However, the positional relationship between the plurality of protruding electrodes BP2 and the plurality of protruding electrodes BP1, and the positional relationship between the plurality of protruding electrodes BP2 and the plurality of protruding electrodes BP3 are similar to those in the semiconductor chip 10 described with reference to Figures 5 and 6, and therefore duplicated explanations will be omitted. Similarly, the positional relationship between the plurality of protruding electrodes BP5 and the plurality of protruding electrodes BP1, and the positional relationship between the plurality of protruding electrodes BP5 and the plurality of protruding electrodes BP6 are similar to those in the semiconductor chip 10 described with reference to Figures 5 and 10, and therefore duplicated explanations will be omitted.

[0154] Moreover, except for the above-mentioned differences, the semiconductor device PKG2 described with reference to Figures 11 and 12 is similar to the semiconductor device PKG1 shown in Figures 5 and 6. Therefore, a duplicated description will be omitted.

[0155] <Variation 2> Next, a description will be given of another modified example of the semiconductor chip 10 shown in Fig. 5. Fig. 14 is a plan view of the electrode arrangement surface side of a semiconductor chip which is another modified example of the semiconductor chip shown in Fig. 5. Fig. 15 is an enlarged plan view of part D in Fig. 14.

[0156] In the case of the semiconductor device PKG1 shown in Fig. 5 and the semiconductor device PKG2 shown in Fig. 11, when the pitches of the multiple protruding electrodes BP3 arranged in the region R3, which is the peripheral region, and the multiple protruding electrodes BP1 arranged in the region R1, which is the central region, are different, the following method was used to prevent gaps from occurring. That is, in the case of the semiconductor device PKG1 and the semiconductor device PKG2, a region R2 is provided between the region R3 and the region R1 shown in Fig. 6, and the Y-direction component (distance P2Y) of the pitch P22 of the multiple protruding electrodes BP2 arranged in the region R2 is longer than the Y-direction component (distance P1Y) of the pitch P11 of the multiple protruding electrodes BP1 arranged in the region R1.

[0157] On the other hand, the semiconductor device PKG3 shown in FIG. 14 differs from the semiconductor device PKG1 and the semiconductor device PKG2 in that the region R8 corresponding to the region R1 shown in FIG. 5 is adjacent to the region R3. The semiconductor device PKG3 also differs from the semiconductor device PKG1 and the semiconductor device PKG2 in the following points. That is, the region R7 is provided between the region R8 corresponding to the region R1 shown in FIG. 5 and the region R9. As shown in FIG. 15, the Y-direction component (distance P7Y) of the pitch P77 of the plurality of protruding electrodes BP7 arranged in the region R7 is longer than the Y-direction component (distance P8Y) of the pitch P88 of the plurality of protruding electrodes BP8 arranged in the region R8. The plurality of protruding electrodes BP7 arranged in the region R7 are protruding electrodes 1BP for adjusting the arrangement to prevent a gap that may cause a void from occurring between the region R8 and the region R3.

[0158] The configuration of the semiconductor device PKG3 will be described in detail below. As shown in Fig. 3, the semiconductor device PKG3 has a wiring board 20, a semiconductor chip 10B mounted on the wiring board 20 via a plurality of protruding electrodes 1BP, and an underfill layer UF disposed between the semiconductor chip 10B and the wiring board 20 and sealing the plurality of protruding electrodes 1BP.

[0159] 9, the semiconductor chip 10B includes a semiconductor substrate 11 having a surface 11t, and a wiring layer RDL formed on the surface 11t. The semiconductor chip 10B also includes an insulating layer 12 having a surface 12b facing the surface 11t of the semiconductor substrate 11 and a surface 12t opposite to the surface 12b, and is disposed so as to cover the wiring layer RDL, and a plurality of protruding electrodes 1BP electrically connected to the wiring layer RDL.

[0160] As shown in FIG. 14, surface 12t of insulating layer 12 includes side 1s1 extending in the X direction, side 1s2 located opposite side 1s1, region R7 located between sides 1s1 and 1s2, region R8 located between side 1s1 and region R7, and region R3 located between side 1s1 and region R8.

[0161] The multiple protruding electrodes 1BP include a protruding electrode BP7 arranged in a position overlapping with region R7 in a planar view, a protruding electrode BP8 arranged in a position overlapping with region R8 in a planar view, and a protruding electrode BP3 arranged in a position overlapping with region R3 in a planar view.

[0162] Each of the plurality of protruding electrodes BP3 is electrically connected to an input / output circuit IO1 (see FIG. 4) of the semiconductor chip 10B. Each of the plurality of protruding electrodes BP7 and each of the plurality of protruding electrodes BP8 are electrically connected to a circuit (for example, a core circuit CC1 shown in FIG. 4) different from the input / output circuit IO1.

[0163] As shown in Fig. 15, the multiple protruding electrodes BP7 are arranged at a pitch P77. The multiple protruding electrodes BP8 are arranged at a pitch P88 that is narrower than the pitch P77. The multiple protruding electrodes BP3 (see Fig. 14) are arranged at a pitch P33 (see Fig. 6) that is different from each of the pitches P77 and P88. In the Y direction perpendicular to the X direction, the component of the pitch P88 along the Y direction (distance P8Y) is smaller than the component of the pitch P77 along the Y direction (distance P7Y).

[0164] In the example shown in Fig. 15, the shortest pitch (pitch P78min) between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP8 is equal to or larger than the pitch P88. In addition, the shortest pitch (pitch P38min) between one of the plurality of protruding electrodes BP3 and one of the plurality of protruding electrodes BP8 shown in Fig. 14 is equal to or larger than the pitch P88 shown in Fig. 15. The pitch P78min shown in Fig. 15 is the minimum value of the pitch between one of the plurality of protruding electrodes BP7 and the protruding electrode BP8 located adjacent to the one protruding electrode BP7. In addition, the pitch P38min shown in Fig. 14 is the minimum value of the pitch between one of the plurality of protruding electrodes BP3 and the protruding electrode BP8 located adjacent to the one protruding electrode BP3.

[0165] The distances P8X and P8Y shown in FIG. 15 are each 92 μm. Therefore, the pitch P88 is 130 μm. The distance P7X shown in FIG. 15 is 92 μm, and the distance P7Y is 108 μm. Therefore, the pitch P77 is 142 μm. Furthermore, the pitch P38min shown in FIG. 14 is equal to the pitch P88. The pitch P78min shown in FIG. 15 is wider than the pitch P11, being 124 μm.

[0166] In this manner, in the case of the semiconductor device PKG3, the plurality of protruding electrodes BP7 arranged in the region R7 are provided so as to facilitate adjustment of the distance between the plurality of protruding electrodes BP8 and the plurality of protruding electrodes BP3. As a result, the distance between the plurality of protruding electrodes BP3 and the plurality of protruding electrodes BP8 shown in FIG. 14 is controlled to an appropriate distance, so that the occurrence of the above-mentioned voids can be suppressed.

[0167] As with the relationship between the pitch P11 and the pitch P22 described in FIG. 6, if the Y-direction component (distance P8Y) of the pitch P88 shown in FIG. 15 is shorter than the Y-direction component (distance P7Y) of the pitch P77, the value of the X-direction component (distance P7X) of the pitch P77 can be set arbitrarily. In the example shown in FIG. 15, the pitch P88 is narrower than the pitch P77. However, as a modified example, depending on the value of the X-direction component (distance P7X) of the pitch P77, the pitch P77 may be the same as the pitch P88, or the pitch P88 may be wider than the pitch P77. As shown in FIG. 15, it is easier to adjust the pitch P77 to fill the gap if it is wider than the pitch P88.

[0168] In this modified example, as shown in FIG. 14, surface 12t of insulating layer 12 further includes region R9 located between side 1s2 and region R7, and region R6 located between side 1s1 and region R9.

[0169] The multiple protruding electrodes 1BP further include a protruding electrode BP7 arranged in a position overlapping with region R7 in a planar view, a protruding electrode BP9 arranged in a position overlapping with region R9 in a planar view, and a protruding electrode BP6 arranged in a position overlapping with region R6 in a planar view.

[0170] Each of the plurality of protruding electrodes BP6 is electrically connected to an input / output circuit IO1 (see FIG. 4) of the semiconductor chip 10B. Each of the plurality of protruding electrodes BP7 and each of the plurality of protruding electrodes BP9 are electrically connected to a circuit (for example, a core circuit CC1 shown in FIG. 4) different from the input / output circuit IO1.

[0171] 15, the multiple protruding electrodes BP9 are arranged at a pitch P99 narrower than the pitch P77. The multiple protruding electrodes BP6 are arranged at a pitch P66 (see FIG. 10) different from each of the pitch P77 and the pitch P99. In the Y direction perpendicular to the X direction, the component of the pitch P99 along the Y direction (distance P9Y) is smaller than the component of the pitch P77 along the Y direction (distance P7Y).

[0172] As with the relationship between the pitch P11 and the pitch P22 described in FIG. 6, if the Y-direction component (distance P9Y) of the pitch P99 shown in FIG. 15 is shorter than the Y-direction component (distance P7Y) of the pitch P77, the value of the X-direction component (distance P7X) of the pitch P77 can be set arbitrarily. In the example shown in FIG. 15, the pitch P99 is narrower than the pitch P77. However, as a modified example, depending on the value of the X-direction component (distance P7X) of the pitch P77, the pitch P99 may be the same as the pitch P77 or may be wider than the pitch P77. As shown in FIG. 15, it is easier to adjust the pitch P77 to fill the gap if it is wider than the pitch P99.

[0173] In the example shown in Fig. 15, the shortest pitch (pitch P79min) between one of the plurality of protruding electrodes BP7 and one of the plurality of protruding electrodes BP9 is equal to or larger than the pitch P99. In addition, the shortest pitch (pitch P69min) between one of the plurality of protruding electrodes BP6 and one of the plurality of protruding electrodes BP9 shown in Fig. 14 is equal to or larger than the pitch P99 shown in Fig. 15. The pitch P79min shown in Fig. 15 is the minimum value of the pitch between one of the plurality of protruding electrodes BP7 and the protruding electrode BP9 located adjacent to the one protruding electrode BP7. In addition, the pitch P69min shown in Fig. 14 is the minimum value of the pitch between one of the plurality of protruding electrodes BP6 and the protruding electrode BP9 located adjacent to the one protruding electrode BP6.

[0174] The distances P9X and P9Y shown in FIG. 15 are each 92 μm. Therefore, the pitch P99 is 130 μm. The distance P7X shown in FIG. 15 is 92 μm, and the distance P7Y is 108 μm. Therefore, the pitch P77 is 142 μm. Furthermore, the pitch P69min shown in FIG. 14 is equal to the pitch P99. The pitch P79min shown in FIG. 15 is wider than the pitch P11, being 124 μm.

[0175] In the semiconductor device PKG3 of this modification, a region R7 for adjusting the arrangement is disposed between the regions R8 and R9. In addition, in the case of the semiconductor device PKG3, the regions R8 and R3 are adjacent to each other, and the regions R9 and R6 are adjacent to each other. Therefore, compared with the semiconductor device PKG1 shown in Fig. 5 or the semiconductor device PKG2 shown in Fig. 11, this is advantageous in that the arrangement space for the protruding electrodes BP7 for adjusting the arrangement can be reduced.

[0176] On the other hand, in terms of ease of adjusting the interval between the protruding electrodes, the semiconductor device PKG1 shown in FIG. 5 or the semiconductor device PKG2 shown in FIG. 11 is more advantageous.

[0177] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the above-mentioned semiconductor device will be briefly described. In the following, as a representative example, the method for manufacturing the semiconductor device PKG1 shown in FIG. 5 will be described. In addition, in the following, the drying process related to the cause of the above-mentioned void generation will be mainly described, and other processes will be described briefly. FIG. 16 is an explanatory diagram showing an example of the flow of the method for manufacturing the semiconductor device shown in FIG. 3.

[0178] As shown in FIG. 16, the method for manufacturing a semiconductor device according to this embodiment includes a wiring substrate preparation step, a semiconductor chip preparation step, a semiconductor chip mounting step, an underfill filling step, a ball mounting step, and a singulation step.

[0179] In the wiring board preparation step shown in Fig. 16, the wiring board 20 shown in Fig. 3 is prepared. Note that the wiring board prepared in this step is a so-called multi-piece board in which a plurality of wiring boards 20 are integrally formed.

[0180] In the semiconductor chip preparation step shown in Fig. 16, the semiconductor chip 10 shown in Fig. 1, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 9, and Fig. 10 is prepared. As a modified example, the semiconductor chip 10A shown in Fig. 11 and Fig. 12 may be prepared in this step. As another modified example, the semiconductor chip 10B shown in Fig. 14 and Fig. 15 may be prepared in this step.

[0181] The semiconductor chip mounting process shown in FIG. 16 includes a chip placement step, a reflow step, a cleaning step, and a drying step.

[0182] In the chip placement process, as shown in Fig. 3, the semiconductor chip 10 is placed on the upper surface 20t of the wiring board 20. In this process, alignment is performed so that the terminals 2PD formed on the wiring board 20 and the protruding electrodes 1BP are positioned to face each other. Also, for example, flux or a paste material in which flux is mixed with a solder material may be applied in advance to each exposed surface of the terminals 2PD. The flux is a material containing an activator that makes it easier to join the solder material and the terminals 2PD.

[0183] In the reflow process carried out after the chip placement process, the temperature of the protruding electrodes 1BP is heated to a temperature at which the solder material contained in the protruding electrodes 1BP melts, and after the solder material and the terminals 2PD are wetted, the temperature is lowered. Through this process, the multiple protruding electrodes 1BP and the multiple terminals 2PD are respectively joined. At this time, for example, flux residue may adhere to the periphery of the protruding electrodes 1BP.

[0184] In order to prevent flux residues from remaining in the product, a cleaning process is carried out after the reflow process. In the cleaning process, water or a cleaning solution made by adding chemicals to water is continuously supplied to the gap between the semiconductor chip 10 and the wiring board 20 shown in Fig. 3. If the moisture supplied in this process remains in the product, it will cause the above-mentioned voids to occur.

[0185] Next, in the drying step, moisture is removed by continuously supplying air (e.g., hot air) into the gap between the semiconductor chip 10 and the wiring substrate 20 shown in Fig. 3. Fig. 17 is a plan view that shows a schematic view of the direction in which air is blown in the drying step shown in Fig. 16.

[0186] In the present embodiment, as shown by the arrows in Fig. 17, the wind VT is continuously sent in a direction from the side 1s2 to the side 1s1 of the semiconductor chip 10. In this case, drying proceeds in order from the position closest to the side 1s2, and the drying process ends when drying is completed up to the side 1s1.

[0187] Some of the moisture remaining around the protruding electrode 1BP is removed by evaporation, while the other is removed by being pushed in the airflow direction. According to the study by the inventors of the present application, in the case of the drying method shown in FIG. 17, the generation of voids can be suppressed not only in the region closer to the side 1s2 than the side 1s1 (corresponding to the blank region RBL2 shown in FIG. 8) but also in the region closer to the side 1s1 than the side 1s2 (corresponding to the blank region RBL1 shown in FIG. 8). More specifically, in the case of the semiconductor chip 10 shown in FIG. 17, the generation of voids can be suppressed not only in the boundary between the region R6 and the region R5 and the boundary between the region R5 and the region R1, but also in the boundary between the region R1 and the region R2 and the boundary between the region R2 and the region R3.

[0188] The same is true for the semiconductor chip 10A shown in Fig. 11. Also, in the case of the semiconductor chip 10B shown in Fig. 15, the occurrence of voids can be suppressed at each of the boundaries between regions R6 and R9, between regions R9 and R7, between regions R7 and R8, and between regions R8 and R3.

[0189] From these results, the structures shown in Figures 5, 11, and 15 can particularly suppress the generation of voids when a drying method is applied in which air VT is continuously blown from the side 1s2 side to the side 1s1 side as shown in Figure 17.

[0190] Next, in the underfill filling step, a paste or liquid resin is supplied into the gap between the semiconductor chip 10 and the wiring board 20 shown in Fig. 3 to seal the multiple protruding electrodes 1BP. In the case of this embodiment, the drying step is completed before the underfill filling step, and the remaining moisture is removed, so that it is possible to prevent voids from occurring after the underfill filling step.

[0191] Next, in the singulation step, the multiple wiring substrates 20 are divided to obtain multiple semiconductor devices PKG1.

[0192] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0193] 1b Back side (front, main side, back side, bottom side) 1BP,51,52,53,54,BP1,BP2,BP3,BP4,BP5,BP6,BP7,BP8,BP9 Protruding electrodes (bump electrodes) 1PD electrode (pad, electrode pad, bonding pad) 1s, 1s1, 1s2, 1s3, 1s4, 20s side 1t Front (front, main surface, front, top) 2Cb bottom surface 2CR Insulation layer (core material, core insulation layer) 2Ct top surface 2D Routing 2DD power supply potential wiring 2DS Reference potential wiring 2E Insulation layer 2LD Land (Land Pattern) 2PD terminal 10, 10A, 10B, 10C1, 10C2 Semiconductor chip 11 Semiconductor substrate 11t surface (principal surface) 12 Insulating layer 12b side 12t side 20 Wiring board 20b Bottom surface (surface, main surface, mounting surface) 20t Top surface (main surface, chip mounting surface) 2THW Through hole wiring 2V Via CC1 Core Circuit DP wiring section IO1, IO2 Input / Output Circuit P1X,P1Y,P2X,P2Y,P3X,P3Y,P4X,P4Y,P5X,P5Y,P6X,P6Y,P7X,P7Y,P8X,P8Y,P9X,P9Y,PPDX,PPDY,PX,PY Distance P11, P12, P12max, P12min, P14, P15max, P15min, P22, P23, P23max, P23min, P33, P38min, P44, P55, P56max, P56min, P66, P69min, P77, P78min, P79min, P88, P99, PPD, PXY Pitch PDD power supply potential pin PDS reference potential terminal PKG1, PKG2, PKG3 Semiconductor device PVD1, PVD2, PVD3 Power supply potential supply path PVS1,PVS2,PVS3 Reference potential supply path R1,R2,R3,R4,R5,R6,R7,R8,R9 area RBL, RBL1, RBL2 Blank area RDL wiring layer RPDD,RPDS Radius RW1,RW2,RW3,RW4 columns SB Solder ball (solder material, external terminal, electrode, external electrode) SG1,SG2,SG3,SG4,SG5,SG6,SG7,SG8 signal SR1, SR2 insulating film UBM Underbump Metal UF Underfill layer (insulating layer, insulating material) VD1,VD2,VD3 Power supply potential VDD3 Power supply potential supply path VDS3 Reference potential supply path VS1,VS2,VS3 Reference potential VT style W2DD,W2DS width WL1-WL8 wiring layer

Claims

1. A wiring board; a semiconductor chip mounted on the wiring board via a plurality of protruding electrodes; a first insulating member disposed between the semiconductor chip and the wiring board and sealing the plurality of protruding electrodes; having The semiconductor chip comprises: a semiconductor substrate having a first surface; a first wiring layer formed on the first surface; a second insulating layer including a second surface facing the first surface of the semiconductor substrate and a third surface opposite to the second surface, the second insulating layer being disposed so as to cover the first wiring layer; the plurality of protruding electrodes electrically connected to the first wiring layer; having The third surface of the second insulating layer has, in a plan view, A first side extending in a first direction; A second side located opposite to the first side; A first region located between the first side and the second side; a second region located between the first side and the first region and adjacent to the first region; a third region located between the first side and the second region and adjacent to the second region; Including, The plurality of protruding electrodes include a plurality of first protruding electrodes arranged at positions overlapping the first region in a plan view; a plurality of second protruding electrodes arranged at positions overlapping the second region in a plan view; a plurality of third protruding electrodes arranged at positions overlapping the third region in a plan view; Including, each of the plurality of third protruding electrodes is electrically connected to a first circuit of the semiconductor chip; each of the first protruding electrodes and the second protruding electrodes is electrically connected to a circuit different from the first circuit; The first protruding electrodes are arranged at a first pitch, The plurality of second protruding electrodes are arranged at a second pitch, the third protruding electrodes are arranged at a pitch different from each of the first pitch and the second pitch, A semiconductor device, wherein in a second direction perpendicular to the first direction, a component of the second pitch along the second direction is larger than a component of the first pitch along the second direction.

2. In claim 1, Among the plurality of protruding electrodes, the plurality of third protruding electrodes include a protruding electrode disposed at a position closest to the first side.

3. In claim 2, The first circuit is an input / output circuit for an electric signal.

4. In claim 1, The plurality of second protruding electrodes are arranged in three or more rows in the second direction.

5. In claim 1, the plurality of first protruding electrodes and the plurality of second protruding electrodes are arranged in a staggered manner.

6. In claim 1, a shortest pitch between one of the plurality of first protruding electrodes and one of the plurality of second protruding electrodes is equal to or greater than the first pitch; a shortest pitch between one of the plurality of third protruding electrodes and one of the plurality of second protruding electrodes is equal to or greater than the first pitch.

7. In claim 6, A semiconductor device, wherein the maximum value of the pitch between one of the plurality of first protruding electrodes and a second protruding electrode among the plurality of second protruding electrodes that is located adjacent to the one first protruding electrode is less than or equal to the second pitch.

8. In claim 6, A semiconductor device, wherein the maximum value of the pitch between one of the plurality of third protruding electrodes and a second protruding electrode among the plurality of second protruding electrodes that is located adjacent to the one third protruding electrode is less than or equal to the second pitch.

9. In claim 1, The third surface of the second insulating layer is A third side extending in the second direction; a fourth region located between the third side and the first region; Further comprising: the plurality of protruding electrodes include a plurality of fourth protruding electrodes arranged at positions overlapping the fourth region in a plan view, each of the plurality of fourth protruding electrodes is electrically connected to a second circuit of the semiconductor chip; each of the first protruding electrodes and the second protruding electrodes is electrically connected to a circuit different from the second circuit; the plurality of fourth protruding electrodes are arranged at the same first pitch as the plurality of first protruding electrodes.

10. In claim 9, A semiconductor device, wherein a component of the first pitch along the second direction is longer than a component of the first pitch along the first direction.

11. In claim 10, each of the plurality of first protruding electrodes is connected to either a power supply potential supply path that supplies a power supply potential to a third circuit of the semiconductor chip or a reference potential supply path that supplies a reference potential to the third circuit; the wiring substrate includes a second wiring layer in which a plurality of terminals connected to any one of the plurality of first protruding electrodes, the plurality of second protruding electrodes, and the plurality of third protruding electrodes are arranged; The second wiring layer is Among the plurality of terminals, a plurality of power supply potential terminals are electrically connected to the power supply potential supply path; Among the plurality of terminals, a plurality of reference potential terminals are electrically connected to the reference potential supply path; a power supply potential wiring connected to each of the plurality of power supply potential terminals arranged along the first direction and extending in the first direction; a reference potential wiring that is connected to each of the plurality of reference potential terminals arranged along the first direction and extends in the first direction; A semiconductor device comprising:

12. In claim 11, an outer edge of each of the plurality of power supply potential terminals forms an arc shape, and a width of the power supply potential wiring in the second direction is equal to or greater than a radius of the arc formed by the power supply potential terminals.

13. In claim 11, an outer edge of each of the plurality of reference potential terminals forms an arc shape, and a width of the reference potential wiring in the second direction is equal to or greater than a radius of the arc formed by the reference potential terminals.

14. A wiring board; a semiconductor chip mounted on the wiring board via a plurality of protruding electrodes; a first insulating member disposed between the semiconductor chip and the wiring board and sealing the plurality of protruding electrodes; having The semiconductor chip comprises: a semiconductor substrate having a first surface; a first wiring layer formed on the first surface; a second insulating layer including a second surface facing the first surface of the semiconductor substrate and a third surface opposite to the second surface, the second insulating layer being disposed so as to cover the first wiring layer; the plurality of protruding electrodes electrically connected to the first wiring layer; having The third surface of the second insulating layer has, in a plan view, A first side extending in a first direction; A second side located opposite to the first side; A first region located between the first side and the second side; a second region located between the first side and the first region; a third region located between the first side and the second region; Including, The plurality of protruding electrodes include a plurality of first protruding electrodes arranged at positions overlapping the first region in a plan view; a plurality of second protruding electrodes arranged at positions overlapping the second region in a plan view; a plurality of third protruding electrodes arranged at positions overlapping the third region in a plan view; Including, each of the plurality of third protruding electrodes is electrically connected to a first circuit of the semiconductor chip; each of the first protruding electrodes and the second protruding electrodes is electrically connected to a circuit different from the first circuit; The first protruding electrodes are arranged at a first pitch, The plurality of second protruding electrodes are arranged at a second pitch, the third protruding electrodes are arranged at a pitch different from each of the first pitch and the second pitch, A semiconductor device, wherein in a second direction perpendicular to the first direction, a component of the second pitch along the second direction is smaller than a component of the first pitch along the second direction.

Images