Wiring board

Abstract

To provide a wiring board having high quality.SOLUTION: A wiring board according to an embodiment includes: a core substrate including a glass substrate, a through-hole passing through the substrate and a through-hole conductor formed in the through-hole; a resin insulation layer which is formed on the core substrate and has a first surface, a second surface and an opening for a via conductor; a first conductor layer formed on the first surface of the resin insulation layer; and the via conductor which is formed in the opening and electrically connected to the through-hole conductor. The first conductor layer and the via conductor are formed of a seed layer and an electrolytic plating layer, and the seed layer is formed by sputtering. The resin insulation layer is formed of a resin and inorganic particles. The inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin. The first inorganic particles each are formed of a first portion protruding from the resin and a second portion embedded in the resin. The first surface is formed of an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a multi-layer substrate having a core made of glass material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-133473 A Summary of the Invention

[0004] [Problem of Patent Document 1] Patent Document 1 controls the light transmittance of the first insulating layer made of a glass material. As an example of a method for controlling the light transmittance, Patent Document 1 states that a colorant is contained in the first insulating layer. It is considered difficult for the first insulating layer made of a glass material to contain a colorant uniformly. [Means for solving the problem]

[0005] The wiring board of the present invention includes a core substrate having a glass substrate, a through hole penetrating the substrate, and a through hole conductor formed in the through hole, a resin insulating layer formed on the core substrate, the resin insulating layer having a first surface, a second surface opposite to the first surface, and an opening for a via conductor extending from the first surface to the second surface, a first conductor layer formed on the first surface of the resin insulating layer, and a via conductor formed in the opening and electrically connected to the through hole conductor. The first conductor layer and the via conductor are formed by a seed layer and an electrolytic plating layer formed on the seed layer, and the seed layer is formed by sputtering. The resin insulating layer is formed of a resin and inorganic particles, the inorganic particles including first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin, the first inorganic particles being formed by a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

[0006] In the wiring board of the embodiment of the present invention, the core substrate includes a glass substrate. The glass substrate has excellent flatness. Therefore, the first surface of the resin insulating layer has excellent flatness. The first surface has excellent smoothness. The embodiment can form fine wiring on the first surface of the resin insulating layer. In the embodiment, almost no recesses are formed on the first surface of the resin insulating layer. Therefore, when a seed layer is formed on the resin insulating layer by sputtering, the embodiment can form a continuous seed layer even if the thickness of the sputtering film is thin. As a result, when the seed layer is removed, the embodiment can reduce the amount of etching. The embodiment can form fine wiring on the resin insulating layer. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view illustrating a wiring board according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the wiring board according to the embodiment. [Figure 3A] FIG. 2 is an enlarged cross-sectional view illustrating a portion of the wiring board according to the embodiment. [Figure 3B] FIG. 4 is an enlarged cross-sectional view showing a schematic view of a part of an inner wall surface. [Figure 3C] FIG. 4 is an enlarged cross-sectional view illustrating a schematic view of a portion of a seed layer. [Figure 4] 4 is a cross-sectional photograph showing a schematic view of a portion of the wiring board according to the embodiment. [Figure 5A] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5B] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5C] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5D] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5E] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5F] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5G] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5H] 5A to 5C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an [Figure 5I] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5J] 5A to 5C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an [Figure 5K] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 5L] 5A to 5C are enlarged cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an [Figure 5M] 1A to 1C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to an embodiment. [Figure 6] 10A to 10C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to a modified [Figure 7] 10A to 10C are cross-sectional views each showing a schematic diagram of a method for manufacturing a wiring board according to a modified DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] [Embodiment] Fig. 1 is a cross-sectional view showing a wiring board 2 of an embodiment. Fig. 2 and Fig. 3A are enlarged cross-sectional views showing a part of the wiring board 2 of the embodiment. As shown in Fig. 1, the wiring board 2 has a core substrate 3, a front-side buildup layer 300F, and a back-side buildup layer 300B.

[0009] The core substrate 3 has a substrate 4, a through hole 6, and a through-hole conductor 8. The substrate 4 has a surface 5F and a back surface 5B opposite the surface 5F. The substrate 4 is made of glass. The through hole 6 penetrates the substrate 4. The shape of the through hole 6 is approximately cylindrical. The diameter of the through hole 6 is approximately constant. The shape of the through hole 6 may be approximately a truncated cone. The shape of the through hole 6 may be a shape obtained by connecting two approximately cones. The two cones are a cone on the surface side and a cone on the back side. The bottom surface of the cone on the surface side is located on the surface 5F, and the bottom surface of the cone on the back side is located on the back surface 5B. In this case, the side surface of the through hole 6 is formed by a surface tapered from the surface 5F toward the back surface 5B and a surface tapered from the back surface 5B toward the surface 5F.

[0010] The through-hole conductor 8 is formed in the through hole 6. The through-hole conductor 8 is mainly formed of copper. The through-hole conductor 8 includes a seed layer 10a formed on the inner wall surface of the through hole 6 and an electrolytic plating layer 10b formed on the seed layer 10a. The electrolytic plating layer 10b fills the through hole 6. The seed layer 10a is formed by electroless plating. The through-hole conductor 8 has an upper end 8F and a lower end 8B. The surface of the upper end 8F and the front surface 5F form substantially the same plane. The surface of the lower end 8B and the back surface 5B form substantially the same plane. The upper end 8F is exposed from the front surface 5F. The lower end 8B is exposed from the back surface 5B.

[0011] The front-side buildup layer 300F is formed on the front surface 5F of the substrate 4. The front-side buildup layer 300F has a front-side resin insulation layer, a front-side conductor layer, and a front-side via conductor penetrating the front-side resin insulation layer. The front-side conductor layer and the front-side via conductor are electrically connected to the through-hole conductor 8. The front-side resin insulation layer and the front-side conductor layer are alternately laminated. The front-side resin insulation layer in FIG. 1 is the first resin insulation layer 20F and the second resin insulation layer 120F. The front-side conductor layer is the first conductor layer 30F and the second conductor layer 130F. The front-side via conductor is the first via conductor 40F and the second via conductor 140F.

[0012] The first resin insulating layer 20F has a first surface 22F and a second surface 24F opposite to the first surface 22F. The first resin insulating layer 20F is formed on the surface 5F of the substrate 4 so that the second surface 24F and the surface 5F face each other. In the example of FIG. 1, the second surface 24F is in contact with the surface 5F. The second surface 24F is in contact with a part of the upper end 8F. There is no conductor circuit between the surface 5F and the second surface 24F. No conductor circuit is formed on the surface 5F. The first resin insulating layer 20F has a first opening 26F that reaches the upper end 8F of the through-hole conductor 8. The first opening 26F has an opening (top opening) on ​​the first surface 22F and an opening (bottom opening) on ​​the second surface 24F. The shapes of the top opening and the bottom opening are approximately circular. The bottom opening can simultaneously expose the upper end 8F and the surface 5F. In this case, the surface 5F around the upper end 8F is exposed. The bottom opening may expose a part of the upper end 8F and the surface 5F around the part (first example). The bottom opening may expose the entire upper end 8F and the surface 5F around the upper end 8F (second example). As shown in FIG. 1, the bottom opening can expose only the upper end 8F (third example). Two of the first, second, and third examples may be mixed. All of the first, second, and third examples may be mixed. It is preferable to mix the first and third examples. In this case, the upper ends 8F of some of the through-hole conductors 8 are exposed in the opening of the first example, and the upper ends 8F of the remaining through-hole conductors 8 are exposed in the opening of the third example. The first resin insulating layer 20F is formed of a resin 80 and a large number of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of the resin are a thermosetting resin and a photosetting resin. The inorganic particles 90 are glass particles. The inorganic particles 90 may be alumina. The content of the inorganic particles 90 in the first resin insulation layer (20F) is 75 wt % or more.

[0013] 1 and 2, the inorganic particles 90 include first inorganic particles 91 partially embedded in the resin 80 and second inorganic particles 92 embedded in the resin 80. The second inorganic particles are completely embedded in the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are spherical in shape. As shown in FIG. 2, the first inorganic particles 91 are formed of a first portion 91a protruding from the resin 80 and a second portion 91b embedded in the resin 80. The first surface 22F of the first resin insulating layer 20F is formed of an upper surface 80R of the resin 80 and an exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80.

[0014] The ratio R of the volume of the first portion 91a to the volume of the first inorganic particles 91 (volume of the first portion 91a / volume of the first inorganic particles 91) is greater than 0 and equal to or less than 0.4. The ratio R is preferably equal to or less than 0.2. The ratio R is more preferably equal to or less than 0.1. The ratio R is most preferably equal to or less than 0.05. When the first portion 91a protrudes from the resin 80, the first surface 22F of the first resin insulating layer 20F has slight irregularities. However, the upper surface 80R of the resin 80 is not roughened. The upper surface 80R of the resin 80 forming the first surface 22F of the first resin insulating layer 20F is almost flat. The upper surface 80R of the resin 80 has almost no recesses. Therefore, the first surface 22F has almost no recesses. The arithmetic mean roughness (Ra) of the first surface 22F is less than 0.08 μm. The roughness Ra of the first surface 22F is preferably equal to or less than 0.05 μm. It is more preferable that the roughness Ra of the first surface 22F is 0.03 μm or less. The arithmetic mean roughness (Ra) of the upper surface 80R of the resin 80 forming the first surface 22F of the first resin insulation layer 20F is less than 0.08 μm. It is preferable that the roughness Ra of the upper surface 80R of the resin 80 is 0.05 μm or less. It is more preferable that the roughness Ra of the upper surface 80R of the resin 80 is 0.03 μm or less.

[0015] As shown in FIG. 3A, the inorganic particles 90 further include third inorganic particles 93 that form the inner wall surface of the opening (opening for the via conductor). The shape of the third inorganic particles 93 is obtained by cutting a sphere with a plane. The shape of the third inorganic particles 93 is obtained by cutting the second inorganic particles 92 with a plane. The shape of the third inorganic particles 93 is approximately a spherical incision. The shape of the third inorganic particles 93 is different from the shape of the second inorganic particles 92. The shape of the third inorganic particles 93 is different from the shape of the first inorganic particles 91. The shape of the first inorganic particles 91 is similar to the shape of the second inorganic particles 92.

[0016] FIG. 4 is a cross-sectional photograph showing an example of the inner wall surface 27F of the first opening 26F. As shown in FIG. 3A and FIG. 4, the inner wall surface 27F of the first opening 26F is formed of the resin 80 and the third inorganic particles 93. The third inorganic particles 93 have a flat portion 93a. The flat portion 93a forms the inner wall surface 27F. The inner wall surface 27F is formed of the resin 80 and the flat portion 93a. The flat portion 93a and the surface of the resin 80 forming the inner wall surface 27F form a substantially common surface. No irregularities are formed on the resin 80 forming the inner wall surface 27F. The surface of the resin 80 forming the inner wall surface 27F is smooth. No irregularities are formed on the exposed surface 93b of the flat portion 93a (the surface forming the inner wall surface 27F). The exposed surface 93b of the flat portion 93a is smooth. The inner wall surface 27F is formed smoothly. The arithmetic mean roughness (Ra) of the inner wall surface 27F is 1.0 μm or less. As shown in FIG. 4, a step 28 is formed at the boundary between the surface 80a of the resin 80 and the flat portion 93a of the third inorganic particle 93. The amount of the step 28 is preferably 3.0 μm or less. The amount of the step 28 is more preferably 1.5 μm or less. The amount of the step 28 is further preferably 0.5 μm or less. For example, the distance between the exposed surface 93b and the surface 80a of the resin 80 (the surface forming the inner wall surface 27F) indicates the amount of the step 28. The exposed surface 93b protrudes from the surface 80a of the resin 80. Alternatively, the exposed surface 93b is recessed from the surface 80a of the resin 80. It is preferable that the exposed surface 93b protrudes.

[0017] The flat portion 93a of the third inorganic particle 93 approximately coincides with a surface obtained by extending the surface 80a (the surface forming the inner wall surface 27F) of the resin 80 formed around the third inorganic particle 93. The flat portion 93a depicted as a substantially straight line in Figures 1 and 3A means a plane. In the cross section shown in Figures 1 and 3A, the flat portion 93a is a plane. The flat portion 93a does not have to be a perfect plane. The flat portion 93a is a substantially flat surface that is approximately smooth.

[0018] Fig. 3B is an enlarged cross-sectional view showing a part of the inner wall surface 27F in Fig. 3A. As shown in Fig. 3B, the surface 80a of the resin 80 located between the reference surface 200 connecting the flat parts 93a of the two third inorganic particles 93 forming the inner wall surface 27F may be recessed or protruding (see the dashed line). It is preferable that there are no other third inorganic particles 93 between the two third inorganic particles 93 forming the reference surface 200. The distance between the reference surface 200 and the surface 80a of the resin 80 may be used as a representative value of the amount of the step 28.

[0019] 3A, inner wall surface 27F of first opening 26F is inclined. An angle (inclination angle) θ1 between surface 5F of substrate 4 and inner wall surface 27F is not less than 70° and not more than 85°. An angle (inclination angle) θ2 between first surface 22F of first resin insulating layer 20F and inner wall surface 27F is not less than 95° and not more than 110°.

[0020] In the cross-sections shown in Figures 1 and 3A, the shape of the first opening 26F is shown as a substantially inverted trapezoid. However, the actual shape of the first opening 26F is a substantially inverted truncated cone. Therefore, the inner wall surface (side wall) 27F of the actual first opening 26F is a substantially curved surface. In other words, the common surface formed by the flat portion 93a and the resin 80 includes the inner wall surface (side wall) 27F formed as a substantially curved surface.

[0021] As shown in FIG. 1, the first conductor layer 30F is formed on the first surface 22F of the first resin insulating layer 20F. The first conductor layer 30F includes a first signal wiring 32F, a second signal wiring 34F, and a land 36F. Although not shown in the figure, the first conductor layer 30F also includes a conductor circuit other than the first signal wiring 32F, the second signal wiring 34F, and the land 36F. The first signal wiring 32F and the second signal wiring 34F form a pair wiring. The first conductor layer 30F is mainly formed of copper. The first conductor layer 30F is formed of a seed layer 30Fa and an electrolytic plating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa is formed by sputtering. The seed layer 30Fa is formed of a first layer 31Fa on the first surface 22F and a second layer 31Fb on the first layer 31Fa. The first layer 31Fa is in contact with the first surface 22F. The second layer 31Fb is not essential. The first layer 31Fa and the second layer 31Fb are formed by sputtering. Both layers are formed by sputtering.

[0022] The first layer 31Fa is made of an alloy containing copper and aluminum. The first layer 31Fa may further contain a specific metal. Examples of the specific metal are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one type of specific metal, two types of specific metals, or three types of specific metals. The content of aluminum in the alloy is 1.0 at% or more and 15.0 at% or less. An example of the specific metal is silicon. The content of the specific metal in the alloy is 0.5 at% or more and 10.0 at% or less. The first layer 31Fa may contain impurities. Examples of the impurities are oxygen and carbon. The first layer 31Fa may contain oxygen or carbon. The first layer 31Fa may contain oxygen and carbon. In the embodiment, the alloy further contains carbon. The content of carbon in the alloy is 50 ppm or less. The alloy further contains oxygen. The content of oxygen in the alloy is 100 ppm or less. The above content values ​​of each element are examples. Among the elements forming the first layer 31Fa, the amount of copper is the largest. The amount of aluminum is the next largest. The amount of the specific metal is smaller than the amount of aluminum. Therefore, copper is the main metal, aluminum is the first minor metal, and the specific metal is the second minor metal. The amount of impurities is smaller than the amount of the specific metal. The first layer 31Fa is a copper alloy.

[0023] The second layer 31Fb is formed of copper. The copper content forming the second layer 31Fb is 99.9 at% or more. The copper content in the second layer 31Fb is preferably 99.95 at% or more. The seed layer 30Fa is a copper alloy. The electrolytic plating layer 30Fb is formed of copper. The copper content forming the electrolytic plating layer 30Fb is 99.9 at% or more. The copper content in the electrolytic plating layer 30Fb is preferably 99.95 at% or more.

[0024] The first resin insulating layer 20F is formed on a glass substrate 4. Since glass has excellent flatness, the first surface 22F of the first resin insulating layer 20F also has excellent flatness. If no conductor circuit is formed between the surface 5F and the first resin insulating layer 20F, the first surface 22F can follow the surface 5F. The first surface 22F can have flatness equivalent to that of the surface 5F. In the embodiment, fine wiring can be formed on the first surface 22F. For example, the first conductor layer 30F can have wiring having a width of 1.5 μm or more and 3.5 μm or less. The width of the space between adjacent wirings is 1.5 μm or more and 3.5 μm or less.

[0025] The first via conductor 40F is formed in the first opening 26F. The first via conductor 40F electrically connects the through-hole conductor 8 and the first conductor layer 30F. The first via conductor 40F electrically connects the through-hole conductor 8 and the land 36F of the first via conductor 40F. The first via conductor 40F is formed of a seed layer 30Fa and an electrolytic plating layer 30Fb on the seed layer 30Fa. The seed layer 30Fa forming the first via conductor 40F and the seed layer 30Fa forming the first conductor layer 30F are common. The electrolytic plating layer 30Fb forming the first via conductor 40F and the electrolytic plating layer 30Fb forming the first conductor layer 30F are common. The seed layer 30Fa forming the first via conductor 40F is formed of a first layer 31Fa formed on the inner wall surface 27F of the first opening 26F and on the upper end 8F of the through-hole conductor 8 exposed from the first opening 26F, and a second layer 31Fb on the first layer 31Fa. The first layer 31Fa forming the first via conductor 40F and the first layer 31Fa forming the first conductor layer 30F are common. The second layer 31Fb forming the first via conductor 40F and the second layer 31Fb forming the first conductor layer 30F are common. In FIG. 1, the first via conductor 40F is connected to the upper end 8F. The first layer 31Fa is in contact with the upper end 8F and the inner wall surface 27F of the through-hole conductor 8. The first via conductor 40F is formed directly above the upper end 8F.

[0026] FIG. 3C is an enlarged cross-sectional view showing a schematic view of a part of the seed layer 30Fa on the inner wall surface 27F in FIG. 3A. FIG. 4 shows an example of the seed layer 30Fa. The seed layer 30Fa on the inner wall surface 27F is in contact with the inner wall surface 27F. As shown in FIG. 3A, FIG. 3C, and FIG. 4, the seed layer 30Fa forming the first via conductor 40F has a substantially smooth first film 60 and a substantially smooth second film 70. The first film 60 and the second film 70 are electrically connected. The first film 60 and the second film 70 are continuous. As shown in FIG. 4, a part of the first film 60 is formed on the second film 70. The leading end 62 of the first film 60 is formed on the trailing end 72 of the second film 70. The first film 60 and the second film 70 are formed at the same time. The cross section of the seed layer 30Fa covering the inner wall surface 27F has a substantially stepped shape.

[0027] As shown in FIG. 3C, the first layer 31Fa of the seed layer 30Fa has a first film 60a and a second film 70a. The first film 60a and the second film 70a are electrically connected. The first film 60a and the second film 70a are continuous. The leading end 62a of the first film 60a is formed on the trailing end 72a of the second film 70a. The cross section of the first layer 31Fa covering the inner wall surface 27F has a substantially stepped shape. The first layer 31Fa on the inner wall surface 27F is in contact with the inner wall surface 27F.

[0028] The second layer 31Fb of the seed layer 30Fa has a first film 60b and a second film 70b. The first film 60b and the second film 70b are electrically connected. The first film 60b and the second film 70b are continuous. The leading end 62b of the first film 60b is formed on the trailing end 72b of the second film 70b. The cross section of the second layer 31Fb formed on the inner wall surface 27F has a substantially stepped shape.

[0029] In the embodiment, a portion of the first film 60 is laminated on the second film 70. A portion of the first film 60 overlaps the second film 70. A leading end 62 of the first film 60 is laminated on a trailing end 72 of the second film 70. A leading end 62 of the first film 60 overlaps on a trailing end 72 of the second film 70.

[0030] In the embodiment, the inner wall surface 27F is formed with a substantially smooth surface. If the first layer 31Fa follows the shape of the inner wall surface 27F, the first layer 31Fa on the inner wall surface 27F has a substantially smooth surface. The cross section of the first layer 31Fa has a linear shape. The seed layer 30Fa on the inner wall surface 27F has a substantially smooth surface. The cross section of the seed layer 30Fa has a linear shape. In this case, the electrolytic plating layer 30Fb forming the first via conductor 40F is formed on a smooth surface. For example, when the wiring board 2 receives a large impact, peeling occurs between the first layer 31Fa on the inner wall surface 27F and the second layer 31Fb on the first layer 31Fa. Alternatively, peeling occurs between the seed layer 30Fa on the inner wall surface 27F and the electrolytic plating layer 30Fb forming the first via conductor 40F. In contrast, the cross sections of the seed layer 30Fa and the first layer 31Fa in the embodiment have a stepped shape. Therefore, peeling is unlikely to occur.

[0031] When the opening for the via conductor exposes the surface 5F, the first layer 31Fa contacts the glass substrate 4. The opening in the first example and the opening in the second example expose the surface 5F. Furthermore, the opening in the first example and the opening in the second example expose the upper end 8F. Since the first layer 31Fa contains aluminum and the glass contains oxygen, it is considered that the bonding strength between the first layer 31Fa and the substrate 4 is increased. Furthermore, when the first layer 31Fa contains silicon, the first layer 31Fa and the substrate 4 contain the same element (silicon). Furthermore, it is considered that the bonding strength between the first layer 31Fa and the substrate 4 is increased. When a part of the seed layer forming the via conductor contacts the glass substrate 4, the via conductor is unlikely to peel off from the through-hole conductor 8 even if the wiring substrate 2 is subjected to a thermal shock. It is preferable that the via conductor contacting the upper end 8F contacts the surface 5F. In this case, the seed layer (e.g., first layer 31Fa) forming such a via conductor contacts both the upper end 8F and the front surface 5F. Similarly, it is preferable that the via conductor contacting the lower end 8B contacts the rear surface 5B. In this case, the seed layer (e.g., first layer) forming such a via conductor contacts both the lower end 8B and the rear surface 5B. When an adhesive layer for adhering a resin insulating layer such as the first resin insulating layer 20F to the substrate 4 is disposed between the front surface 5F and the second surface 24F, the adhesive layer may be a part of the resin insulating layer. The adhesive layer is included in the resin insulating layer. The adhesive layer includes an organic adhesive layer and an inorganic adhesive layer. The adhesive layer is formed of an insulating material.

[0032] The second resin insulating layer 120F is formed on the first surface 22F of the first resin insulating layer 20F and the first conductor layer 30F. The first conductor layer 30F is formed between the second resin insulating layer 120F and the first resin insulating layer 20F. The second resin insulating layer 120F has a first surface 122F and a second surface 124F opposite to the first surface 122F. The second surface 124F of the second resin insulating layer 120F faces the first conductor layer 30F. The second resin insulating layer 120F is formed of resin 80 and inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90, similar to the first resin insulating layer 20F. Therefore, the material of the second resin insulating layer 120F is the same as the material of the first resin insulating layer 20F. The first surface 122F of the second resin insulating layer 120F is the same as the first surface 22F of the first resin insulating layer 20F. The first inorganic particles 91 forming the second resin insulating layer 120F have a first portion 91a and a second portion 91b, and an exposed surface 91aR of the first portion 91a forms a first surface 122F of the second resin insulating layer 120F. The first inorganic particles 91 in the first resin insulating layer 20F and the first inorganic particles 91 in the second resin insulating layer 120F have a similar ratio R.

[0033] The second resin insulating layer 120F has a second opening 126F that exposes the first conductor layer 30F. The second opening 126F exposes the land 36F. The second opening 126F has an inner wall surface 127F. The first opening 26F and the second opening 126F are similar. Therefore, the inner wall surface 27F of the first opening 26F and the inner wall surface 127F of the second opening 126F are similar.

[0034] The second conductor layer 130F is formed on the first surface 122F of the second resin insulating layer 120F. The second conductor layer 130F includes a first signal wiring 132F, a second signal wiring 134F, and a land 136F. Although not shown in the figure, the second conductor layer 130F also includes a conductor circuit other than the first signal wiring 132F, the second signal wiring 134F, and the land 136F. The first signal wiring 132F and the second signal wiring 134F form a pair wiring. The second conductor layer 130F and the first conductor layer 30F are similar. Therefore, the second conductor layer 130F is formed of a seed layer 130Fa and an electrolytic plating layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed of a first layer 131Fa and a second layer 131Fb on the first layer 131Fa. First layer 131Fa forming second conductor layer 130F is similar to first layer 31Fa forming first conductor layer 30F. Second layer 131Fb forming second conductor layer 130F is similar to second layer 31Fb forming first conductor layer 30F. Electrolytically plated layer 130Fb forming second conductor layer 130F is similar to electrolytically plated layer 30Fb forming first conductor layer 30F.

[0035] The second via conductor 140F is formed in the second opening 126F. The second via conductor 140F electrically connects the first conductor layer 30F and the second conductor layer 130F. In FIG. 1, the second via conductor 140F electrically connects the land 36F and the land 136F. The second via conductor 140F and the first via conductor 40F are similar. Therefore, the second via conductor 140F is formed of the seed layer 130Fa and the electrolytic plating layer 130Fb on the seed layer 130Fa. The seed layer 130Fa is formed of the first layer 131Fa and the second layer 131Fb on the first layer 131Fa. The first layer 131Fa forming the second via conductor 140F and the first layer 31Fa forming the first conductor layer 30F are similar. The second layer 131Fb forming the second via conductor 140F and the second layer 31Fb forming the first conductor layer 30F are similar. Electrolytic plating layer 130Fb forming second via conductor 140F and electrolytic plating layer 30Fb forming first conductor layer 30F are similar. First layer 131Fa forming second via conductor 140F and first layer 131Fa forming second conductor layer 130F are common. Second layer 131Fb forming second via conductor 140F and second layer 131Fb forming second conductor layer 130F are common. Electrolytic plating layer 130Fb forming second via conductor 140F and electrolytic plating layer 130Fb forming second conductor layer 130F are common.

[0036] The back-side buildup layer 300B has a back-side resin insulating layer, a back-side conductor layer, and a back-side via conductor penetrating the back-side resin insulating layer. The back-side resin insulating layer and the back-side conductor layer are alternately laminated. The back-side conductor layer and the back-side via conductor are electrically connected to the through-hole conductor 8. The back-side resin insulating layer in FIG. 1 is the first resin insulating layer 20B having the first surface 22B and the second surface 24B, and the second resin insulating layer 120B having the first surface 122B and the second surface 124B. The back-side conductor layer is the first conductor layer 30B and the second conductor layer 130B. The first conductor layer 30B and the second conductor layer 130B include the first signal wiring 32B, 132B and the second signal wiring 34B, 134B. The back-side via conductor is the first via conductor 40B and the second via conductor 140B.

[0037] The front-side buildup layer 300F and the rear-side buildup layer 300B are similar. Therefore, the front-side resin insulation layer forming the front-side buildup layer 300F and the rear-side resin insulation layer forming the rear-side buildup layer 300B are similar. Each rear-side resin insulation layer is formed of resin 80 and inorganic particles 90. Each rear-side resin insulation layer includes first inorganic particles 91, second inorganic particles 92, and third inorganic particles 93. The first surface of each resin insulation layer is formed of the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The front-side conductor layer and the rear-side conductor layer are similar. The openings for the front-side via conductors and the openings for the rear-side via conductors are similar. The inner wall surface of each opening for the via conductor is formed of the surface (exposed surface) 80a of the resin 80 and the exposed surface 93b of the inorganic particles. The surface 80a of the resin 80 and the exposed surface 93b of the inorganic particles form an almost common surface. The front side via conductors and the back side via conductors are similar.

[0038] The length of each side of the wiring board 2 is 50 mm or more. The length of each side is preferably 100 mm or more. The length of each side is 250 mm or less. The length of the signal wiring formed according to the embodiment is 5 mm or more. The length of the signal wiring may be 10 mm or more and 20 mm or less.

[0039] [Method of Manufacturing Wiring Board 2 of the Embodiment] 5A to 5M show a method for manufacturing the wiring board 2 of the embodiment. FIGS. 5A to 5G, 5I, 5K, and 5M are cross-sectional views. FIGS. 5H, 5J, and 5L are enlarged cross-sectional views. FIG. 5A shows a glass substrate 4. The substrate 4 has a front surface 5F and a back surface 5B. As shown in FIG. 5B, a through hole 6 is formed from the front surface 5F to the back surface 5B. The through hole 6 penetrates the substrate 4. A laser beam is irradiated from the front surface 5F side of the substrate 4. The substrate 4 is then immersed in hydrofluoric acid. The through hole 6 is formed.

[0040] 5C, the seed layer 10a is formed. The seed layer 10a is formed by electroless plating. The seed layer 10a is formed on the inner wall surface of the through hole 6, on the front surface 5F, and on the back surface 5B.

[0041] 5D, an electrolytic plating layer 10b is formed on the seed layer 10a. The electrolytic plating layer 10b fills the through holes 6.

[0042] As shown in FIG. 5E, the electrolytic plating layer 10b and seed layer 10a on the front surface 5F are removed by polishing. The electrolytic plating layer 10b and seed layer 10a on the back surface 5B are removed by polishing. The front surface 5F and back surface 5B of the substrate 4 are exposed. The through-hole conductor 8 is formed by the seed layer 10a on the inner wall surface of the through hole 6 and the electrolytic plating layer 10b on the seed layer 10a. The upper end 8F of the through-hole conductor 8 is exposed from the front surface 5F. The lower end 8B of the through-hole conductor 8 is exposed from the back surface 5B. The surface forming the upper end 8F and the front surface 5F form the same plane. The surface forming the lower end 8B and the back surface 5B form the same plane. The core substrate 3 is formed. The core substrate 3 does not have a conductive circuit on the front surface 5F. The core substrate 3 does not have a conductive circuit on the back surface 5B.

[0043] The front-side buildup layer 300F and the back-side buildup layer 300B are formed in a similar manner on the core substrate 3. The method of forming the front-side buildup layer 300F is shown below. The back-side buildup layer 300B is also shown in the figure.

[0044] As shown in FIG. 5F, the first resin insulating layer 20F and the protective film 50F are formed on the surface 5F and the upper end 8F of the substrate 4. The second surface 24F of the first resin insulating layer 20F faces the surface 5F of the substrate 4. The protective film 50F is formed on the first surface 22F of the first resin insulating layer 20F. The first resin insulating layer 20F has a resin 80 and inorganic particles (second inorganic particles 92) 90. The inorganic particles 90 are embedded in the resin 80. The first surface 22F of the first resin insulating layer 20F is formed only with the resin 80. The inorganic particles 90 are not exposed from the first surface 22F. The first surface 22F does not include the surfaces of the inorganic particles 90. The first surface 22F of the first resin insulating layer 20F does not have any unevenness. The first resin insulating layer 20F is formed on a plane formed by the surface 5F and the upper end 8F. Therefore, the first surface 22F is formed as a substantially flat surface. The surface 5F and the first surface 22F are substantially parallel to each other.

[0045] As shown in FIG. 5G, laser light L is irradiated from above protective film 50F. Laser light L penetrates protective film 50F and first resin insulating layer 20F at the same time. A first opening 26F for a via conductor is formed, which reaches an upper end 8F of through-hole conductor 8. Laser light L is, for example, UV laser light or CO2 laser light. The upper end 8F of through-hole conductor 8 is exposed by first opening 26F. When first opening 26F is formed, first surface 22F is covered with protective film 50F. Even if resin scatters when first opening 26F is formed, adhesion of resin to first surface 22F is suppressed.

[0046] The first surface 22F has excellent flatness. When the laser light L is irradiated to the first surface 22F, the laser light L is unlikely to be diffusely reflected. When each first opening 26F is formed, the focal position of the laser light L is likely to coincide. The embodiment can form an opening for a via conductor having a small diameter. The diameters of the openings for each via conductor are approximately equal. For example, the embodiment can form an opening for a via conductor having a diameter of 15 μm or more and 35 μm or less. The size of the diameter is measured on the first surface 22F.

[0047] FIG. 5H shows the inner wall surface 27Fb of the first opening 26F after the laser light irradiation. The inner wall surface 27Fb is formed of the resin 80 and the inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 27Fb after the laser light irradiation is treated. It is preferable to selectively remove the inorganic particles 90 protruding from the resin 80. As a result, the third inorganic particles 93 are formed from the inorganic particles 90. For example, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 27Fb after the laser light irradiation with a chemical. Alternatively, the inorganic particles 90 protruding from the resin 80 are selectively removed by treating the inner wall surface 27Fb after the laser light irradiation with plasma. The selective removal includes that the etching rate of the inorganic particles 90 is higher than the etching rate of the resin 80. For example, the difference in etching rate between the two is 10 times or more. Alternatively, the difference in etching rate between the two is 50 times or more. Alternatively, the difference in etching rate between the two is 100 times or more. By processing the inner wall surface 27Fb after the laser beam irradiation, the third inorganic particles 93 having the flat portion 93a are obtained. By controlling the conditions for processing the inner wall surface 27Fb after the laser beam irradiation, the embodiment can control the shape of the inner wall surface 27F. Examples of the conditions are temperature, concentration, time, and type and pressure of gas. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.

[0048] By irradiating the first resin insulating layer 20F with the laser light L, a part of the second inorganic particles 92 buried in the resin 80 forms the inner wall surface 27Fb after the laser light irradiation. The second inorganic particles 92 forming the inner wall surface 27Fb after the laser light irradiation are formed by a protruding portion P protruding from the resin 80 and a portion E buried in the resin 80. The inorganic particles having the protruding portion P are called protruding particles. For example, the protruding portion P is not removed at all for the protruding particles. The inner wall surface 27Fb after the laser light irradiation is treated. For example, the inner wall surface 27Fb is treated with plasma of a gas containing tetrafluoromethane. The protruding portion P is selectively removed to form the inner wall surface 27F of the embodiment. The third inorganic particles 93 are formed from the second inorganic particles 92. The third inorganic particles 93 having a flat portion 93a are formed by selectively removing the protruding portion P. The flat portion 93a is a flat surface. When the second inorganic particles 92 having a spherical shape are cut by a flat surface, the shape of the third inorganic particles 93 is obtained. The shape of the third inorganic particle 93 is substantially a spherical indentation. The inner wall surface 27F is formed by the flat portion 93a and the surface 80a of the resin 80, and the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on approximately the same plane. As shown in FIG. 4, a step 28 is formed at the boundary between the surface 80a of the resin 80 forming the inner wall surface 27F and the flat portion 93a of the third inorganic particle 93. For example, when the seed layer 30Fa is formed on the inner wall surface 27Fb by sputtering, the protruding portion P inhibits the growth of the sputtered film (sputtering film formation). For example, the seed layer 30Fa that is continuous on the inner wall surface 27Fb is not formed. Alternatively, it is necessary to increase the thickness of the seed layer 30Fa. If the printed wiring board contains protruding particles, it is considered difficult to form a fine conductor circuit. In the embodiment, the protruding portion P is removed. In the embodiment, the thickness of the seed layer 30Fa formed by sputtering can be reduced. Even if the seed layer 30Fa formed by sputtering is thin, a continuous seed layer 30Fa can be obtained. When the step 28 exists, the resin surface 80a is preferably recessed from the exposed surface 93b of the flat portion 93a. The resin surface 80a may protrude from the exposed surface 93b of the flat portion 93a. The size of the unevenness and the size of the step 28 can be controlled by controlling the conditions for processing the inner wall surface 27Fb after the laser light irradiation.

[0049] Forming the first opening 26F includes forming inorganic particles (second inorganic particles 92) 90 having protruding portions P. The protruding portions P protrude from the resin 80 forming the inner wall surface 27Fb of the first opening 26F. The third inorganic particles 93 are formed by removing the protruding portions P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 27F of the first opening 26F includes exposed surfaces 93b of the third inorganic particles 93. The exposed surfaces 93b of the third inorganic particles 93 are formed by removing the protruding portions P.

[0050] Obtaining the shape of the third inorganic particle 93 by cutting the spherical second inorganic particle 92 on a plane includes removing the protruding portion P of the inorganic particle 90. The actual inner wall surface 27F of the first opening 26F is a substantially curved surface. Since the flat portion 93a is formed by removing the protruding portion P, the exposed surface 93b of the flat portion 93a includes a curved surface. In other words, forming a common surface between the flat portion 93a and the resin 80 includes forming the inner wall surface 27F that is substantially formed as a curved surface.

[0051] The inside of the first opening 26F is cleaned. By cleaning the inside of the first opening 26F, resin residue generated when the first opening 26F is formed is removed. The inside of the first opening 26F is cleaned by plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmear process.

[0052] When the inside of first opening 26F is cleaned, first surface 22F of first resin insulating layer 20F is covered with protective film 50F. First surface 22F is not affected by plasma. First surface 22F is formed only of resin 80. Inorganic particles 90 are not exposed from first surface 22F. First surface 22F does not include the surfaces of inorganic particles 90. First surface 22F of first resin insulating layer 20F does not have irregularities. First surface 22F is formed smoothly.

[0053] When processing the inner wall surface 27Fb after the laser light irradiation includes cleaning the inside of the first opening 26F, the embodiment can omit cleaning the inside of the first opening 26F.

[0054] As shown in FIG. 5I, after cleaning the inside of the first opening 26F, the protective film 50F is removed from the first resin insulating layer 20F. When processing the inner wall surface 27Fb after the laser light irradiation includes cleaning the inside of the first opening 26F, the protective film 50F is removed from the first resin insulating layer 20F after processing the inner wall surface 27Fb after the laser light irradiation. When the inner wall surface 27Fb after the laser light irradiation is processed, the protective film 50F covers the first surface 22F of the first resin insulating layer 20F. After removing the protective film 50F, the first surface 22F of the first resin insulating layer 20F is not roughened.

[0055] After removing the protective film 50F, the first surface 22F of the first resin insulating layer 20F is cleaned. The resin 80 forming the first surface 22F is removed by a dry process. For example, the first surface 22F of the first resin insulating layer 20F is cleaned by reverse sputtering. For example, cleaning the first surface 22F of the first resin insulating layer 20F is performed by sputtering using argon gas (argon sputtering). Figures 5J(a) and (b) show the first surface 22F of the first resin insulating layer 20F before and after cleaning. As shown in Figures 5J(a) and (b), the resin 80 forming the first resin insulating layer 20F is removed by about 20 nm by cleaning by sputtering or the like. For example, the adhesive for bonding the protective film 50F to the first resin insulating layer 20F is removed. The resin 80 is selectively removed by cleaning. The thickness of the resin 80 becomes thinner. A part of the inorganic particles (second inorganic particles 92) 90 is partially exposed from the upper surface of the resin 80 by washing. The first inorganic particles 91 are obtained by exposing the second inorganic particles 92 buried in the resin 80 from the upper surface of the resin 80. The first inorganic particles 91 are formed from the second inorganic particles 92. The first inorganic particles 91 and the second inorganic particles 92 have the same shape. Both are spherical. As shown in FIG. 5J(b), the first inorganic particles 91 are formed of a first portion 91a protruding from the resin 80 and a second portion 91b buried in the resin 80. The first surface 22F of the first resin insulating layer 20F is formed of the upper surface 80R of the resin 80 and an exposed surface 91aR of the first portion 91a protruding from the upper surface 80R of the resin 80. The exposed surface 91aR of the first portion 91a is exposed by washing. The first surface 22F of the first resin insulating layer 20F is not roughened. Therefore, almost no recesses are formed on first surface 22F. First surface 22F has almost no recesses. Top surface 80R of resin 80 is almost flat. Top surface 80R of resin 80 has no recesses.

[0056] The ratio R is calculated, for example, using a cross-sectional view of the first inorganic particle 91 shown in FIG. 5J(b). FIG. 5J(b) is obtained by cutting the first resin insulating layer 20F on a plane perpendicular to the upper surface 80R. The first conductor layer 30F is omitted in FIG. 5J(b). The first conductor layer 30F is formed on the first inorganic particle 91 in FIG. 5J(b). The exposed surface 91aR in FIG. 5J(b) is covered with the first conductor layer 30F. Using FIG. 5J(b), the cross-sectional area 91aS of the first portion 91a is obtained. Similarly, the cross-sectional area 91S of the first inorganic particle 91 is obtained. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (cross-sectional area 91aS of the first portion 91a / cross-sectional area 91S of the first inorganic particle 91). For example, when the ratio R is evaluated, 50 first inorganic particles 91 are observed. Fifty of the first inorganic particles 91 satisfy the ratio R.

[0057] As shown in FIG. 5K, a seed layer 30Fa is formed on the first surface 22F of the first resin insulating layer 20F. The seed layer 30Fa is formed by sputtering. The seed layer 30Fa is formed by a dry process. The seed layer 30Fa is also formed on the upper end 8F of the through-hole conductor 8 exposed from the first opening 26F and on the inner wall surface 27F of the first opening 26F. The seed layer 30Fa is mainly made of copper. The first layer 31Fa is formed on the first surface 22F by sputtering. The first layer 31Fa is formed on the inner wall surface 27F exposed from the first opening 26F and on the upper end 8F of the through-hole conductor 8 by sputtering. The second layer 31Fb is formed on the first layer 31Fa by sputtering. The first layer 31Fa is formed of an alloy containing copper, aluminum, and a specific metal (e.g., silicon). The second layer 31Fb is formed of copper.

[0058] As shown in FIG. 5L, the first layer 31Fa formed on the inner wall surface 27F has a first film 60a and a second film 70a. The first film 60a and the second film 70a are formed simultaneously. The first film 60a and the second film 70a are electrically connected. The leading end 62a of the first film 60a is formed on the rear end 72a of the second film 70a. The cross section of the first layer 31Fa formed on the inner wall surface 27F has a substantially stepped shape. Examples of sputtering conditions are as follows. The distance between the target and the first surface 22F of the first resin insulating layer 20F is 50 mm or more and 250 mm or less. The voltage is 15 eV or more and 50 eV or less. The gas concentration is 0.1 Pa or more and 1.0 Pa or less.

[0059] The second layer 31Fb formed on the first layer 31Fa covering the inner wall surface 27F has a first film 60b and a second film 70b. The first film 60b and the second film 70b are formed simultaneously. The first film 60b and the second film 70b are electrically connected. The leading end 62b of the first film 60b is formed on the trailing end 72b of the second film 70b. The cross section of the second layer 31Fb formed on the inner wall surface 27F has a substantially stepped shape. The sputtering conditions are substantially the same as those described above.

[0060] In the embodiment, the inner wall surface 27F is formed by the surface 80a of the resin 80 and the exposed surface 93b of the third inorganic particle 93. Both of them form a substantially common surface. The surface 80a of the resin and the exposed surface 93b are formed of different materials. The first layer 31Fa is formed by sputtering. It is considered that the growth of the first layer 31Fa formed on the surface 80a of the resin 80 is different from the growth of the first layer 31Fa formed on the exposed surface 93b. It is considered that the growth of the seed layer 30Fa formed on the surface 80a of the resin 80 is different from the growth of the seed layer 30Fa formed on the exposed surface 93b. Therefore, in the embodiment, it is considered that the first film 60a and the second film 70a are formed. It is considered that the leading end 62a of the first film 60a is formed on the rear end 72a of the second film 70a. It is considered that the cross section of the first layer 31Fa has a substantially stepped shape. It is considered that the second layer 31Fb follows the first layer 31Fa. Therefore, the second layer 31Fb is considered to have a first film 60b and a second film 70b. The leading end 62b of the first film 60b of the second layer 31Fb is considered to be formed on the rear end 72b of the second film 70b of the second layer 31Fb. The cross section of the second layer 31Fb is considered to have a substantially stepped shape. Similarly, the seed layer 30Fa is considered to have a first film 60 and a second film 70. The leading end 62 of the first film 60 of the seed layer 30Fa is considered to be formed on the rear end 72 of the second film 70 of the seed layer 30Fa. The cross section of the seed layer 30Fa is considered to have a substantially stepped shape.

[0061] When the inner wall surface 27F has the step 28 shown in FIG. 4, the first layer 31Fa having the first film 60a and the second film 70a can be easily formed by sputtering. In the embodiment, the seed layer 30Fa having the first film 60 and the second film 70 can be easily formed. In the embodiment, the leading end 62a of the first film 60a can be formed on the trailing end 72a of the second film 70a. In the embodiment, the leading end 62 of the first film 60 can be formed on the trailing end 72 of the second film 70. In the embodiment, the first layer 31Fa having a substantially stepped shape can be easily formed. In the embodiment, the seed layer 30Fa having a substantially stepped shape can be easily formed.

[0062] The first layer 31Fa on the inner wall surface 27F is formed on the substantially smooth inner wall surface 27F. Therefore, in the embodiment, the surface of the first film 60a of the first layer 31Fa and the surface of the second film 70a of the first layer 31Fa can be formed substantially smooth. Similarly, the surface of the first film 60b of the second layer 31Fb and the surface of the second film 70b of the second layer 31Fb can be formed substantially smooth. The surface of the first film 60 of the seed layer 30Fa and the surface of the second film 70 of the seed layer 30Fa can be formed substantially smooth. Since the surfaces are smooth, the embodiment can reduce transmission loss.

[0063] The first layer 31Fa of the seed layer 30Fa is formed of an alloy containing copper and aluminum. Aluminum has high ductility and high malleability. Therefore, the adhesion between the first resin insulating layer 20F and the first layer 31Fa is high. Even if the first resin insulating layer 20F expands and contracts due to heat cycles, it is considered that the seed layer 30Fa containing aluminum can follow the expansion and contraction. Even if the first surface 22F is smooth, the seed layer 30Fa is difficult to peel off from the first resin insulating layer 20F. It is considered that aluminum is easily oxidized. If the third inorganic particles 93 are inorganic particles 90 containing oxygen (oxygen element), it is considered that the first layer 31Fa formed on the inner wall surface 27F of the first opening 26F adheres to the third inorganic particles 93 via the oxygen in the inorganic particles 90 forming the inner wall surface 27F. The first layer 31Fa and the inner wall surface 27F are strongly bonded. The embodiment can increase the adhesion between the inner wall surface 27F of the first opening 26F and the first layer 31Fa. The seed layer 30Fa is unlikely to peel off from the inner wall surface 27F. The inorganic particles 90 forming the inner wall surface 27F preferably contain oxygen elements. When the third inorganic particles 93 are glass particles and the first layer 31Fa further contains silicon, both contain silicon. In this case, the first layer 31Fa is formed of an alloy containing copper, aluminum, and silicon. It is believed that the two are strongly bonded via silicon. Therefore, it is believed that the adhesive strength between the first layer 31Fa and the third inorganic particles 93 is further improved.

[0064] The first surface 22F has excellent flatness. When the seed layer 30Fa is formed on the first surface 22F by sputtering, the distance between the target and the first surface 22F is almost constant. In the embodiment, the seed layer 30Fa having a nearly uniform thickness can be formed.

[0065] The first layer 31Fa of the seed layer 30Fa contacts the exposed surface 91aR of the first portion 91a of the first inorganic particles 91 forming the first surface 22F of the first resin insulating layer 20F. When the first layer 31Fa contains aluminum and the first inorganic particles 91 contain oxygen, it is considered that the adhesive strength between the first layer 31Fa and the first inorganic particles 91 is improved. Examples of inorganic particles (such as the first inorganic particles) 90 containing oxygen are glass particles and alumina particles. Therefore, when the first layer 31Fa is formed of an alloy containing copper and aluminum, the first layer 31Fa is unlikely to peel off from the first resin insulating layer 20F even if the first surface 22F of the first resin insulating layer 20F has almost no recesses. The amount of aluminum in the first layer 31Fa is 1.0 at% or more and 15.0 at% or less. When the inorganic particles including the first inorganic particles 91 (the first inorganic particles 91, the second inorganic particles 92, and the third inorganic particles 93) are glass particles and the first layer 31Fa further includes silicon, both of them include silicon. In this case, the first layer 31Fa is formed of an alloy including copper, aluminum, and silicon. The amount of silicon is 0.5 at% or more and 10.0 at% or less. It is considered that the two are strongly bonded via silicon. Therefore, it is considered that the adhesive force between the first layer 31Fa and the inorganic particles including the first inorganic particles 91 is further improved. In the embodiment, fine first signal wiring 32F and second signal wiring 34F can be formed. The width of the fine first signal wiring 32F and second signal wiring 34F is 1 μm or more and 3 μm or less. Even if the wiring board 2 having the fine first signal wiring 32F and second signal wiring 34F is subjected to a thermal shock, the first signal wiring 32F and the second signal wiring 34F are unlikely to peel off from the first resin insulating layer 20F.

[0066] A plating resist is formed on the seed layer 30Fa. The plating resist has openings for forming the first signal wiring 32F, the second signal wiring 34F, and the land 36F. If the first surface 22F has a recess, air due to the recess is likely to be trapped between the plating resist and the seed layer 30Fa. However, in the embodiment, the first surface 22F has almost no recess. Therefore, the seed layer 30Fa on the first surface 22F is formed almost flat. The seed layer 30Fa has almost no recess. Air is unlikely to remain between the plating resist and the seed layer 30Fa. The contact area between the plating resist and the seed layer 30Fa is large. Even if the width of the plating resist for forming the space between the signal wirings is 10 μm or less, the plating resist is unlikely to peel off from the upper surface of the seed layer 30Fa. Even if the width of the plating resist is 3 μm or more and 8 μm or less, the embodiment can form the plating resist on the seed layer 30Fa. Even if the width of the plating resist is 6 μm or less, the plating resist is unlikely to peel off from the seed layer 30Fa.

[0067] An electrolytic plating layer 30Fb is formed on the seed layer 30Fa exposed from the plating resist. The electrolytic plating layer 30Fb fills the first opening 26F. The seed layer 30Fa and the electrolytic plating layer 30Fb on the first surface 22F form a first signal wiring 32F, a second signal wiring 34F, and a land 36F. The first conductor layer 30F is formed. The seed layer 30Fa and the electrolytic plating layer 30Fb in the first opening 26F form a first via conductor 40F. The first via conductor 40F connects the through-hole conductor 8 and the land 36F. The first signal wiring 32F and the second signal wiring 34F form a pair wiring.

[0068] The plating resist is removed. The seed layer 30Fa exposed from the electrolytic plating layer 30Fb is removed. As shown in FIG 5M, the first conductor layer 30F and the first via conductors 40F are simultaneously formed.

[0069] The second resin insulating layer (120F) is formed on the first surface (22F) of the first resin insulating layer (20F) and the first conductor layer (30F). The second conductor layer (130F) is formed on the first surface (122F) of the second resin insulating layer (120F). The second via conductor (140F) is formed in the second opening (126F) of the second resin insulating layer (120F). The second resin insulating layer (120F) is formed in the same manner as the first resin insulating layer (20F). The second conductor layer (130F) is formed in the same manner as the first conductor layer (30F). The second via conductor (140F) is formed in the same manner as the first via conductor (40F). The wiring board (2) of the embodiment is obtained.

[0070] The core substrate 3 of the wiring substrate 2 of the embodiment includes a substrate 4 made of glass. The substrate 4 made of glass has excellent flatness. The first surfaces 22F, 22B of the first resin insulating layers 20F, 20B have excellent flatness and smoothness. In the embodiment, fine signal wiring 32F, 32B, 34F, 34B can be formed on the first surfaces 22F, 22B of the first resin insulating layers 20F, 20B. The first surfaces 122F, 122B of the second resin insulating layers 120F, 120B are also similar to the first surfaces 22F, 22B of the first resin insulating layers 20F, 20B. Therefore, in the embodiment, fine signal wiring 132F, 132B, 134F, 134B can be formed on the first surfaces 122F, 122B of the second resin insulating layers 120F, 120B. The L / S of the signal wiring formed in the embodiment is, for example, less than 5 μm / 5 μm. The L / S of the signal wiring is preferably 1.5 μm / 1.5 μm or more and 3.5 μm / 3.5 μm or less, where L means the width of the signal wiring and S means the width of the space between adjacent signal wirings.

[0071] In the embodiment, the first layer formed on the inner wall surface of the opening for the via conductor is formed by sputtering. The resin insulating layer on the glass substrate 4 is not easily warped. Gaps that inhibit the growth of the sputtering film are not easily generated between the resin 80 forming the inner wall surface of the opening for the via conductor and the third inorganic particles 93. The inner wall surface of the opening is not easily wavy or has large irregularities. Even if the thickness of the sputtering film on the inner wall surface is thin, the embodiment can form a continuous sputtering film.

[0072] The inner wall surface of the opening (first opening, second opening) for the via conductor is formed by the resin 80 and the exposed surface 93b of the flat portion 93a of the third inorganic particles 93. When the first layer is formed, it is considered that the particles forming the sputtering film adhere to the third inorganic particles 93. It is considered that the particles forming the sputtering film are not buried in the third inorganic particles 93. The embodiment can form a thin and continuous seed layer on the inner wall surface. The embodiment can form a thin and continuous seed layer on the first surface and the inner wall surface. When the seed layer is removed, the amount of etching is small. Therefore, the amount of etching of the electrolytic plating layer is small. The signal wiring has a width as designed. The embodiment can form fine signal wiring. A wiring board 2 having high quality is provided.

[0073] In the wiring board 2 of the embodiment, the first surface 22F of the first resin insulating layer 20F is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The first surface 22F and the upper surface 80R have almost no recesses. Therefore, when the seed layer 30Fa is formed on the first resin insulating layer 20F by sputtering, the embodiment can form a continuous seed layer 30Fa even if the thickness of the sputtering film is thin. The seed layer 30Fa is formed thin. When the seed layer 30Fa is removed, the amount of etching is small. Therefore, the amount of etching of the electrolytic plating layer 30Fb is small. The signal wiring has a width according to the design value. Fine wiring is formed. A wiring board 2 having high quality is provided.

[0074] In the embodiment, the thickness of the first layer 31Fa made of an alloy containing copper and aluminum can be reduced. The aluminum content in the signal wiring is small, and the copper content is large. In the embodiment, a signal wiring having low resistance can be provided. In the embodiment, a signal wiring having high adhesion to a resin insulating layer can be provided.

[0075] In the wiring board 2 of the embodiment, the first surfaces 22F, 22B of the first resin insulating layers 20F, 20B have almost no recesses. The standard deviation of the relative dielectric constant of the first resin insulating layers 20F, 20B near the first surfaces 22F, 22B is suppressed from increasing. The relative dielectric constant of the first surfaces 22F, 22B does not vary greatly depending on the location. Even if the first signal wiring 32F, 32B and the second signal wiring 34F, 34B are in contact with the first surfaces 22F, 22B, the embodiment can reduce the difference in the propagation speed of the electric signal between the first signal wiring 32F, 32B and the second signal wiring 34F, 34B. Therefore, the wiring board 2 of the embodiment suppresses noise. Even if a logic IC is mounted on the wiring board 2 of the embodiment, data transmitted by the first signal wiring 32F, 32B and data transmitted by the second signal wiring 34F, 34B reach the logic IC with almost no delay. The embodiment can suppress malfunction of the logic IC. Even if the length of the first signal wiring 32F, 32B and the length of the second signal wiring 34F, 34B are 5 mm or more, the embodiment can reduce the difference in propagation speed between them. Even if the length of the first signal wiring 32F, 32B and the length of the second signal wiring 34F, 34B are 10 mm or more and 20 mm or less, the embodiment can suppress the malfunction of the logic IC. The first surfaces 122F, 122B of the second resin insulating layers 120F, 120B are also similar to the first surfaces 22F, 22B of the first resin insulating layers 20F, 20B. Therefore, the first signal wiring 132F, 132B and the second signal wiring 134F, 134B have the same effect as the first signal wiring 32F, 32B and the second signal wiring 34F, 34B. A wiring board 2 having high quality is provided.

[0076] In the embodiment, a part of the first film of the seed layer covering the inner wall surface of the opening (first opening, second opening) for the via conductor is formed on the second film. The first film and the second film are partially overlapped. Therefore, the strength of the seed layer is high. Since the thermal expansion coefficient of the glass core substrate 3 and the thermal expansion coefficient of the resin insulating layer are significantly different, when the wiring board 2 is subjected to a heat cycle, stress acts between the resin insulating layer and the seed layer. Even if the resin insulating layer expands and contracts due to the heat cycle, it is considered that the stress is alleviated by partially overlapping the first film and the second film. Alternatively, it is considered that the seed layer can follow the expansion and contraction. Therefore, the seed layer is unlikely to break. The seed layer is formed of a substantially smooth first film and a substantially smooth second film. Therefore, when a high-frequency signal is transmitted, the transmission loss is small. A high-quality wiring board 2 is provided.

[0077] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the third inorganic particles 93 on the inner wall surface contain silicon. The first layer and the first inorganic particles 91 on the first surface contain silicon. It is considered that the two are strongly bonded via silicon. The seed layer is difficult to peel off from the inner wall surface. The seed layer is difficult to peel off from the first surface. For this reason, it is preferable that the first layer is an alloy containing copper, aluminum, and silicon.

[0078] When the first layer contains aluminum and the inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90 contain oxygen, it is believed that the first layer and the inorganic particles (inorganic particles containing oxygen, such as glass particles) 90 are strongly bonded. When the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer does not need to contain the specific metal. In this case, the first layer is formed of copper, aluminum, and impurities.

[0079] [Example 1 of the embodiment] In another embodiment, the specific metal contained in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.

[0080] [Another Example 2 of the embodiment] In another embodiment, the alloy forming the first layer does not contain carbon.

[0081] [Example 3 of the embodiment] In another embodiment, the alloy forming the first layer does not contain oxygen.

[0082] [Modifications of the embodiment] The wiring board of the modified example has a core substrate 3, a front side buildup layer 300F, and a rear side buildup layer 300B, similar to the embodiment. The core substrate 3 of the embodiment and the core substrate 3 of the modified example are different. The front side buildup layer 300F of the embodiment and the front side buildup layer 300F of the modified example are similar. The rear side buildup layer 300B of the embodiment and the rear side buildup layer 300B of the modified example are similar. A cross section of the core substrate 3 of the modified example is shown in FIG. 6 and FIG. 7. As shown in FIG. 6 and FIG. 7, the core substrate 3 of the modified example has conductor layers 10F, 11F on the front side 5F of the glass substrate 4. The conductor layers 10F, 11F include lands 14F covering the upper ends 8F of the through-hole conductors 8. Furthermore, the core substrate 3 of the modified example has conductor layers 10B, 11B on the rear side 5B of the substrate 4. The conductor layers 10B, 11B include lands 14B covering the lower ends 8B of the through-hole conductors 8. Land 14F and land 14B are electrically connected by a through-hole conductor 8. Core substrate 3 of the embodiment does not have a conductor layer on front surface 5F and a conductor layer on back surface 5B.

[0083] In the modified example, the resin insulating layer on the front side (resin insulating layer directly above the core substrate) forming the front buildup layer 300F is formed on the conductor layers 10F and 11F and the front surface 5F. The resin insulating layer (first resin insulating layer 20F) directly above the core substrate has an opening (first opening 26F) for a via conductor that reaches the land 14F. A via conductor (first via conductor 40F) similar to that of the embodiment is formed in the opening for the via conductor. The via conductor that penetrates the resin insulating layer directly above the core substrate reaches the land 14F, so the seed layer (first layer 31Fa) that forms the via conductor is in contact with the upper surface of the land 14F and the inner wall surface of the opening. The via conductor that penetrates the resin insulating layer directly above the core substrate is electrically connected to the through-hole conductor 8 via the land 14F.

[0084] In the modified example, the back-side resin insulation layer (resin insulation layer directly below the core substrate) forming the back-side buildup layer 300B is formed on the conductor layers 10B and 11B and the back surface 5B. The resin insulation layer (first resin insulation layer 20B) directly below the core substrate has an opening (first opening) for a via conductor that reaches the land 14B. A via conductor (first via conductor 40B) similar to that of the embodiment is formed in the opening for the via conductor. The via conductor that penetrates the resin insulation layer directly below the core substrate reaches the land 14B, so that the seed layer that forms the via conductor is in contact with the upper surface of the land 14B and the inner wall surface of the opening. The via conductor that penetrates the resin insulation layer directly below the core substrate is electrically connected to the through-hole conductor 8 via the land 14B.

[0085] [Modified Example of Manufacturing Method of Wiring Board] The core substrate 3 shown in FIG. 6 is a first example of the core substrate 3. A method for manufacturing the first example of the core substrate 3 is described below. An intermediate substrate shown in FIG. 5D is prepared. A conductor layer 10F is formed on the front surface 5F by a subtractive method. A conductor layer 10B is formed on the back surface 5B. A core substrate 3 according to the first example of the modified example is obtained.

[0086] The conductor layer 10F is formed of a seed layer 10a and an electrolytic plating layer 10b on the seed layer 10a. The conductor layer 10B is formed of a seed layer 10a and an electrolytic plating layer 10b on the seed layer 10a. The seed layer 10a is formed by electroless plating. The seed layer 10a forming the conductor layer 10F, the seed layer 10a forming the conductor layer 10B, and the seed layer 10a forming the through-hole conductor 8 are common. The electrolytic plating layer 10b forming the conductor layer 10F, the electrolytic plating layer 10b forming the conductor layer 10B, and the electrolytic plating layer 10b forming the through-hole conductor 8 are common. The conductor layers 10F, 10B, and the through-hole conductor 8 are formed simultaneously. The through-hole conductor 8 and the lands 14F, 14B are formed simultaneously. The through-hole conductor 8 and the lands 14F, 14B are formed integrally. There is no seed layer between the upper end 8F and the land 14F. There is no seed layer between the lower end 8B and the land 14B.

[0087] The core substrate 3 shown in FIG. 7 is a core substrate 3 of the second example. The manufacturing method of the core substrate 3 of the second example is shown below. An intermediate substrate shown in FIG. 5E is prepared. Seed layers 11Fa, 11Ba are formed on the front surface 5F and the back surface 5B. The seed layers 11Fa, 11Ba are formed by electroless plating. The seed layers 11Fa, 11Ba may be formed by sputtering. The seed layer 11Fa covers the front surface 5F of the substrate 4 and the upper end 8F of the through-hole conductor 8. The seed layer 11Ba covers the back surface 5B of the substrate 4 and the lower end 8B of the through-hole conductor 8. Electrolytic plating layers 11Fb, 11Bb are formed on the seed layers 11Fa, 11Ba. Then, conductor layers 11F, 11B are formed by a subtractive method. A core substrate 3 according to the second example of the modified example is obtained.

[0088] The conductor layer 11F is formed of a seed layer 11Fa and an electrolytic plating layer 11Fb on the seed layer 11Fa. The conductor layer 11B is formed of a seed layer 11Ba and an electrolytic plating layer 11Bb on the seed layer 11Ba. The seed layer 11Fa is formed on the front surface 5F of the substrate 4. The seed layer 11Fa covers the upper end 8F of the through-hole conductor 8. The seed layer 11Ba is formed on the back surface 5B of the substrate 4. The seed layer 11Ba covers the lower end 8B of the through-hole conductor 8. The seed layers 11Fa and 11Ba are formed by electroless plating. The seed layers 11Fa and 11Ba may be formed by sputtering. The seed layers 11Fa and 11Ba forming the conductor layers 11F and 11B are different from the seed layer 10a forming the through-hole conductor 8. The electrolytic plating layers 11Fb and 11Bb forming the conductor layers 11F and 11B are different from the electrolytic plating layer 10b forming the through-hole conductor 8. Conductor layers 11F, 11B and through-hole conductor 8 are formed separately. In the second example, seed layer 11Fa forming land 14F is present between electrolytic plating layer 10b forming upper end 8F and electrolytic plating layer 11Fb forming land 14F. Seed layer 11Ba forming land 14B is present between electrolytic plating layer 10b forming lower end 8B and electrolytic plating layer 11Bb forming land 14B. In contrast, in the first example (FIG. 6), electrolytic plating layer 10b forming upper end 8F and electrolytic plating layer 10b forming land 14F are continuous. Electrolytic plating layer 10b forming lower end 8B and electrolytic plating layer 10b forming land 14B are continuous.

[0089] On the core substrate 3 of the modified example, a front-side buildup layer 300F and a back-side buildup layer 300B are formed in the same manner as in the embodiment.

[0090] In this specification, the term "plane" is used for the shape of the inner wall surface, the shape of the flat portion 93a, and the shape of the third inorganic particle 93. The meaning of the plane used for these is shown in FIG. 1 and FIG. 3A. That is, in FIG. 1 and FIG. 3A, the inner wall surface is drawn almost straight. The shape of the inner wall surface in FIG. 1 and FIG. 3A is almost straight. The plane in this specification includes a substantially straight line shown in a cross section. As shown in the cross section of the third inorganic particle 93 in FIG. 1 and FIG. 3A, in a cross section, cutting with a plane includes cutting with a straight line. The plane in this specification does not mean a perfect plane but includes a substantially flat plane. The substantially flat plane may include small irregularities. [Explanation of symbols]

[0091] 2: Wiring board 3: Core board 4: Substrate 5F: Surface 5B: Back 6:Through hole 8:Through hole conductor 10F, 10B: Conductive layer 11F, 11B: Conductive layer 14F, 14B: Land 20F, 20B: First resin insulating layer 22F, 22B: 1st page 24F, 24B: 2nd side 26F: 1st opening 27F: Inner wall 30F, 30B: first conductor layer 30Fa: seed layer 30Fb: Electrolytic plating layer 32F, 32B: 1st signal wiring 34F, 34B: 2nd signal wiring 36F: Land 40F, 40B: first via conductor 60, 60a, 60b: first film 62, 62a, 62b: Tip 70, 70a, 70b: Second film 72, 72a, 72b: Rear end 80: Resin 90: Inorganic particles 91: 1st inorganic particle 92:Second inorganic particle 93:Third inorganic particle 93a: Flat part 93b: Exposed surface 120F, 120B: second resin insulating layer 122F, 122B: 1st page 124F, 124B: 2nd side 126F: 2nd opening 127F: Inner wall 130F, 130B: second conductor layer 130Fa: seed layer 130Fb: Electrolytic plating layer 132F, 132B: First signal wiring 134F, 134B: Second signal wiring 136F: Land 140F, 140B: second via conductor 300F: Surface build-up layer 300B: Backside build-up layer

Claims

1. a core substrate having a glass substrate, a through hole penetrating the substrate, and a through hole conductor formed in the through hole; a resin insulating layer formed on the core substrate, the resin insulating layer having a first surface, a second surface opposite to the first surface, and an opening for a via conductor extending from the first surface to the second surface; a first conductor layer formed on the first surface of the resin insulating layer; a via conductor formed in the opening and electrically connected to the through-hole conductor, the first conductor layer and the via conductor are formed by a seed layer and an electrolytic plating layer formed on the seed layer, the seed layer being formed by sputtering; The resin insulation layer is formed of resin and inorganic particles, the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles embedded in the resin, the first inorganic particles are formed of a first portion protruding from the resin and a second portion embedded in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface.

2. 2. The wiring board according to claim 1, wherein a ratio of a volume of the first portion to a volume of the first inorganic particles is greater than 0 and is equal to or smaller than 0.

4.

3. 2. The wiring board according to claim 1, wherein the inorganic particles are glass particles.

4. A wiring board according to claim 1, wherein the inorganic particles further include third inorganic particles forming an inner wall surface of the opening, the inner wall surface being formed by the third inorganic particles and the resin, the third inorganic particles having a flat portion, and the flat portion forming the inner wall surface.

5. 5. The wiring board according to claim 4, wherein the flat portion and a surface of the resin forming the inner wall surface form a substantially common surface.

6. 5. The wiring board according to claim 4, wherein the second inorganic particles have a spherical shape, and the shape of the third inorganic particles is obtained by cutting the second inorganic particles along a plane.

7. A wiring board according to claim 4, wherein forming the opening includes forming the inorganic particles having protruding portions protruding from the resin forming the inner wall surface of the opening, and the third inorganic particles are formed by removing the protruding portions of the inorganic particles.

8. A wiring board according to claim 4, wherein forming the opening includes forming an inorganic particle having a protruding portion from the second inorganic particle, and the inner wall surface of the opening includes an exposed surface of the third inorganic particle formed by removing the protruding portion.

9. 2. The wiring board according to claim 1, wherein the inorganic particles contain oxygen elements.

10. 2. The wiring board of claim 1, wherein the seed layer has a first layer and a second layer formed on the first layer, the first layer being made of an alloy containing copper and aluminum.

11. 11. The wiring board of claim 10, wherein the alloy further comprises silicon.

12. 2. The wiring board of claim 1, wherein the seed layer covering the inner wall surface of the opening has a substantially smooth first film and a substantially smooth second film, the first film and the second film are electrically connected, and a portion of the first film is formed on the second film.

13. 13. The wiring board according to claim 12, wherein a leading end of the first film is formed on a trailing end of the second film.

14. 13. The wiring board according to claim 12, wherein the first film and the second film are formed simultaneously.

15. 13. The wiring board according to claim 12, wherein the cross section of the seed layer covering the inner wall surface has a substantially stepped shape.

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