Wiring board, semiconductor device, and manufacturing method of the wiring board

Abstract

To provide a wiring board capable of suppressing deterioration of a connection reliability.SOLUTION: A wiring board 20 includes: a wiring layer 62; an insulation layer 63 that covers the wiring layer 62; and a wiring layer 64 that is formed onto an upper surface of the insulation layer 63, and is electrically connected to the wiring layer 62. The wiring board 20 includes: an insulation layer 65 that is formed onto the upper surface of the insulation layer 63; and a wiring layer 66 that is formed onto the upper surface of the insulation layer 65, and is electrically connected to the wiring layer 64. The wiring layer 64 includes: a first connection pad P1 connected to a first electron component 71; and a wiring pattern 64A electrically connected to the wiring layer 66. The insulation layer 65 includes an open part 65X penetrating the insulation layer 65 in a thickness direction and exposing the first connection pad P1 and one part of the upper surface of the insulation layer 63. The wiring layer 66 includes a second connection pad P2 connected to a second electron component 72. The wiring layer 62 includes wiring 62A that electrically connects the first connection pad P1 and the second connection pad P2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, semiconductor devices having a plurality of electronic components mounted on a wiring board are known (see, for example, Patent Document 1). In this type of semiconductor device, an underfill material is filled between the wiring board and the electronic components to protect the connection between the wiring board and the electronic components from external stress and the like, thereby improving the connection reliability at the connection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-107681 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when multiple electronic components are densely mounted on a wiring board, the underfill material is likely to unintentionally flow into the gaps between the other electronic components and the wiring board. This may result in a shortage or excess of underfill material. In this case, the underfill material cannot be filled evenly, and the connection reliability between the wiring board and the electronic components may decrease. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer formed on an upper surface of the first insulating layer and electrically connected to the first wiring layer, a second insulating layer formed on the upper surface of the first insulating layer, and a third wiring layer formed on the upper surface of the second insulating layer and electrically connected to the second wiring layer, wherein the second wiring layer has a first connection pad connected to a first electronic component and a wiring pattern electrically connected to the third wiring layer, the second insulating layer has an opening that penetrates the second insulating layer in a thickness direction and exposes the first connection pad and a portion of the upper surface of the first insulating layer, the third wiring layer has a second connection pad connected to a second electronic component different from the first electronic component, and the first wiring layer has wiring that electrically connects the first connection pad and the second connection pad. Effect of the Invention

[0006] Advantageous Effects of Invention According to one aspect of the present invention, an effect is achieved in that a decrease in connection reliability can be suppressed. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment will be described with reference to the accompanying drawings. In the attached drawings, for convenience, characteristic parts may be shown enlarged to make the features easier to understand, and the dimensional ratios of each component may differ from one drawing to another. In addition, in the cross-sectional views, in order to make the cross-sectional structure of each component easier to understand, the hatching of some components is shown as a matte finish, and the hatching of some components is omitted.

[0009] (Overall Configuration of Semiconductor Device 10) As shown in FIG. 1, the semiconductor device 10 includes a wiring substrate 20, a plurality of electronic components, in this embodiment a first electronic component 71 and a second electronic component 72, underfill materials 81 and 82, and an external connection terminal 90.

[0010] (Structure of wiring board 20) The wiring board 20 has a wiring structure 21, a wiring structure 22 formed on the upper surface of the wiring structure 21, a solder resist layer 23 laminated on the upper surface of the wiring structure 22, and a solder resist layer 24 laminated on the lower surface of the wiring structure 21. The wiring structure 21 is, for example, a low-density wiring layer in which a wiring layer with a lower wiring density than the wiring structure 22 is formed. The wiring structure 22 is, for example, a high-density wiring layer in which a wiring layer with a higher wiring density than the wiring structure 21 is formed. The planar shape of the wiring board 20 can be any shape and size. The planar shape of the wiring board 20 can be, for example, a quadrangle of about 20 mm×20 mm to 40 mm×40 mm.

[0011] (Specific structure of wiring structure 21) The wiring structure 21 has a core substrate 30. The core substrate 30 is provided, for example, at the center of the wiring structure 21 in the thickness direction. The core substrate 30 may be a so-called glass epoxy substrate, which is made by impregnating a reinforcing material, glass cloth (woven glass fabric), with a thermosetting insulating resin mainly composed of an epoxy resin and hardening the material. The reinforcing material is not limited to glass cloth, and may be, for example, a glass nonwoven fabric, an aramid woven fabric, an aramid nonwoven fabric, a liquid crystal polymer (LCP: Liquid Crystal Polymer) woven fabric, or an LCP nonwoven fabric. The thermosetting insulating resin is not limited to epoxy resin, and may be, for example, a resin material such as a polyimide resin or a cyanate resin. The core substrate 30 may contain, for example, a filler such as silica (SiO2) or alumina (Al2O3). The thickness of the core substrate 30 may be, for example, about 800 μm to 2000 μm.

[0012] The core substrate 30 has through holes 30X at required locations (9 locations in FIG. 1). The through holes 30X are formed so as to penetrate the core substrate 30 in the thickness direction. A through electrode 31 is formed in the through hole 30X so as to penetrate the core substrate 30 in the thickness direction. The through electrode 31 is formed, for example, so as to fill the through hole 30X. The material of the through electrode 31 can be, for example, copper (Cu) or a copper alloy.

[0013] A wiring layer 32 is formed on the upper surface of the core substrate 30, and a wiring layer 33 is formed on the lower surface of the core substrate 30. These wiring layers 32, 33 are electrically connected to each other via through electrodes 31. The wiring layers 32, 33 may be made of, for example, copper or a copper alloy. The thickness of the wiring layers 32, 33 may be, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layers 32, 33 may be, for example, about 20 μm / 20 μm. Here, the line and space refers to the width of the wiring and the distance between adjacent wirings.

[0014] An insulating layer 41, a wiring layer 42, an insulating layer 43, and a via wiring 44 are laminated in this order on the upper surface of the core substrate 30. The insulating layers 41 and 43 may be made of a non-photosensitive insulating resin mainly composed of a thermosetting resin such as an epoxy resin or a polyimide resin. The insulating layers 41 and 43 may contain a filler such as silica or alumina. The wiring layer 42 and the via wiring 44 may be made of copper or a copper alloy. The insulating layers 41 and 43 may have a thickness of, for example, about 20 μm to 45 μm. The wiring layer 42 may have a thickness of, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layer 42 may be about 20 μm / 20 μm.

[0015] The insulating layer 41 is laminated on the upper surface of the core substrate 30 so as to cover the wiring layer 32. The wiring layer 42 is laminated on the upper surface of the insulating layer 41. The wiring layer 42 is formed integrally with, for example, via wiring that penetrates the insulating layer 41 in the thickness direction, and is electrically connected to the wiring layer 32 through the via wiring.

[0016] The insulating layer 43 is the uppermost insulating layer in the wiring structure 21. The insulating layer 43 is laminated on the upper surface of the insulating layer 41 so as to cover the wiring layer 42. The insulating layer 43 has a through hole 43X formed therein, which penetrates the insulating layer 43 in the thickness direction and exposes a part of the upper surface of the wiring layer 42.

[0017] The upper surface of insulating layer 43 is a smooth surface (low roughness surface) with few irregularities. The upper surface of insulating layer 43 is, for example, a polished surface. The roughness of the upper surface of insulating layer 43 is set to, for example, a surface roughness Ra value of about 15 nm to 40 nm. Here, the surface roughness Ra value is a type of numerical value representing surface roughness, and is called the arithmetic mean roughness, and specifically, is the arithmetic mean of absolute values ​​of height changes within a measurement region measured from the surface, which is the average line.

[0018] The via wiring 44 is formed in the through hole 43X. The via wiring 44 electrically connects the wiring layer 42 and the wiring layer 60 formed on the upper surface of the insulating layer 43. The via wiring 44 is formed so as to fill the through hole 43X. The via wiring 44 is formed in the same shape as the through hole 43X. The via wiring 44 is formed in a tapered shape in which the diameter becomes smaller from the upper side (the wiring layer 60 side) to the lower side (the wiring layer 42 side) in FIG. 1. For example, the via wiring 44 is formed in an inverted truncated cone shape in which the upper end face has a larger diameter than the lower end face. The upper end face of the via wiring 44 is exposed from the insulating layer 43. The upper end face of the via wiring 44 is formed, for example, flush with the upper surface of the insulating layer 43. The upper end face of the via wiring 44 is, for example, a polished surface. The diameter of the upper end face of the via wiring 44 can be, for example, about 60 μm to 70 μm.

[0019] An insulating layer 51, a wiring layer 52, an insulating layer 53, and a wiring layer 54 are laminated in this order on the lower surface of the core substrate 30. The insulating layers 51 and 53 may be made of a non-photosensitive insulating resin mainly composed of a thermosetting resin such as an epoxy resin or a polyimide resin. The insulating layers 51 and 53 may contain a filler such as silica or alumina. The wiring layers 52 and 54 may be made of copper or a copper alloy. The insulating layers 51 and 53 may have a thickness of, for example, about 20 μm to 45 μm. The wiring layers 52 and 54 may have a thickness of, for example, about 15 μm to 35 μm. The line and space (L / S) of the wiring layers 52 and 54 may be about 20 μm / 20 μm.

[0020] The insulating layer 51 is laminated on the lower surface of the core substrate 30 so as to cover the wiring layer 33. The wiring layer 52 is laminated on the lower surface of the insulating layer 51. The wiring layer 52 is formed integrally with, for example, via wiring penetrating the insulating layer 51 in the thickness direction, and is electrically connected to the wiring layer 33 through the via wiring. The insulating layer 53 is laminated on the lower surface of the insulating layer 51 so as to cover the wiring layer 52. The insulating layer 53 is an insulating layer formed in the lowest layer of the wiring structure 21. The wiring layer 54 is laminated on the lower surface of the insulating layer 53. The wiring layer 54 is a wiring layer formed in the lowest layer of the wiring structure 21. The wiring layer 54 is formed integrally with, for example, via wiring penetrating the insulating layer 53 in the thickness direction, and is electrically connected to the wiring layer 52 through the via wiring.

[0021] (Specific structure of solder resist layer 24) The solder resist layer 24 is the outermost insulating layer (here, the lowest layer) of the wiring board 20. The solder resist layer 24 is formed on the lower surface of the wiring structure 21, specifically, on the lower surface of the insulating layer 53 formed on the lowest layer of the wiring structure 21 so as to cover the lowest wiring layer 54. The material of the solder resist layer 24 may be, for example, an insulating resin containing a photosensitive resin such as a phenolic resin or a polyimide resin as a main component. The solder resist layer 24 may contain, for example, a filler such as silica or alumina.

[0022] Openings 24X are formed in the solder resist layer 24 to expose parts of the lowermost wiring layer 54 as external connection pads 54P. External connection terminals 90 used when mounting the wiring board 20 on a mounting board such as a motherboard are connected to the external connection pads 54P.

[0023] A surface treatment layer is formed on the lower surface of the wiring layer 54 exposed at the bottom of the opening 24X, as necessary. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order). Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating a Ni layer and a Pd layer in this order), and a Pd layer / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. The Au layer, Ni layer, and Pd layer may be, for example, a metal layer (electroless plating layer) formed by electroless plating or a metal layer (electrolytic plating layer) formed by electrolytic plating. The surface treatment layer may be an OSP film formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment on the lower surface of the wiring layer 54 exposed in the opening 24X. The OSP film may be an organic coating such as an azole compound or an imidazole compound. When a surface treatment layer is formed on the lower surface of the wiring layer 54, the surface treatment layer functions as the external connection pad 54P. The wiring layer 54 exposed from the opening 24X (or, when a surface treatment layer is formed on the wiring layer 54, the surface treatment layer) itself may be used as the external connection terminal.

[0024] The planar shape of the external connection pads 54P and the openings 24X may be any shape and any size. For example, the planar shape of the external connection pads 54P and the openings 24X may be a circle with a diameter of about 100 μm to 300 μm.

[0025] (Specific structure of wiring structure 22) The wiring structure 22 has a structure in which a wiring layer 60, an insulating layer 61, a wiring layer 62, an insulating layer 63, a wiring layer 64, an insulating layer 65, and a wiring layer 66 are laminated in this order on the upper surface of the insulating layer 43. The wiring structure 22 has a first connection pad P1 to which a first electronic component 71 is connected, and a second connection pad P2 to which a second electronic component 72 is connected. The first connection pad P1 and the second connection pad P2 are provided on different planes.

[0026] Here, for example, copper or a copper alloy can be used as the material of the wiring layers 60, 62, 64, and 66. For example, a photosensitive insulating resin containing a phenolic resin, a polyimide resin, or the like as a main component can be used as the material of the insulating layers 61, 63, and 65. For example, the insulating layers 61, 63, and 65 may contain a filler such as silica or alumina.

[0027] Each of the wiring layers 60, 62, 64, and 66 is a wiring layer thinner than each of the wiring layers 32, 33, 42, 52, and 54 of the wiring structure 21. The thickness of the wiring layers 60 and 62 can be, for example, about 1 μm to 3 μm. The thickness of the wiring layers 64 and 66 can be, for example, about 1 μm to 15 μm. The line and space (L / S) of the wiring layers 60, 62, 64, and 66 can be, for example, about 2 μm / 2 μm. Each of the insulating layers 61, 63, and 65 is an insulating layer thinner than each of the insulating layers 41, 43, 51, and 53 of the wiring structure 21. The thickness of the insulating layers 61, 63, and 65 can be, for example, about 5 μm to 10 μm.

[0028] The wiring layer 60 is laminated on the upper surface of the insulating layer 43 so as to be connected to the upper end surface of the via wiring 44. That is, a part of the lower surface of the wiring layer 60 contacts the upper end surface of the via wiring 44, and the wiring layer 60 and the via wiring 44 are electrically connected. In other words, the wiring layer 60 and the via wiring 44 are electrically connected but are not integrated. Specifically, the wiring layer 60 has, for example, a seed layer formed on the upper end surface of the via wiring 44 and a metal layer formed on the seed layer.

[0029] The insulating layer 61 is formed on the upper surface of the insulating layer 43 so as to cover the wiring layer 60. The wiring layer 62 is laminated on the upper surface of the insulating layer 61. The wiring layer 62 is formed integrally with, for example, via wiring penetrating the insulating layer 61 in the thickness direction, and is electrically connected to the wiring layer 60 through the via wiring. The wiring layer 62 has wiring 62A that electrically connects the first connection pad P1 and the second connection pad P2. The insulating layer 63 is formed on the upper surface of the insulating layer 61 so as to cover the wiring layer 62.

[0030] The wiring layer 64 is laminated on the upper surface of the insulating layer 63. The wiring layer 64 is formed integrally with, for example, via wiring penetrating the insulating layer 63 in the thickness direction, and is electrically connected to the wiring layer 62 through the via wiring.

[0031] The wiring layer 64 has one or more first connection pads P1 connected to the first electronic component 71, and one or more wiring patterns 64A. The first connection pads P1 and the wiring patterns 64A are formed on the same plane. Specifically, the first connection pads P1 and the wiring patterns 64A are both formed on the upper surface of the insulating layer 63.

[0032] The first connection pads P1 are provided in the first mounting region R1 on which the first electronic component 71 is mounted. The upper and side surfaces of the first connection pads P1 are formed so as to be exposed from the insulating layer 65. The first connection pads P1 are formed so as to protrude upward from the upper surface of the insulating layer 63 exposed from the insulating layer 65. The planar shape of the first connection pads P1 can be any shape and any size. The planar shape of the first connection pads P1 can be, for example, a circular shape with a diameter of about 20 μm to 30 μm. The pitch of the first connection pads P1 can be, for example, about 40 μm to 60 μm. The first connection pads P1 function as pads for mounting electronic components for electrical connection with the first electronic component 71.

[0033] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the first connection pad P1. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd layer / Au layer, and an OSP film.

[0034] The upper surface and side surfaces of the wiring pattern 64A are covered with an insulating layer 65. The wiring pattern 64A is provided in an area other than the first mounting area R1. The wiring pattern 64A is provided so as not to overlap the first mounting area R1 in a plan view. The thickness of the first connection pad P1 and the thickness of the wiring pattern 64A may be the same as each other, or may be different from each other. For example, the thickness of the first connection pad P1 may be formed to be thicker than the wiring pattern 64A. In this case, the thickness of the first connection pad P1 may be about 10 μm to 15 μm, and the thickness of the wiring pattern 64A may be about 1 μm to 3 μm.

[0035] The insulating layer 65 is formed on the upper surface of the insulating layer 63 so as to cover the wiring pattern 64A of the wiring layer 64. The insulating layer 65 has an opening 65X formed therein, which penetrates the insulating layer 65 in the thickness direction and exposes the first connection pad P1 and a part of the upper surface of the insulating layer 63. The opening 65X is formed so as to expose the entire upper surface and the entire side surface of the first connection pad P1. The opening 65X is formed so as to overlap the first mounting region R1 in which the first electronic component 71 is mounted in a plan view. The planar shape of the opening 65X is formed in a shape corresponding to the planar shape of the first mounting region R1, for example, a rectangular shape. The opening 65X is formed so as to collectively expose the multiple first connection pads P1 provided in the first mounting region R1 and to expose the entire upper surface of the insulating layer 63 in the first mounting region R1. In other words, the insulating layer 65 is formed so as to surround the first mounting region R1. Here, the upper surface of the insulating layer 63 exposed from the opening 65X is formed flat. The upper surface of the insulating layer 63 exposed from the opening 65X has the same flatness as, for example, the upper surface of the insulating layer 63 in the portion covered with the insulating layer 65.

[0036] In the wiring structure 22, a step is formed by the upper surface of the insulating layer 65, the inner wall surface of the opening 65X, and the upper surface of the insulating layer 63 exposed from the opening 65X. The wiring layer 66 is laminated on the upper surface of the insulating layer 65. The wiring layer 66 is formed integrally with, for example, via wiring penetrating the insulating layer 65 in the thickness direction, and is electrically connected to the wiring layer 64 through the via wiring. The wiring layer 66 has a second connection pad P2 connected to the second electronic component 72. The second connection pad P2 is provided in the second mounting region R2 in which the second electronic component 72 is mounted. The second connection pad P2 is provided so as not to overlap with the first mounting region R1 in a plan view. The second connection pad P2 of this embodiment is provided in a peripheral region from the first mounting region R1 in a plan view. The second connection pad P2 is provided above the first connection pad P1. The second connection pad P2 is electrically connected to the wiring pattern 64A through, for example, via wiring penetrating the insulating layer 65 in the thickness direction. The second connection pad P2 is formed so as to protrude upward from the upper surface of the insulating layer 65. The second connection pads P2 may have any shape and size in plan view. The second connection pads P2 may have a circular shape with a diameter of, for example, about 20 μm to 30 μm. The pitch of the second connection pads P2 may be, for example, about 40 μm to 60 μm. The second connection pads P2 may have a thickness of, for example, about 10 μm to 15 μm. The second connection pads P2 function as pads for mounting electronic components for electrical connection with the second electronic components 72.

[0037] If necessary, a surface treatment layer may be formed on the surface (top and side surfaces, or only the top surface) of the second connection pad P2. Examples of the surface treatment layer include metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, or a Pd layer / Au layer, and an OSP film.

[0038] (Specific structure of solder resist layer 23) The solder resist layer 23 is the outermost insulating layer (here, the uppermost layer) of the wiring board 20. The solder resist layer 23 is formed on the upper surface of the wiring structure 22, specifically, on the upper surface of the insulating layer 65 formed on the uppermost layer of the wiring structure 22. The material of the solder resist layer 23 may be, for example, an insulating resin containing a photosensitive resin such as a phenolic resin or a polyimide resin as a main component. The solder resist layer 23 may contain a filler such as silica or alumina.

[0039] The solder resist layer 23 is laminated on the upper surface of the insulating layer 65 so as to expose the first connection pads P1 and the second connection pads P2. For example, the solder resist layer 23 is formed so as to surround the first mounting region R1 and the second mounting region R2 in a plan view. In other words, the solder resist layer 23 has an opening 23X that exposes the upper surface of the wiring structure 22 in the first mounting region R1 and the second mounting region R2. The opening 23X is formed so as to penetrate the solder resist layer 23 in the thickness direction. The opening 23X is formed so as to expose the upper surface of the insulating layer 63 and the first connection pads P1 in the first mounting region R1. The opening 23X is formed so as to expose the upper surface of the insulating layer 65 and the second connection pads P2 in the second mounting region R2.

[0040] (Specific Structures of the First Electronic Component 71 and the Second Electronic Component 72) Each of the first electronic component 71 and the second electronic component 72 is mounted on the wiring board 20. Each of the first electronic component 71 and the second electronic component 72 is mounted on the upper surface of the wiring structure 22. For example, the first electronic component 71 and the second electronic component 72 can be active components such as semiconductor chips, transistors, and diodes, or passive components such as chip capacitors, chip inductors, and chip resistors. For example, the first electronic component 71 and the second electronic component 72 can be silicon components or ceramic components. For example, the first electronic component 71 and the second electronic component 72 are different types of electronic components. In this embodiment, the first electronic component 71 is a semiconductor chip, and the second electronic component 72 is a chip capacitor. For example, logic chips such as a CPU (Central Processing Unit) chip and a GPU (Graphics Processing Unit) chip can be used as the semiconductor chip. In addition, for example, memory chips such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, and a flash memory chip can be used as the semiconductor chip.

[0041] The first electronic component 71 is flip-chip mounted on the first connection pad P1. For example, bumps 73 formed on a circuit formation surface (here, the lower surface) of the first electronic component 71 are joined to the first connection pad P1, so that the first electronic component 71 is electrically connected to the first connection pad P1 via the bumps 73.

[0042] The second electronic component 72 is flip-chip mounted on the second connection pad P2. For example, the second electronic component 72 is electrically connected to the second connection pad P2 via the bump 74 by bonding the bump 74 formed on the lower surface of the second electronic component 72 to the second connection pad P2.

[0043] For example, gold bumps or solder bumps can be used as the bumps 73 and 74. For example, alloys containing lead (Pb), alloys of tin (Sn) and Au, alloys of Sn and Cu, alloys of Sn and silver (Ag), alloys of Sn, Ag and Cu, etc. can be used as the material of the solder bumps.

[0044] (Specific Structure of Underfill Materials 81, 82) The underfill material 81 is provided so as to fill the gap between the wiring board 20 and the first electronic component 71. The underfill material 81 is provided so as to fill the gap between the upper surface of the insulating layer 63 exposed in the opening 65X and the lower surface of the first electronic component 71. The underfill material 81 is formed so as to cover the bump 73 and the first connection pad P1. The underfill material 81 has a function of protecting the connection portion between the bump 73 and the first connection pad P1 from external stress and the like, and improving the connection reliability at the connection portion. The underfill material 81 is provided inside the opening 65X. For example, an epoxy resin can be used as the material of the underfill material 81.

[0045] The underfill material 82 is provided so as to fill the gap between the wiring board 20 and the second electronic component 72. The underfill material 82 is provided so as to fill the gap between the upper surface of the insulating layer 65 and the lower surface of the second electronic component 72. The underfill material 82 is formed so as to cover the bumps 74 and the second connection pads P2. The underfill material 82 has a function of protecting the connection portion between the bumps 74 and the second connection pads P2 from external stress and the like, and improving the connection reliability at the connection portion. The underfill material 82 is provided apart from the underfill material 81. For example, an epoxy resin can be used as the material of the underfill material 82.

[0046] (Specific structure of external connection terminal 90) The external connection terminals 90 are formed on the external connection pads 54P of the wiring board 20. The external connection terminals 90 are connection terminals that are electrically connected to pads provided on a mounting board such as a motherboard (not shown). The external connection terminals 90 may be, for example, solder balls or lead pins. The external connection terminals 90 in this example are solder balls.

[0047] (Method of Manufacturing Semiconductor Device 10) Next, a description will be given of a method for manufacturing the semiconductor device 10. For convenience of explanation, the parts that will ultimately become the components of the semiconductor device 10 will be described by using the reference numerals of the final components.

[0048] 2, a structure is prepared in which wiring layer 32, insulating layer 41, wiring layer 42, insulating layer 43, and via wiring 44 are laminated in this order on the upper surface of core substrate 30, and wiring layer 33, insulating layer 51, wiring layer 52, insulating layer 53, and wiring layer 54 are laminated in this order on the lower surface of core substrate 30. This structure can be manufactured by a known manufacturing method, and therefore a detailed description thereof will be omitted here.

[0049] Next, the upper surface of the insulating layer 43 and the upper end surface of the via wiring 44 are polished by a CMP (Chemical Mechanical Polishing) method or the like. By this process, the upper surface of the insulating layer 43 and the upper end surface of the via wiring 44 are formed to be flush with each other. Furthermore, by polishing the upper surface of the insulating layer 43, the upper surface of the insulating layer 43 is smoothed. For example, the roughness of the upper surface of the insulating layer 43 before polishing is about 300 nm to 400 nm in terms of surface roughness Ra, whereas the roughness of the upper surface of the insulating layer 43 can be made to about 15 nm to 40 nm in terms of surface roughness Ra by polishing. In other words, in this process, the upper surface of the insulating layer 43 is polished so as to be smoothed. By the polishing in this process, the upper surface of the insulating layer 43 and the upper end surface of the via wiring 44 become polished surfaces.

[0050] Through the above manufacturing steps, the wiring structure 21 is manufactured. 3, the wiring layer 60 is formed on the upper surface of the insulating layer 43. The wiring layer 60 can be formed by using various wiring formation methods such as a subtractive method or a semi-additive method.

[0051] Next, an insulating layer 61 having a through hole 61X exposing a part of the upper surface of the wiring layer 60 is formed on the upper surface of the insulating layer 43. For example, when a resin film is used as the insulating layer 61, the resin film is laminated on the upper surface of the insulating layer 43 by thermocompression bonding, and the resin film is patterned by a photolithography method to form the insulating layer 61. As the resin film, for example, a film of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. Also, when a liquid or paste insulating resin is used as the insulating layer 61, for example, the liquid or paste insulating resin is applied to the upper surface of the insulating layer 43 by a spin coat method or the like, and the insulating resin is patterned by a photolithography method to form the insulating layer 61. As the liquid or paste insulating resin, for example, a photosensitive resin such as a phenolic resin or a polyimide resin can be used.

[0052] The upper surface of insulating layer 61 made of such a photosensitive resin may have a surface roughness Ra value of about 2 nm to 10 nm. That is, the upper surface of insulating layer 61 has a smaller surface roughness than the upper surface of insulating layer 43.

[0053] Next, a via wiring filled in the through hole 61X and a wiring layer 62 electrically connected to the wiring layer 60 through the via wiring and laminated on the upper surface of the insulating layer 61 are formed. The via wiring and the wiring layer 62 can be formed by using, for example, a semi-additive method. The wiring layer 62 is formed to have a wiring 62A.

[0054] 4, an insulating layer 63 having a through hole 63X exposing a part of the upper surface of the wiring layer 62 is formed on the upper surface of the insulating layer 61. The insulating layer 63 can be formed in the same manner as the insulating layer 61, for example.

[0055] 5, a seed layer 64B is formed so as to cover the upper surface of the insulating layer 63 and the entire inner surface of the through hole 63X. The seed layer 64B in this example is formed so as to continuously cover the entire upper surface of the insulating layer 63, the entire inner wall surface of the through hole 63X, and the entire upper surface of the wiring layer 62 exposed at the bottom of the through hole 63X. The seed layer 64B can be formed by, for example, a sputtering method or an electroless plating method. For example, when the seed layer 64B is formed by a sputtering method, first, titanium (Ti) is deposited by sputtering to cover the upper surface of the insulating layer 63 and the inner surface of the through hole 63X to form a Ti layer. Then, copper is deposited by sputtering on the Ti layer to form a Cu layer. This allows the seed layer 64B to have a two-layer structure (Ti layer / Cu layer). At this time, for example, the thickness of the Ti layer can be about 20 nm to 50 nm, and the thickness of the Cu layer can be about 100 nm to 300 nm. By forming the Ti layer in this manner, it is possible to improve the adhesion between the insulating layer 63 and the seed layer 64B. The Ti layer may be changed to a TiN layer made of titanium nitride (TiN), and the seed layer 64B may have a two-layer structure made of a TiN layer and a Cu layer. Titanium and titanium nitride are metals that are more corrosion-resistant than copper, and have higher adhesion to the insulating layer 63 than copper. When the seed layer 64B is formed by electroless plating, for example, the seed layer 64B made of a Cu layer (one-layer structure) may be formed by electroless copper plating.

[0056] Next, in the process shown in FIG. 6, a resist layer 100 having an opening pattern 101 is formed on the seed layer 64B. The opening pattern 101 is formed so as to expose the seed layer 64B in a portion corresponding to the formation region of the wiring layer 64 shown in FIG. 1. For example, a material having plating resistance against the electrolytic plating process in the next process can be used as the material of the resist layer 100. For example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used as the material of the resist layer 100. For example, when a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 64B by thermocompression bonding, and the dry film is patterned by a photolithography method to form the resist layer 100 having the opening pattern 101. Note that even when a liquid photoresist is used, the resist layer 100 can be formed through the same process.

[0057] 7, the seed layer 64B is subjected to electrolytic plating using the resist layer 100 as a plating mask, with the seed layer 64B serving as a plating power supply layer. That is, the upper surface of the seed layer 64B exposed from the opening pattern 101 of the resist layer 100 is subjected to electrolytic plating, here, electrolytic Cu plating. This process fills the through-holes 63X located inside the seed layer 64B and forms the metal layer 64C provided inside the opening pattern 101.

[0058] Subsequently, in a process shown in FIG. 8, the resist layer 100 shown in FIG. 7 is removed by an alkaline stripping solution (for example, an organic amine stripping solution, caustic soda, acetone, ethanol, or the like).

[0059] 9, a resist layer 102 is formed to cover the seed layer 64B and the metal layer 64C in the portion corresponding to the first mounting region R1. The resist layer 102 is formed to cover the entire upper surface of the seed layer 64B in the first mounting region R1 and the entire upper surface and the entire side surface of the metal layer 64C in the first mounting region R1. The resist layer 102 is formed to expose the seed layer 64B and the metal layer 64C in the portion other than the first mounting region R1. For example, a material having etching resistance against the etching process in the next process can be used as the material of the resist layer 102. For example, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used as the material of the resist layer 102. For example, when a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 64B by thermocompression bonding, and the dry film is patterned by a photolithography method to form the resist layer 102. It should be noted that even when a liquid photoresist is used, the resist layer 102 can be formed through similar steps.

[0060] 10, the unnecessary seed layer 64B is removed by etching using the metal layer 64C and the resist layer 102 as an etching mask. As a result, the seed layer 64B exposed from the metal layer 64C and the resist layer 102, that is, the unnecessary seed layer 64B in the region other than the first mounting region R1, is removed. By this process, in the region outside the first mounting region R1, via wiring filling the through hole 63X is formed, and a wiring pattern 64A composed of the seed layer 64B and the metal layer 64C is formed on the upper surface of the insulating layer 63. In this way, the via wiring and the wiring pattern 64A are formed by using a semi-additive method. On the other hand, the seed layer 64B in the first mounting region R1 is not removed by this process because it is covered by the resist layer 102. In other words, in this process, an etching process is performed so as to leave the seed layer 64B in the first mounting region R1.

[0061] 11, the resist layer 102 shown in FIG. 10 is removed by an alkaline remover (e.g., an organic amine-based remover, caustic soda, acetone, ethanol, etc.). This exposes the seed layer 64B in the first mounting region R1. At this time, the entire upper surface of the insulating layer 63 in the first mounting region R1 is covered with the seed layer 64B.

[0062] 12, an insulating layer 65 having a through hole 65Y exposing a part of the upper surface of the wiring pattern 64A is formed on the upper surface of the insulating layer 63. At this time, the insulating layer 65 is formed so as to cover the seed layer 64B and the metal layer 64C in the first mounting region R1. The insulating layer 65 can be formed in the same manner as the insulating layer 61, for example.

[0063] 13, a via wiring filled in the through hole 65Y and a wiring layer 66 electrically connected to the wiring pattern 64A through the via wiring and laminated on the upper surface of the insulating layer 65 are formed. The via wiring and the wiring layer 62 can be formed by using, for example, a semi-additive method. Through this process, a second connection pad P2 is formed in the second mounting region R2.

[0064] 14, a mask 105 having an opening 106 is prepared, and the mask 105 is placed above the insulating layer 65. The opening 106 is formed to correspond to the first mounting region R1. That is, the opening 106 is formed so as to expose the insulating layer 65 in the first mounting region R1. Next, a laser beam L is irradiated onto the upper surface of the insulating layer 65 through the opening 106 of the mask 105.

[0065] As a result, as shown in FIG. 15, the insulating layer 65 is removed from the portion irradiated with the laser light L, that is, the insulating layer 65 is partially removed. In this process, an opening 65X is formed in the first mounting region R1 exposed by the opening 106 of the mask 105, penetrating the insulating layer 65 in the thickness direction. The opening 65X is formed so as to expose the seed layer 64B formed on the upper surface of the insulating layer 65. In this manner, the opening 65X can be formed by a laser processing method. For example, an excimer laser or a YAG laser can be used as the laser light L. In this process, the seed layer 64B functions as a stopper layer for the laser processing. This can prevent, for example, the insulating layer 63 below the insulating layer 65 from being thinned by excessive laser processing.

[0066] 16, the unnecessary seed layer 64B in the first mounting region R1 is removed by etching using the metal layer 64C as an etching mask. By this process, the first connection pad P1 composed of the seed layer 64B and the metal layer 64C is formed on the upper surface of the insulating layer 63 in the first mounting region R1. As a result, the wiring layer 64 having the first connection pad P1 and the wiring pattern 64A is formed on the upper surface of the insulating layer 63.

[0067] Through the above manufacturing steps, the wiring structure 22 is formed on the upper surface of the wiring structure 21. In the following Figs. 17 to 20, the seed layer 64B and the metal layer 64C are omitted and are illustrated as the wiring layer 64.

[0068] 17, a solder resist layer 23 having openings 23X for exposing the first mounting region R1 and the second mounting region R2 is laminated on the upper surface of the uppermost insulating layer 65 of the wiring structure 22. Similarly, a solder resist layer 24 having openings 24X for exposing parts of the wiring layer 54 as external connection pads 54P is laminated on the lower surface of the lowermost insulating layer 53 of the wiring structure 21. These solder resist layers 23, 24 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.

[0069] If necessary, a surface treatment layer may be formed on the first connection pads P1, the second connection pads P2, and the external connection pads 54P. Through the above manufacturing process, the wiring board 20 can be manufactured.

[0070] 18, external connection terminals 90 are formed on the external connection pads 54P. For example, after flux is appropriately applied onto the external connection pads 54P, the external connection terminals 90 (solder balls in this case) are mounted and fixed by reflow at a temperature of about 240° C. to 260° C. The surface is then washed to remove the flux.

[0071] 18, a first electronic component 71 is mounted on the wiring board 20. More specifically, bumps 73 of the first electronic component 71 are flip-chip bonded onto first connection pads P1 of the wiring board 20. Also, a second electronic component 72 is mounted on the wiring board 20. More specifically, bumps 74 of the second electronic component 72 are flip-chip bonded onto second connection pads P2 of the wiring board 20.

[0072] 19, the gap between the first electronic component 71 and the wiring board 20, which are flip-chip bonded, is filled with underfill material 81, and the underfill material 81 is cured. For example, the gap between the lower surface of the first electronic component 71 and the upper surface of the insulating layer 63 exposed in the opening 65X is filled with the underfill material 81 using a dispenser or the like. The underfill material 81 spreads into the gap between the lower surface of the first electronic component 71 and the upper surface of the insulating layer 63 by capillary action, and spreads in a planar direction perpendicular to the lamination direction of the wiring board 20. At this time, since a step is formed by forming the opening 65X, the underfill material 81 can be suitably suppressed from spreading in the planar direction by the inner wall surface of the opening 65X. That is, the inner wall surface of the opening 65X can stop the underfill material 81 from spreading in the planar direction. This makes it possible to suitably prevent a shortage of the amount of underfill material 81 filling the gap between the first electronic component 71 and the insulating layer 63, which would otherwise occur if the underfill material 81 spreads unnecessarily in the planar direction.

[0073] 20, the gap between the second electronic component 72 and the wiring board 20, which are flip-chip bonded, is filled with an underfill material 82, and the underfill material 82 is cured. For example, the underfill material 82 is filled into the gap between the lower surface of the second electronic component 72 and the upper surface of the insulating layer 65 using a dispenser or the like. The underfill material 82 spreads into the gap between the lower surface of the second electronic component 72 and the upper surface of the insulating layer 65 by capillary action, and spreads in the planar direction of the wiring board 20. At this time, since a step is formed by forming the opening 65X, the gap between the second electronic component 72 and the insulating layer 65 is formed on a different plane from the gap between the first electronic component 71 and the insulating layer 63. Therefore, the underfill material 82 can be suitably suppressed from spreading into the gap between the first electronic component 71 and the insulating layer 63. This makes it possible to suitably prevent a shortage of the amount of underfill material 82 filling the gap between the second electronic component 72 and the insulating layer 65, which would otherwise occur if the underfill material 82 spreads unnecessarily in the planar direction.

[0074] Through the above manufacturing steps, the semiconductor device 10 of the present embodiment can be manufactured. Next, the effects of this embodiment will be described. (1) The wiring board 20 has a wiring layer 62, an insulating layer 63 covering the wiring layer 62, and a wiring layer 64 formed on the upper surface of the insulating layer 63 and electrically connected to the wiring layer 62. The wiring board 20 has an insulating layer 65 formed on the upper surface of the insulating layer 63, and a wiring layer 66 formed on the upper surface of the insulating layer 65 and electrically connected to the wiring layer 64. The wiring layer 64 has a first connection pad P1 connected to the first electronic component 71 and a wiring pattern 64A electrically connected to the wiring layer 66. The insulating layer 65 has an opening 65X that penetrates the insulating layer 65 in the thickness direction and exposes the first connection pad P1 and a part of the upper surface of the insulating layer 63. The wiring layer 66 has a second connection pad P2 connected to a second electronic component 72 different from the first electronic component 71. The wiring layer 62 has a wiring 62A that electrically connects the first connection pad P1 and the second connection pad P2.

[0075] According to this configuration, the first connection pad P1 is formed on the upper surface of the insulating layer 63 exposed in the opening 65X, and the second connection pad P2 is formed on the upper surface of the insulating layer 65 laminated on the upper surface of the insulating layer 63. Therefore, the first connection pad P1 connected to the first electronic component 71 and the second connection pad P2 connected to the second electronic component 72 are provided on different planes. Therefore, when the first electronic component 71 and the second electronic component 72 are mounted on the wiring board 20, the gap between the first electronic component 71 and the insulating layer 63 and the gap between the second electronic component 72 and the insulating layer 65 are formed on different planes. Therefore, the underfill material 81 filled between the first electronic component 71 and the insulating layer 63 can be suitably suppressed from spreading into the gap between the other second electronic component 72 and the insulating layer 65. Similarly, the underfill material 82 filled between the second electronic component 72 and the insulating layer 65 can be suitably suppressed from spreading into the gap between the other first electronic component 71 and the insulating layer 63. This can suitably prevent the amount of the underfill materials 81, 82 from being insufficient due to unnecessary spreading of the underfill materials 81, 82 in the planar direction. Therefore, the amount of the underfill materials 81, 82 can be easily adjusted, and the underfill materials 81, 82 can be uniformly filled in the gap between the first electronic component 71 and the insulating layer 63 and the gap between the second electronic component 72 and the insulating layer 65. As a result, it is possible to suitably prevent a decrease in connection reliability in the connection portion between the bump 73 of the first electronic component 71 and the first connection pad P1, and in the connection portion between the bump 74 of the second electronic component 72 and the second connection pad P2.

[0076] (2) The opening 65X is formed so as to expose the entire upper surface and the entire side surface of the first connection pad P1. Therefore, when the first electronic component 71 is mounted on the first connection pad P1, the bump 73 of the first electronic component 71 can be bonded to the upper surface and the side surface of the first connection pad P1. This makes it possible to increase the bonding area between the bump 73 and the first connection pad P1 compared to a case in which the bump 73 is bonded only to the upper surface of the first connection pad P1, thereby improving the connection reliability between the bump 73 and the first connection pad P1.

[0077] (3) The upper surface of the insulating layer 63 exposed from the opening 65X is formed flat. Therefore, when filling the gap between the first electronic component 71 and the insulating layer 63 with the underfill material 81, a decrease in the filling property of the underfill material 81 can be preferably suppressed compared to a case where the upper surface of the insulating layer 63 is formed uneven. As a result, the underfill material 81 can be uniformly filled in the gap between the first electronic component 71 and the insulating layer 63.

[0078] (4) When forming the wiring layer 64, the seed layer 64B formed on the upper surface of the insulating layer 63 is left in the first mounting region R1, and the insulating layer 65 is formed on the upper surface of the insulating layer 63 so as to cover the remaining seed layer 64B. Furthermore, the insulating layer 65 is partially removed using the remaining seed layer 64B as a stopper layer to form an opening 65X in the insulating layer 65. As a result, when the insulating layer 65 is partially removed, the seed layer 64B functions as a stopper layer for laser processing, for example, so that the insulating layer 63 below the insulating layer 65 can be prevented from being thinned by excessive laser processing. Therefore, it is possible to prevent unevenness from being formed on the upper surface of the insulating layer 63 exposed from the opening 65X, and the upper surface of the insulating layer 63 exposed from the opening 65X can be maintained flat. As a result, when filling the gap between the first electronic component 71 and the insulating layer 63 with the underfill material 81, it is possible to suitably prevent the filling property of the underfill material 81 from being reduced.

[0079] (Other embodiments) The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0080] In the above embodiment, one step is provided on the upper surface of the wiring structure 22 by forming the opening 65X in the insulating layer 65, but this is not limited to the above. For example, two or more steps may be provided on the upper surface of the wiring structure 22.

[0081] In the above embodiment, one opening 65X is formed in the insulating layer 65. However, the present invention is not limited to this. For example, the insulating layer 65 may have a plurality of openings 65X formed therein.

[0082] In the above embodiment, one first electronic component 71 is mounted on the first connection pad P1 exposed in the opening 65X, but this is not limiting. For example, multiple electronic components may be mounted on the first connection pad P1 exposed in the opening 65X.

[0083] In the above embodiment, one second electronic component 72 is mounted on the second connection pad P2 formed on the upper surface of the insulating layer 65, but this is not limiting. For example, multiple electronic components may be mounted on the second connection pad P2 formed on the upper surface of the insulating layer 65.

[0084] The number of wiring layers and insulating layers in the wiring structure 21 of the above embodiment, the layout of the wiring, and the like can be modified and changed in various ways. In the above embodiment, the upper and lower wiring layers 32, 33 of the core substrate 30 are electrically connected to each other via the through electrodes 31 filling the through holes 30X of the core substrate 30. However, the present invention is not limited to this, and the upper and lower wiring layers 32, 33 of the core substrate 30 may be electrically connected to each other via a through-hole plating layer provided on the inner wall of the through hole 30X. In this case, the hole of the through hole 30X formed on the inside of the through-hole plating layer may be filled with resin.

[0085] The wiring structure 21 may be omitted. The number of wiring layers and insulating layers in the wiring structure 22 of the above embodiment, the layout of the wiring, and the like can be modified and changed in various ways.

[0086] In the above embodiment, the solder resist layers 23 and 24 are given as an example of the protective insulating layer that is the outermost layer of the wiring board 20. However, the protective insulating layer can be formed from various insulating resins having photosensitivity.

[0087] In the above embodiment, the solder resist layer 23 may be formed on the upper surface of the insulating layer 63 exposed in the opening 65X. The solder resist layers 23 and 24 in the above embodiment may be omitted.

[0088] In the manufacturing method of the above embodiment, the opening 65X is formed by laser processing, but the method of forming the opening 65X is not limited to this. For example, the opening 65X may be formed by partially removing the insulating layer 65 by plasma processing or blasting.

[0089] In the manufacturing method of the above embodiment, the timing for forming the external connection terminals 90 can be changed as appropriate. For example, the external connection terminals 90 may be formed after the first electronic component 71 and the second electronic component 72 are mounted on the wiring board 20. [Explanation of symbols]

[0090] 10 Semiconductor device 20 Wiring board 21 Wiring structure (1st wiring structure) 22 Wiring structure (second wiring structure) 43 Insulating layer (third insulating layer) 43X through hole 44 Via wiring 62 Wiring layer (1st wiring layer) 62A Wiring 63 Insulating layer (first insulating layer) 63X through hole (1st through hole) 64 Wiring layer (2nd wiring layer) 64A Wiring Pattern 64B Seed layer 64C metal layer 65 Insulation layer (second insulation layer) 65X opening 66 Wiring layer (3rd wiring layer) 71 First Electronic Component 72 Secondary Electronic Components 81 Underfill material (first underfill material) 82 Underfill material (second underfill material) 100 Resist layer (first resist layer) 101 Opening Pattern 102 resist layer (second resist layer) P1 First connection pad P2 Second connection pad R1 First mounting area R2 Second mounting area

Claims

1. A first wiring layer; a first insulating layer covering the first wiring layer; a second wiring layer formed on an upper surface of the first insulating layer and electrically connected to the first wiring layer; a second insulating layer formed on an upper surface of the first insulating layer; a third wiring layer formed on an upper surface of the second insulating layer and electrically connected to the second wiring layer; the second wiring layer has a first connection pad connected to a first electronic component and a wiring pattern electrically connected to the third wiring layer; the second insulating layer has an opening that penetrates the second insulating layer in a thickness direction and exposes the first connection pad and a portion of an upper surface of the first insulating layer; the third wiring layer has a second connection pad connected to a second electronic component different from the first electronic component; The first wiring layer is a wiring board having wiring that electrically connects the first connection pad and the second connection pad.

2. The wiring board according to claim 1 , wherein the opening is formed so as to expose the entire upper surface and the entire side surface of the first connection pad.

3. a step formed by an upper surface of the second insulating layer, an inner wall surface of the opening, and an upper surface of the first insulating layer exposed through the opening; The wiring board according to claim 1 , wherein an upper surface of the first insulating layer exposed from the opening is formed flat.

4. a planar shape of the opening portion is formed to correspond to a planar shape of a first mounting region in which the first electronic component is mounted, 2. The wiring board according to claim 1, wherein the opening is formed so as to collectively expose the first connection pads provided in the first mounting area and to expose the entire upper surface of the first insulating layer in the first mounting area.

5. a first wiring structure including a third insulating layer and a via wiring filling a through hole penetrating the third insulating layer in a thickness direction and having an upper end surface exposed from the third insulating layer; a second wiring structure laminated on an upper surface of the third insulating layer; the second wiring structure includes the first wiring layer, the first insulating layer, the second wiring layer, the second insulating layer, and the third wiring layer; The wiring board according to claim 1 , wherein the second wiring structure has a higher wiring density than the first wiring structure.

6. A wiring board according to any one of claims 1 to 5, the first electronic component flip-chip mounted on the first connection pad; the second electronic component flip-chip mounted on the second connection pad; a first underfill material formed between the first electronic component and the first insulating layer; a second underfill material formed between the second electronic component and the second insulating layer; A semiconductor device having the above structure.

7. forming a first insulating layer covering the first wiring layer; forming a second wiring layer including a first connection pad and a wiring pattern electrically connected to the first wiring layer on an upper surface of the first insulating layer; forming a second insulating layer on an upper surface of the first insulating layer to cover the second wiring layer; forming a third wiring layer on an upper surface of the second insulating layer, the third wiring layer including a second connection pad electrically connected to the wiring pattern; a step of partially removing the second insulating layer to form an opening portion that exposes the first connection pad in the second wiring layer, The opening is formed so as to penetrate the second insulating layer in a thickness direction and to expose a portion of an upper surface of the first insulating layer.

8. In the step of forming the first insulating layer, a first insulating layer having a first through hole exposing a part of an upper surface of the first wiring layer is formed, The step of forming the second wiring layer includes: forming a seed layer covering the entire upper surface of the first insulating layer and the entire inner surface of the first through hole; forming a first resist layer having an opening pattern on the seed layer; forming a metal layer on the seed layer by electrolytic plating using the first resist layer as a plating mask; removing the first resist layer; forming a second resist layer on the seed layer, the second resist layer covering the metal layer and the seed layer in an area where the first connection pad is to be formed; removing the seed layer exposed from the metal layer and the second resist layer and leaving the seed layer in a portion covered with the second resist layer; removing the second resist layer; The second insulating layer is formed to cover the remaining seed layer; The method for manufacturing a wiring board according to claim 7 , wherein the opening is formed by partially removing the second insulating layer using the remaining seed layer as a stopper layer.

9. The method for manufacturing a wiring board according to claim 8 , wherein the opening is formed by a laser processing method using the remaining seed layer as a stopper layer.

Images