Insulation chip and semiconductor device

Abstract

To suppress warping of a semiconductor substrate.SOLUTION: A semiconductor device comprises: a first unit 50 and a second unit 60; and a third unit 70 that is arranged onto the first unit 50 and the second unit 60. The first unit 50 contains a first semiconductor substrate 51, a first element insulation layer 52, and a first coil 41. The second unit 60 contains a second semiconductor substrate 61, a second element insulation layer 62, and a fourth coil 44. The third unit 70 contains a third semiconductor substrate 71, a third element insulation layer 72, a second coil 42, and a third coil 43. In the unit arrangement state, the first coil 41 and the second coil 42 are oppositely arranged in a Z direction, and the third coil 43 and the fourth coil 44 are oppositely arranged in the Z direction.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present disclosure relates to insulating chips and semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a transformer chip including a semiconductor substrate, an insulating layer laminated structure formed on the substrate, and an upper coil and a lower coil formed in the insulating layer laminated structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-78169 A

[0004] [overview] Incidentally, in order to improve the withstand voltage of a transformer chip, it is necessary to increase the distance between the upper coil and the lower coil, so it is possible to increase the number of insulating layers in the insulating layer stacking structure. In this case, the semiconductor substrate becomes more prone to warping as the insulating layers are increased. Note that this problem is not limited to transformer chips that include coils, but can also occur in insulating chips that use capacitors.

[0005] An insulating chip according to one embodiment of the present disclosure includes a first unit and a second unit arranged at a distance from each other in a first direction, and a third unit disposed on the first unit and on the second unit so as to straddle the first unit and the second unit in the first direction, the first unit including a first semiconductor substrate, a first element front surface facing the third unit, and a first element back surface opposite to the first element front surface, the first unit including a first element insulating layer in which the first element back surface is in contact with the first semiconductor substrate, and a first insulating element embedded in the first element insulating layer at a position spaced apart from the first element front surface in a thickness direction of the first element insulating layer, the second unit including a second semiconductor substrate, a second element front surface facing the third unit, and a second element back surface opposite to the second element front surface, the second unit including a second element insulating layer in which the second element back surface is in contact with the second semiconductor substrate, and the second insulating element embedded in the first element insulating layer at a position spaced apart from the first element front surface in a thickness direction of the second element insulating layer, the third unit includes a third semiconductor substrate, a third element front surface, and a third element back surface opposite the third element front surface, the third element insulating layer having the third element back surface in contact with the third semiconductor substrate, and a third insulating element and a fourth insulating element embedded in the third element insulating layer at a position separated from the third element front surface in a thickness direction of the third element insulating layer, arranged at a distance from each other in the first direction and electrically connected to each other, and in a unit arrangement state in which the third element insulating layer of the third unit is arranged on both the first element insulating layer of the first unit and the second element insulating layer of the second unit, the first insulating element and the third insulating element are arranged opposite each other in the thickness direction of the first element insulating layer, and the second insulating element and the fourth insulating element are arranged opposite each other in the thickness direction of the second element insulating layer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic circuit diagram of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of a first unit in the semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of the first unit taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic plan view of a second unit in the semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the second unit taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic plan view of the third unit in the semiconductor device of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the third unit taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is an enlarged schematic cross-sectional view of the first unit, the second unit, the third unit and their surroundings in FIG. [Figure 11] FIG. 11 is a schematic plan view of the third unit in the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view of the semiconductor device taken along line F12-F12 in FIG. [Figure 13] FIG. 13 is a schematic plan view of a second coil, a third coil, and connection wiring in a modification of the semiconductor device of the second embodiment. [Figure 14] FIG. 14 is a schematic plan view of a second coil, a third coil, and connection wiring in a modification of the semiconductor device of the second embodiment. [Figure 15] FIG. 15 is a schematic plan view of the semiconductor device according to the third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the semiconductor device taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of the semiconductor device in a state where the third unit is separated from the first unit. [Figure 18]FIG. 18 is a schematic plan view of a semiconductor device in a modification of the semiconductor device of the third embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of the semiconductor device taken along line F19-F19 in FIG. [Figure 20] FIG. 20 is a schematic plan view of a semiconductor device in a modified example of the semiconductor device of the third embodiment in which the third unit is omitted. [Figure 21] FIG. 21 is a cross-sectional structure of the semiconductor device taken along line F21-F21 in FIG. 20, and is a schematic cross-sectional view showing a state in which the third unit is separated from the first unit and the second unit. [Figure 22] FIG. 22 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a schematic plan view of a semiconductor device according to a modified example. [Diagram 25] FIG. 25 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0007] [Detailed Description] Hereinafter, some embodiments of the insulating chip and semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure. Terms such as "first", "second", and "third" in the present disclosure are used merely to distinguish objects and are not used to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The term "at least one" as used herein means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this specification, "the length (dimension) of A is equal to the length (dimension) of B" or "the length (dimension) of A and the length (dimension) of B are equal to each other" also includes a relationship in which the difference between the length (dimension) of A and the length (dimension) of B is within 10% of the length (dimension) of A, for example.

[0011] First Embodiment [Schematic configuration of semiconductor device] A schematic configuration of a semiconductor device 10 according to a first embodiment will be described with reference to Figs. 1 to 3. Fig. 1 diagrammatically illustrates the circuit configuration of the semiconductor device 10 according to the first embodiment. Fig. 2 diagrammatically illustrates an example of the internal configuration (planar structure) of the semiconductor device 10. In Fig. 2, a sealing resin 100, which will be described later, is indicated by a two-dot chain line in order to illustrate the internal configuration of the semiconductor device 10. Fig. 3 diagrammatically illustrates a cross-sectional structure of the semiconductor device 10 of Fig. 2 taken along line F3-F3.

[0012] In addition, since the circuit configuration of the semiconductor device 10 is shown in a simplified manner in Fig. 1, the number of external terminals of the semiconductor device 10 in Fig. 2 is greater than the number of external terminals of the semiconductor device 10 in Fig. 1. Here, the number of external terminals of the semiconductor device 10 refers to the number of external electrodes capable of connecting the semiconductor device 10 to electronic components external to the semiconductor device 10.

[0013] 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and a transformer 40. The transformer 40 provides electrical insulation between the first circuit 20 and the second circuit 30. The first circuit 20 is configured to operate by a first voltage V1. In one example, the first circuit 20 includes a transmitting circuit or a receiving circuit. In the first embodiment, the first circuit 20 includes a transmitting circuit 21. The transmitting circuit 21 includes at least one transistor. The second circuit 30 is configured to operate by a second voltage V2. In one example, the second circuit 30 includes a transmitting circuit or a receiving circuit. In the first embodiment, the second circuit 30 includes a receiving circuit 31. The receiving circuit 31 includes at least one transistor. The first voltage V1 and the second voltage V2 may be the same as each other or may be different. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. Therefore, the semiconductor device 10 can also be referred to as a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30.

[0014] The transformer 40 includes a first transformer 40A connected to the transmitting circuit 21 of the first circuit 20 and a second transformer 40B connected to the receiving circuit 31 of the second circuit 30. The first transformer 40A and the second transformer 40B are connected in series. In this manner, the transformer 40 has a structure that provides double insulation between the first circuit 20 and the second circuit 30.

[0015] The first transformer 40A includes a first coil 41 and a second coil 42. The second transformer 40B includes a third coil 43 and a fourth coil 44. The first coil 41 is electrically connected to the transmission circuit 21 of the first circuit 20. The fourth coil 44 is electrically connected to the reception circuit 31 of the second circuit 30. The second coil 42 and the third coil 43 are electrically connected to each other.

[0016] The transmitting circuit 21 of the first circuit 20 receives an input signal and pulse-drives the first transformer 40A. The pulse signal excited in the first coil 41 of the first transformer 40A is transmitted through the second coil 42 of the first transformer 40A and the third coil 43 and fourth coil 44 of the second transformer 40B, and is input to the receiving circuit 31 of the second circuit 30. The receiving circuit 31 outputs an output signal based on the input pulse signal.

[0017] (Internal structure of semiconductor device) 2, in the semiconductor device 10, a first unit 50, a second unit 60, and a third unit 70 are packaged as a plurality of semiconductor chips. In this specification, the semiconductor chip formed by the first unit 50, the second unit 60, and the third unit 70 is referred to as an "insulating chip 40P." In the first embodiment, the insulating chip 40P is a transformer chip.

[0018] The package format of the semiconductor device 10 is an SO (Small Outline) type, which is an SOP (Small Outline Package) in the first embodiment. The package format of the semiconductor device 10 can be changed arbitrarily. The package format is not limited to SOP, and may be QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), SOJ (Small Outline J-leaded Package), or various package structures similar to these.

[0019] The semiconductor device 10 includes a first unit 50, a second unit 60, a third unit 70, a first lead frame 80, a second lead frame 90, and a sealing resin 100. The sealing resin 100 is configured to seal the first unit 50, the second unit 60, and the third unit 70, and to partially seal the first lead frame 80 and the second lead frame 90. In FIG. 2, the sealing resin 100 is indicated by a two-dot chain line for the convenience of explaining the internal configuration of the semiconductor device 10.

[0020] The sealing resin 100 is made of a resin material having electrical insulation properties. The resin material includes, for example, black epoxy resin. The sealing resin 100 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 100 has four sealing side surfaces 101 to 104. More specifically, the sealing resin 100 has sealing side surfaces 101 and 102 as both end surfaces in the X direction and sealing side surfaces 103 and 104 as both end surfaces in the Y direction. The X direction and the Y direction are directions perpendicular to the Z direction. The X direction and the Y direction are perpendicular to each other when viewed from the Z direction. The sealing resin 100 is rectangular in shape with the X direction as the long side direction and the Y direction as the short side direction when viewed from the Z direction. Here, the X direction corresponds to the "first direction". In the following description, "plan view" means viewing from the Z direction.

[0021] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed of a material including, for example, Cu (copper), Fe (iron), Al (aluminum), etc. Each of the lead frames 80, 90 is provided straddling the inside and outside of the sealing resin 100.

[0022] The first lead frame 80 has a first die pad 81 disposed within the sealing resin 100, and a plurality of first leads 82 disposed across the inside and outside of the sealing resin 100. Each of the first leads 82 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0023] The first unit 50 is mounted on the first die pad 81. In plan view, the first die pad 81 is disposed such that the center in the Y direction is closer to the sealing side surface 101 than the center in the Y direction of the sealing resin 100. In the first embodiment, the first die pad 81 is not exposed from the sealing resin 100. In one example, the shape of the first die pad 81 in plan view is a rectangle whose long side direction is the X direction and whose short side direction is the Y direction.

[0024] The multiple first leads 82 are arranged spaced apart from one another in the Y direction. Of the multiple first leads 82, the first leads 82 arranged at the end closer to the sealing side surface 103 in the Y direction are integrated with the first die pad 81. The remaining first leads 82 are arranged spaced apart from the first die pad 81 in the X direction. A portion of each first lead 82 protrudes from the sealing side surface 101 outward from the sealing resin 100.

[0025] The second lead frame 90 has a second die pad 91 disposed within the sealing resin 100, and a plurality of second leads 92 disposed across the inside and outside of the sealing resin 100. Each of the second leads 92 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0026] The second unit 60 is mounted on the second die pad 91. In a plan view, the second die pad 91 is disposed closer to the sealing side surface 102 in the X direction than the first die pad 81. That is, the first die pad 81 and the second die pad 91 are arranged apart from each other in the X direction. Therefore, the X direction can also be said to be the arrangement direction of both die pads 81, 91. The first unit 50 and the second unit 60 are arranged apart from each other in the X direction. In the first embodiment, the second die pad 91 is not exposed from the sealing resin 100. In one example, the shape of the second die pad 91 in a plan view is a rectangle whose long side is in the X direction and whose short side is in the Y direction.

[0027] The multiple second leads 92 are arranged spaced apart from one another in the Y direction. Of the multiple second leads 92, the second leads 92 arranged at the ends closer to the sealing side surface 104 in the Y direction are integrated with the second die pad 91. The remaining second leads 92 are arranged spaced apart from the second die pad 91 in the X direction. A portion of each second lead 92 protrudes from the sealing side surface 102 outward from the sealing resin 100.

[0028] In the first embodiment, the number of second leads 92 is the same as the number of first leads 82. As can be seen from Fig. 2, the multiple first leads 82 and the multiple second leads 92 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 81 and the second die pad 91 in a plan view. Note that the number of second leads 92 and the number of first leads 82 can each be changed arbitrarily. In one example, the number of first leads 82 and the number of second leads 92 may be different from each other.

[0029] In the first embodiment, the first die pad 81 is supported by a first lead 82 that is integrated with the first die pad 81. The second die pad 91 is supported by a second lead 92 that is integrated with the second die pad 91. Therefore, each of the die pads 81, 91 is not provided with a hanging lead that is exposed from the sealing side surfaces 103, 104. Therefore, the insulation distance (creepage distance) between the first lead frame 80 and the second lead frame 90 can be made large.

[0030] The first unit 50 mounted on the first die pad 81 is a semiconductor chip including the first circuit 20 and the first coil 41 of the first transformer 40A in FIG. 1. The first unit 50 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the first unit 50 is mounted on the first die pad 81 so that the long side is aligned along the X direction and the short side is aligned along the Y direction. As shown in FIG. 3, the first unit 50 is bonded to the first die pad 81 by a conductive bonding material SD. The conductive bonding material SD may be a solder paste, an Ag (silver) paste, or the like. Here, the first coil 41 included in the first unit 50 is an example of a "first insulating element."

[0031] As shown in FIG. 2, the second unit 60 mounted on the second die pad 91 is a semiconductor chip including the second circuit 30 and the fourth coil 44 of the second transformer 40B in FIG. 1. The second unit 60 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the second unit 60 is mounted on the second die pad 91 so that the long side is aligned along the X direction and the short side is aligned along the Y direction. As shown in FIG. 3, the second unit 60 is bonded to the second die pad 91 by a conductive bonding material SD. Here, the fourth coil 44 included in the second unit 60 is an example of a "second insulating element."

[0032] In order to set the dielectric strength voltage of the semiconductor device 10 to a preset dielectric strength voltage, the first die pad 81 and the second die pad 91, which are closest to each other on the lead frames 80, 90, must be spaced apart from each other. In one example, the distance between the first unit 50 and the second unit 60 in the X direction may be, for example, equal to or greater than the dimension of the first unit 50 in the Z direction. This distance may also be, for example, equal to or greater than the dimension of the second unit 60 in the Z direction.

[0033] As shown in FIG. 2 and FIG. 3, the third unit 70 is disposed on the first unit 50 and on the second unit 60 so as to straddle the first unit 50 and the second unit 60 in the X direction in a plan view. The third unit 70 is a semiconductor chip including the second coil 42 of the first transformer 40A and the third coil 43 of the second transformer 40B. The third unit 70 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the third unit 70 is disposed on the first unit 50 and on the second unit 60 so that the long side is along the X direction and the short side is along the Y direction. As shown in FIG. 2, in the first embodiment, the dimension of the third unit 70 in the Y direction is smaller than both the dimension of the first unit 50 in the Y direction and the dimension of the second unit 60 in the Y direction. Here, the second coil 42 included in the third unit 70 is an example of a "third insulating element", and the third coil 43 included in the third unit 70 is an example of a "fourth insulating element".

[0034] 1 to 3 is an example, and the circuit configurations included in the first unit 50 and the second unit 60 may be changed as appropriate. The first circuit 20 may include a circuit other than the transmitting circuit 21. The second circuit 30 may include a circuit other than the receiving circuit 31. For example, the first circuit 20 may include an analog-digital conversion circuit. In this case, the semiconductor device 10 is configured as an isolated A / D conversion device.

[0035] For example, the second circuit 30 may include a driver circuit that drives the gate of the switching element. The driver circuit may be connected to an external terminal of the semiconductor device 10 (for example, the second lead 92 shown in FIG. 2). In this case, the semiconductor device 10 is configured as an insulated gate driver that drives the switching element. The switching element is a power semiconductor element such as a SiMOSFET (Si Metal-Oxide-Semiconductor Field-Effect Transistor), a SiCMOSFET, or an IGBT (Insulated Gate Bipolar Transistor). The driver circuit is generally a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0036] A semiconductor device 10 used as an insulated gate driver applies a drive voltage signal to a control terminal of a switching element. In this case, a transmission circuit 21 of a first circuit 20 converts a control signal input from, for example, a control device into a pulse signal. A driver circuit of a second circuit 30 outputs a drive voltage signal to a control terminal of a switching element according to a signal received by a reception circuit 31 through a first transformer 40A and a second transformer 40B.

[0037] Thus, in the semiconductor device 10 used as an insulated gate driver, the power supply voltage of the first circuit 20 that receives a signal from the control device is 5V, 3.3V, etc., with respect to the ground potential. On the other hand, in the case of the second circuit 30 connected to the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or more) is applied transiently. For this reason, the semiconductor device 10 is required to have a dielectric strength voltage between the first circuit 20 and the second circuit 30, more specifically, between the first coil 41 and the second coil 42 of the first transformer 40A and the second transformer 40B, and between the third coil 43 and the fourth coil 44. This dielectric strength voltage is 2500Vrms or more and 7500Vrms or less. In one example, the dielectric strength voltage of the semiconductor device 10 is about 5000Vrms. However, the specific value of the dielectric strength voltage of the semiconductor device 10 is not limited to this and is arbitrary.

[0038] [Detailed configuration of the insulating chip] An example of the configuration of the insulating chip 40P will be described with reference to Figures 2 to 10. In the following description, in the Z direction, the direction from the first die pad 81 (second die pad 91) to the third unit 70 shown in Figure 3 is defined as the upper direction, and the direction from the third unit 70 to the first die pad 81 (second die pad 91) is defined as the lower direction.

[0039] (1st Unit) The configuration of the first unit 50 of the insulating chip 40P will be described with reference to Fig. 2 to Fig. 5. Fig. 4 typically shows a planar structure of the first unit 50. Fig. 5 typically shows a cross-sectional structure of the first unit 50 taken along line F5-F5 in Fig. 4. Note that Fig. 5 shows one transistor of the transmission circuit 21 as the transmission circuit 21.

[0040] As shown in FIG. 2 and FIG. 4, the first unit 50 includes a plurality of first pads 55. The plurality of first pads 55 are electrically connected to the first circuit 20. The plurality of first pads 55 are also individually connected to a plurality of first leads 82 by wires W1. Each of the first pads 55 is formed of a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag, Cu, Al (aluminum), and W (tungsten). Each of the wires W1 is a bonding wire formed by a wire bonding device, and is formed of a conductor including, for example, Au, Al, Cu, etc.

[0041] As shown in FIG. 5, the first unit 50 includes a first semiconductor substrate 51 and a first element insulating layer 52 formed on the first semiconductor substrate 51. The first semiconductor substrate 51 constitutes the unit back surface of the first unit 50. This unit back surface is the surface of the first unit 50 that faces the first die pad 81 (see FIG. 3). The unit back surface is bonded to the first die pad 81 by a conductive bonding material SD (see FIG. 3). The first semiconductor substrate 51 is formed of, for example, a material containing Si. In the first embodiment, the first semiconductor substrate 51 is a Si substrate. Note that a wide band gap semiconductor or a compound semiconductor may be used for the first semiconductor substrate 51. The wide band gap semiconductor is a semiconductor substrate having a band gap of 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V group compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0042] The first element insulating layer 52 includes a first element front surface 52S facing the third unit 70 (see FIG. 3) and a first element back surface 52R opposite to the first element front surface 52S. The first element back surface 52R is in contact with the first semiconductor substrate 51. The first element front surface 52S constitutes the unit front surface of the first unit 50. The unit front surface of the first unit 50 is, for example, the surface in contact with the third unit 70.

[0043] The first element insulating layer 52 includes a plurality of first insulating films 52P and a plurality of second insulating films 52Q. That is, the first element insulating layer 52 includes an insulator 52T which is a laminate of the plurality of first insulating films 52P and the plurality of second insulating films 52Q. The insulator 52T is configured by laminating the plurality of first insulating films 52P and the plurality of second insulating films 52Q one by one alternately in the Z direction. For this reason, the Z direction can also be said to be the thickness direction of the first element insulating layer 52.

[0044] The first insulating film 52P is an etching stopper film, and is formed of a material including at least one of, for example, SiN (silicon nitride), SiC, and SiCN (nitrogen-doped silicon carbide). The first insulating film 52P may have a function of preventing the diffusion of, for example, Cu. That is, the first insulating film 52P may be a diffusion prevention film for Cu.

[0045] The second insulating film 52Q is an interlayer insulating film, and is, for example, an oxide film formed of a material containing SiO2 (silicon oxide). The second insulating film 52Q has a thickness greater than that of the first insulating film 52P. The first insulating film 52P has a thickness of, for example, 50 nm or more and less than 1000 nm. The second insulating film 52Q has a thickness of, for example, 500 nm or more and 5000 nm or less. In the first embodiment, the first insulating film 52P has a thickness of about 300 nm, and the second insulating film 52Q has a thickness of about 2000 nm. In one example, both the uppermost and lowermost insulating films of the insulator 52T are composed of the second insulating film 52Q. In addition, in order to easily understand the drawings, the ratio of the thickness of the first insulating film 52P to the thickness of the second insulating film 52Q in the drawings is different from the actual ratio of the thickness of the first insulating film 52P to the thickness of the second insulating film 52Q.

[0046] The first element insulating layer 52 includes a first protective film 53 and a first passivation film 54 . The first protective film 53 is a film that protects the insulator 52T, which is a laminate of a plurality of first insulating films 52P and a plurality of second insulating films 52Q. The first protective film 53 is formed on the insulator 52T. The first protective film 53 is formed of a material containing, for example, SiO2. In one example, the first protective film 53 is formed over the entire surface of the insulator 52T in a plan view. The material constituting the first protective film 53 can be arbitrarily changed. The first protective film 53 may be formed of a material containing, for example, SiN.

[0047] The first passivation film 54 is a surface protective film of the first unit 50. The first passivation film 54 is formed on the first protective film 53. The first passivation film 54 constitutes the first element surface 52S of the first element insulating layer 52. The first passivation film 54 is formed of a material containing at least one of PI (polyimide), SiN, and SiO2. In one example, the first passivation film 54 is formed of a material containing SiO2. In one example, the first passivation film 54 is formed over the entire surface of the first protective film 53 in a plan view. The material constituting the first passivation film 54 can be changed arbitrarily. The first passivation film 54 may be formed of the same material as the first protective film 53, or may be formed of a material different from the first protective film 53.

[0048] The first coil 41 formed in the first unit 50 is formed in a spiral shape in a plan view. As shown in Fig. 3, the first coil 41 is disposed closer to the second unit 60 in the first unit 50 in the X direction. In one example, the first coil 41 is disposed closer to the second unit 60 than the center of the first unit 50 in the X direction. More specifically, the first coil 41 is disposed at one of both ends of the first unit 50 in the X direction that is closer to the second unit 60.

[0049] The first coil 41 is embedded in the first element insulating layer 52 at a position spaced apart from the first element front surface 52S in the Z direction. The first coil 41 is also embedded in the first element insulating layer 52 at a position spaced apart from the first element back surface 52R in the Z direction. In the first embodiment, the first coil 41 is disposed closer to the first element front surface 52S than to the center of the first element insulating layer 52 in the Z direction. In one example, as shown in FIG. 5, the first coil 41 is provided in the second insulating film 52Q, which is the uppermost layer of the insulator 52T.

[0050] The first coil 41 is formed of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In the first embodiment, the first coil 41 is formed of a material containing Cu.

[0051] As shown by the double-dashed line frame in Fig. 4, the first circuit 20 formed in the first unit 50 is formed over most of the first unit 50 in a plan view. As shown in Fig. 5, the first circuit 20 is provided on, for example, a first semiconductor substrate 51. The first coil 41 is disposed at a position overlapping the first circuit 20 in a plan view. The transmission circuit 21 of the first circuit 20 is disposed at a position overlapping the first coil 41 in a plan view. The size of the formation area of ​​the first circuit 20 can be arbitrarily changed depending on the function of the first circuit 20, etc.

[0052] As shown in FIG. 2, the multiple first pads 55 are arranged at a position different from the third unit 70 in a plan view. The multiple first pads 55 are located on the opposite side of the third unit 70 from the second unit 60 in the X direction. The multiple first pads 55 are arranged at one of both ends of the first unit 50 in the X direction that is farther from the second unit 60. It can also be said that the multiple first pads 55 are arranged closer to the first lead 82 than the third unit 70 in the X direction. As shown in FIG. 5, each first pad 55 is exposed from the first element insulating layer 52 in the Z direction.

[0053] The first unit 50 includes a plurality of first wirings 56A, 56B and a plurality of second wirings 57A to 57C. The plurality of first wirings 56A, 56B and the plurality of second wirings 57A to 57C are provided in the first element insulating layer 52. The first wirings 56A, 56B and the plurality of second wirings 57A to 57C are formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W, for example.

[0054] The first wiring 56A and the second wiring 57A are wirings that electrically connect the first pad 55 and the transmission circuit 21 of the first circuit 20. The first wiring 56A extends in the X direction. The first wiring 56A includes a first end that overlaps the first pad 55 in a plan view and a second end that overlaps the transmission circuit 21. The first wiring 56A is electrically connected to the transmission circuit 21 at the second end. The first wiring 56A is connected to the second wiring 57A at the first end. The second wiring 57A is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 57A connects the first end of the first wiring 56A and the first pad 55.

[0055] The first wiring 56B and the second wiring 57B, 57C are wirings that electrically connect the first coil 41 and the first circuit 20. The first wiring 56B is disposed on the opposite side of the first wiring 56A with respect to the transmission circuit 21 in the X direction. The first wiring 56B extends in the X direction. The first wiring 56B includes a first end that overlaps with an inner end of the first coil 41 in a plan view and a second end that overlaps with the transmission circuit 21. The first wiring 56B is electrically connected to the transmission circuit 21 at the second end. The first wiring 56B is connected to the second wiring 57B at the first end. The second wiring 57B is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 57B connects the first end of the first wiring 56B and the inner end of the first coil 41.

[0056] The second wiring 57C is a wiring that electrically connects the outer end of the first coil 41 and the transmission circuit 21. As a result, both the inner and outer ends of the first coil 41 are electrically connected to the transmission circuit 21. The second wiring 57C is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 57C is connected to the second end of the first wiring 56A. That is, the second wiring 57C connects the outer end of the first coil 41 and the first wiring 56A. Therefore, the outer end of the first coil 41 is electrically connected to both the first pad 55 and the transmission circuit 21. In this way, the first circuit 20, the first coil 41, and the first pad 55 are electrically connected in the first unit 50, more specifically, in the first element insulating layer 52, by the plurality of first wirings 56A and 56B and the plurality of second wirings 57A to 57C.

[0057] (Unit 2) The configuration of the second unit 60 of the insulating chip 40P will be described with reference to Figures 2, 3, 6, and 7. Figure 6 shows a schematic planar structure of the second unit 60. Figure 7 shows a schematic cross-sectional structure of the second unit 60 taken along line F7-F7 in Figure 6. Note that Figure 7 shows one transistor of the receiving circuit 31 as the receiving circuit 31.

[0058] As shown in FIG. 2 and FIG. 6, the second unit 60 includes a plurality of second pads 65. The plurality of second pads 65 are electrically connected to the second circuit 30. The plurality of second pads 65 are also individually connected to a plurality of second leads 92 by wires W2. Each of the second pads 65 is formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Each of the wires W2 is a bonding wire formed by a wire bonding device, and is formed of a conductor including, for example, Au, Al, Cu, etc.

[0059] As shown in FIG. 7, the second unit 60 includes a second semiconductor substrate 61 and a second element insulating layer 62 formed on the second semiconductor substrate 61. In the first embodiment, the configuration of the second semiconductor substrate 61 is the same as that of the first semiconductor substrate 51 (see FIG. 5). The dimension (thickness) in the Z direction of the second semiconductor substrate 61 is the same as the dimension (thickness) in the Z direction of the first semiconductor substrate 51. The dimension (thickness) in the Z direction of the second element insulating layer 62 is the same as the dimension (thickness) in the Z direction of the first element insulating layer 52 (see FIG. 5). Therefore, the dimension in the Z direction of the second unit 60 is the same as the dimension in the Z direction of the first unit 50.

[0060] The second element insulating layer 62 includes a second element front surface 62S facing the third unit 70 (see FIG. 3) and a second element back surface 62R opposite to the second element front surface 62S. The second element back surface 62R is in contact with the second semiconductor substrate 61. The second element front surface 62S constitutes the unit front surface of the second unit 60. The unit front surface of the second unit 60 is, for example, the surface in contact with the third unit 70.

[0061] The second element insulating layer 62 includes a plurality of first insulating films 62P and a plurality of second insulating films 62Q. That is, the second element insulating layer 62 includes an insulator 62T which is a laminate of a plurality of first insulating films 62P and a plurality of second insulating films 62Q. The insulator 62T is configured by laminating a plurality of first insulating films 62P and a plurality of second insulating films 62Q one by one in the Z direction. For this reason, the Z direction can also be said to be the thickness direction of the second element insulating layer 62. The configuration of the first insulating film 62P is the same as the first insulating film 52P (see FIG. 5) of the first element insulating layer 52, and the configuration of the second insulating film 62Q is the same as the second insulating film 52Q (see FIG. 5) of the first element insulating layer 52. The thickness of the first insulating film 62P is the same as the thickness of the first insulating film 52P, and the thickness of the second insulating film 62Q is the same as the thickness of the second insulating film 52Q.

[0062] The second element insulating layer 62 includes a second protective film 63 and a second passivation film 64 . The second protective film 63 is a film that protects the insulator 62T. The second protective film 63 is formed on the insulator 62T. The second protective film 63 is formed of a material containing SiO2, for example. In one example, the second protective film 63 is formed over the entire surface of the insulator 62T in a plan view. The material constituting the second protective film 63 can be changed arbitrarily. In one example, the second protective film 63 may be formed of a material containing SiN.

[0063] The second passivation film 64 is a surface protective film of the second unit 60. The second passivation film 64 is formed on the second protective film 63. The second passivation film 64 constitutes the second element surface 62S of the second element insulating layer 62. The second passivation film 64 is formed of a material containing at least one of PI, SiN, and SiO2, for example. In one example, the second passivation film 64 is formed of a material containing SiO2. In one example, the second passivation film 64 is formed over the entire surface of the second protective film 63 in a plan view. The material constituting the second passivation film 64 can be changed arbitrarily. The second passivation film 64 may be formed of the same material as the second protective film 63, or may be formed of a material different from the second protective film 63.

[0064] The fourth coil 44 formed in the second unit 60 is formed in a spiral shape in a plan view. As shown in Fig. 3, the fourth coil 44 is disposed closer to the first unit 50 in the second unit 60 in the X direction. In one example, the fourth coil 44 is disposed closer to the first unit 50 than the center of the second unit 60 in the X direction. More specifically, the fourth coil 44 is disposed at one of both ends of the second unit 60 in the X direction that is closer to the first unit 50.

[0065] The fourth coil 44 is embedded in the second element insulating layer 62 at a position spaced apart from the second element front surface 62S in the Z direction. The fourth coil 44 is embedded in the second element insulating layer 62 at a position spaced apart from the second element back surface 62R in the Z direction. In the first embodiment, the fourth coil 44 is disposed closer to the second element front surface 62S than to the center of the second element insulating layer 62 in the Z direction. In one example, the fourth coil 44 is provided in the second insulating film 62Q, which is the uppermost layer of the insulator 62T. In other words, the fourth coil 44 is disposed in the same position as the first coil 41 in the Z direction.

[0066] The fourth coil 44 is formed of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the fourth coil 44 may be formed of the same material as the first coil 41. In the first embodiment, the fourth coil 44 is formed of a material containing Cu.

[0067] As shown in the double-dashed line frame in Fig. 6, the second circuit 30 formed in the second unit 60 is formed over most of the second unit 60 in a plan view. As shown in Fig. 7, the second circuit 30 is provided on, for example, a second semiconductor substrate 61. The fourth coil 44 is disposed at a position overlapping the second circuit 30 in a plan view. The receiving circuit 31 of the second circuit 30 is disposed at a position overlapping the fourth coil 44 in a plan view.

[0068] The multiple second pads 65 are arranged at a position different from the third unit 70 in a plan view. The multiple second pads 65 are located on the opposite side of the third unit 70 from the first unit 50 in the X direction. The multiple second pads 65 are arranged at one of both ends of the second unit 60 in the X direction that is farther from the first unit 50. It can also be said that the multiple second pads 65 are arranged closer to the second lead 92 than the third unit 70 in the X direction. Each second pad 65 is exposed from the second element insulating layer 62 in the Z direction.

[0069] The second unit 60 includes a plurality of first wirings 66A, 66B and a plurality of second wirings 67A to 67C. The plurality of first wirings 66A, 66B and the plurality of second wirings 67A to 67C are provided in a second element insulating layer 62. The first wirings 66A, 66B and the plurality of second wirings 67A to 67C are formed of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W, for example.

[0070] The first wiring 66A and the second wiring 67A are wirings that electrically connect the second pad 65 and the receiving circuit 31 of the second circuit 30. The first wiring 66A extends in the X direction. The first wiring 66A includes a first end that overlaps the second pad 65 in a plan view and a second end that overlaps the receiving circuit 31. The first wiring 66A is electrically connected to the receiving circuit 31 at the second end. The first wiring 66A is connected to the second wiring 67A at the first end. The second wiring 67A is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 67A connects the first end of the first wiring 66A and the second pad 65.

[0071] The first wiring 66B and the second wiring 67B, 67C are wirings that electrically connect the fourth coil 44 and the second circuit 30. The first wiring 66B is disposed on the opposite side of the first wiring 66A with respect to the receiving circuit 31 in the X direction. The first wiring 66B extends in the X direction. The first wiring 66B includes a first end that overlaps with an inner end of the fourth coil 44 in a plan view and a second end that overlaps with the receiving circuit 31. The first wiring 66B is electrically connected to the receiving circuit 31 at the second end. The first wiring 66B is connected to the second wiring 67B at the first end. The second wiring 67B is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 67B connects the first end of the first wiring 66B and the inner end of the fourth coil 44.

[0072] The second wiring 67C is a wiring that electrically connects the outer end of the fourth coil 44 and the receiving circuit 31. As a result, both the inner and outer ends of the fourth coil 44 are electrically connected to the receiving circuit 31. The second wiring 67C is a wiring in which a plurality of vias and a plurality of wiring layers are alternately stacked one by one in the Z direction. The second wiring 67C is connected to the second end of the first wiring 66A. That is, the second wiring 67C connects the outer end of the fourth coil 44 and the first wiring 66A. Therefore, the outer end of the fourth coil 44 is electrically connected to both the second pad 65 and the receiving circuit 31. In this way, the second circuit 30, the fourth coil 44, and the second pad 65 are electrically connected in the second unit 60, more specifically, in the second element insulating layer 62, by the plurality of first wirings 66A and 66B and the plurality of second wirings 67A to 67C.

[0073] (Unit 3) The configuration of the third unit 70 of the insulating chip 40P will be described with reference to Figures 2, 3, 8, and 9. Figure 8 shows a schematic planar structure of the third unit 70. Figure 9 shows a schematic cross-sectional structure of the third unit 70 taken along line F9-F9 in Figure 8.

[0074] 3, the third unit 70 is electrically insulated from the first unit 50 and the second unit 60. The third unit 70 is also electrically insulated from the first lead frame 80 and the second lead frame 90. In this manner, the third unit 70 is in an electrically floating state.

[0075] As shown in FIG. 9, the third unit 70 includes a third semiconductor substrate 71 and a third element insulating layer 72 formed on the third semiconductor substrate 71. The third element insulating layer 72 is located below the third semiconductor substrate 71. In other words, the third element insulating layer 72 is located closer to the first unit 50 and the second unit 60 (see FIG. 3) than the third semiconductor substrate 71. The configuration of the third semiconductor substrate 71 is the same as that of the first semiconductor substrate 51 (see FIG. 5). The Z-direction dimension (thickness) of the third semiconductor substrate 71 may be the same as the Z-direction dimension (thickness) of the first semiconductor substrate 51, for example. The Z-direction dimension (thickness) of the third element insulating layer 72 may be smaller than the Z-direction dimension (thickness) of the first element insulating layer 52 (see FIG. 5), for example. For this reason, the Z-direction dimension of the third unit 70 may be smaller than the Z-direction dimension of the first unit 50.

[0076] Here, the dimension in the Z direction of the third semiconductor substrate 71 can be changed arbitrarily. In one example, the dimension in the Z direction of the third semiconductor substrate 71 may be smaller than the dimension in the Z direction of the first semiconductor substrate 51. In one example, the dimension in the Z direction of the third element insulating layer 72 can be changed arbitrarily. In one example, the dimension in the Z direction of the third element insulating layer 72 may be equal to or larger than the dimension in the Z direction of the first element insulating layer 52.

[0077] The third element insulating layer 72 includes a third element front surface 72S facing the first unit 50 and the second unit 60 (see FIG. 3), and a third element back surface 72R opposite to the third element front surface 72S. The third element back surface 72R is in contact with the third semiconductor substrate 71. The third element front surface 72S constitutes the unit front surface of the third unit 70. The unit front surface of the third unit 70 is, for example, a surface in contact with both the unit front surface of the first unit 50 and the unit front surface of the second unit 60.

[0078] The third element insulating layer 72 includes a plurality of first insulating films 72P and a plurality of second insulating films 72Q. That is, the third element insulating layer 72 includes an insulator 72T which is a laminate of a plurality of first insulating films 72P and a plurality of second insulating films 72Q. The insulator 72T is configured by laminating a plurality of first insulating films 72P and a plurality of second insulating films 72Q one by one in the Z direction. For this reason, the Z direction can also be said to be the thickness direction of the third element insulating layer 72. The configuration of the first insulating film 72P is the same as the first insulating film 52P (see FIG. 5) of the first element insulating layer 52, and the configuration of the second insulating film 72Q is the same as the second insulating film 52Q (see FIG. 5) of the first element insulating layer 52. The thickness of the first insulating film 72P is the same as the thickness of the first insulating film 52P, and the thickness of the second insulating film 72Q is the same as the thickness of the second insulating film 52Q.

[0079] The third element insulating layer 72 includes a third protective film 73 and a third passivation film 74 . The third protective film 73 is a film that protects the insulator 72T, which is a laminate of a plurality of first insulating films 72P and a plurality of second insulating films 72Q. The third protective film 73 is formed on the insulator 72T. The third protective film 73 is formed of a material containing, for example, SiO2. In one example, the third protective film 73 is formed over the entire surface of the insulator 72T in a plan view. The material constituting the third protective film 73 can be changed arbitrarily. In one example, the third protective film 73 may be formed of a material containing SiN.

[0080] The third passivation film 74 is a surface protective film of the third unit 70. The third passivation film 74 is formed on the third protective film 73. The third passivation film 74 constitutes the third element surface 72S of the third element insulating layer 72. The third passivation film 74 is formed of a material containing at least one of PI, SiN, and SiO2, for example. In one example, the third passivation film 74 is formed of a material containing SiO2. In one example, the third passivation film 74 is formed over the entire surface of the third protective film 73 in a plan view. Note that the material constituting the third passivation film 74 can be changed arbitrarily. The third passivation film 74 may be formed of the same material as the third protective film 73, or may be formed of a material different from the third protective film 73.

[0081] Both the second coil 42 and the third coil 43 formed in the third unit 70 are formed in a spiral shape in a plan view. The second coil 42 and the third coil 43 are arranged apart from each other in the X direction and are electrically connected to each other. The second coil 42 and the third coil 43 are arranged to be at the same position in the Y direction. The number of turns of the second coil 42 and the third coil 43 can be changed arbitrarily. In one example, the number of turns of the second coil 42 may be the same as the number of turns of the first coil 41 (see FIG. 3). In one example, the number of turns of the second coil 42 may be less than the number of turns of the first coil 41. In one example, the number of turns of the second coil 42 may be more than the number of turns of the first coil 41. In one example, the number of turns of the third coil 43 may be the same as the number of turns of the fourth coil 44 (see FIG. 3). In one example, the number of turns of the third coil 43 may be less than the number of turns of the fourth coil 44. In one example, the number of turns of the third coil 43 may be greater than the number of turns of the fourth coil 44.

[0082] Both the second coil 42 and the third coil 43 are embedded in the third element insulating layer 72 at a position spaced apart from the third element front surface 72S in the Z direction. Also, both the second coil 42 and the third coil 43 are embedded in the third element insulating layer 72 at a position spaced apart from the third element back surface 72R in the Z direction. In one example, the second coil 42 and the third coil 43 are disposed at the same position as each other in the Z direction. In the first embodiment, both the second coil 42 and the third coil 43 are disposed closer to the third element back surface 72R than the center of the third element insulating layer 72 in the Z direction.

[0083] 8, the second coil 42 includes a first coil end 42A and a second coil end 42B. The first coil end 42A is provided on the inside of the second coil 42. The second coil end 42B is provided on the outside of the second coil 42.

[0084] The third coil 43 includes a third coil end portion 43A and a fourth coil end portion 43B. The third coil end portion 43A is provided on the inside of the third coil 43. The fourth coil end portion 43B is provided on the outside of the third coil 43.

[0085] Both the second coil 42 and the third coil 43 are formed of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, both the second coil 42 and the third coil 43 may be formed of the same material as the first coil 41. In one example, both the second coil 42 and the third coil 43 may be formed of the same material as the fourth coil 44. In the first embodiment, both the second coil 42 and the third coil 43 are formed of a material containing Cu.

[0086] The third unit 70 includes a first connection wiring 75 and a second connection wiring 76 that electrically connect the second coil 42 and the third coil 43 to each other. As shown in FIG. 9, the first connection wiring 75 connects the first coil end 42A of the second coil 42 and the third coil end 43A of the third coil 43. The first connection wiring 75 includes a first wiring portion 75A extending in the X direction, a first via 75B connecting the first wiring portion 75A and the first coil end 42A, and a second via 75C connecting the first wiring portion 75A and the third coil end 43A. In one example, the first wiring portion 75A is disposed closer to the third element rear surface 72R than the second coil 42 and the third coil 43 in the Z direction. The first wiring portion 75A extends in the X direction in a plan view.

[0087] The second connection wiring 76 connects the second coil end 42B of the second coil 42 and the fourth coil end 43B of the third coil 43. The second connection wiring 76 is disposed at the same position as the second coil 42 and the third coil 43 in the Z direction. The second connection wiring 76 extends in the X direction. In one example, the second connection wiring 76 is disposed at a position overlapping the first connection wiring 75 in a plan view. Note that in FIG. 8, in order to easily understand the drawing, the second connection wiring 76 is shown to be shifted in the Y direction relative to the first connection wiring 75 in a plan view. However, in reality, the position of the second connection wiring 76 in the Y direction is the same as the position of the first connection wiring 75 in the Y direction in a plan view.

[0088] The first connection wiring 75 and the second connection wiring 76 are formed of a material including one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W. In one example, both the first connection wiring 75 and the second connection wiring 76 may be formed of the same material as the second coil 42 and the third coil 43. In one example, both the first connection wiring 75 and the second connection wiring 76 may be formed of a material different from the second coil 42 and the third coil 43.

[0089] (Unit placement configuration) Next, a configuration in a state in which the third element insulating layer 72 of the third unit 70 is disposed on both the first element insulating layer 52 of the first unit 50 and the second element insulating layer 62 of the second unit 60 (hereinafter referred to as the "unit arrangement state") will be described with reference to Fig. 10. Fig. 10 shows a schematic cross-sectional structure of the first unit 50, the second unit 60, and the third unit 70 in the unit arrangement state.

[0090] As shown in FIG. 10, in the first embodiment, in the unit arrangement state, the third element insulating layer 72 is in contact with both the first element insulating layer 52 and the second element insulating layer 62. More specifically, in the unit arrangement state, the third element surface 72S of the third element insulating layer 72 is in contact with both the first element surface 52S of the first element insulating layer 52 and the second element surface 62S of the second element insulating layer 62. That is, the third passivation film 74 of the third element insulating layer 72 is in contact with both the first passivation film 54 of the first element insulating layer 52 and the second passivation film 64 of the second element insulating layer 62. On the other hand, in the first embodiment, the third element insulating layer 72 is not bonded to both the first element insulating layer 52 and the second element insulating layer 62.

[0091] In the unit arrangement state, the first coil 41 of the first unit 50 and the third coil 43 of the third unit 70 are arranged to face each other in the Z direction. In the unit arrangement state, the second coil 42 of the second unit 60 and the fourth coil 44 of the third unit 70 are arranged to face each other in the Z direction.

[0092] In the first embodiment, the distance D1 between the first coil 41 and the second coil 42 in the Z direction is less than the thickness T1 of the first element insulating layer 52. The distance D1 is also less than the thickness T3 of the third element insulating layer 72. The distance D2 between the third coil 43 and the fourth coil 44 in the Z direction is also less than the thickness T2 of the second element insulating layer 62. The distance D2 is also less than the thickness T3 of the third element insulating layer 72. In one example, the distance D2 and the distance D1 are equal to each other.

[0093] The distance D3 between the first coil 41 and the fourth coil 44 in the X direction is equal to or greater than the distance D1 between the first coil 41 and the second coil 42 in the Z direction, and equal to or greater than the distance D2 between the third coil 43 and the fourth coil 44 in the Z direction. In the first embodiment, the distance D3 is greater than the distance D1 and greater than the distance D2. In one example, the distance D3 is greater than the thickness T1 of the first element insulating layer 52. In one example, the distance D3 is greater than the thickness T2 of the second element insulating layer 62. The distance D3 is greater than the thickness T3 of the third element insulating layer 72.

[0094] The minimum distance between the multiple first pads 55 and the second coil 42 is greater than the distance D1 between the first coil 41 and the second coil 42 in the Z direction. The minimum distance between the multiple second pads 65 and the fourth coil 44 is greater than the distance D2 between the third coil 43 and the fourth coil 44 in the Z direction.

[0095] [Method of manufacturing semiconductor device] Next, an example of a method for manufacturing the semiconductor device 10 of the first embodiment will be described. In the following description, for the reference numerals relating to the components of the semiconductor device 10, please refer to FIGS.

[0096] The manufacturing method of the semiconductor device 10 includes the steps of preparing a first unit 50, a second unit 60, a third unit 70, and a first lead frame 80 and a second lead frame 90.

[0097] The step of preparing the first unit 50 includes a step of forming a first element insulating layer 52, a first coil 41, a plurality of first pads 55, a plurality of first wirings 56A, 56B, and a plurality of second wirings 57A to 57C on a first semiconductor substrate 51 on which the first circuit 20 is formed. The first coil 41, the plurality of first pads 55, the plurality of first wirings 56A, 56B, and the plurality of second wirings 57A to 57C are formed by etching and sputtering using a metal mask in the process of laminating the first insulating film 52P and the second insulating film 52Q of the first element insulating layer 52.

[0098] The step of preparing the second unit 60 includes a step of forming a second element insulating layer 62, a second coil 42, a plurality of second pads 65, a plurality of first wirings 66A, 66B, and a plurality of second wirings 67A to 67C on a second semiconductor substrate 61 on which the second circuit 30 is formed. The second coil 42, the plurality of second pads 65, the plurality of first wirings 66A, 66B, and the plurality of second wirings 67A to 67C are formed by etching and sputtering using a metal mask in the process of laminating the first insulating film 62P and the second insulating film 62Q of the second element insulating layer 62.

[0099] The process of preparing the third unit 70 includes a process of forming a third element insulating layer 72, a third coil 43, a fourth coil 44, a first connection wiring 75, and a second connection wiring 76 on a third semiconductor substrate 71. The third coil 43, the fourth coil 44, the first connection wiring 75, and the second connection wiring 76 are formed by etching and sputtering using a metal mask in the process of laminating the first insulating film 72P and the second insulating film 72Q of the third element insulating layer 72.

[0100] The method for manufacturing the semiconductor device 10 includes a step of mounting the first unit 50 on the first die pad 81 of the first lead frame 80 and a step of mounting the second unit 60 on the second die pad 91 of the second lead frame 90.

[0101] In the process of mounting the first unit 50 on the first die pad 81, first, a conductive bonding material SD is applied to the first die pad 81. Next, the first unit 50 is placed on the conductive bonding material SD. Next, the first unit 50 is bonded to the first die pad 81 by melting and solidifying the conductive bonding material SD.

[0102] In the process of mounting the second unit 60 on the second die pad 91, first, a conductive bonding material SD is applied to the second die pad 91. Then, the second unit 60 is placed on the conductive bonding material SD. Then, the conductive bonding material SD is melted and solidified to bond the second unit 60 to the second die pad 91. Here, the conductive bonding material SD applied to the first die pad 81 and the conductive bonding material SD applied to the second die pad 91 may be melted and solidified at the same time.

[0103] The manufacturing method of the semiconductor device 10 includes a step of forming a plurality of wires W1 and a plurality of wires W2. The plurality of wires W1 are formed using a wire bonding apparatus so as to individually connect the plurality of first pads 55 and the plurality of first leads 82 of the first lead frame 80. The plurality of wires W2 are formed using a wire bonding apparatus so as to individually connect the plurality of second pads 65 and the plurality of second leads 92 of the second lead frame 90.

[0104] The manufacturing method of the semiconductor device 10 includes a step of arranging the third unit 70 on the first unit 50 and on the second unit 60 so as to straddle the gap between the first unit 50 and the second unit 60 in the X direction. By arranging the third unit 70 on the first unit 50 and on the second unit 60, the third element insulating layer 72 of the third unit 70 contacts the first element insulating layer 52 of the first unit 50 and the second element insulating layer 62 of the second unit 60.

[0105] The manufacturing method of the semiconductor device 10 includes a step of forming the sealing resin 100. In this step, the sealing resin 100 is formed by, for example, transfer molding. As a result, the sealing resin 100 seals the first unit 50, the second unit 60, the third unit 70, the first die pad 81, the second die pad 91, and the multiple wires W1 and W2. Through the above steps, the semiconductor device 10 is manufactured.

[0106] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described. The semiconductor device 10 includes a first unit 50 including a first element insulating layer 52 in which the first coil 41 is embedded, a second unit 60 including a second element insulating layer 62 in which the fourth coil 44 is embedded, and a third unit 70 including a third element insulating layer 72 in which the second coil 42 and the third coil 43 are embedded. In the unit arrangement state, the first coil 41 and the second coil 42 face each other in the Z direction, and the third coil 43 and the fourth coil 44 face each other. Therefore, both the first element insulating layer 52 and the third element insulating layer 72 are interposed between the first coil 41 and the second coil 42 in the Z direction, and both the second element insulating layer 62 and the third element insulating layer 72 are interposed between the third coil 43 and the fourth coil 44 in the Z direction.

[0107] In this way, the element insulating layer between the first coil 41 and the second coil 42 is configured by a laminated structure of the first element insulating layer 52 formed on the first semiconductor substrate 51 and the third element insulating layer 72 formed on the third semiconductor substrate 71. Therefore, compared with the case where the element insulating layer between the first coil 41 and the second coil 42 is configured by an element insulating layer formed on one semiconductor substrate, both the thickness T1 of the first element insulating layer 52 and the thickness T3 of the third element insulating layer 72 can be made thinner. Therefore, both the first semiconductor substrate 51 and the third semiconductor substrate 71 are less likely to warp. In addition, the element insulating layer between the third coil 43 and the fourth coil 44 is configured by a laminated structure of the second element insulating layer 62 formed on the second semiconductor substrate 61 and the third element insulating layer 72 formed on the third semiconductor substrate 71. Therefore, compared to a case where the element insulating layer between the third coil 43 and the fourth coil 44 is configured by an element insulating layer formed on one semiconductor substrate, it is possible to reduce both the thickness T2 of the second element insulating layer 62 and the thickness T3 of the third element insulating layer 72. As a result, both the second semiconductor substrate 61 and the third semiconductor substrate 71 are less likely to warp.

[0108] [Effects of the first embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a first unit 50 and a second unit 60 arranged at a distance from each other in the X direction, and a third unit 70 disposed on the first unit 50 and the second unit 60 so as to straddle the X direction between the first unit 50 and the second unit 60. The first unit 50 includes a first semiconductor substrate 51, a first element insulating layer 52 including a first element front surface 52S facing the third unit 70 and a first element back surface 52R opposite to the first element front surface 52S, the first element back surface 52R being in contact with the first semiconductor substrate 51, and a first coil 41 embedded in the first element insulating layer 52 at a position spaced apart from the first element front surface 52S in the Z direction. The second unit 60 includes a second semiconductor substrate 61, a second element insulating layer 62 including a second element front surface 62S facing the third unit 70 and a second element back surface 62R opposite to the second element front surface 62S, with the second element back surface 62R in contact with the second semiconductor substrate 61, and a fourth coil 44 embedded in the second element insulating layer 62 at a position spaced apart from the second element front surface 62S in the Z direction. The third unit 70 includes a third semiconductor substrate 71, a third element insulating layer 72 including a third element front surface 72S and a third element back surface 72R opposite to the third element front surface 72S, with the third element back surface 72R in contact with the third semiconductor substrate 71, and a second coil 42 and a third coil 43 embedded in the third element insulating layer 72 at a position spaced apart from the third element front surface 72S in the Z direction, arranged at a distance from each other in the X direction, and electrically connected to each other. In a unit arrangement state in which the third element insulating layer 72 of the third unit 70 is arranged on both the first element insulating layer 52 of the first unit 50 and the second element insulating layer 62 of the second unit 60, the first coil 41 and the second coil 42 are arranged opposite each other in the Z direction, and the third coil 43 and the fourth coil 44 are arranged opposite each other in the Z direction.

[0109] According to this configuration, the space between the first coil 41 and the second coil 42 in the Z direction is formed by a laminated structure of the first element insulating layer 52 and the third element insulating layer 72. Therefore, compared to a case in which the space between the first coil 41 and the second coil 42 in the Z direction is formed by an element insulating layer formed on one semiconductor substrate, it is possible to reduce the thicknesses T2, T3 of both the first element insulating layer 52 and the third element insulating layer 72. Therefore, both the first semiconductor substrate 51 and the third semiconductor substrate 71 are less likely to warp.

[0110] Furthermore, the space between the third coil 43 and the fourth coil 44 in the Z direction is formed by the second element insulating layer 62 and the third element insulating layer 72. Therefore, compared to a case in which the space between the third coil 43 and the fourth coil 44 in the Z direction is formed by one element insulating layer, the thicknesses T2, T3 of both the second element insulating layer 62 and the third element insulating layer 72 can be made thinner. Therefore, both the second semiconductor substrate 61 and the third semiconductor substrate 71 are less likely to warp.

[0111] (1-2) The first unit 50 includes a first pad 55 electrically connected to the first coil 41. The first pad 55 is located on the opposite side of the third unit 70 from the second unit 60 in the X direction. The first pad 55 is exposed from the first element insulating layer 52 in the Z direction.

[0112] According to this configuration, since the first pad 55 is exposed from the first element insulating layer 52 at a position away from the third unit 70, the wire W1 can be easily connected to the first pad 55.

[0113] (1-3) The first unit 50 includes a first wiring 56A electrically connected to the first coil 41, and a second wiring 57A connecting the first wiring 56A and the first pad 55. According to this configuration, since the first pad 55 is provided on the first element insulating layer 52, the dimension of the second wiring 57A in the Z direction can be reduced. In other words, the number of insulating films of the first element insulating layer 52 for forming the second wiring 57A can be reduced compared to a case where the space between the first coil 41 and the second coil 42 is constituted by an element insulating layer formed on one semiconductor substrate. Therefore, the number of metal masks for forming the second wiring 57A can also be reduced. Therefore, the manufacturing cost of the first unit 50 can be reduced.

[0114] (1-4) The second unit 60 includes a second pad 65 electrically connected to the fourth coil 44. The second pad 65 is located on the opposite side of the third unit 70 from the first unit 50 in the X direction. The second pad 65 is exposed from the second element insulating layer 62 in the Z direction.

[0115] According to this configuration, since the second pad 65 is exposed from the second element insulating layer 62 at a position away from the third unit 70, the wire W2 can be easily connected to the second pad 65.

[0116] (1-5) The second unit 60 includes a first wiring 66A electrically connected to the fourth coil 44, and a second wiring 67A connecting the first wiring 66A and the second pad 65. According to this configuration, since the second pad 65 is provided on the second element insulating layer 62, the dimension of the second wiring 67A in the Z direction can be reduced. In other words, the number of insulating films of the second element insulating layer 62 for forming the second wiring 67A can be reduced compared to the case where the space between the third coil 43 and the fourth coil 44 is constituted by an element insulating layer formed on one semiconductor substrate. Therefore, the number of metal masks for forming the second wiring 67A can also be reduced. Therefore, the manufacturing cost of the second unit 60 can be reduced.

[0117] (1-6) The third element surface 72S of the third element insulating layer 72 of the third unit 70 contacts both the first element surface 52S of the first element insulating layer 52 of the first unit 50 and the second element surface 62S of the second element insulating layer 62 of the second unit 60. The second coil 42 and the third coil 43 of the third unit 70 are in an electrically floating state.

[0118] According to this configuration, the third unit 70 is merely disposed relative to the first unit 50 and the second unit 60, and is not joined to the first unit 50 and the second unit 60. Therefore, there is a risk that the position of the third unit 70 may be shifted relative to the first unit 50 and the second unit 60 during resin molding.

[0119] In this regard, since the second coil 42 and the third coil 43 of the third unit 70 are in an electrically floating state, even if the position of the third unit 70 is shifted relative to the first unit 50 and the second unit 60 during resin molding, it is permissible since there is no electrical connection as long as the first coil 41 and the second coil 42 are within a range in which they can be magnetically coupled, and the third coil 43 and the fourth coil 44 are within a range in which they can be magnetically coupled. Therefore, it is not necessary to determine the position of the third unit 70 with high precision relative to the first unit 50 and the second unit 60. This makes it possible to easily manufacture the semiconductor device 10.

[0120] (1-7) The first unit 50 includes a first circuit 20. The second unit 60 includes a second circuit 30. According to this configuration, the number of semiconductor chips can be reduced compared to a configuration in which a dedicated semiconductor chip for the first circuit 20 and a dedicated semiconductor chip for the second circuit 30 are provided in addition to the first to third units 50, 60, and 70. Therefore, the semiconductor device 10 can be made smaller and less expensive.

[0121] (1-8) The first circuit 20 includes a transmitting circuit 21 electrically connected to the first coil 41. The second circuit 30 includes a receiving circuit 31 electrically connected to the fourth coil 44. The transmitting circuit 21 is disposed at a position overlapping the first coil 41 in a planar view. The receiving circuit 31 is disposed at a position overlapping the fourth coil 44 in a planar view.

[0122] According to this configuration, the length of the conductive path between the first coil 41 and the transmission circuit 21 can be shortened. Therefore, the inductance caused by the length of this conductive path can be reduced. Also, the length of the conductive path between the fourth coil 44 and the reception circuit 31 can be shortened. Therefore, the inductance caused by the length of this conductive path can be reduced.

[0123] (1-9) Distance D3 between first coil 41 and fourth coil 44 in the X direction is equal to or greater than distance D1 between first coil 41 and second coil 42 in the Z direction, and is equal to or greater than distance D2 between third coil 43 and fourth coil 44 in the Z direction. This configuration can suppress a decrease in the breakdown voltage of semiconductor device 10, compared to a case in which distance D3 is smaller than distances D1 and D2.

[0124] (1-10) A first unit 50 including a first coil 41, a second unit 60 including a fourth coil 44, and a third unit 70 including a second coil 42 and a third coil 43 are provided separately.

[0125] According to this configuration, for example, by changing the number of insulating films in the third element insulating layer 72 of the third unit 70, it is possible to manufacture a plurality of types of semiconductor devices 10 having different withstand voltages. Therefore, it is possible to easily provide a variety of semiconductor devices 10 having different withstand voltages.

[0126] (1-11) The first coil 41 is disposed closer to the second unit 60 than the center in the X direction of the first element insulating layer 52. The fourth coil 44 is disposed closer to the first unit 50 than the center in the X direction of the second element insulating layer 62.

[0127] According to this configuration, by reducing the distance D3 between the first coil 41 and the fourth coil 44 in the X direction, it is possible to reduce the distance in the X direction between the second coil 42 arranged to face the first coil 41 in the Z direction and the third coil 43 arranged to face the fourth coil 44 in the Z direction. This makes it possible to reduce the size of the third unit 70 in the X direction.

[0128] <Second embodiment> A semiconductor device 10 of the second embodiment will be described with reference to Figs. 11 and 12. The semiconductor device 10 of the second embodiment is different from the semiconductor device 10 of the first embodiment mainly in the configuration of the third coil 43 and the fourth coil 44 of the third unit 70. In the following description, differences from the first embodiment will be described in detail, and components common to the first embodiment will be given the same reference numerals and their description will be omitted. Fig. 11 shows a schematic planar structure of the third unit 70. Fig. 12 shows a schematic cross-sectional structure of the semiconductor device 10 cut along the line F12-F12 in Fig. 11.

[0129] 11, both the second coil 42 and the third coil 43 in the third unit 70 are formed into an open ring shape in a plan view. The second coil 42 opens toward the third coil 43 in the X direction. The third coil 43 opens toward the second coil 42 in the X direction. Here, the second coil 42 is an example of a "coil of a third insulating element," and the third coil 43 is an example of a "coil of a fourth insulating element."

[0130] The second coil 42 includes a first coil end 42A and a second coil end 42B that are spaced apart from each other. In one example, the first coil end 42A and the second coil end 42B are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction.

[0131] The third coil 43 includes a third coil end 43A and a fourth coil end 43B spaced apart from each other. In one example, the third coil end 43A and the fourth coil end 43B are arranged at the same position in the X direction and spaced apart from each other in the Y direction. The third coil end 43A is disposed at a position facing the first coil end 42A in the X direction. The fourth coil end 43B is disposed at a position facing the second coil end 42B in the X direction.

[0132] The third unit 70 includes a connection wiring 110 that connects the second coil 42 and the third coil 43. As shown in Fig. 12, the second coil 42, the third coil 43, and the connection wiring 110 are disposed at the same positions as each other in the Z direction.

[0133] 11, the connection wiring 110 includes a first connection wiring 111 that connects the first coil end 42A of the second coil 42 and the third coil end 43A of the third coil 43, and a second connection wiring 112 that connects the second coil end 42B of the second coil 42 and the fourth coil end 43B of the third coil 43. Both the first connection wiring 111 and the second connection wiring 112 extend in the X direction in a plan view. The first connection wiring 111 and the second connection wiring 112 are arranged to be spaced apart from each other in the Y direction.

[0134] Because the second coil 42 is formed by a single open annular loop, the number of turns of the second coil 42 is less than the number of turns of the first coil 41. Because the third coil 43 is formed by a single open annular loop, the number of turns of the third coil 43 is less than the number of turns of the fourth coil 44.

[0135] [effect] According to the semiconductor device 10 of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0136] (2-1) The third unit 70 includes a connection wiring 110 that connects the second coil 42 and the third coil 43. The second coil 42, the third coil 43, and the connection wiring 110 are disposed at the same positions as each other in the Z direction.

[0137] This configuration makes it possible to reduce the number of insulating layers in the third element insulating layer 72 of the third unit 70, compared to a configuration in which the connection wiring 110 is provided in an insulating layer different from the second coil 42 and the third coil 43. This makes it possible to reduce the height and cost of the semiconductor device 10.

[0138] <Modification of the second embodiment> Next, as a modification of the semiconductor device 10 of the second embodiment, a modification of the configuration of the third coil 43 and the fourth coil 44 will be described with reference to Fig. 13 and Fig. 14. Fig. 13 and Fig. 14 both show schematic planar structures of the second coil 42, the third coil 43, and the connection wiring 110.

[0139] As shown in FIG. 13, the second coil 42 includes a plurality of first concentric coils 42C formed in a concentric circle shape. Each of the first concentric coils 42C is formed in an open annular shape. Each of the plurality of first concentric coils 42C includes a first coil end 42A and a second coil end 42B spaced apart from each other. Each of the first concentric coils 42C opens toward the third coil 43 in the X direction. The plurality of first coil ends 42A are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The plurality of second coil ends 42B are arranged at a distance from the plurality of first coil ends 42A in the Y direction. The plurality of second coil ends 42B are arranged at the same position in the Y direction and spaced apart from each other in the X direction.

[0140] The third coil 43 includes a plurality of second concentric coils 43C formed in a concentric circle shape. Each of the second concentric coils 43C is formed in an open annular shape. Each of the plurality of second concentric coils 43C includes a third coil end 43A and a fourth coil end 43B that are spaced apart from each other. Each of the second concentric coils 43C opens toward the second coil 42 in the X direction. The plurality of third coil ends 43A are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The plurality of fourth coil ends 43B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The plurality of third coil ends 43A are arranged at the same position in the Y direction as the plurality of first coil ends 42A. The plurality of fourth coil ends 43B are arranged at the same position in the Y direction as the plurality of second coil ends 42B.

[0141] The first connection wiring 111 commonly connects the multiple first coil ends 42A and the multiple third coil ends 43A. The first connection wiring 111 extends in the X direction. The second connection wiring 112 commonly connects the multiple second coil ends 42B and the multiple fourth coil ends 43B. The second connection wiring 112 extends in the X direction. With this configuration, the number of turns of the second coil 42 and the number of turns of the third coil 43 can be increased, and the effect of the second embodiment can also be obtained.

[0142] As shown in Fig. 14, the second coil 42 includes a plurality of first concentric coils 42C, similar to the second coil 42 shown in Fig. 13. The third coil 43 includes a plurality of second concentric coils 43C, similar to the third coil 43 shown in Fig. 13.

[0143] The connection wiring 110 includes a plurality of first connection wirings 111 and a plurality of second connection wirings 112. The plurality of first connection wirings 111 individually connect the plurality of first coil ends 42A and the plurality of third coil ends 43A. The plurality of second connection wirings 112 individually connect the plurality of second coil ends 42B and the plurality of fourth coil ends 43B. Each of the first connection wirings 111 and each of the second connection wirings 112 extends in the X direction. According to this configuration, the number of turns of the second coil 42 and the number of turns of the third coil 43 can be increased, and the effect of the second embodiment can also be obtained. Note that the number of the plurality of first concentric coils 42C and the number of the plurality of second concentric coils 43C is not limited to the example shown in FIG. 13 and FIG. 14, and can be changed arbitrarily.

[0144] <Third embodiment> A semiconductor device 10 of the third embodiment will be described with reference to Figures 15 to 17. The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in that a positioning section 120 that positions the third unit 70 relative to the first unit 50 and the second unit 60 is added. In the following description, differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

[0145] Fig. 15 is a schematic diagram showing a planar structure of the semiconductor device 10 of the third embodiment. Fig. 16 is a schematic diagram showing a cross-sectional structure of the semiconductor device 10 taken along line F16-F16 in Fig. 15. Fig. 17 is a schematic diagram showing a cross-sectional structure in a state in which the third unit 70 and the first unit 50 are separated from each other.

[0146] 15, the positioning portions 120 are provided at the four corners of the third unit 70. That is, the positioning portions 120 are provided outward from the first to fourth coils 41 to 44 in a plan view. As shown in FIGS. 16 and 17, the positioning portions 120 are composed of recesses 121 provided in both the first unit 50 and the second unit 60, and bumps 122 provided on the third unit 70.

[0147] 16, the recesses 121 of the first unit 50 are provided so as to penetrate the first passivation film 54 of the first unit 50 in the Z direction. The recesses 121 of the first unit 50 are provided at positions corresponding to two of the four corners of the third unit 70 in the unit arrangement state.

[0148] The recesses 121 of the second unit 60 are provided so as to penetrate the second passivation film 64 of the second unit 60 in the Z direction. The recesses 121 of the second unit 60 are provided at positions corresponding to two of the four corners of the third unit 70 other than the ones corresponding to the first unit 50 in the unit arrangement state.

[0149] 15, the bumps 122 of the third unit 70 are provided at the four corners of the third unit 70 in a plan view. As shown in FIG. 17, the bumps 122 are formed in a columnar shape, such as a cylindrical shape or a rectangular columnar shape. The bumps 122 are attached to the third unit 70 so as to penetrate the third passivation film 74 in the Z direction, for example. The bumps 122 protrude in the Z direction from the third element surface 72S of the third element insulating layer 72. The multiple bumps 122 are inserted in a distributed manner into the recesses 121 of the first unit 50 and the recesses 121 of the second unit 60.

[0150] The bumps 122 may be made of a metal material such as Cu, Al, etc. In this case, the bumps 122 are in an electrically floating state. Note that the material of the bumps 122 may be an insulating material such as a resin material or ceramic, instead of a metal material.

[0151] [effect] According to the semiconductor device 10 of the third embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0152] (3-1) The first unit 50, the second unit 60, and the third unit 70 are provided with a positioning unit 120 that determines the position of the third unit 70 relative to the first unit 50 and the second unit 60. According to this configuration, the positioning unit 120 makes it possible to easily position the third unit 70 relative to the first unit 50 and the second unit 60 at a preset position.

[0153] (3-2) The positioning portion 120 is constituted by recesses 121 provided in both the first unit 50 and the second unit 60, and bumps 122 provided in the third unit .

[0154] According to this configuration, the bumps 122 of the third unit 70 are fitted into the recesses 121 of both the first unit 50 and the second unit 60, so that the third unit 70 can be easily disposed at a preset position relative to the first unit 50 and the second unit 60. In addition, since the movement of the bumps 122 in the recesses 121 in a direction perpendicular to the Z direction is restricted, for example, in the step of forming the sealing resin 100, the resin material forming the sealing resin 100 can suppress the movement of the third unit 70 in a direction perpendicular to the Z direction relative to the first unit 50 and the second unit 60.

[0155] <Modification of the third embodiment> Next, modified examples of the semiconductor device 10 of the third embodiment will be described with reference to Figs. 18 to 21. Fig. 18 shows a schematic planar structure of the semiconductor device 10 of a first modified example. Fig. 19 shows a schematic cross-sectional structure of the semiconductor device 10 cut along line F19-F19 in Fig. 18. Fig. 20 shows a schematic planar structure of the semiconductor device 10 of a second modified example in a state where the third unit 70 is omitted. Fig. 21 shows a schematic cross-sectional structure of the semiconductor device 10 cut along line F21-F21 in Fig. 20, showing a cross-sectional structure in a state where the third unit 70 is separated from the first unit 50 and the second unit 60.

[0156] As shown in Figures 18 and 19, in the first modified example semiconductor device 10, the positioning portion 120 is composed of a positioning mark 123 formed on both the first element surface 52S of the first element insulating layer 52 of the first unit 50 and the second element surface 62S of the second element insulating layer 62 of the second unit 60.

[0157] As shown in Fig. 18, four positioning marks 123 are provided corresponding to the four corners of the third unit 70. Each positioning mark 123 is formed in an L-shape surrounding the side surface of the third unit 70 in a plan view. The positioning marks 123 are formed of a metal material such as Cu or Al. The positioning marks 123 are formed on the first passivation film 54 of the first unit 50 and the second passivation film 64 of the second unit 60 by, for example, sputtering. As shown in Fig. 19, the positioning marks 123 contact the side surfaces of the third unit 70 in the unit arrangement state.

[0158] According to this configuration, when the third unit 70 is arranged on the first unit 50 and the second unit 60, the third unit 70 is arranged so as to align with the positioning marks 123, for example, by image processing. This allows the third unit 70 to be accurately arranged with respect to the first unit 50 and the second unit 60. In addition, since the positioning marks 123 are in contact with the side surfaces of the third unit 70 in the unit arrangement state, for example, in the step of forming the sealing resin 100, it is possible to prevent the third unit 70 from moving with respect to the first unit 50 and the second unit 60 due to the resin material forming the sealing resin 100.

[0159] Note that, although the positioning marks 123 are provided on both the first unit 50 and the second unit 60, this is not limited to the above. In one example, the two positioning marks 123 on the second unit 60 may be omitted. In one example, the two positioning marks 123 on the first unit 50 may be omitted. In one example, one of the two positioning marks 123 on the first unit 50 and one of the two positioning marks 123 on the second unit 60 may be omitted.

[0160] 20 and 21, in the semiconductor device 10 of the second modified example, the positioning portion 120 is configured by cutting out both the first passivation film 54 of the first unit 50 and the second passivation film 64 of the second unit 60 to match the third unit 70. More specifically, as shown in Fig. 20, the first passivation film 54 includes a first cutout portion 124A as the positioning portion 120. The second passivation film 64 includes a second cutout portion 124B as the positioning portion.

[0161] The first cutout 124A and the second cutout 124B are formed in a rectangular shape to match the side surface of the third unit 70 in a plan view. The first cutout 124A is formed in a portion closer to the second unit 60 than the center of the first unit 50 in the X direction. The first cutout 124A opens toward the second unit 60 at an end portion of the first unit 50 closer to the second unit 60 in the X direction in a plan view. The second cutout 124B is formed in a portion closer to the first unit 50 than the center of the second unit 60 in the X direction. The second cutout 124B opens toward the first unit 50 at an end portion of the second unit 60 closer to the first unit 50 in the X direction in a plan view. The first cutout 124A penetrates the first passivation film 54 in the Z direction, and therefore exposes the first protective film 53 in a plan view. The second cutout portion 124B penetrates the second passivation film 64 in the Z direction, and therefore exposes the second protective film 63 in plan view.

[0162] 21, the third unit 70 is disposed in the first cutout portion 124A and the second cutout portion 124B. Therefore, the third passivation film 74 of the third element insulating layer 72 in the third unit 70 contacts the first protective film 53 and the second protective film 63 in the unit disposed state.

[0163] According to this configuration, when the third unit 70 is disposed on the first unit 50 and the second unit 60, the third unit 70 is fitted into the first notch 124A and the second notch 124B. This allows the third unit 70 to be disposed with high precision relative to the first unit 50 and the second unit 60. In addition, since both the first passivation film 54 and the second passivation film 64 are in contact with the side surfaces of the third unit 70 in the unit disposed state, for example, in the step of forming the sealing resin 100, the third unit 70 can be prevented from moving relative to the first unit 50 and the second unit 60 by the resin material forming the sealing resin 100.

[0164] <Example of change> The above-described embodiments can be modified as follows: The following modified examples can be combined with each other as long as no technical contradiction occurs.

[0165] The second and third embodiments may be implemented in combination with each other. In the third embodiment, the number of the positioning portion 120 can be changed arbitrarily. At least one positioning portion 120 is required.

[0166] In the third embodiment, the bump 122 is provided on the third unit 70, and the recess 121 is provided on both the first unit 50 and the second unit 60, but this is not limited to the above. For example, the recess 121 may be provided on the third unit 70, and the bump 122 may be provided on both the first unit 50 and the second unit 60.

[0167] In each embodiment, the positions of the first coil 41 and the fourth coil 44 in the Z direction can be changed arbitrarily. In one example, as shown in FIG. 22, the first coil 41 may be disposed closer to the first semiconductor substrate 51 than the center of the first element insulating layer 52 in the Z direction. In other words, the first coil 41 may be disposed closer to the first element rear surface 52R than the center of the first element insulating layer 52 in the Z direction. In this case, the distance D1 between the first coil 41 and the second coil 42 in the Z direction can be set to be equal to or greater than the thickness T1 of the first element insulating layer 52. This can improve the breakdown voltage of the semiconductor device 10 compared to when the distance D1 is smaller than the thickness T1 of the first element insulating layer 52. In addition, the distance D1 can be set to be equal to or greater than the thickness T3 of the third element insulating layer 72 of the third unit 70. This can improve the breakdown voltage of the semiconductor device 10 compared to when the distance D1 is smaller than the thickness T3 of the third element insulating layer 72.

[0168] In one example, the fourth coil 44 may be disposed closer to the second semiconductor substrate 61 than the center of the second element insulating layer 62 in the Z direction. In other words, the fourth coil 44 may be disposed closer to the second element rear surface 62R than the center of the second element insulating layer 62 in the Z direction. In this case, the distance D2 between the third coil 43 and the fourth coil 44 in the Z direction can be set to be equal to or greater than the thickness T2 of the second element insulating layer 62. This can improve the breakdown voltage of the semiconductor device 10 compared to when the distance D2 is smaller than the thickness T2 of the second element insulating layer 62. In addition, the distance D2 can be set to be equal to or greater than the thickness T3 of the third element insulating layer 72 of the third unit 70. This can improve the breakdown voltage of the semiconductor device 10 compared to when the distance D2 is smaller than the thickness T3 of the third element insulating layer 72. In addition, in the modified example shown in Figure 22, any one of the configurations of the second coil 42 and the third coil 43 of the third embodiment, the configurations of the second coil 42 and the third coil 43 shown in Figure 13, and the configurations of the second coil 42 and the third coil 43 shown in Figure 14 may be applied.

[0169] In each embodiment, the positions of the first coil 41 and the fourth coil 44 in the direction perpendicular to the Z direction can be changed as desired. In one example, the first coil 41 may be disposed at the center of the first element insulating layer 52 in the X direction. In another example, the fourth coil 44 may be disposed at the center of the second element insulating layer 62 in the X direction.

[0170] In each embodiment, the positional relationship between the first coil 41 and the fourth coil 44 in the Z direction can be changed as desired. In one example, the first coil 41 may be disposed closer to the third unit 70 than the fourth coil 44 in the Z direction. The first coil 41 may be disposed at a position farther from the third unit 70 than the fourth coil 44 in the Z direction. Also, the fourth coil 44 may be disposed closer to the third unit 70 than the first coil 41 in the Z direction. The fourth coil 44 may be disposed at a position farther from the third unit 70 than the first coil 41 in the Z direction.

[0171] In each embodiment, the positional relationship between the second coil 42 and the third coil 43 in the Z direction can be changed arbitrarily. In one example, the second coil 42 may be disposed closer to the third element back surface 72R of the third element insulating layer 72 than the third coil 43 in the Z direction. The second coil 42 may be disposed closer to the third element front surface 72S of the third element insulating layer 72 than the third coil 43 in the Z direction. In one example, the third coil 43 may be disposed closer to the third element back surface 72R than the second coil 42 in the Z direction. The third coil 43 may be disposed closer to the third element front surface 72S than the second coil 42 in the Z direction.

[0172] In each embodiment, the relationship between the distance D1 between the first coil 41 and the second coil 42 in the Z direction and the distance D2 between the third coil 43 and the fourth coil 44 in the Z direction can be changed arbitrarily. In one example, the distance D1 may be greater than the distance D2, or the distance D2 may be greater than the distance D1.

[0173] In each embodiment, the positional relationship between the transmission circuit 21 and the first coil 41 of the first circuit 20 provided in the first unit 50 can be changed as desired. In one example, the transmission circuit 21 may be disposed outward of the first coil 41 in a plan view.

[0174] In each embodiment, the positional relationship between the receiving circuit 31 and the fourth coil 44 of the second circuit 30 provided in the second unit 60 can be changed as desired. In one example, the receiving circuit 31 may be disposed outward of the fourth coil 44 in a plan view.

[0175] In each embodiment, the first circuit 20 provided in the first unit 50 may include a receiving circuit instead of the transmitting circuit 21. In this case, the second circuit 30 provided in the second unit 60 may include a transmitting circuit instead of the receiving circuit 31.

[0176] In each embodiment, the first circuit 20 provided in the first unit 50 may include both a transmitting circuit 21 and a receiving circuit. The second circuit 30 provided in the second unit 60 may include both a transmitting circuit and a receiving circuit 31.

[0177] In each embodiment, the configuration of the first element insulating layer 52 of the first unit 50 can be changed as desired. In one example, the first insulating film 52P may be omitted from the first element insulating layer 52. In other words, the first element insulating layer 52 may be configured with a stacked structure of multiple second insulating films 52Q.

[0178] In each embodiment, the configuration of the second element insulating layer 62 of the second unit 60 can be changed as desired. In one example, the first insulating film 62P may be omitted from the second element insulating layer 62. In other words, the second element insulating layer 62 may be configured with a stacked structure of multiple second insulating films 62Q.

[0179] In each embodiment, the configuration of the third element insulating layer 72 of the third unit 70 can be changed as desired. In one example, the first insulating film 72P may be omitted from the third element insulating layer 72. In other words, the third element insulating layer 72 may be formed of a stacked structure of multiple second insulating films 72Q.

[0180] In each embodiment, the third unit 70 may be adhered to the first unit 50 and the second unit 60 by, for example, an adhesive. In this case, the adhesive is in contact with the third element surface 72S of the third element insulating layer 72 and the first element surface 52S of the first element insulating layer 52. The adhesive is also in contact with the third element surface 72S and the second element surface 62S of the second element insulating layer 62.

[0181] In each embodiment, the first to fourth insulating elements are not limited to the first to fourth coils 41 to 44. In one example, as shown in FIG. 23, each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element may be an electrode plate. That is, the first unit 50 includes a first electrode plate 131 instead of the first coil 41 as the first insulating element. The second unit 60 includes a fourth electrode plate 134 instead of the fourth coil 44 as the second insulating element. The third unit 70 includes a second electrode plate 132 and a third electrode plate 133 instead of the second coil 42 and the third coil 43 as the third insulating element and the fourth insulating element. In the third unit 70, the connection wiring layer 78 is disposed at the same position as the second electrode plate 132 and the third electrode plate 133 in the Z direction. For this reason, the first connection wiring 75 and the second connection wiring 76 are omitted from the third unit 70.

[0182] In the unit arrangement state, the first electrode plate 131 and the second electrode plate 132 are arranged to face each other. The first electrode plate 131 and the second electrode plate 132 form a first capacitor. In addition, in the unit arrangement state, the third electrode plate 133 and the fourth electrode plate 134 are arranged to face each other. The third electrode plate 133 and the fourth electrode plate 134 form a second capacitor.

[0183] In each embodiment, the first unit 50 may not include the first circuit 20, and the second unit 60 may not include the second circuit 30. In one example, as shown in Figures 24 and 25, the semiconductor device 10 includes a first circuit chip 140 that is a semiconductor chip dedicated to the first circuit 20, and a second circuit chip 150 that is a semiconductor chip dedicated to the second circuit 30.

[0184] The first circuit chip 140 is disposed on the first die pad 81. The second circuit chip 150 is disposed on the second die pad 91. The insulation chip 40P is disposed between the first circuit chip 140 and the second circuit chip 150 in the X direction.

[0185] 25, the first circuit chip 140 includes a semiconductor substrate 141, an element insulating layer 142 formed on the semiconductor substrate 141, and a plurality of first pads 143 and a plurality of second pads 144 formed on the element insulating layer 142. The first circuit 20 is formed on, for example, the semiconductor substrate 141. The first circuit 20 is electrically connected to a predetermined first pad 143 and a predetermined second pad 144 via a wiring layer formed on the element insulating layer 142.

[0186] 24, the first pads 143 are individually and electrically connected to the first leads 82 by wires W3. The second pads 144 are individually and electrically connected to the first pads 55 of the first unit 50 by wires W1. As a result, the first coil 41 (see FIG. 3) is electrically connected to the first circuit 20.

[0187] 25, the second circuit chip 150 includes a semiconductor substrate 151, an element insulating layer 152 formed on the semiconductor substrate 151, and a first pad 153 and a second pad 154 formed on the element insulating layer 152. The second circuit 30 is formed on, for example, the semiconductor substrate 151. The second circuit 30 is electrically connected to the first pad 153 and the second pad 154 via a wiring layer formed on the element insulating layer 152.

[0188] 24, the first pads 153 are individually and electrically connected to the second leads 92 by wires W4. The second pads 154 are individually and electrically connected to the second pads 65 of the second unit 60 by wires W2. As a result, the fourth coil 44 (see FIG. 3) is electrically connected to the second circuit 30.

[0189] In each embodiment, the second unit 60 does not have to include the second circuit 30. In one example, as shown in Fig. 26, the semiconductor device 10 includes an insulating chip 40P and a second circuit chip 150 that is a semiconductor chip dedicated to the second circuit 30. The second circuit chip 150 has the same configuration as the second circuit chip 150 in Figs. 24 and 25.

[0190] In each embodiment, the first unit 50 does not have to include the first circuit 20. In one example, as shown in Fig. 27, the semiconductor device 10 includes an insulating chip 40P and a first circuit chip 140 that is a semiconductor chip dedicated to the first circuit 20. The first circuit chip 140 has the same configuration as the first circuit chip 140 in Figs. 24 and 25.

[0191] In each embodiment and each modified example, the semiconductor device 10 is embodied as a signal transmission device, but is not limited thereto. For example, the semiconductor device 10 may be embodied as a power transmission device that transmits power. In this case, the semiconductor device 10 is electrically connected to, for example, a DC power source. The first circuit 20 of the semiconductor device 10 includes, for example, an inverter circuit and a control circuit that controls the inverter circuit. The second circuit 30 includes, for example, a rectifier circuit and a capacitor. In the semiconductor device 10, the inverter circuit converts the power of the DC power source into AC power and outputs it to the transformers 40A, 40B (capacitors 120A, 120B). The AC power is converted into DC power by being input to the rectifier circuit via the transformers 40A, 40B (capacitors 120A, 120B). Then, the DC power is supplied to a load electrically connected to the semiconductor device 10.

[0192] One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0193] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this specification being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0194] <Additional Notes> The technical ideas that can be understood from this disclosure are described below. Note that the reference numerals of the components of the embodiment corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0195] [Appendix 1] A first unit (50) and a second unit (60) arranged apart from each other in a first direction (X direction); a third unit (70) disposed above the first unit (50) and above the second unit (60) so as to straddle the first direction (X direction) between the first unit (50) and the second unit (60); Equipped with The first unit (50) comprises: A first semiconductor substrate (51); a first element insulating layer (52) including a first element front surface (52S) facing the third unit (70) and a first element back surface (52R) opposite to the first element front surface (52S), the first element back surface (52R) being in contact with the first semiconductor substrate (51); a first insulating element (41) embedded in the first element insulating layer (52) at a position spaced apart from the first element surface (52S) in a thickness direction (Z direction) of the first element insulating layer (52); Including, The second unit (60) comprises: A second semiconductor substrate (61); a second element insulating layer (62) including a second element front surface (62S) facing the third unit (70) and a second element back surface (62R) opposite to the second element front surface (62S), the second element back surface (62R) being in contact with the second semiconductor substrate (61); a second insulating element (44) embedded in the second element insulating layer (62) at a position spaced apart from the second element surface (62S) in a thickness direction (Z direction) of the second element insulating layer (62); Including, The third unit (70) comprises: A third semiconductor substrate (71); a third element insulating layer (72) including a third element front surface (72S) and a third element back surface (72R) opposite to the third element front surface (72S), the third element back surface (72R) being in contact with the third semiconductor substrate (71); a third insulating element (42) and a fourth insulating element (43) embedded in the third element insulating layer (72) at a position spaced apart from the third element surface (72S) in a thickness direction (Z direction) of the third element insulating layer (72), arranged at a distance from each other in the first direction (X direction) and electrically connected to each other; Including, In a unit arrangement state in which the third element insulating layer (72) of the third unit (70) is arranged on both the first element insulating layer (52) of the first unit (50) and the second element insulating layer (62) of the second unit (60), the first insulating element (41) and the third insulating element (42) are arranged opposite each other in the thickness direction (Z direction) of the first element insulating layer (52), and the second insulating element (44) and the fourth insulating element (43) are arranged opposite each other in the thickness direction (Z direction) of the second element insulating layer (62). Insulated tip(40P).

[0196] [Appendix 2] At least one of the first unit (50), the second unit (60), and the third unit (70) is provided with a positioning portion (120) that determines the position of the third unit (70) relative to the first unit (50) and the second unit (60). 2. The insulated tip of claim 1.

[0197] [Appendix 3] The positioning portion (120) is constituted by one of a bump (122) and a recess (121) provided on at least one of the first unit (50) and the second unit (60), and the other of the bump (122) and the recess (121) provided on the third unit (70). 2. An insulated tip as described in appended claim 2.

[0198] [Appendix 4] The positioning portion (120) is constituted by a positioning mark (123) formed on at least one of the first element surface (52S) of the first unit (50) and the second element surface (62S) of the second unit (60). 2. An insulated tip as described in appended claim 2.

[0199] [Appendix 5] the first element insulating layer (52) includes a first passivation film (54) constituting the first element surface (52S); the second element insulating layer (62) includes a second passivation film (64) constituting the second element surface (62S); The positioning portion (120) is configured by cutting out both the first passivation film (54) and the second passivation film (64) to fit the third unit (70). 2. An insulated tip as described in appended claim 2.

[0200] [Appendix 6] the third unit (70) includes a connection wiring (110) that connects the third insulating element (42) and the fourth insulating element (43), The third insulating element (42), the fourth insulating element (43), and the connection wiring (110) are disposed at the same position as one another in the thickness direction (Z direction) of the third element insulating layer (72). 6. An insulating tip according to any one of claims 1 to 5.

[0201] [Appendix 7] the third insulating element (42) includes a coil (42) formed in an open annular shape including a first coil end (42A) and a second coil end (42B) spaced apart from each other, the fourth insulating element (43) includes a coil (43) formed in an open annular shape including a third coil end (43A) and a fourth coil end (43B) spaced apart from each other, The connection wiring (110) is a first connection wiring (111) that connects the first coil end (42A) and the third coil end (43A); a second connection wiring (112) that connects the second coil end (42B) and the fourth coil end (43B); Includes 7. The insulated tip of claim 6.

[0202] [Appendix 8] The third insulating element (42) includes a first concentric coil (42C) formed into a plurality of open annular shapes formed concentrically, The fourth insulating element (43) includes a second concentric coil (43C) formed into a plurality of open annular shapes formed concentrically, Each of the plurality of first concentric coils (42C) includes a first coil end (42A) and a second coil end (42B) spaced apart from each other, Each of the plurality of second concentric coils (42C) includes a third coil end (43A) and a fourth coil end (43B) spaced apart from each other, The connection wiring (110) is a first connection wiring (111) that commonly connects the plurality of first coil ends (42A) and the plurality of third coil ends (43A); a second connection wiring (112) commonly connecting the second coil ends (42B) and the fourth coil ends (43B); Includes 7. The insulated tip of claim 6.

[0203] [Appendix 9] The third insulating element (42) includes a first concentric coil (42C) formed into a plurality of open annular shapes formed concentrically, The fourth insulating element (43) includes a second concentric coil (43C) formed into a plurality of open annular shapes formed concentrically, Each of the plurality of first concentric coils (42C) includes a first coil end (42A) and a second coil end (42B) spaced apart from each other, Each of the plurality of second concentric coils (43C) includes a third coil end (43A) and a fourth coil end (43B) spaced apart from each other, The connection wiring (110) is a plurality of first connection wirings (111) that individually connect the plurality of first coil ends (42A) and the plurality of third coil ends (43A); a plurality of second connection wirings (112) that individually connect the plurality of second coil ends (42B) and the plurality of fourth coil ends (43B); Includes 7. The insulated tip of claim 6.

[0204] [Appendix 10] The first unit (50) includes a first pad (55) electrically connected to the first insulating element (41), The first pad (55) is located on the opposite side of the third unit (70) to the second unit (60) in the first direction (X direction), and is exposed from the first element insulating layer (52) in the thickness direction (Z direction) of the first element insulating layer (52). 10. An insulating tip according to any one of claims 1 to 9.

[0205] [Appendix 11] The distance between the first pad (55) and the third insulating element (42) is greater than the distance (D1) between the first insulating element (41) and the third insulating element (42) in the thickness direction (Z direction) of the first element insulating layer (52). 11. The insulated tip of claim 10.

[0206] [Appendix 12] the second unit (60) includes a second pad (65) electrically connected to the second insulating element (44); The second pad (65) is located on the opposite side of the third unit (70) to the first unit (50) in the first direction (X direction), and is exposed from the second element insulating layer (62) in the thickness direction (Z direction) of the second element insulating layer (62). 12. An insulating tip according to any one of claims 1 to 11.

[0207] [Appendix 13] The distance between the second pad (65) and the fourth insulating element (43) is greater than the distance (D2) between the second insulating element (44) and the fourth insulating element (43) in the thickness direction (Z direction) of the second element insulating layer (62). 13. The insulated tip of claim 12.

[0208] [Appendix 14] The first unit (50) includes a first circuit (20), The second unit (60) includes a second circuit (30). 14. An insulating tip according to any one of claims 1 to 13.

[0209] [Appendix 15] the first circuit (20) includes a transmitting circuit (21) or a receiving circuit electrically connected to the first insulating element (41); The second circuit (30) includes a transmitting circuit or a receiving circuit (31) electrically connected to the second insulating element (44). 15. The insulated tip of claim 14.

[0210] [Appendix 16] the transmission circuit (21) or the reception circuit of the first circuit (20) is disposed at a position overlapping with the first insulation element (41) when viewed from a thickness direction (Z direction) of the first element insulation layer (52), The transmitting circuit or the receiving circuit (31) of the second circuit (30) is disposed at a position overlapping the second insulating element (44) when viewed from the thickness direction (Z direction) of the second element insulating layer (62). 16. The insulated tip of claim 15.

[0211] [Appendix 17] Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is a coil (41 to 44). 17. An insulating tip according to any one of claims 1 to 16.

[0212] [Appendix 18] Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is an electrode plate (131 to 134). 17. An insulating tip according to any one of claims 1 to 16.

[0213] [Appendix 19] A semiconductor device (10) including an insulating chip (40P) according to any one of claims 1 to 18, a first die pad (81) that supports the first unit (50); a second die pad (91) disposed apart from the first die pad (81) in the first direction (X direction) and supporting the second unit (60); a sealing resin (100) that seals the first die pad (81), the second die pad (91), the first unit (50), the second unit (60), and the third unit (70); 13. A semiconductor device comprising:

[0214] [Appendix 20] A distance (D1) between the first insulating element (41) and the third insulating element (42) in a thickness direction (Z direction) of the first element insulating layer (52) is equal to or greater than a thickness (T1) of the first element insulating layer (52). 19. An insulating tip according to any one of claims 1 to 18.

[0215] [Appendix 21] A distance (D2) between the second insulating element (44) and the fourth insulating element (43) in a thickness direction (Z direction) of the second element insulating layer (62) is equal to or greater than a thickness (T2) of the second element insulating layer (62). 19. An insulating tip according to any one of claims 1 to 18.

[0216] [Appendix 22] A distance (D1) between the first insulating element (41) and the third insulating element (42) in a thickness direction (Z direction) of the first element insulating layer (52) is equal to or greater than a thickness (T3) of the third element insulating layer (72). 19. An insulating tip according to any one of claims 1 to 18.

[0217] [Appendix 23] A distance (D2) between the second insulating element (44) and the fourth insulating element (43) in a thickness direction (Z direction) of the second element insulating layer (62) is equal to or greater than a thickness (T3) of the third element insulating layer (72). 19. An insulating tip according to any one of claims 1 to 18.

[0218] [Appendix 24] In the thickness direction (Z direction) of the first element insulating layer (52), the first insulating element (41) is disposed closer to the first element rear surface (52R) than to the center of the first element insulating layer (52). 21. The insulated tip of claim 20.

[0219] [Appendix 25] In the thickness direction (Z direction) of the second element insulating layer (62), the second insulating element (44) is disposed closer to the second element rear surface (52R) than the center of the second element insulating layer (62). 22. The insulated tip of claim 21.

[0220] [Appendix 26] In the thickness direction (Z direction) of the third element insulating layer (72), both the third insulating element (42) and the fourth insulating element (43) are disposed closer to the third element rear surface (72R) than to the center of the third element insulating layer (72). 24. The insulated tip of claim 22 or 23.

[0221] [Appendix 27] A distance (D1) between the first insulating element (41) and the third insulating element (42) and a distance (D2) between the second insulating element (44) and the fourth insulating element (43) are equal to each other. 19. An insulating tip according to any one of claims 1 to 18.

[0222] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0223] 10...Semiconductor device 20...1st circuit 21...Transmitting circuit 30…Second circuit 31...Receiver circuit 40...Trans 40A…First transformer 40B…Second transformer 40P…insulating tip 41~44: 1st to 4th coils 42A…First coil end 42B…Second coil end 42C…First concentric coil 43A…Third coil end 43B…Fourth coil end 43C…Second concentric coil 50…1st unit 51...first semiconductor substrate 52...first element insulating layer 52S…First element surface 52R…Back side of first element 52P…First insulating film 52Q…Second insulating film 52T…insulator 53…First protective film 54…First passivation film 55…First pad 56A, 56B…First wiring 57A~57C…Second wiring 60…Second Unit 61...second semiconductor substrate 62...Second element insulating layer 62S: Second element surface 62R…Second element back side 62P…First insulating film 62Q…Second insulating film 62T…Insulator 63…Second protective film 64…Second passivation film 65…Second pad 66A, 66B…First wiring 67A~67C…Second wiring 70…3rd Unit 71...Third semiconductor substrate 72...Third element insulating layer 72S…Third element surface 72R…3rd element back side 72P…First insulating film 72Q…Second insulating film 72T…Insulator 73…Third protective film 74…Third passivation film 75…First connection wire 75A…1st wiring section 75B…First via 75C…Second via 76…Second connection wire 78…Connection wiring layer 80…First lead frame 81…First die pad 82…1st lead 90…2nd lead frame 91…Second die pad 92…2nd lead 100…Sealing resin 101~104…Sealing side 110…Connection wiring 111…First connection wire 112…Second connection wire 120... Positioning part 121…Recess 122…Bump 123... Positioning mark 124A…First notch 124B…Second notch 131~134...1st~4th electrode plate 140…First circuit chip 141...Semiconductor substrate 142...element insulating layer 143…First pad 144…Second pad 150…Second circuit chip 151...Semiconductor substrate 152...element insulating layer 153…First pad 154…Second pad D1: Distance between the first and second coils D2: Distance between the third and fourth coils D3: Distance between the 1st and 4th coils T1: Thickness of the first element insulating layer T2: Thickness of the second element insulating layer T3: Thickness of the third element insulating layer

Claims

1. a first unit and a second unit arranged apart from each other in a first direction; a third unit disposed above the first unit and above the second unit so as to straddle the first direction between the first unit and the second unit; Equipped with The first unit is A first semiconductor substrate; a first element insulating layer including a first element front surface facing the third unit and a first element back surface opposite to the first element front surface, the first element back surface being in contact with the first semiconductor substrate; a first insulating element embedded in the first element insulating layer at a position spaced apart from a surface of the first element in a thickness direction of the first element insulating layer; Including, The second unit is A second semiconductor substrate; a second element insulating layer including a second element front surface facing the third unit and a second element back surface opposite to the second element front surface, the second element back surface being in contact with the second semiconductor substrate; a second insulating element embedded in the second element insulating layer at a position spaced apart from a surface of the second element in a thickness direction of the second element insulating layer; Including, The third unit is A third semiconductor substrate; a third element insulating layer including a third element front surface and a third element back surface opposite to the third element front surface, the third element back surface being in contact with the third semiconductor substrate; a third insulating element and a fourth insulating element embedded in the third element insulating layer at a position spaced apart from a surface of the third element in a thickness direction of the third element insulating layer, arranged at a distance from each other in the first direction, and electrically connected to each other; Including, In a unit arrangement state in which the third element insulating layer of the third unit is arranged on both the first element insulating layer of the first unit and the second element insulating layer of the second unit, the first insulating element and the third insulating element are arranged opposite to each other in the thickness direction of the first element insulating layer, and the second insulating element and the fourth insulating element are arranged opposite to each other in the thickness direction of the second element insulating layer. Insulated tip.

2. At least one of the first unit, the second unit, and the third unit is provided with a positioning portion that determines the position of the third unit relative to the first unit and the second unit. The insulating tip of claim 1 .

3. The positioning portion is constituted by one of a bump and a recess provided on at least one of the first unit and the second unit, and the other of the bump and the recess provided on the third unit. The insulating tip of claim 2.

4. The positioning portion is configured by a positioning mark formed on at least one of the first element surface of the first unit and the second element surface of the second unit. The insulating tip of claim 2.

5. the first element insulating layer includes a first passivation film constituting the first element surface; the second element insulating layer includes a second passivation film constituting the second element surface; The positioning portion is configured by cutting out both the first passivation film and the second passivation film in accordance with the third unit. The insulating tip of claim 2.

6. the third unit includes a connection wiring that connects the third isolation element and the fourth isolation element, The third insulating element, the fourth insulating element, and the connection wiring are disposed at the same positions as one another in a thickness direction of the third element insulating layer. The insulating tip of claim 1 .

7. the third insulating element includes a coil formed into an open annular shape including first and second coil ends spaced apart from one another; the fourth insulating element includes a coil formed into an open annular shape including a third coil end and a fourth coil end spaced apart from one another; The connection wiring is a first connection wiring that connects the first coil end and the third coil end; a second connection wiring that connects the second coil end and the fourth coil end; Includes The insulating tip of claim 6.

8. the third insulating element includes a first concentric coil formed into a plurality of open annular rings formed concentrically; the fourth insulating element includes a second concentric coil formed into a plurality of open annular rings formed concentrically; each of the plurality of first concentric coils includes a first coil end and a second coil end spaced apart from one another; each of the plurality of second concentric coils includes a third coil end and a fourth coil end spaced apart from one another; The connection wiring is a first connection wiring that commonly connects the first coil ends and the third coil ends; a second connection wiring that commonly connects the second coil ends and the fourth coil ends; Includes The insulating tip of claim 6.

9. the third insulating element includes a first concentric coil formed into a plurality of open annular rings formed concentrically; the fourth insulating element includes a second concentric coil formed into a plurality of open annular rings formed concentrically; each of the plurality of first concentric coils includes a first coil end and a second coil end spaced apart from one another; each of the plurality of second concentric coils includes a third coil end and a fourth coil end spaced apart from one another; The connection wiring is a plurality of first connection wirings that individually connect the plurality of first coil ends and the plurality of third coil ends; a plurality of second connection wirings that individually connect the second coil ends and the fourth coil ends; Includes The insulating tip of claim 6.

10. the first unit includes a first pad electrically connected to the first insulating element; The first pad is located on the opposite side of the third unit from the second unit in the first direction, and is exposed from the first element insulating layer in a thickness direction of the first element insulating layer. The insulating tip of claim 1 .

11. The distance between the first pad and the third insulating element is greater than the distance between the first insulating element and the third insulating element in the thickness direction of the first element insulating layer. The insulating tip of claim 10.

12. the second unit includes a second pad electrically connected to the second insulating element; The second pad is located on the opposite side of the third unit from the first unit in the first direction, and is exposed from the second element insulating layer in a thickness direction of the second element insulating layer. The insulating tip of claim 1 .

13. The distance between the second pad and the fourth insulating element is greater than the distance between the second insulating element and the fourth insulating element in the thickness direction of the second element insulating layer. The insulated tip of claim 12.

14. the first unit includes a first circuit; The second unit includes a second circuit. The insulating tip of claim 1 .

15. the first circuit includes a transmitting circuit or a receiving circuit electrically connected to the first isolation element; The second circuit includes a transmitting circuit or a receiving circuit electrically connected to the second isolation element.

15. The insulated tip of claim 14.

16. the transmitting circuit or the receiving circuit of the first circuit is disposed at a position overlapping the first insulating element when viewed in a thickness direction of the first element insulating layer, The transmitting circuit or the receiving circuit of the second circuit is disposed at a position overlapping the second insulating element when viewed in a thickness direction of the second element insulating layer.

16. The insulated tip of claim 15.

17. Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is a coil. The insulating tip of claim 1 .

18. Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is an electrode plate. The insulating tip of claim 1 .

19. A semiconductor device including the insulating chip according to any one of claims 1 to 18, a first die pad supporting the first unit; a second die pad spaced apart from the first die pad in the first direction and supporting the second unit; a sealing resin that seals the first die pad, the second die pad, the first unit, the second unit, and the third unit; 13. A semiconductor device comprising:

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